1350 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs4 *5 * Copyright (c) 2016 BayLibre, SAS.6 * Author: Kevin Hilman <khilman@baylibre.com>7 */8#include <linux/kernel.h>9#include <linux/module.h>10#include <linux/init.h>11#include <linux/delay.h>12#include <linux/device.h>13#include <linux/iopoll.h>14#include <linux/of.h>15#include <linux/platform_device.h>16#include <linux/ioport.h>17#include <linux/dma-mapping.h>18#include <linux/mmc/host.h>19#include <linux/mmc/mmc.h>20#include <linux/mmc/sdio.h>21#include <linux/mmc/slot-gpio.h>22#include <linux/io.h>23#include <linux/clk.h>24#include <linux/clk-provider.h>25#include <linux/regulator/consumer.h>26#include <linux/reset.h>27#include <linux/interrupt.h>28#include <linux/bitfield.h>29#include <linux/pinctrl/consumer.h>30 31#define DRIVER_NAME "meson-gx-mmc"32 33#define SD_EMMC_CLOCK 0x034#define CLK_DIV_MASK GENMASK(5, 0)35#define CLK_SRC_MASK GENMASK(7, 6)36#define CLK_CORE_PHASE_MASK GENMASK(9, 8)37#define CLK_TX_PHASE_MASK GENMASK(11, 10)38#define CLK_RX_PHASE_MASK GENMASK(13, 12)39#define CLK_PHASE_0 040#define CLK_PHASE_180 241#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)42#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)43#define CLK_V2_ALWAYS_ON BIT(24)44#define CLK_V2_IRQ_SDIO_SLEEP BIT(25)45 46#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)47#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)48#define CLK_V3_ALWAYS_ON BIT(28)49#define CLK_V3_IRQ_SDIO_SLEEP BIT(29)50 51#define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)52#define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)53#define CLK_ALWAYS_ON(h) (h->data->always_on)54#define CLK_IRQ_SDIO_SLEEP(h) (h->data->irq_sdio_sleep)55 56#define SD_EMMC_DELAY 0x457#define SD_EMMC_ADJUST 0x858#define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)59#define ADJUST_DS_EN BIT(15)60#define ADJUST_ADJ_EN BIT(13)61 62#define SD_EMMC_DELAY1 0x463#define SD_EMMC_DELAY2 0x864#define SD_EMMC_V3_ADJUST 0xc65 66#define SD_EMMC_CALOUT 0x1067#define SD_EMMC_START 0x4068#define START_DESC_INIT BIT(0)69#define START_DESC_BUSY BIT(1)70#define START_DESC_ADDR_MASK GENMASK(31, 2)71 72#define SD_EMMC_CFG 0x4473#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)74#define CFG_BUS_WIDTH_1 0x075#define CFG_BUS_WIDTH_4 0x176#define CFG_BUS_WIDTH_8 0x277#define CFG_DDR BIT(2)78#define CFG_BLK_LEN_MASK GENMASK(7, 4)79#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)80#define CFG_RC_CC_MASK GENMASK(15, 12)81#define CFG_STOP_CLOCK BIT(22)82#define CFG_CLK_ALWAYS_ON BIT(18)83#define CFG_CHK_DS BIT(20)84#define CFG_AUTO_CLK BIT(23)85#define CFG_ERR_ABORT BIT(27)86 87#define SD_EMMC_STATUS 0x4888#define STATUS_BUSY BIT(31)89#define STATUS_DESC_BUSY BIT(30)90#define STATUS_DATI GENMASK(23, 16)91 92#define SD_EMMC_IRQ_EN 0x4c93#define IRQ_RXD_ERR_MASK GENMASK(7, 0)94#define IRQ_TXD_ERR BIT(8)95#define IRQ_DESC_ERR BIT(9)96#define IRQ_RESP_ERR BIT(10)97#define IRQ_CRC_ERR \98 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)99#define IRQ_RESP_TIMEOUT BIT(11)100#define IRQ_DESC_TIMEOUT BIT(12)101#define IRQ_TIMEOUTS \102 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)103#define IRQ_END_OF_CHAIN BIT(13)104#define IRQ_RESP_STATUS BIT(14)105#define IRQ_SDIO BIT(15)106#define IRQ_EN_MASK \107 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN)108 109#define SD_EMMC_CMD_CFG 0x50110#define SD_EMMC_CMD_ARG 0x54111#define SD_EMMC_CMD_DAT 0x58112#define SD_EMMC_CMD_RSP 0x5c113#define SD_EMMC_CMD_RSP1 0x60114#define SD_EMMC_CMD_RSP2 0x64115#define SD_EMMC_CMD_RSP3 0x68116 117#define SD_EMMC_RXD 0x94118#define SD_EMMC_TXD 0x94119#define SD_EMMC_LAST_REG SD_EMMC_TXD120 121#define SD_EMMC_SRAM_DATA_BUF_LEN 1536122#define SD_EMMC_SRAM_DATA_BUF_OFF 0x200123 124#define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */125#define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */126#define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */127#define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */128#define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */129#define SD_EMMC_DESC_BUF_LEN PAGE_SIZE130 131#define SD_EMMC_PRE_REQ_DONE BIT(0)132#define SD_EMMC_DESC_CHAIN_MODE BIT(1)133 134#define MUX_CLK_NUM_PARENTS 2135 136struct meson_mmc_data {137 unsigned int tx_delay_mask;138 unsigned int rx_delay_mask;139 unsigned int always_on;140 unsigned int adjust;141 unsigned int irq_sdio_sleep;142};143 144struct sd_emmc_desc {145 u32 cmd_cfg;146 u32 cmd_arg;147 u32 cmd_data;148 u32 cmd_resp;149};150 151struct meson_host {152 struct device *dev;153 const struct meson_mmc_data *data;154 struct mmc_host *mmc;155 struct mmc_command *cmd;156 157 void __iomem *regs;158 struct clk *mux_clk;159 struct clk *mmc_clk;160 unsigned long req_rate;161 bool ddr;162 163 bool dram_access_quirk;164 165 struct pinctrl *pinctrl;166 struct pinctrl_state *pins_clk_gate;167 168 unsigned int bounce_buf_size;169 void *bounce_buf;170 void __iomem *bounce_iomem_buf;171 dma_addr_t bounce_dma_addr;172 struct sd_emmc_desc *descs;173 dma_addr_t descs_dma_addr;174 175 int irq;176 177 bool needs_pre_post_req;178 179 spinlock_t lock;180};181 182#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)183#define CMD_CFG_BLOCK_MODE BIT(9)184#define CMD_CFG_R1B BIT(10)185#define CMD_CFG_END_OF_CHAIN BIT(11)186#define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)187#define CMD_CFG_NO_RESP BIT(16)188#define CMD_CFG_NO_CMD BIT(17)189#define CMD_CFG_DATA_IO BIT(18)190#define CMD_CFG_DATA_WR BIT(19)191#define CMD_CFG_RESP_NOCRC BIT(20)192#define CMD_CFG_RESP_128 BIT(21)193#define CMD_CFG_RESP_NUM BIT(22)194#define CMD_CFG_DATA_NUM BIT(23)195#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)196#define CMD_CFG_ERROR BIT(30)197#define CMD_CFG_OWNER BIT(31)198 199#define CMD_DATA_MASK GENMASK(31, 2)200#define CMD_DATA_BIG_ENDIAN BIT(1)201#define CMD_DATA_SRAM BIT(0)202#define CMD_RESP_MASK GENMASK(31, 1)203#define CMD_RESP_SRAM BIT(0)204 205static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)206{207 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;208 209 if (!timeout)210 return SD_EMMC_CMD_TIMEOUT_DATA;211 212 timeout = roundup_pow_of_two(timeout);213 214 return min(timeout, 32768U); /* max. 2^15 ms */215}216 217static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)218{219 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)220 return cmd->mrq->cmd;221 else if (mmc_op_multi(cmd->opcode) &&222 (!cmd->mrq->sbc || cmd->error || cmd->data->error))223 return cmd->mrq->stop;224 else225 return NULL;226}227 228static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,229 struct mmc_request *mrq)230{231 struct meson_host *host = mmc_priv(mmc);232 struct mmc_data *data = mrq->data;233 struct scatterlist *sg;234 int i;235 236 /*237 * When Controller DMA cannot directly access DDR memory, disable238 * support for Chain Mode to directly use the internal SRAM using239 * the bounce buffer mode.240 */241 if (host->dram_access_quirk)242 return;243 244 /* SD_IO_RW_EXTENDED (CMD53) can also use block mode under the hood */245 if (data->blocks > 1 || mrq->cmd->opcode == SD_IO_RW_EXTENDED) {246 /*247 * In block mode DMA descriptor format, "length" field indicates248 * number of blocks and there is no way to pass DMA size that249 * is not multiple of SDIO block size, making it impossible to250 * tie more than one memory buffer with single SDIO block.251 * Block mode sg buffer size should be aligned with SDIO block252 * size, otherwise chain mode could not be used.253 */254 for_each_sg(data->sg, sg, data->sg_len, i) {255 if (sg->length % data->blksz) {256 dev_warn_once(mmc_dev(mmc),257 "unaligned sg len %u blksize %u, disabling descriptor DMA for transfer\n",258 sg->length, data->blksz);259 return;260 }261 }262 }263 264 for_each_sg(data->sg, sg, data->sg_len, i) {265 /* check for 8 byte alignment */266 if (sg->offset % 8) {267 dev_warn_once(mmc_dev(mmc),268 "unaligned sg offset %u, disabling descriptor DMA for transfer\n",269 sg->offset);270 return;271 }272 }273 274 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;275}276 277static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)278{279 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;280}281 282static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)283{284 return data && data->flags & MMC_DATA_READ &&285 !meson_mmc_desc_chain_mode(data);286}287 288static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)289{290 struct mmc_data *data = mrq->data;291 292 if (!data)293 return;294 295 meson_mmc_get_transfer_mode(mmc, mrq);296 data->host_cookie |= SD_EMMC_PRE_REQ_DONE;297 298 if (!meson_mmc_desc_chain_mode(data))299 return;300 301 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,302 mmc_get_dma_dir(data));303 if (!data->sg_count)304 dev_err(mmc_dev(mmc), "dma_map_sg failed");305}306 307static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,308 int err)309{310 struct mmc_data *data = mrq->data;311 312 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)313 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,314 mmc_get_dma_dir(data));315}316 317/*318 * Gating the clock on this controller is tricky. It seems the mmc clock319 * is also used by the controller. It may crash during some operation if the320 * clock is stopped. The safest thing to do, whenever possible, is to keep321 * clock running at stop it at the pad using the pinmux.322 */323static void meson_mmc_clk_gate(struct meson_host *host)324{325 u32 cfg;326 327 if (host->pins_clk_gate) {328 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);329 } else {330 /*331 * If the pinmux is not provided - default to the classic and332 * unsafe method333 */334 cfg = readl(host->regs + SD_EMMC_CFG);335 cfg |= CFG_STOP_CLOCK;336 writel(cfg, host->regs + SD_EMMC_CFG);337 }338}339 340static void meson_mmc_clk_ungate(struct meson_host *host)341{342 u32 cfg;343 344 if (host->pins_clk_gate)345 pinctrl_select_default_state(host->dev);346 347 /* Make sure the clock is not stopped in the controller */348 cfg = readl(host->regs + SD_EMMC_CFG);349 cfg &= ~CFG_STOP_CLOCK;350 writel(cfg, host->regs + SD_EMMC_CFG);351}352 353static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,354 bool ddr)355{356 struct mmc_host *mmc = host->mmc;357 int ret;358 u32 cfg;359 360 /* Same request - bail-out */361 if (host->ddr == ddr && host->req_rate == rate)362 return 0;363 364 /* stop clock */365 meson_mmc_clk_gate(host);366 host->req_rate = 0;367 mmc->actual_clock = 0;368 369 /* return with clock being stopped */370 if (!rate)371 return 0;372 373 /* Stop the clock during rate change to avoid glitches */374 cfg = readl(host->regs + SD_EMMC_CFG);375 cfg |= CFG_STOP_CLOCK;376 writel(cfg, host->regs + SD_EMMC_CFG);377 378 if (ddr) {379 /* DDR modes require higher module clock */380 rate <<= 1;381 cfg |= CFG_DDR;382 } else {383 cfg &= ~CFG_DDR;384 }385 writel(cfg, host->regs + SD_EMMC_CFG);386 host->ddr = ddr;387 388 ret = clk_set_rate(host->mmc_clk, rate);389 if (ret) {390 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",391 rate, ret);392 return ret;393 }394 395 host->req_rate = rate;396 mmc->actual_clock = clk_get_rate(host->mmc_clk);397 398 /* We should report the real output frequency of the controller */399 if (ddr) {400 host->req_rate >>= 1;401 mmc->actual_clock >>= 1;402 }403 404 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);405 if (rate != mmc->actual_clock)406 dev_dbg(host->dev, "requested rate was %lu\n", rate);407 408 /* (re)start clock */409 meson_mmc_clk_ungate(host);410 411 return 0;412}413 414/*415 * The SD/eMMC IP block has an internal mux and divider used for416 * generating the MMC clock. Use the clock framework to create and417 * manage these clocks.418 */419static int meson_mmc_clk_init(struct meson_host *host)420{421 struct clk_init_data init;422 struct clk_mux *mux;423 struct clk_divider *div;424 char clk_name[32];425 int i, ret = 0;426 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];427 const char *clk_parent[1];428 u32 clk_reg;429 430 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */431 clk_reg = CLK_ALWAYS_ON(host);432 clk_reg |= CLK_DIV_MASK;433 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);434 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);435 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);436 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)437 clk_reg |= CLK_IRQ_SDIO_SLEEP(host);438 writel(clk_reg, host->regs + SD_EMMC_CLOCK);439 440 /* get the mux parents */441 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {442 struct clk *clk;443 char name[16];444 445 snprintf(name, sizeof(name), "clkin%d", i);446 clk = devm_clk_get(host->dev, name);447 if (IS_ERR(clk))448 return dev_err_probe(host->dev, PTR_ERR(clk),449 "Missing clock %s\n", name);450 451 mux_parent_names[i] = __clk_get_name(clk);452 }453 454 /* create the mux */455 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);456 if (!mux)457 return -ENOMEM;458 459 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));460 init.name = clk_name;461 init.ops = &clk_mux_ops;462 init.flags = 0;463 init.parent_names = mux_parent_names;464 init.num_parents = MUX_CLK_NUM_PARENTS;465 466 mux->reg = host->regs + SD_EMMC_CLOCK;467 mux->shift = __ffs(CLK_SRC_MASK);468 mux->mask = CLK_SRC_MASK >> mux->shift;469 mux->hw.init = &init;470 471 host->mux_clk = devm_clk_register(host->dev, &mux->hw);472 if (WARN_ON(IS_ERR(host->mux_clk)))473 return PTR_ERR(host->mux_clk);474 475 /* create the divider */476 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);477 if (!div)478 return -ENOMEM;479 480 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));481 init.name = clk_name;482 init.ops = &clk_divider_ops;483 init.flags = CLK_SET_RATE_PARENT;484 clk_parent[0] = __clk_get_name(host->mux_clk);485 init.parent_names = clk_parent;486 init.num_parents = 1;487 488 div->reg = host->regs + SD_EMMC_CLOCK;489 div->shift = __ffs(CLK_DIV_MASK);490 div->width = __builtin_popcountl(CLK_DIV_MASK);491 div->hw.init = &init;492 div->flags = CLK_DIVIDER_ONE_BASED;493 494 host->mmc_clk = devm_clk_register(host->dev, &div->hw);495 if (WARN_ON(IS_ERR(host->mmc_clk)))496 return PTR_ERR(host->mmc_clk);497 498 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */499 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);500 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);501 if (ret)502 return ret;503 504 return clk_prepare_enable(host->mmc_clk);505}506 507static void meson_mmc_disable_resampling(struct meson_host *host)508{509 unsigned int val = readl(host->regs + host->data->adjust);510 511 val &= ~ADJUST_ADJ_EN;512 writel(val, host->regs + host->data->adjust);513}514 515static void meson_mmc_reset_resampling(struct meson_host *host)516{517 unsigned int val;518 519 meson_mmc_disable_resampling(host);520 521 val = readl(host->regs + host->data->adjust);522 val &= ~ADJUST_ADJ_DELAY_MASK;523 writel(val, host->regs + host->data->adjust);524}525 526static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)527{528 struct meson_host *host = mmc_priv(mmc);529 unsigned int val, dly, max_dly, i;530 int ret;531 532 /* Resampling is done using the source clock */533 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),534 clk_get_rate(host->mmc_clk));535 536 val = readl(host->regs + host->data->adjust);537 val |= ADJUST_ADJ_EN;538 writel(val, host->regs + host->data->adjust);539 540 if (mmc_doing_retune(mmc))541 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;542 else543 dly = 0;544 545 for (i = 0; i < max_dly; i++) {546 val &= ~ADJUST_ADJ_DELAY_MASK;547 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);548 writel(val, host->regs + host->data->adjust);549 550 ret = mmc_send_tuning(mmc, opcode, NULL);551 if (!ret) {552 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",553 (dly + i) % max_dly);554 return 0;555 }556 }557 558 meson_mmc_reset_resampling(host);559 return -EIO;560}561 562static int meson_mmc_prepare_ios_clock(struct meson_host *host,563 struct mmc_ios *ios)564{565 bool ddr;566 567 switch (ios->timing) {568 case MMC_TIMING_MMC_DDR52:569 case MMC_TIMING_UHS_DDR50:570 ddr = true;571 break;572 573 default:574 ddr = false;575 break;576 }577 578 return meson_mmc_clk_set(host, ios->clock, ddr);579}580 581static void meson_mmc_check_resampling(struct meson_host *host,582 struct mmc_ios *ios)583{584 switch (ios->timing) {585 case MMC_TIMING_LEGACY:586 case MMC_TIMING_MMC_HS:587 case MMC_TIMING_SD_HS:588 case MMC_TIMING_MMC_DDR52:589 meson_mmc_disable_resampling(host);590 break;591 }592}593 594static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)595{596 struct meson_host *host = mmc_priv(mmc);597 u32 bus_width, val;598 int err;599 600 /*601 * GPIO regulator, only controls switching between 1v8 and602 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.603 */604 switch (ios->power_mode) {605 case MMC_POWER_OFF:606 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);607 mmc_regulator_disable_vqmmc(mmc);608 609 break;610 611 case MMC_POWER_UP:612 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);613 614 break;615 616 case MMC_POWER_ON:617 mmc_regulator_enable_vqmmc(mmc);618 619 break;620 }621 622 /* Bus width */623 switch (ios->bus_width) {624 case MMC_BUS_WIDTH_1:625 bus_width = CFG_BUS_WIDTH_1;626 break;627 case MMC_BUS_WIDTH_4:628 bus_width = CFG_BUS_WIDTH_4;629 break;630 case MMC_BUS_WIDTH_8:631 bus_width = CFG_BUS_WIDTH_8;632 break;633 default:634 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",635 ios->bus_width);636 bus_width = CFG_BUS_WIDTH_4;637 }638 639 val = readl(host->regs + SD_EMMC_CFG);640 val &= ~CFG_BUS_WIDTH_MASK;641 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);642 writel(val, host->regs + SD_EMMC_CFG);643 644 meson_mmc_check_resampling(host, ios);645 err = meson_mmc_prepare_ios_clock(host, ios);646 if (err)647 dev_err(host->dev, "Failed to set clock: %d\n,", err);648 649 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);650}651 652static void meson_mmc_request_done(struct mmc_host *mmc,653 struct mmc_request *mrq)654{655 struct meson_host *host = mmc_priv(mmc);656 657 host->cmd = NULL;658 if (host->needs_pre_post_req)659 meson_mmc_post_req(mmc, mrq, 0);660 mmc_request_done(host->mmc, mrq);661}662 663static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)664{665 struct meson_host *host = mmc_priv(mmc);666 u32 cfg, blksz_old;667 668 cfg = readl(host->regs + SD_EMMC_CFG);669 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);670 671 if (!is_power_of_2(blksz))672 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);673 674 blksz = ilog2(blksz);675 676 /* check if block-size matches, if not update */677 if (blksz == blksz_old)678 return;679 680 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,681 blksz_old, blksz);682 683 cfg &= ~CFG_BLK_LEN_MASK;684 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);685 writel(cfg, host->regs + SD_EMMC_CFG);686}687 688static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)689{690 if (cmd->flags & MMC_RSP_PRESENT) {691 if (cmd->flags & MMC_RSP_136)692 *cmd_cfg |= CMD_CFG_RESP_128;693 *cmd_cfg |= CMD_CFG_RESP_NUM;694 695 if (!(cmd->flags & MMC_RSP_CRC))696 *cmd_cfg |= CMD_CFG_RESP_NOCRC;697 698 if (cmd->flags & MMC_RSP_BUSY)699 *cmd_cfg |= CMD_CFG_R1B;700 } else {701 *cmd_cfg |= CMD_CFG_NO_RESP;702 }703}704 705static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)706{707 struct meson_host *host = mmc_priv(mmc);708 struct sd_emmc_desc *desc = host->descs;709 struct mmc_data *data = host->cmd->data;710 struct scatterlist *sg;711 u32 start;712 int i;713 714 if (data->flags & MMC_DATA_WRITE)715 cmd_cfg |= CMD_CFG_DATA_WR;716 717 if (data->blocks > 1) {718 cmd_cfg |= CMD_CFG_BLOCK_MODE;719 meson_mmc_set_blksz(mmc, data->blksz);720 }721 722 for_each_sg(data->sg, sg, data->sg_count, i) {723 unsigned int len = sg_dma_len(sg);724 725 if (data->blocks > 1)726 len /= data->blksz;727 728 desc[i].cmd_cfg = cmd_cfg;729 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);730 if (i > 0)731 desc[i].cmd_cfg |= CMD_CFG_NO_CMD;732 desc[i].cmd_arg = host->cmd->arg;733 desc[i].cmd_resp = 0;734 desc[i].cmd_data = sg_dma_address(sg);735 }736 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;737 738 dma_wmb(); /* ensure descriptor is written before kicked */739 start = host->descs_dma_addr | START_DESC_BUSY;740 writel(start, host->regs + SD_EMMC_START);741}742 743/* local sg copy for dram_access_quirk */744static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data,745 size_t buflen, bool to_buffer)746{747 unsigned int sg_flags = SG_MITER_ATOMIC;748 struct scatterlist *sgl = data->sg;749 unsigned int nents = data->sg_len;750 struct sg_mapping_iter miter;751 unsigned int offset = 0;752 753 if (to_buffer)754 sg_flags |= SG_MITER_FROM_SG;755 else756 sg_flags |= SG_MITER_TO_SG;757 758 sg_miter_start(&miter, sgl, nents, sg_flags);759 760 while ((offset < buflen) && sg_miter_next(&miter)) {761 unsigned int buf_offset = 0;762 unsigned int len, left;763 u32 *buf = miter.addr;764 765 len = min(miter.length, buflen - offset);766 left = len;767 768 if (to_buffer) {769 do {770 writel(*buf++, host->bounce_iomem_buf + offset + buf_offset);771 772 buf_offset += 4;773 left -= 4;774 } while (left);775 } else {776 do {777 *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset);778 779 buf_offset += 4;780 left -= 4;781 } while (left);782 }783 784 offset += len;785 }786 787 sg_miter_stop(&miter);788}789 790static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)791{792 struct meson_host *host = mmc_priv(mmc);793 struct mmc_data *data = cmd->data;794 u32 cmd_cfg = 0, cmd_data = 0;795 unsigned int xfer_bytes = 0;796 797 /* Setup descriptors */798 dma_rmb();799 800 host->cmd = cmd;801 802 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);803 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */804 805 meson_mmc_set_response_bits(cmd, &cmd_cfg);806 807 /* data? */808 if (data) {809 data->bytes_xfered = 0;810 cmd_cfg |= CMD_CFG_DATA_IO;811 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,812 ilog2(meson_mmc_get_timeout_msecs(data)));813 814 if (meson_mmc_desc_chain_mode(data)) {815 meson_mmc_desc_chain_transfer(mmc, cmd_cfg);816 return;817 }818 819 if (data->blocks > 1) {820 cmd_cfg |= CMD_CFG_BLOCK_MODE;821 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,822 data->blocks);823 meson_mmc_set_blksz(mmc, data->blksz);824 } else {825 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);826 }827 828 xfer_bytes = data->blksz * data->blocks;829 if (data->flags & MMC_DATA_WRITE) {830 cmd_cfg |= CMD_CFG_DATA_WR;831 WARN_ON(xfer_bytes > host->bounce_buf_size);832 if (host->dram_access_quirk)833 meson_mmc_copy_buffer(host, data, xfer_bytes, true);834 else835 sg_copy_to_buffer(data->sg, data->sg_len,836 host->bounce_buf, xfer_bytes);837 dma_wmb();838 }839 840 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;841 } else {842 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,843 ilog2(SD_EMMC_CMD_TIMEOUT));844 }845 846 /* Last descriptor */847 cmd_cfg |= CMD_CFG_END_OF_CHAIN;848 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);849 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);850 writel(0, host->regs + SD_EMMC_CMD_RSP);851 wmb(); /* ensure descriptor is written before kicked */852 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);853}854 855static int meson_mmc_validate_dram_access(struct mmc_host *mmc, struct mmc_data *data)856{857 struct scatterlist *sg;858 int i;859 860 /* Reject request if any element offset or size is not 32bit aligned */861 for_each_sg(data->sg, sg, data->sg_len, i) {862 if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||863 !IS_ALIGNED(sg->length, sizeof(u32))) {864 dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n",865 data->sg->offset, data->sg->length);866 return -EINVAL;867 }868 }869 870 return 0;871}872 873static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)874{875 struct meson_host *host = mmc_priv(mmc);876 host->needs_pre_post_req = mrq->data &&877 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);878 879 /*880 * The memory at the end of the controller used as bounce buffer for881 * the dram_access_quirk only accepts 32bit read/write access,882 * check the aligment and length of the data before starting the request.883 */884 if (host->dram_access_quirk && mrq->data) {885 mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data);886 if (mrq->cmd->error) {887 mmc_request_done(mmc, mrq);888 return;889 }890 }891 892 if (host->needs_pre_post_req) {893 meson_mmc_get_transfer_mode(mmc, mrq);894 if (!meson_mmc_desc_chain_mode(mrq->data))895 host->needs_pre_post_req = false;896 }897 898 if (host->needs_pre_post_req)899 meson_mmc_pre_req(mmc, mrq);900 901 /* Stop execution */902 writel(0, host->regs + SD_EMMC_START);903 904 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);905}906 907static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)908{909 struct meson_host *host = mmc_priv(mmc);910 911 if (cmd->flags & MMC_RSP_136) {912 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);913 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);914 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);915 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);916 } else if (cmd->flags & MMC_RSP_PRESENT) {917 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);918 }919}920 921static void __meson_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)922{923 struct meson_host *host = mmc_priv(mmc);924 u32 reg_irqen = IRQ_EN_MASK;925 926 if (enable)927 reg_irqen |= IRQ_SDIO;928 writel(reg_irqen, host->regs + SD_EMMC_IRQ_EN);929}930 931static irqreturn_t meson_mmc_irq(int irq, void *dev_id)932{933 struct meson_host *host = dev_id;934 struct mmc_command *cmd;935 u32 status, raw_status, irq_mask = IRQ_EN_MASK;936 irqreturn_t ret = IRQ_NONE;937 938 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)939 irq_mask |= IRQ_SDIO;940 raw_status = readl(host->regs + SD_EMMC_STATUS);941 status = raw_status & irq_mask;942 943 if (!status) {944 dev_dbg(host->dev,945 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",946 irq_mask, raw_status);947 return IRQ_NONE;948 }949 950 /* ack all raised interrupts */951 writel(status, host->regs + SD_EMMC_STATUS);952 953 cmd = host->cmd;954 955 if (status & IRQ_SDIO) {956 spin_lock(&host->lock);957 __meson_mmc_enable_sdio_irq(host->mmc, 0);958 sdio_signal_irq(host->mmc);959 spin_unlock(&host->lock);960 status &= ~IRQ_SDIO;961 if (!status)962 return IRQ_HANDLED;963 }964 965 if (WARN_ON(!cmd))966 return IRQ_NONE;967 968 cmd->error = 0;969 if (status & IRQ_CRC_ERR) {970 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);971 cmd->error = -EILSEQ;972 ret = IRQ_WAKE_THREAD;973 goto out;974 }975 976 if (status & IRQ_TIMEOUTS) {977 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);978 cmd->error = -ETIMEDOUT;979 ret = IRQ_WAKE_THREAD;980 goto out;981 }982 983 meson_mmc_read_resp(host->mmc, cmd);984 985 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {986 struct mmc_data *data = cmd->data;987 988 if (data && !cmd->error)989 data->bytes_xfered = data->blksz * data->blocks;990 991 return IRQ_WAKE_THREAD;992 }993 994out:995 if (cmd->error) {996 /* Stop desc in case of errors */997 u32 start = readl(host->regs + SD_EMMC_START);998 999 start &= ~START_DESC_BUSY;1000 writel(start, host->regs + SD_EMMC_START);1001 }1002 1003 return ret;1004}1005 1006static int meson_mmc_wait_desc_stop(struct meson_host *host)1007{1008 u32 status;1009 1010 /*1011 * It may sometimes take a while for it to actually halt. Here, we1012 * are giving it 5ms to comply1013 *1014 * If we don't confirm the descriptor is stopped, it might raise new1015 * IRQs after we have called mmc_request_done() which is bad.1016 */1017 1018 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,1019 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)),1020 100, 5000);1021}1022 1023static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)1024{1025 struct meson_host *host = dev_id;1026 struct mmc_command *next_cmd, *cmd = host->cmd;1027 struct mmc_data *data;1028 unsigned int xfer_bytes;1029 1030 if (WARN_ON(!cmd))1031 return IRQ_NONE;1032 1033 if (cmd->error) {1034 meson_mmc_wait_desc_stop(host);1035 meson_mmc_request_done(host->mmc, cmd->mrq);1036 1037 return IRQ_HANDLED;1038 }1039 1040 data = cmd->data;1041 if (meson_mmc_bounce_buf_read(data)) {1042 xfer_bytes = data->blksz * data->blocks;1043 WARN_ON(xfer_bytes > host->bounce_buf_size);1044 if (host->dram_access_quirk)1045 meson_mmc_copy_buffer(host, data, xfer_bytes, false);1046 else1047 sg_copy_from_buffer(data->sg, data->sg_len,1048 host->bounce_buf, xfer_bytes);1049 }1050 1051 next_cmd = meson_mmc_get_next_command(cmd);1052 if (next_cmd)1053 meson_mmc_start_cmd(host->mmc, next_cmd);1054 else1055 meson_mmc_request_done(host->mmc, cmd->mrq);1056 1057 return IRQ_HANDLED;1058}1059 1060static void meson_mmc_cfg_init(struct meson_host *host)1061{1062 u32 cfg = 0;1063 1064 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,1065 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));1066 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));1067 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));1068 1069 /* abort chain on R/W errors */1070 cfg |= CFG_ERR_ABORT;1071 1072 writel(cfg, host->regs + SD_EMMC_CFG);1073}1074 1075static int meson_mmc_card_busy(struct mmc_host *mmc)1076{1077 struct meson_host *host = mmc_priv(mmc);1078 u32 regval;1079 1080 regval = readl(host->regs + SD_EMMC_STATUS);1081 1082 /* We are only interrested in lines 0 to 3, so mask the other ones */1083 return !(FIELD_GET(STATUS_DATI, regval) & 0xf);1084}1085 1086static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)1087{1088 int ret;1089 1090 /* vqmmc regulator is available */1091 if (!IS_ERR(mmc->supply.vqmmc)) {1092 /*1093 * The usual amlogic setup uses a GPIO to switch from one1094 * regulator to the other. While the voltage ramp up is1095 * pretty fast, care must be taken when switching from 3.3v1096 * to 1.8v. Please make sure the regulator framework is aware1097 * of your own regulator constraints1098 */1099 ret = mmc_regulator_set_vqmmc(mmc, ios);1100 return ret < 0 ? ret : 0;1101 }1102 1103 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */1104 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)1105 return 0;1106 1107 return -EINVAL;1108}1109 1110static void meson_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)1111{1112 struct meson_host *host = mmc_priv(mmc);1113 unsigned long flags;1114 1115 spin_lock_irqsave(&host->lock, flags);1116 __meson_mmc_enable_sdio_irq(mmc, enable);1117 spin_unlock_irqrestore(&host->lock, flags);1118}1119 1120static void meson_mmc_ack_sdio_irq(struct mmc_host *mmc)1121{1122 meson_mmc_enable_sdio_irq(mmc, 1);1123}1124 1125static const struct mmc_host_ops meson_mmc_ops = {1126 .request = meson_mmc_request,1127 .set_ios = meson_mmc_set_ios,1128 .get_cd = mmc_gpio_get_cd,1129 .pre_req = meson_mmc_pre_req,1130 .post_req = meson_mmc_post_req,1131 .execute_tuning = meson_mmc_resampling_tuning,1132 .card_busy = meson_mmc_card_busy,1133 .start_signal_voltage_switch = meson_mmc_voltage_switch,1134 .enable_sdio_irq = meson_mmc_enable_sdio_irq,1135 .ack_sdio_irq = meson_mmc_ack_sdio_irq,1136};1137 1138static int meson_mmc_probe(struct platform_device *pdev)1139{1140 struct resource *res;1141 struct meson_host *host;1142 struct mmc_host *mmc;1143 struct clk *core_clk;1144 int cd_irq, ret;1145 1146 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct meson_host));1147 if (!mmc)1148 return -ENOMEM;1149 host = mmc_priv(mmc);1150 host->mmc = mmc;1151 host->dev = &pdev->dev;1152 dev_set_drvdata(&pdev->dev, host);1153 1154 /* The G12A SDIO Controller needs an SRAM bounce buffer */1155 host->dram_access_quirk = device_property_read_bool(&pdev->dev,1156 "amlogic,dram-access-quirk");1157 1158 /* Get regulators and the supported OCR mask */1159 ret = mmc_regulator_get_supply(mmc);1160 if (ret)1161 return ret;1162 1163 ret = mmc_of_parse(mmc);1164 if (ret)1165 return dev_err_probe(&pdev->dev, ret, "error parsing DT\n");1166 1167 mmc->caps |= MMC_CAP_CMD23;1168 1169 if (mmc->caps & MMC_CAP_SDIO_IRQ)1170 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;1171 1172 host->data = of_device_get_match_data(&pdev->dev);1173 if (!host->data)1174 return -EINVAL;1175 1176 ret = device_reset_optional(&pdev->dev);1177 if (ret)1178 return dev_err_probe(&pdev->dev, ret, "device reset failed\n");1179 1180 host->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);1181 if (IS_ERR(host->regs))1182 return PTR_ERR(host->regs);1183 1184 host->irq = platform_get_irq(pdev, 0);1185 if (host->irq < 0)1186 return host->irq;1187 1188 cd_irq = platform_get_irq_optional(pdev, 1);1189 mmc_gpio_set_cd_irq(mmc, cd_irq);1190 1191 host->pinctrl = devm_pinctrl_get(&pdev->dev);1192 if (IS_ERR(host->pinctrl))1193 return PTR_ERR(host->pinctrl);1194 1195 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,1196 "clk-gate");1197 if (IS_ERR(host->pins_clk_gate)) {1198 dev_warn(&pdev->dev,1199 "can't get clk-gate pinctrl, using clk_stop bit\n");1200 host->pins_clk_gate = NULL;1201 }1202 1203 core_clk = devm_clk_get_enabled(&pdev->dev, "core");1204 if (IS_ERR(core_clk))1205 return PTR_ERR(core_clk);1206 1207 ret = meson_mmc_clk_init(host);1208 if (ret)1209 return ret;1210 1211 /* set config to sane default */1212 meson_mmc_cfg_init(host);1213 1214 /* Stop execution */1215 writel(0, host->regs + SD_EMMC_START);1216 1217 /* clear, ack and enable interrupts */1218 writel(0, host->regs + SD_EMMC_IRQ_EN);1219 writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS);1220 writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN);1221 1222 ret = request_threaded_irq(host->irq, meson_mmc_irq,1223 meson_mmc_irq_thread, IRQF_ONESHOT,1224 dev_name(&pdev->dev), host);1225 if (ret)1226 goto err_init_clk;1227 1228 spin_lock_init(&host->lock);1229 1230 if (host->dram_access_quirk) {1231 /* Limit segments to 1 due to low available sram memory */1232 mmc->max_segs = 1;1233 /* Limit to the available sram memory */1234 mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN /1235 mmc->max_blk_size;1236 } else {1237 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;1238 mmc->max_segs = SD_EMMC_DESC_BUF_LEN /1239 sizeof(struct sd_emmc_desc);1240 }1241 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;1242 mmc->max_seg_size = mmc->max_req_size;1243 1244 /*1245 * At the moment, we don't know how to reliably enable HS400.1246 * From the different datasheets, it is not even clear if this mode1247 * is officially supported by any of the SoCs1248 */1249 mmc->caps2 &= ~MMC_CAP2_HS400;1250 1251 if (host->dram_access_quirk) {1252 /*1253 * The MMC Controller embeds 1,5KiB of internal SRAM1254 * that can be used to be used as bounce buffer.1255 * In the case of the G12A SDIO controller, use these1256 * instead of the DDR memory1257 */1258 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;1259 host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;1260 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;1261 } else {1262 /* data bounce buffer */1263 host->bounce_buf_size = mmc->max_req_size;1264 host->bounce_buf =1265 dmam_alloc_coherent(host->dev, host->bounce_buf_size,1266 &host->bounce_dma_addr, GFP_KERNEL);1267 if (host->bounce_buf == NULL) {1268 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");1269 ret = -ENOMEM;1270 goto err_free_irq;1271 }1272 }1273 1274 host->descs = dmam_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,1275 &host->descs_dma_addr, GFP_KERNEL);1276 if (!host->descs) {1277 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");1278 ret = -ENOMEM;1279 goto err_free_irq;1280 }1281 1282 mmc->ops = &meson_mmc_ops;1283 ret = mmc_add_host(mmc);1284 if (ret)1285 goto err_free_irq;1286 1287 return 0;1288 1289err_free_irq:1290 free_irq(host->irq, host);1291err_init_clk:1292 clk_disable_unprepare(host->mmc_clk);1293 return ret;1294}1295 1296static void meson_mmc_remove(struct platform_device *pdev)1297{1298 struct meson_host *host = dev_get_drvdata(&pdev->dev);1299 1300 mmc_remove_host(host->mmc);1301 1302 /* disable interrupts */1303 writel(0, host->regs + SD_EMMC_IRQ_EN);1304 free_irq(host->irq, host);1305 1306 clk_disable_unprepare(host->mmc_clk);1307}1308 1309static const struct meson_mmc_data meson_gx_data = {1310 .tx_delay_mask = CLK_V2_TX_DELAY_MASK,1311 .rx_delay_mask = CLK_V2_RX_DELAY_MASK,1312 .always_on = CLK_V2_ALWAYS_ON,1313 .adjust = SD_EMMC_ADJUST,1314 .irq_sdio_sleep = CLK_V2_IRQ_SDIO_SLEEP,1315};1316 1317static const struct meson_mmc_data meson_axg_data = {1318 .tx_delay_mask = CLK_V3_TX_DELAY_MASK,1319 .rx_delay_mask = CLK_V3_RX_DELAY_MASK,1320 .always_on = CLK_V3_ALWAYS_ON,1321 .adjust = SD_EMMC_V3_ADJUST,1322 .irq_sdio_sleep = CLK_V3_IRQ_SDIO_SLEEP,1323};1324 1325static const struct of_device_id meson_mmc_of_match[] = {1326 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data },1327 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data },1328 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data },1329 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data },1330 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data },1331 {}1332};1333MODULE_DEVICE_TABLE(of, meson_mmc_of_match);1334 1335static struct platform_driver meson_mmc_driver = {1336 .probe = meson_mmc_probe,1337 .remove_new = meson_mmc_remove,1338 .driver = {1339 .name = DRIVER_NAME,1340 .probe_type = PROBE_PREFER_ASYNCHRONOUS,1341 .of_match_table = meson_mmc_of_match,1342 },1343};1344 1345module_platform_driver(meson_mmc_driver);1346 1347MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");1348MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");1349MODULE_LICENSE("GPL v2");1350