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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Copyright (C) 2020 Martin Blumenstingl <martin.blumenstingl@googlemail.com>4 */5 6#ifndef _MESON_MX_SDHC_H_7#define _MESON_MX_SDHC_H_8 9#include <linux/bitfield.h>10 11#define MESON_SDHC_ARGU 0x0012 13#define MESON_SDHC_SEND 0x0414 #define MESON_SDHC_SEND_CMD_INDEX GENMASK(5, 0)15 #define MESON_SDHC_SEND_CMD_HAS_RESP BIT(6)16 #define MESON_SDHC_SEND_CMD_HAS_DATA BIT(7)17 #define MESON_SDHC_SEND_RESP_LEN BIT(8)18 #define MESON_SDHC_SEND_RESP_NO_CRC BIT(9)19 #define MESON_SDHC_SEND_DATA_DIR BIT(10)20 #define MESON_SDHC_SEND_DATA_STOP BIT(11)21 #define MESON_SDHC_SEND_R1B BIT(12)22 #define MESON_SDHC_SEND_TOTAL_PACK GENMASK(31, 16)23 24#define MESON_SDHC_CTRL 0x0825 #define MESON_SDHC_CTRL_DAT_TYPE GENMASK(1, 0)26 #define MESON_SDHC_CTRL_DDR_MODE BIT(2)27 #define MESON_SDHC_CTRL_TX_CRC_NOCHECK BIT(3)28 #define MESON_SDHC_CTRL_PACK_LEN GENMASK(12, 4)29 #define MESON_SDHC_CTRL_RX_TIMEOUT GENMASK(19, 13)30 #define MESON_SDHC_CTRL_RX_PERIOD GENMASK(23, 20)31 #define MESON_SDHC_CTRL_RX_ENDIAN GENMASK(26, 24)32 #define MESON_SDHC_CTRL_SDIO_IRQ_MODE BIT(27)33 #define MESON_SDHC_CTRL_DAT0_IRQ_SEL BIT(28)34 #define MESON_SDHC_CTRL_TX_ENDIAN GENMASK(31, 29)35 36#define MESON_SDHC_STAT 0x0c37 #define MESON_SDHC_STAT_CMD_BUSY BIT(0)38 #define MESON_SDHC_STAT_DAT3_0 GENMASK(4, 1)39 #define MESON_SDHC_STAT_CMD BIT(5)40 #define MESON_SDHC_STAT_RXFIFO_CNT GENMASK(12, 6)41 #define MESON_SDHC_STAT_TXFIFO_CNT GENMASK(19, 13)42 #define MESON_SDHC_STAT_DAT7_4 GENMASK(23, 20)43 44#define MESON_SDHC_CLKC 0x1045 #define MESON_SDHC_CLKC_CLK_DIV GENMASK(11, 0)46 #define MESON_SDHC_CLKC_CLK_JIC BIT(24)47 #define MESON_SDHC_CLKC_MEM_PWR_OFF GENMASK(26, 25)48 49#define MESON_SDHC_ADDR 0x1450 51#define MESON_SDHC_PDMA 0x1852 #define MESON_SDHC_PDMA_DMA_MODE BIT(0)53 #define MESON_SDHC_PDMA_PIO_RDRESP GENMASK(3, 1)54 #define MESON_SDHC_PDMA_DMA_URGENT BIT(4)55 #define MESON_SDHC_PDMA_WR_BURST GENMASK(9, 5)56 #define MESON_SDHC_PDMA_RD_BURST GENMASK(14, 10)57 #define MESON_SDHC_PDMA_RXFIFO_TH GENMASK(21, 15)58 #define MESON_SDHC_PDMA_TXFIFO_TH GENMASK(28, 22)59 #define MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH GENMASK(30, 29)60 #define MESON_SDHC_PDMA_TXFIFO_FILL BIT(31)61 62#define MESON_SDHC_MISC 0x1c63 #define MESON_SDHC_MISC_WCRC_ERR_PATT GENMASK(6, 4)64 #define MESON_SDHC_MISC_WCRC_OK_PATT GENMASK(9, 7)65 #define MESON_SDHC_MISC_BURST_NUM GENMASK(21, 16)66 #define MESON_SDHC_MISC_THREAD_ID GENMASK(27, 22)67 #define MESON_SDHC_MISC_MANUAL_STOP BIT(28)68 #define MESON_SDHC_MISC_TXSTART_THRES GENMASK(31, 29)69 70#define MESON_SDHC_DATA 0x2071 72#define MESON_SDHC_ICTL 0x2473 #define MESON_SDHC_ICTL_RESP_OK BIT(0)74 #define MESON_SDHC_ICTL_RESP_TIMEOUT BIT(1)75 #define MESON_SDHC_ICTL_RESP_ERR_CRC BIT(2)76 #define MESON_SDHC_ICTL_RESP_OK_NOCLEAR BIT(3)77 #define MESON_SDHC_ICTL_DATA_1PACK_OK BIT(4)78 #define MESON_SDHC_ICTL_DATA_TIMEOUT BIT(5)79 #define MESON_SDHC_ICTL_DATA_ERR_CRC BIT(6)80 #define MESON_SDHC_ICTL_DATA_XFER_OK BIT(7)81 #define MESON_SDHC_ICTL_RX_HIGHER BIT(8)82 #define MESON_SDHC_ICTL_RX_LOWER BIT(9)83 #define MESON_SDHC_ICTL_DAT1_IRQ BIT(10)84 #define MESON_SDHC_ICTL_DMA_DONE BIT(11)85 #define MESON_SDHC_ICTL_RXFIFO_FULL BIT(12)86 #define MESON_SDHC_ICTL_TXFIFO_EMPTY BIT(13)87 #define MESON_SDHC_ICTL_ADDI_DAT1_IRQ BIT(14)88 #define MESON_SDHC_ICTL_ALL_IRQS GENMASK(14, 0)89 #define MESON_SDHC_ICTL_DAT1_IRQ_DELAY GENMASK(17, 16)90 91#define MESON_SDHC_ISTA 0x2892 #define MESON_SDHC_ISTA_RESP_OK BIT(0)93 #define MESON_SDHC_ISTA_RESP_TIMEOUT BIT(1)94 #define MESON_SDHC_ISTA_RESP_ERR_CRC BIT(2)95 #define MESON_SDHC_ISTA_RESP_OK_NOCLEAR BIT(3)96 #define MESON_SDHC_ISTA_DATA_1PACK_OK BIT(4)97 #define MESON_SDHC_ISTA_DATA_TIMEOUT BIT(5)98 #define MESON_SDHC_ISTA_DATA_ERR_CRC BIT(6)99 #define MESON_SDHC_ISTA_DATA_XFER_OK BIT(7)100 #define MESON_SDHC_ISTA_RX_HIGHER BIT(8)101 #define MESON_SDHC_ISTA_RX_LOWER BIT(9)102 #define MESON_SDHC_ISTA_DAT1_IRQ BIT(10)103 #define MESON_SDHC_ISTA_DMA_DONE BIT(11)104 #define MESON_SDHC_ISTA_RXFIFO_FULL BIT(12)105 #define MESON_SDHC_ISTA_TXFIFO_EMPTY BIT(13)106 #define MESON_SDHC_ISTA_ADDI_DAT1_IRQ BIT(14)107 #define MESON_SDHC_ISTA_ALL_IRQS GENMASK(14, 0)108 109#define MESON_SDHC_SRST 0x2c110 #define MESON_SDHC_SRST_MAIN_CTRL BIT(0)111 #define MESON_SDHC_SRST_RXFIFO BIT(1)112 #define MESON_SDHC_SRST_TXFIFO BIT(2)113 #define MESON_SDHC_SRST_DPHY_RX BIT(3)114 #define MESON_SDHC_SRST_DPHY_TX BIT(4)115 #define MESON_SDHC_SRST_DMA_IF BIT(5)116 117#define MESON_SDHC_ESTA 0x30118 #define MESON_SDHC_ESTA_11_13 GENMASK(13, 11)119 120#define MESON_SDHC_ENHC 0x34121 #define MESON_SDHC_ENHC_MESON8M2_WRRSP_MODE BIT(0)122 #define MESON_SDHC_ENHC_MESON8M2_CHK_WRRSP BIT(1)123 #define MESON_SDHC_ENHC_MESON8M2_CHK_DMA BIT(2)124 #define MESON_SDHC_ENHC_MESON8M2_DEBUG GENMASK(5, 3)125 #define MESON_SDHC_ENHC_MESON6_RX_TIMEOUT GENMASK(7, 0)126 #define MESON_SDHC_ENHC_MESON6_DMA_RD_RESP BIT(16)127 #define MESON_SDHC_ENHC_MESON6_DMA_WR_RESP BIT(17)128 #define MESON_SDHC_ENHC_SDIO_IRQ_PERIOD GENMASK(15, 8)129 #define MESON_SDHC_ENHC_RXFIFO_TH GENMASK(24, 18)130 #define MESON_SDHC_ENHC_TXFIFO_TH GENMASK(31, 25)131 132#define MESON_SDHC_CLK2 0x38133 #define MESON_SDHC_CLK2_RX_CLK_PHASE GENMASK(11, 0)134 #define MESON_SDHC_CLK2_SD_CLK_PHASE GENMASK(23, 12)135 136struct clk_bulk_data;137 138int meson_mx_sdhc_register_clkc(struct device *dev, void __iomem *base,139 struct clk_bulk_data *clk_bulk_data);140 141#endif /* _MESON_MX_SDHC_H_ */142