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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * meson-mx-sdio.c - Meson6, Meson8 and Meson8b SDIO/MMC Host Controller4 *5 * Copyright (C) 2015 Endless Mobile, Inc.6 * Author: Carlo Caione <carlo@endlessm.com>7 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>8 */9 10#include <linux/bitfield.h>11#include <linux/clk.h>12#include <linux/clk-provider.h>13#include <linux/delay.h>14#include <linux/device.h>15#include <linux/dma-mapping.h>16#include <linux/module.h>17#include <linux/interrupt.h>18#include <linux/io.h>19#include <linux/ioport.h>20#include <linux/platform_device.h>21#include <linux/of_platform.h>22#include <linux/timer.h>23#include <linux/types.h>24 25#include <linux/mmc/host.h>26#include <linux/mmc/mmc.h>27#include <linux/mmc/sdio.h>28#include <linux/mmc/slot-gpio.h>29 30#define MESON_MX_SDIO_ARGU 0x0031 32#define MESON_MX_SDIO_SEND 0x0433 #define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK GENMASK(7, 0)34 #define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK GENMASK(15, 8)35 #define MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7 BIT(16)36 #define MESON_MX_SDIO_SEND_RESP_HAS_DATA BIT(17)37 #define MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8 BIT(18)38 #define MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY BIT(19)39 #define MESON_MX_SDIO_SEND_DATA BIT(20)40 #define MESON_MX_SDIO_SEND_USE_INT_WINDOW BIT(21)41 #define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK GENMASK(31, 24)42 43#define MESON_MX_SDIO_CONF 0x0844 #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT 045 #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH 1046 #define MESON_MX_SDIO_CONF_CMD_DISABLE_CRC BIT(10)47 #define MESON_MX_SDIO_CONF_CMD_OUT_AT_POSITIVE_EDGE BIT(11)48 #define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK GENMASK(17, 12)49 #define MESON_MX_SDIO_CONF_RESP_LATCH_AT_NEGATIVE_EDGE BIT(18)50 #define MESON_MX_SDIO_CONF_DATA_LATCH_AT_NEGATIVE_EDGE BIT(19)51 #define MESON_MX_SDIO_CONF_BUS_WIDTH BIT(20)52 #define MESON_MX_SDIO_CONF_M_ENDIAN_MASK GENMASK(22, 21)53 #define MESON_MX_SDIO_CONF_WRITE_NWR_MASK GENMASK(28, 23)54 #define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK GENMASK(31, 29)55 56#define MESON_MX_SDIO_IRQS 0x0c57 #define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK GENMASK(3, 0)58 #define MESON_MX_SDIO_IRQS_CMD_BUSY BIT(4)59 #define MESON_MX_SDIO_IRQS_RESP_CRC7_OK BIT(5)60 #define MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK BIT(6)61 #define MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK BIT(7)62 #define MESON_MX_SDIO_IRQS_IF_INT BIT(8)63 #define MESON_MX_SDIO_IRQS_CMD_INT BIT(9)64 #define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK GENMASK(15, 12)65 #define MESON_MX_SDIO_IRQS_TIMING_OUT_INT BIT(16)66 #define MESON_MX_SDIO_IRQS_AMRISC_TIMING_OUT_INT_EN BIT(17)67 #define MESON_MX_SDIO_IRQS_ARC_TIMING_OUT_INT_EN BIT(18)68 #define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK GENMASK(31, 19)69 70#define MESON_MX_SDIO_IRQC 0x1071 #define MESON_MX_SDIO_IRQC_ARC_IF_INT_EN BIT(3)72 #define MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN BIT(4)73 #define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK GENMASK(7, 6)74 #define MESON_MX_SDIO_IRQC_FORCE_DATA_CLK BIT(8)75 #define MESON_MX_SDIO_IRQC_FORCE_DATA_CMD BIT(9)76 #define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK GENMASK(13, 10)77 #define MESON_MX_SDIO_IRQC_SOFT_RESET BIT(15)78 #define MESON_MX_SDIO_IRQC_FORCE_HALT BIT(30)79 #define MESON_MX_SDIO_IRQC_HALT_HOLE BIT(31)80 81#define MESON_MX_SDIO_MULT 0x1482 #define MESON_MX_SDIO_MULT_PORT_SEL_MASK GENMASK(1, 0)83 #define MESON_MX_SDIO_MULT_MEMORY_STICK_ENABLE BIT(2)84 #define MESON_MX_SDIO_MULT_MEMORY_STICK_SCLK_ALWAYS BIT(3)85 #define MESON_MX_SDIO_MULT_STREAM_ENABLE BIT(4)86 #define MESON_MX_SDIO_MULT_STREAM_8BITS_MODE BIT(5)87 #define MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX BIT(8)88 #define MESON_MX_SDIO_MULT_DAT0_DAT1_SWAPPED BIT(10)89 #define MESON_MX_SDIO_MULT_DAT1_DAT0_SWAPPED BIT(11)90 #define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK GENMASK(15, 12)91 92#define MESON_MX_SDIO_ADDR 0x1893 94#define MESON_MX_SDIO_EXT 0x1c95 #define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK GENMASK(29, 16)96 97#define MESON_MX_SDIO_BOUNCE_REQ_SIZE (128 * 1024)98#define MESON_MX_SDIO_RESPONSE_CRC16_BITS (16 - 1)99#define MESON_MX_SDIO_MAX_SLOTS 3100 101struct meson_mx_mmc_host {102 struct device *controller_dev;103 104 struct clk *parent_clk;105 struct clk *core_clk;106 struct clk_divider cfg_div;107 struct clk *cfg_div_clk;108 struct clk_fixed_factor fixed_factor;109 struct clk *fixed_factor_clk;110 111 void __iomem *base;112 int irq;113 spinlock_t irq_lock;114 115 struct timer_list cmd_timeout;116 117 unsigned int slot_id;118 struct mmc_host *mmc;119 120 struct mmc_request *mrq;121 struct mmc_command *cmd;122 int error;123};124 125static void meson_mx_mmc_mask_bits(struct mmc_host *mmc, char reg, u32 mask,126 u32 val)127{128 struct meson_mx_mmc_host *host = mmc_priv(mmc);129 u32 regval;130 131 regval = readl(host->base + reg);132 regval &= ~mask;133 regval |= (val & mask);134 135 writel(regval, host->base + reg);136}137 138static void meson_mx_mmc_soft_reset(struct meson_mx_mmc_host *host)139{140 writel(MESON_MX_SDIO_IRQC_SOFT_RESET, host->base + MESON_MX_SDIO_IRQC);141 udelay(2);142}143 144static struct mmc_command *meson_mx_mmc_get_next_cmd(struct mmc_command *cmd)145{146 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)147 return cmd->mrq->cmd;148 else if (mmc_op_multi(cmd->opcode) &&149 (!cmd->mrq->sbc || cmd->error || cmd->data->error))150 return cmd->mrq->stop;151 else152 return NULL;153}154 155static void meson_mx_mmc_start_cmd(struct mmc_host *mmc,156 struct mmc_command *cmd)157{158 struct meson_mx_mmc_host *host = mmc_priv(mmc);159 unsigned int pack_size;160 unsigned long irqflags, timeout;161 u32 mult, send = 0, ext = 0;162 163 host->cmd = cmd;164 165 if (cmd->busy_timeout)166 timeout = msecs_to_jiffies(cmd->busy_timeout);167 else168 timeout = msecs_to_jiffies(1000);169 170 switch (mmc_resp_type(cmd)) {171 case MMC_RSP_R1:172 case MMC_RSP_R1B:173 case MMC_RSP_R3:174 /* 7 (CMD) + 32 (response) + 7 (CRC) -1 */175 send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 45);176 break;177 case MMC_RSP_R2:178 /* 7 (CMD) + 120 (response) + 7 (CRC) -1 */179 send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 133);180 send |= MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8;181 break;182 default:183 break;184 }185 186 if (!(cmd->flags & MMC_RSP_CRC))187 send |= MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7;188 189 if (cmd->flags & MMC_RSP_BUSY)190 send |= MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY;191 192 if (cmd->data) {193 send |= FIELD_PREP(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK,194 (cmd->data->blocks - 1));195 196 pack_size = cmd->data->blksz * BITS_PER_BYTE;197 if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)198 pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 4;199 else200 pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 1;201 202 ext |= FIELD_PREP(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK,203 pack_size);204 205 if (cmd->data->flags & MMC_DATA_WRITE)206 send |= MESON_MX_SDIO_SEND_DATA;207 else208 send |= MESON_MX_SDIO_SEND_RESP_HAS_DATA;209 210 cmd->data->bytes_xfered = 0;211 }212 213 send |= FIELD_PREP(MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK,214 (0x40 | cmd->opcode));215 216 spin_lock_irqsave(&host->irq_lock, irqflags);217 218 mult = readl(host->base + MESON_MX_SDIO_MULT);219 mult &= ~MESON_MX_SDIO_MULT_PORT_SEL_MASK;220 mult |= FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK, host->slot_id);221 mult |= BIT(31);222 writel(mult, host->base + MESON_MX_SDIO_MULT);223 224 /* enable the CMD done interrupt */225 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQC,226 MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN,227 MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN);228 229 /* clear pending interrupts */230 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQS,231 MESON_MX_SDIO_IRQS_CMD_INT,232 MESON_MX_SDIO_IRQS_CMD_INT);233 234 writel(cmd->arg, host->base + MESON_MX_SDIO_ARGU);235 writel(ext, host->base + MESON_MX_SDIO_EXT);236 writel(send, host->base + MESON_MX_SDIO_SEND);237 238 spin_unlock_irqrestore(&host->irq_lock, irqflags);239 240 mod_timer(&host->cmd_timeout, jiffies + timeout);241}242 243static void meson_mx_mmc_request_done(struct meson_mx_mmc_host *host)244{245 struct mmc_request *mrq;246 247 mrq = host->mrq;248 249 if (host->cmd->error)250 meson_mx_mmc_soft_reset(host);251 252 host->mrq = NULL;253 host->cmd = NULL;254 255 mmc_request_done(host->mmc, mrq);256}257 258static void meson_mx_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)259{260 struct meson_mx_mmc_host *host = mmc_priv(mmc);261 unsigned short vdd = ios->vdd;262 unsigned long clk_rate = ios->clock;263 264 switch (ios->bus_width) {265 case MMC_BUS_WIDTH_1:266 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF,267 MESON_MX_SDIO_CONF_BUS_WIDTH, 0);268 break;269 270 case MMC_BUS_WIDTH_4:271 meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF,272 MESON_MX_SDIO_CONF_BUS_WIDTH,273 MESON_MX_SDIO_CONF_BUS_WIDTH);274 break;275 276 case MMC_BUS_WIDTH_8:277 default:278 dev_err(mmc_dev(mmc), "unsupported bus width: %d\n",279 ios->bus_width);280 host->error = -EINVAL;281 return;282 }283 284 host->error = clk_set_rate(host->cfg_div_clk, ios->clock);285 if (host->error) {286 dev_warn(mmc_dev(mmc),287 "failed to set MMC clock to %lu: %d\n",288 clk_rate, host->error);289 return;290 }291 292 mmc->actual_clock = clk_get_rate(host->cfg_div_clk);293 294 switch (ios->power_mode) {295 case MMC_POWER_OFF:296 vdd = 0;297 fallthrough;298 case MMC_POWER_UP:299 if (!IS_ERR(mmc->supply.vmmc)) {300 host->error = mmc_regulator_set_ocr(mmc,301 mmc->supply.vmmc,302 vdd);303 if (host->error)304 return;305 }306 break;307 }308}309 310static int meson_mx_mmc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq)311{312 struct mmc_data *data = mrq->data;313 int dma_len;314 struct scatterlist *sg;315 316 if (!data)317 return 0;318 319 sg = data->sg;320 if (sg->offset & 3 || sg->length & 3) {321 dev_err(mmc_dev(mmc),322 "unaligned scatterlist: offset %x length %d\n",323 sg->offset, sg->length);324 return -EINVAL;325 }326 327 dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,328 mmc_get_dma_dir(data));329 if (dma_len <= 0) {330 dev_err(mmc_dev(mmc), "dma_map_sg failed\n");331 return -ENOMEM;332 }333 334 return 0;335}336 337static void meson_mx_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)338{339 struct meson_mx_mmc_host *host = mmc_priv(mmc);340 struct mmc_command *cmd = mrq->cmd;341 342 if (!host->error)343 host->error = meson_mx_mmc_map_dma(mmc, mrq);344 345 if (host->error) {346 cmd->error = host->error;347 mmc_request_done(mmc, mrq);348 return;349 }350 351 host->mrq = mrq;352 353 if (mrq->data)354 writel(sg_dma_address(mrq->data->sg),355 host->base + MESON_MX_SDIO_ADDR);356 357 if (mrq->sbc)358 meson_mx_mmc_start_cmd(mmc, mrq->sbc);359 else360 meson_mx_mmc_start_cmd(mmc, mrq->cmd);361}362 363static void meson_mx_mmc_read_response(struct mmc_host *mmc,364 struct mmc_command *cmd)365{366 struct meson_mx_mmc_host *host = mmc_priv(mmc);367 u32 mult;368 int i, resp[4];369 370 mult = readl(host->base + MESON_MX_SDIO_MULT);371 mult |= MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX;372 mult &= ~MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK;373 mult |= FIELD_PREP(MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK, 0);374 writel(mult, host->base + MESON_MX_SDIO_MULT);375 376 if (cmd->flags & MMC_RSP_136) {377 for (i = 0; i <= 3; i++)378 resp[3 - i] = readl(host->base + MESON_MX_SDIO_ARGU);379 cmd->resp[0] = (resp[0] << 8) | ((resp[1] >> 24) & 0xff);380 cmd->resp[1] = (resp[1] << 8) | ((resp[2] >> 24) & 0xff);381 cmd->resp[2] = (resp[2] << 8) | ((resp[3] >> 24) & 0xff);382 cmd->resp[3] = (resp[3] << 8);383 } else if (cmd->flags & MMC_RSP_PRESENT) {384 cmd->resp[0] = readl(host->base + MESON_MX_SDIO_ARGU);385 }386}387 388static irqreturn_t meson_mx_mmc_process_cmd_irq(struct meson_mx_mmc_host *host,389 u32 irqs, u32 send)390{391 struct mmc_command *cmd = host->cmd;392 393 /*394 * NOTE: even though it shouldn't happen we sometimes get command395 * interrupts twice (at least this is what it looks like). Ideally396 * we find out why this happens and warn here as soon as it occurs.397 */398 if (!cmd)399 return IRQ_HANDLED;400 401 cmd->error = 0;402 meson_mx_mmc_read_response(host->mmc, cmd);403 404 if (cmd->data) {405 if (!((irqs & MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK) ||406 (irqs & MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK)))407 cmd->error = -EILSEQ;408 } else {409 if (!((irqs & MESON_MX_SDIO_IRQS_RESP_CRC7_OK) ||410 (send & MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7)))411 cmd->error = -EILSEQ;412 }413 414 return IRQ_WAKE_THREAD;415}416 417static irqreturn_t meson_mx_mmc_irq(int irq, void *data)418{419 struct meson_mx_mmc_host *host = (void *) data;420 u32 irqs, send;421 irqreturn_t ret;422 423 spin_lock(&host->irq_lock);424 425 irqs = readl(host->base + MESON_MX_SDIO_IRQS);426 send = readl(host->base + MESON_MX_SDIO_SEND);427 428 if (irqs & MESON_MX_SDIO_IRQS_CMD_INT)429 ret = meson_mx_mmc_process_cmd_irq(host, irqs, send);430 else431 ret = IRQ_HANDLED;432 433 /* finally ACK all pending interrupts */434 writel(irqs, host->base + MESON_MX_SDIO_IRQS);435 436 spin_unlock(&host->irq_lock);437 438 return ret;439}440 441static irqreturn_t meson_mx_mmc_irq_thread(int irq, void *irq_data)442{443 struct meson_mx_mmc_host *host = (void *) irq_data;444 struct mmc_command *cmd = host->cmd, *next_cmd;445 446 if (WARN_ON(!cmd))447 return IRQ_HANDLED;448 449 del_timer_sync(&host->cmd_timeout);450 451 if (cmd->data) {452 dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg,453 cmd->data->sg_len,454 mmc_get_dma_dir(cmd->data));455 456 cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks;457 }458 459 next_cmd = meson_mx_mmc_get_next_cmd(cmd);460 if (next_cmd)461 meson_mx_mmc_start_cmd(host->mmc, next_cmd);462 else463 meson_mx_mmc_request_done(host);464 465 return IRQ_HANDLED;466}467 468static void meson_mx_mmc_timeout(struct timer_list *t)469{470 struct meson_mx_mmc_host *host = from_timer(host, t, cmd_timeout);471 unsigned long irqflags;472 u32 irqc;473 474 spin_lock_irqsave(&host->irq_lock, irqflags);475 476 /* disable the CMD interrupt */477 irqc = readl(host->base + MESON_MX_SDIO_IRQC);478 irqc &= ~MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN;479 writel(irqc, host->base + MESON_MX_SDIO_IRQC);480 481 spin_unlock_irqrestore(&host->irq_lock, irqflags);482 483 /*484 * skip the timeout handling if the interrupt handler already processed485 * the command.486 */487 if (!host->cmd)488 return;489 490 dev_dbg(mmc_dev(host->mmc),491 "Timeout on CMD%u (IRQS = 0x%08x, ARGU = 0x%08x)\n",492 host->cmd->opcode, readl(host->base + MESON_MX_SDIO_IRQS),493 readl(host->base + MESON_MX_SDIO_ARGU));494 495 host->cmd->error = -ETIMEDOUT;496 497 meson_mx_mmc_request_done(host);498}499 500static struct mmc_host_ops meson_mx_mmc_ops = {501 .request = meson_mx_mmc_request,502 .set_ios = meson_mx_mmc_set_ios,503 .get_cd = mmc_gpio_get_cd,504 .get_ro = mmc_gpio_get_ro,505};506 507static struct platform_device *meson_mx_mmc_slot_pdev(struct device *parent)508{509 struct device_node *slot_node;510 struct platform_device *pdev;511 512 /*513 * TODO: the MMC core framework currently does not support514 * controllers with multiple slots properly. So we only register515 * the first slot for now516 */517 slot_node = of_get_compatible_child(parent->of_node, "mmc-slot");518 if (!slot_node) {519 dev_warn(parent, "no 'mmc-slot' sub-node found\n");520 return ERR_PTR(-ENOENT);521 }522 523 pdev = of_platform_device_create(slot_node, NULL, parent);524 of_node_put(slot_node);525 526 return pdev;527}528 529static int meson_mx_mmc_add_host(struct meson_mx_mmc_host *host)530{531 struct mmc_host *mmc = host->mmc;532 struct device *slot_dev = mmc_dev(mmc);533 int ret;534 535 if (of_property_read_u32(slot_dev->of_node, "reg", &host->slot_id)) {536 dev_err(slot_dev, "missing 'reg' property\n");537 return -EINVAL;538 }539 540 if (host->slot_id >= MESON_MX_SDIO_MAX_SLOTS) {541 dev_err(slot_dev, "invalid 'reg' property value %d\n",542 host->slot_id);543 return -EINVAL;544 }545 546 /* Get regulators and the supported OCR mask */547 ret = mmc_regulator_get_supply(mmc);548 if (ret)549 return ret;550 551 mmc->max_req_size = MESON_MX_SDIO_BOUNCE_REQ_SIZE;552 mmc->max_seg_size = mmc->max_req_size;553 mmc->max_blk_count =554 FIELD_GET(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK,555 0xffffffff);556 mmc->max_blk_size = FIELD_GET(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK,557 0xffffffff);558 mmc->max_blk_size -= (4 * MESON_MX_SDIO_RESPONSE_CRC16_BITS);559 mmc->max_blk_size /= BITS_PER_BYTE;560 561 /* Get the min and max supported clock rates */562 mmc->f_min = clk_round_rate(host->cfg_div_clk, 1);563 mmc->f_max = clk_round_rate(host->cfg_div_clk,564 clk_get_rate(host->parent_clk));565 566 mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY;567 mmc->ops = &meson_mx_mmc_ops;568 569 ret = mmc_of_parse(mmc);570 if (ret)571 return ret;572 573 ret = mmc_add_host(mmc);574 if (ret)575 return ret;576 577 return 0;578}579 580static int meson_mx_mmc_register_clks(struct meson_mx_mmc_host *host)581{582 struct clk_init_data init;583 const char *clk_div_parent, *clk_fixed_factor_parent;584 585 clk_fixed_factor_parent = __clk_get_name(host->parent_clk);586 init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL,587 "%s#fixed_factor",588 dev_name(host->controller_dev));589 if (!init.name)590 return -ENOMEM;591 592 init.ops = &clk_fixed_factor_ops;593 init.flags = 0;594 init.parent_names = &clk_fixed_factor_parent;595 init.num_parents = 1;596 host->fixed_factor.div = 2;597 host->fixed_factor.mult = 1;598 host->fixed_factor.hw.init = &init;599 600 host->fixed_factor_clk = devm_clk_register(host->controller_dev,601 &host->fixed_factor.hw);602 if (WARN_ON(IS_ERR(host->fixed_factor_clk)))603 return PTR_ERR(host->fixed_factor_clk);604 605 clk_div_parent = __clk_get_name(host->fixed_factor_clk);606 init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL,607 "%s#div", dev_name(host->controller_dev));608 if (!init.name)609 return -ENOMEM;610 611 init.ops = &clk_divider_ops;612 init.flags = CLK_SET_RATE_PARENT;613 init.parent_names = &clk_div_parent;614 init.num_parents = 1;615 host->cfg_div.reg = host->base + MESON_MX_SDIO_CONF;616 host->cfg_div.shift = MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT;617 host->cfg_div.width = MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH;618 host->cfg_div.hw.init = &init;619 host->cfg_div.flags = CLK_DIVIDER_ALLOW_ZERO;620 621 host->cfg_div_clk = devm_clk_register(host->controller_dev,622 &host->cfg_div.hw);623 if (WARN_ON(IS_ERR(host->cfg_div_clk)))624 return PTR_ERR(host->cfg_div_clk);625 626 return 0;627}628 629static int meson_mx_mmc_probe(struct platform_device *pdev)630{631 struct platform_device *slot_pdev;632 struct mmc_host *mmc;633 struct meson_mx_mmc_host *host;634 int ret, irq;635 u32 conf;636 637 slot_pdev = meson_mx_mmc_slot_pdev(&pdev->dev);638 if (!slot_pdev)639 return -ENODEV;640 else if (IS_ERR(slot_pdev))641 return PTR_ERR(slot_pdev);642 643 mmc = mmc_alloc_host(sizeof(*host), &slot_pdev->dev);644 if (!mmc) {645 ret = -ENOMEM;646 goto error_unregister_slot_pdev;647 }648 649 host = mmc_priv(mmc);650 host->mmc = mmc;651 host->controller_dev = &pdev->dev;652 653 spin_lock_init(&host->irq_lock);654 timer_setup(&host->cmd_timeout, meson_mx_mmc_timeout, 0);655 656 platform_set_drvdata(pdev, host);657 658 host->base = devm_platform_ioremap_resource(pdev, 0);659 if (IS_ERR(host->base)) {660 ret = PTR_ERR(host->base);661 goto error_free_mmc;662 }663 664 irq = platform_get_irq(pdev, 0);665 if (irq < 0) {666 ret = irq;667 goto error_free_mmc;668 }669 670 ret = devm_request_threaded_irq(host->controller_dev, irq,671 meson_mx_mmc_irq,672 meson_mx_mmc_irq_thread, IRQF_ONESHOT,673 NULL, host);674 if (ret)675 goto error_free_mmc;676 677 host->core_clk = devm_clk_get(host->controller_dev, "core");678 if (IS_ERR(host->core_clk)) {679 ret = PTR_ERR(host->core_clk);680 goto error_free_mmc;681 }682 683 host->parent_clk = devm_clk_get(host->controller_dev, "clkin");684 if (IS_ERR(host->parent_clk)) {685 ret = PTR_ERR(host->parent_clk);686 goto error_free_mmc;687 }688 689 ret = meson_mx_mmc_register_clks(host);690 if (ret)691 goto error_free_mmc;692 693 ret = clk_prepare_enable(host->core_clk);694 if (ret) {695 dev_err(host->controller_dev, "Failed to enable core clock\n");696 goto error_free_mmc;697 }698 699 ret = clk_prepare_enable(host->cfg_div_clk);700 if (ret) {701 dev_err(host->controller_dev, "Failed to enable MMC clock\n");702 goto error_disable_core_clk;703 }704 705 conf = 0;706 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK, 39);707 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_M_ENDIAN_MASK, 0x3);708 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_NWR_MASK, 0x2);709 conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK, 0x2);710 writel(conf, host->base + MESON_MX_SDIO_CONF);711 712 meson_mx_mmc_soft_reset(host);713 714 ret = meson_mx_mmc_add_host(host);715 if (ret)716 goto error_disable_clks;717 718 return 0;719 720error_disable_clks:721 clk_disable_unprepare(host->cfg_div_clk);722error_disable_core_clk:723 clk_disable_unprepare(host->core_clk);724error_free_mmc:725 mmc_free_host(mmc);726error_unregister_slot_pdev:727 of_platform_device_destroy(&slot_pdev->dev, NULL);728 return ret;729}730 731static void meson_mx_mmc_remove(struct platform_device *pdev)732{733 struct meson_mx_mmc_host *host = platform_get_drvdata(pdev);734 struct device *slot_dev = mmc_dev(host->mmc);735 736 del_timer_sync(&host->cmd_timeout);737 738 mmc_remove_host(host->mmc);739 740 of_platform_device_destroy(slot_dev, NULL);741 742 clk_disable_unprepare(host->cfg_div_clk);743 clk_disable_unprepare(host->core_clk);744 745 mmc_free_host(host->mmc);746}747 748static const struct of_device_id meson_mx_mmc_of_match[] = {749 { .compatible = "amlogic,meson8-sdio", },750 { .compatible = "amlogic,meson8b-sdio", },751 { /* sentinel */ }752};753MODULE_DEVICE_TABLE(of, meson_mx_mmc_of_match);754 755static struct platform_driver meson_mx_mmc_driver = {756 .probe = meson_mx_mmc_probe,757 .remove_new = meson_mx_mmc_remove,758 .driver = {759 .name = "meson-mx-sdio",760 .probe_type = PROBE_PREFER_ASYNCHRONOUS,761 .of_match_table = of_match_ptr(meson_mx_mmc_of_match),762 },763};764 765module_platform_driver(meson_mx_mmc_driver);766 767MODULE_DESCRIPTION("Meson6, Meson8 and Meson8b SDIO/MMC Host Driver");768MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");769MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");770MODULE_LICENSE("GPL v2");771