735 lines · c
1/*2 * MOXA ART MMC host driver.3 *4 * Copyright (C) 2014 Jonas Jensen5 *6 * Jonas Jensen <jonas.jensen@gmail.com>7 *8 * Based on code from9 * Moxa Technologies Co., Ltd. <www.moxa.com>10 *11 * This file is licensed under the terms of the GNU General Public12 * License version 2. This program is licensed "as is" without any13 * warranty of any kind, whether express or implied.14 */15 16#include <linux/module.h>17#include <linux/init.h>18#include <linux/platform_device.h>19#include <linux/delay.h>20#include <linux/errno.h>21#include <linux/interrupt.h>22#include <linux/blkdev.h>23#include <linux/dma-mapping.h>24#include <linux/dmaengine.h>25#include <linux/mmc/host.h>26#include <linux/mmc/sd.h>27#include <linux/sched.h>28#include <linux/io.h>29#include <linux/of_address.h>30#include <linux/of_irq.h>31#include <linux/clk.h>32#include <linux/bitops.h>33#include <linux/of_dma.h>34#include <linux/spinlock.h>35 36#define REG_COMMAND 037#define REG_ARGUMENT 438#define REG_RESPONSE0 839#define REG_RESPONSE1 1240#define REG_RESPONSE2 1641#define REG_RESPONSE3 2042#define REG_RESPONSE_COMMAND 2443#define REG_DATA_CONTROL 2844#define REG_DATA_TIMER 3245#define REG_DATA_LENGTH 3646#define REG_STATUS 4047#define REG_CLEAR 4448#define REG_INTERRUPT_MASK 4849#define REG_POWER_CONTROL 5250#define REG_CLOCK_CONTROL 5651#define REG_BUS_WIDTH 6052#define REG_DATA_WINDOW 6453#define REG_FEATURE 6854#define REG_REVISION 7255 56/* REG_COMMAND */57#define CMD_SDC_RESET BIT(10)58#define CMD_EN BIT(9)59#define CMD_APP_CMD BIT(8)60#define CMD_LONG_RSP BIT(7)61#define CMD_NEED_RSP BIT(6)62#define CMD_IDX_MASK 0x3f63 64/* REG_RESPONSE_COMMAND */65#define RSP_CMD_APP BIT(6)66#define RSP_CMD_IDX_MASK 0x3f67 68/* REG_DATA_CONTROL */69#define DCR_DATA_FIFO_RESET BIT(8)70#define DCR_DATA_THRES BIT(7)71#define DCR_DATA_EN BIT(6)72#define DCR_DMA_EN BIT(5)73#define DCR_DATA_WRITE BIT(4)74#define DCR_BLK_SIZE 0x0f75 76/* REG_DATA_LENGTH */77#define DATA_LEN_MASK 0xffffff78 79/* REG_STATUS */80#define WRITE_PROT BIT(12)81#define CARD_DETECT BIT(11)82/* 1-10 below can be sent to either registers, interrupt or clear. */83#define CARD_CHANGE BIT(10)84#define FIFO_ORUN BIT(9)85#define FIFO_URUN BIT(8)86#define DATA_END BIT(7)87#define CMD_SENT BIT(6)88#define DATA_CRC_OK BIT(5)89#define RSP_CRC_OK BIT(4)90#define DATA_TIMEOUT BIT(3)91#define RSP_TIMEOUT BIT(2)92#define DATA_CRC_FAIL BIT(1)93#define RSP_CRC_FAIL BIT(0)94 95#define MASK_RSP (RSP_TIMEOUT | RSP_CRC_FAIL | \96 RSP_CRC_OK | CARD_DETECT | CMD_SENT)97 98#define MASK_DATA (DATA_CRC_OK | DATA_END | \99 DATA_CRC_FAIL | DATA_TIMEOUT)100 101#define MASK_INTR_PIO (FIFO_URUN | FIFO_ORUN | CARD_CHANGE)102 103/* REG_POWER_CONTROL */104#define SD_POWER_ON BIT(4)105#define SD_POWER_MASK 0x0f106 107/* REG_CLOCK_CONTROL */108#define CLK_HISPD BIT(9)109#define CLK_OFF BIT(8)110#define CLK_SD BIT(7)111#define CLK_DIV_MASK 0x7f112 113/* REG_BUS_WIDTH */114#define BUS_WIDTH_4_SUPPORT BIT(3)115#define BUS_WIDTH_4 BIT(2)116#define BUS_WIDTH_1 BIT(0)117 118#define MMC_VDD_360 23119#define MIN_POWER (MMC_VDD_360 - SD_POWER_MASK)120#define MAX_RETRIES 500000121 122struct moxart_host {123 spinlock_t lock;124 125 void __iomem *base;126 127 phys_addr_t reg_phys;128 129 struct dma_chan *dma_chan_tx;130 struct dma_chan *dma_chan_rx;131 struct dma_async_tx_descriptor *tx_desc;132 struct mmc_host *mmc;133 struct mmc_request *mrq;134 struct scatterlist *cur_sg;135 struct completion dma_complete;136 struct completion pio_complete;137 138 u32 num_sg;139 u32 data_remain;140 u32 data_len;141 u32 fifo_width;142 u32 timeout;143 u32 rate;144 145 long sysclk;146 147 bool have_dma;148 bool is_removed;149};150 151static inline void moxart_init_sg(struct moxart_host *host,152 struct mmc_data *data)153{154 host->cur_sg = data->sg;155 host->num_sg = data->sg_len;156 host->data_remain = host->cur_sg->length;157 158 if (host->data_remain > host->data_len)159 host->data_remain = host->data_len;160}161 162static inline int moxart_next_sg(struct moxart_host *host)163{164 int remain;165 struct mmc_data *data = host->mrq->cmd->data;166 167 host->cur_sg++;168 host->num_sg--;169 170 if (host->num_sg > 0) {171 host->data_remain = host->cur_sg->length;172 remain = host->data_len - data->bytes_xfered;173 if (remain > 0 && remain < host->data_remain)174 host->data_remain = remain;175 }176 177 return host->num_sg;178}179 180static int moxart_wait_for_status(struct moxart_host *host,181 u32 mask, u32 *status)182{183 int ret = -ETIMEDOUT;184 u32 i;185 186 for (i = 0; i < MAX_RETRIES; i++) {187 *status = readl(host->base + REG_STATUS);188 if (!(*status & mask)) {189 udelay(5);190 continue;191 }192 writel(*status & mask, host->base + REG_CLEAR);193 ret = 0;194 break;195 }196 197 if (ret)198 dev_err(mmc_dev(host->mmc), "timed out waiting for status\n");199 200 return ret;201}202 203 204static void moxart_send_command(struct moxart_host *host,205 struct mmc_command *cmd)206{207 u32 status, cmdctrl;208 209 writel(RSP_TIMEOUT | RSP_CRC_OK |210 RSP_CRC_FAIL | CMD_SENT, host->base + REG_CLEAR);211 writel(cmd->arg, host->base + REG_ARGUMENT);212 213 cmdctrl = cmd->opcode & CMD_IDX_MASK;214 if (cmdctrl == SD_APP_SET_BUS_WIDTH || cmdctrl == SD_APP_OP_COND ||215 cmdctrl == SD_APP_SEND_SCR || cmdctrl == SD_APP_SD_STATUS ||216 cmdctrl == SD_APP_SEND_NUM_WR_BLKS)217 cmdctrl |= CMD_APP_CMD;218 219 if (cmd->flags & MMC_RSP_PRESENT)220 cmdctrl |= CMD_NEED_RSP;221 222 if (cmd->flags & MMC_RSP_136)223 cmdctrl |= CMD_LONG_RSP;224 225 writel(cmdctrl | CMD_EN, host->base + REG_COMMAND);226 227 if (moxart_wait_for_status(host, MASK_RSP, &status) == -ETIMEDOUT)228 cmd->error = -ETIMEDOUT;229 230 if (status & RSP_TIMEOUT) {231 cmd->error = -ETIMEDOUT;232 return;233 }234 if (status & RSP_CRC_FAIL) {235 cmd->error = -EIO;236 return;237 }238 if (status & RSP_CRC_OK) {239 if (cmd->flags & MMC_RSP_136) {240 cmd->resp[3] = readl(host->base + REG_RESPONSE0);241 cmd->resp[2] = readl(host->base + REG_RESPONSE1);242 cmd->resp[1] = readl(host->base + REG_RESPONSE2);243 cmd->resp[0] = readl(host->base + REG_RESPONSE3);244 } else {245 cmd->resp[0] = readl(host->base + REG_RESPONSE0);246 }247 }248}249 250static void moxart_dma_complete(void *param)251{252 struct moxart_host *host = param;253 254 complete(&host->dma_complete);255}256 257static bool moxart_use_dma(struct moxart_host *host)258{259 return (host->data_len > host->fifo_width) && host->have_dma;260}261 262static void moxart_transfer_dma(struct mmc_data *data, struct moxart_host *host)263{264 u32 len, dir_slave;265 struct dma_async_tx_descriptor *desc = NULL;266 struct dma_chan *dma_chan;267 268 if (host->data_len == data->bytes_xfered)269 return;270 271 if (data->flags & MMC_DATA_WRITE) {272 dma_chan = host->dma_chan_tx;273 dir_slave = DMA_MEM_TO_DEV;274 } else {275 dma_chan = host->dma_chan_rx;276 dir_slave = DMA_DEV_TO_MEM;277 }278 279 len = dma_map_sg(dma_chan->device->dev, data->sg,280 data->sg_len, mmc_get_dma_dir(data));281 282 if (len > 0) {283 desc = dmaengine_prep_slave_sg(dma_chan, data->sg,284 len, dir_slave,285 DMA_PREP_INTERRUPT |286 DMA_CTRL_ACK);287 } else {288 dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");289 }290 291 if (desc) {292 host->tx_desc = desc;293 desc->callback = moxart_dma_complete;294 desc->callback_param = host;295 dmaengine_submit(desc);296 dma_async_issue_pending(dma_chan);297 }298 299 wait_for_completion_interruptible_timeout(&host->dma_complete,300 host->timeout);301 302 data->bytes_xfered = host->data_len;303 304 dma_unmap_sg(dma_chan->device->dev,305 data->sg, data->sg_len,306 mmc_get_dma_dir(data));307}308 309 310static void moxart_transfer_pio(struct moxart_host *host)311{312 struct mmc_data *data = host->mrq->cmd->data;313 u32 *sgp, len = 0, remain, status;314 315 if (host->data_len == data->bytes_xfered)316 return;317 318 sgp = sg_virt(host->cur_sg);319 remain = host->data_remain;320 321 if (data->flags & MMC_DATA_WRITE) {322 while (remain > 0) {323 if (moxart_wait_for_status(host, FIFO_URUN, &status)324 == -ETIMEDOUT) {325 data->error = -ETIMEDOUT;326 complete(&host->pio_complete);327 return;328 }329 for (len = 0; len < remain && len < host->fifo_width;) {330 iowrite32(*sgp, host->base + REG_DATA_WINDOW);331 sgp++;332 len += 4;333 }334 remain -= len;335 }336 337 } else {338 while (remain > 0) {339 if (moxart_wait_for_status(host, FIFO_ORUN, &status)340 == -ETIMEDOUT) {341 data->error = -ETIMEDOUT;342 complete(&host->pio_complete);343 return;344 }345 for (len = 0; len < remain && len < host->fifo_width;) {346 *sgp = ioread32(host->base + REG_DATA_WINDOW);347 sgp++;348 len += 4;349 }350 remain -= len;351 }352 }353 354 data->bytes_xfered += host->data_remain - remain;355 host->data_remain = remain;356 357 if (host->data_len != data->bytes_xfered)358 moxart_next_sg(host);359 else360 complete(&host->pio_complete);361}362 363static void moxart_prepare_data(struct moxart_host *host)364{365 struct mmc_data *data = host->mrq->cmd->data;366 u32 datactrl;367 int blksz_bits;368 369 if (!data)370 return;371 372 host->data_len = data->blocks * data->blksz;373 blksz_bits = ffs(data->blksz) - 1;374 BUG_ON(1 << blksz_bits != data->blksz);375 376 moxart_init_sg(host, data);377 378 datactrl = DCR_DATA_EN | (blksz_bits & DCR_BLK_SIZE);379 380 if (data->flags & MMC_DATA_WRITE)381 datactrl |= DCR_DATA_WRITE;382 383 if (moxart_use_dma(host))384 datactrl |= DCR_DMA_EN;385 386 writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL);387 writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR);388 writel(host->rate, host->base + REG_DATA_TIMER);389 writel(host->data_len, host->base + REG_DATA_LENGTH);390 writel(datactrl, host->base + REG_DATA_CONTROL);391}392 393static void moxart_request(struct mmc_host *mmc, struct mmc_request *mrq)394{395 struct moxart_host *host = mmc_priv(mmc);396 unsigned long flags;397 u32 status;398 399 spin_lock_irqsave(&host->lock, flags);400 401 init_completion(&host->dma_complete);402 init_completion(&host->pio_complete);403 404 host->mrq = mrq;405 406 if (readl(host->base + REG_STATUS) & CARD_DETECT) {407 mrq->cmd->error = -ETIMEDOUT;408 goto request_done;409 }410 411 moxart_prepare_data(host);412 moxart_send_command(host, host->mrq->cmd);413 414 if (mrq->cmd->data) {415 if (moxart_use_dma(host)) {416 417 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);418 419 spin_unlock_irqrestore(&host->lock, flags);420 421 moxart_transfer_dma(mrq->cmd->data, host);422 423 spin_lock_irqsave(&host->lock, flags);424 } else {425 426 writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK);427 428 spin_unlock_irqrestore(&host->lock, flags);429 430 /* PIO transfers start from interrupt. */431 wait_for_completion_interruptible_timeout(&host->pio_complete,432 host->timeout);433 434 spin_lock_irqsave(&host->lock, flags);435 }436 437 if (host->is_removed) {438 dev_err(mmc_dev(host->mmc), "card removed\n");439 mrq->cmd->error = -ETIMEDOUT;440 goto request_done;441 }442 443 if (moxart_wait_for_status(host, MASK_DATA, &status)444 == -ETIMEDOUT) {445 mrq->cmd->data->error = -ETIMEDOUT;446 goto request_done;447 }448 449 if (status & DATA_CRC_FAIL)450 mrq->cmd->data->error = -ETIMEDOUT;451 452 if (mrq->cmd->data->stop)453 moxart_send_command(host, mrq->cmd->data->stop);454 }455 456request_done:457 spin_unlock_irqrestore(&host->lock, flags);458 mmc_request_done(host->mmc, mrq);459}460 461static irqreturn_t moxart_irq(int irq, void *devid)462{463 struct moxart_host *host = (struct moxart_host *)devid;464 u32 status;465 466 spin_lock(&host->lock);467 468 status = readl(host->base + REG_STATUS);469 if (status & CARD_CHANGE) {470 host->is_removed = status & CARD_DETECT;471 if (host->is_removed && host->have_dma) {472 dmaengine_terminate_all(host->dma_chan_tx);473 dmaengine_terminate_all(host->dma_chan_rx);474 }475 host->mrq = NULL;476 writel(MASK_INTR_PIO, host->base + REG_CLEAR);477 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);478 mmc_detect_change(host->mmc, 0);479 }480 if (status & (FIFO_ORUN | FIFO_URUN) && host->mrq)481 moxart_transfer_pio(host);482 483 spin_unlock(&host->lock);484 485 return IRQ_HANDLED;486}487 488static void moxart_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)489{490 struct moxart_host *host = mmc_priv(mmc);491 unsigned long flags;492 u8 power, div;493 u32 ctrl;494 495 spin_lock_irqsave(&host->lock, flags);496 497 if (ios->clock) {498 for (div = 0; div < CLK_DIV_MASK; ++div) {499 if (ios->clock >= host->sysclk / (2 * (div + 1)))500 break;501 }502 ctrl = CLK_SD | div;503 host->rate = host->sysclk / (2 * (div + 1));504 if (host->rate > host->sysclk)505 ctrl |= CLK_HISPD;506 writel(ctrl, host->base + REG_CLOCK_CONTROL);507 }508 509 if (ios->power_mode == MMC_POWER_OFF) {510 writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON,511 host->base + REG_POWER_CONTROL);512 } else {513 if (ios->vdd < MIN_POWER)514 power = 0;515 else516 power = ios->vdd - MIN_POWER;517 518 writel(SD_POWER_ON | (u32) power,519 host->base + REG_POWER_CONTROL);520 }521 522 switch (ios->bus_width) {523 case MMC_BUS_WIDTH_4:524 writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH);525 break;526 default:527 writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH);528 break;529 }530 531 spin_unlock_irqrestore(&host->lock, flags);532}533 534 535static int moxart_get_ro(struct mmc_host *mmc)536{537 struct moxart_host *host = mmc_priv(mmc);538 539 return !!(readl(host->base + REG_STATUS) & WRITE_PROT);540}541 542static const struct mmc_host_ops moxart_ops = {543 .request = moxart_request,544 .set_ios = moxart_set_ios,545 .get_ro = moxart_get_ro,546};547 548static int moxart_probe(struct platform_device *pdev)549{550 struct device *dev = &pdev->dev;551 struct device_node *node = dev->of_node;552 struct resource res_mmc;553 struct mmc_host *mmc;554 struct moxart_host *host = NULL;555 struct dma_slave_config cfg;556 struct clk *clk;557 void __iomem *reg_mmc;558 int irq, ret;559 u32 i;560 561 mmc = mmc_alloc_host(sizeof(struct moxart_host), dev);562 if (!mmc) {563 dev_err(dev, "mmc_alloc_host failed\n");564 ret = -ENOMEM;565 goto out_mmc;566 }567 568 ret = of_address_to_resource(node, 0, &res_mmc);569 if (ret) {570 dev_err(dev, "of_address_to_resource failed\n");571 goto out_mmc;572 }573 574 irq = irq_of_parse_and_map(node, 0);575 if (irq <= 0) {576 dev_err(dev, "irq_of_parse_and_map failed\n");577 ret = -EINVAL;578 goto out_mmc;579 }580 581 clk = devm_clk_get(dev, NULL);582 if (IS_ERR(clk)) {583 ret = PTR_ERR(clk);584 goto out_mmc;585 }586 587 reg_mmc = devm_ioremap_resource(dev, &res_mmc);588 if (IS_ERR(reg_mmc)) {589 ret = PTR_ERR(reg_mmc);590 goto out_mmc;591 }592 593 ret = mmc_of_parse(mmc);594 if (ret)595 goto out_mmc;596 597 host = mmc_priv(mmc);598 host->mmc = mmc;599 host->base = reg_mmc;600 host->reg_phys = res_mmc.start;601 host->timeout = msecs_to_jiffies(1000);602 host->sysclk = clk_get_rate(clk);603 host->fifo_width = readl(host->base + REG_FEATURE) << 2;604 host->dma_chan_tx = dma_request_chan(dev, "tx");605 host->dma_chan_rx = dma_request_chan(dev, "rx");606 607 spin_lock_init(&host->lock);608 609 mmc->ops = &moxart_ops;610 mmc->f_max = DIV_ROUND_CLOSEST(host->sysclk, 2);611 mmc->f_min = DIV_ROUND_CLOSEST(host->sysclk, CLK_DIV_MASK * 2);612 mmc->ocr_avail = 0xffff00; /* Support 2.0v - 3.6v power. */613 mmc->max_blk_size = 2048; /* Max. block length in REG_DATA_CONTROL */614 mmc->max_req_size = DATA_LEN_MASK; /* bits 0-23 in REG_DATA_LENGTH */615 mmc->max_blk_count = mmc->max_req_size / 512;616 617 if (IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) {618 if (PTR_ERR(host->dma_chan_tx) == -EPROBE_DEFER ||619 PTR_ERR(host->dma_chan_rx) == -EPROBE_DEFER) {620 ret = -EPROBE_DEFER;621 goto out;622 }623 if (!IS_ERR(host->dma_chan_tx)) {624 dma_release_channel(host->dma_chan_tx);625 host->dma_chan_tx = NULL;626 }627 if (!IS_ERR(host->dma_chan_rx)) {628 dma_release_channel(host->dma_chan_rx);629 host->dma_chan_rx = NULL;630 }631 dev_dbg(dev, "PIO mode transfer enabled\n");632 host->have_dma = false;633 634 mmc->max_seg_size = mmc->max_req_size;635 } else {636 dev_dbg(dev, "DMA channels found (%p,%p)\n",637 host->dma_chan_tx, host->dma_chan_rx);638 host->have_dma = true;639 640 memset(&cfg, 0, sizeof(cfg));641 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;642 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;643 644 cfg.direction = DMA_MEM_TO_DEV;645 cfg.src_addr = 0;646 cfg.dst_addr = host->reg_phys + REG_DATA_WINDOW;647 dmaengine_slave_config(host->dma_chan_tx, &cfg);648 649 cfg.direction = DMA_DEV_TO_MEM;650 cfg.src_addr = host->reg_phys + REG_DATA_WINDOW;651 cfg.dst_addr = 0;652 dmaengine_slave_config(host->dma_chan_rx, &cfg);653 654 mmc->max_seg_size = min3(mmc->max_req_size,655 dma_get_max_seg_size(host->dma_chan_rx->device->dev),656 dma_get_max_seg_size(host->dma_chan_tx->device->dev));657 }658 659 if (readl(host->base + REG_BUS_WIDTH) & BUS_WIDTH_4_SUPPORT)660 mmc->caps |= MMC_CAP_4_BIT_DATA;661 662 writel(0, host->base + REG_INTERRUPT_MASK);663 664 writel(CMD_SDC_RESET, host->base + REG_COMMAND);665 for (i = 0; i < MAX_RETRIES; i++) {666 if (!(readl(host->base + REG_COMMAND) & CMD_SDC_RESET))667 break;668 udelay(5);669 }670 671 ret = devm_request_irq(dev, irq, moxart_irq, 0, "moxart-mmc", host);672 if (ret)673 goto out;674 675 dev_set_drvdata(dev, mmc);676 ret = mmc_add_host(mmc);677 if (ret)678 goto out;679 680 dev_dbg(dev, "IRQ=%d, FIFO is %d bytes\n", irq, host->fifo_width);681 682 return 0;683 684out:685 if (!IS_ERR_OR_NULL(host->dma_chan_tx))686 dma_release_channel(host->dma_chan_tx);687 if (!IS_ERR_OR_NULL(host->dma_chan_rx))688 dma_release_channel(host->dma_chan_rx);689out_mmc:690 if (mmc)691 mmc_free_host(mmc);692 return ret;693}694 695static void moxart_remove(struct platform_device *pdev)696{697 struct mmc_host *mmc = dev_get_drvdata(&pdev->dev);698 struct moxart_host *host = mmc_priv(mmc);699 700 if (!IS_ERR_OR_NULL(host->dma_chan_tx))701 dma_release_channel(host->dma_chan_tx);702 if (!IS_ERR_OR_NULL(host->dma_chan_rx))703 dma_release_channel(host->dma_chan_rx);704 mmc_remove_host(mmc);705 706 writel(0, host->base + REG_INTERRUPT_MASK);707 writel(0, host->base + REG_POWER_CONTROL);708 writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF,709 host->base + REG_CLOCK_CONTROL);710 mmc_free_host(mmc);711}712 713static const struct of_device_id moxart_mmc_match[] = {714 { .compatible = "moxa,moxart-mmc" },715 { .compatible = "faraday,ftsdc010" },716 { }717};718MODULE_DEVICE_TABLE(of, moxart_mmc_match);719 720static struct platform_driver moxart_mmc_driver = {721 .probe = moxart_probe,722 .remove_new = moxart_remove,723 .driver = {724 .name = "mmc-moxart",725 .probe_type = PROBE_PREFER_ASYNCHRONOUS,726 .of_match_table = moxart_mmc_match,727 },728};729module_platform_driver(moxart_mmc_driver);730 731MODULE_ALIAS("platform:mmc-moxart");732MODULE_DESCRIPTION("MOXA ART MMC driver");733MODULE_LICENSE("GPL v2");734MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");735