1570 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * linux/drivers/mmc/host/omap.c4 *5 * Copyright (C) 2004 Nokia Corporation6 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>7 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>8 * Other hacks (DMA, SD, etc) by David Brownell9 */10 11#include <linux/module.h>12#include <linux/moduleparam.h>13#include <linux/init.h>14#include <linux/ioport.h>15#include <linux/platform_device.h>16#include <linux/interrupt.h>17#include <linux/dmaengine.h>18#include <linux/dma-mapping.h>19#include <linux/delay.h>20#include <linux/spinlock.h>21#include <linux/timer.h>22#include <linux/of.h>23#include <linux/mmc/host.h>24#include <linux/mmc/card.h>25#include <linux/mmc/mmc.h>26#include <linux/clk.h>27#include <linux/scatterlist.h>28#include <linux/slab.h>29#include <linux/gpio/consumer.h>30#include <linux/platform_data/mmc-omap.h>31#include <linux/workqueue.h>32 33 34#define OMAP_MMC_REG_CMD 0x0035#define OMAP_MMC_REG_ARGL 0x0136#define OMAP_MMC_REG_ARGH 0x0237#define OMAP_MMC_REG_CON 0x0338#define OMAP_MMC_REG_STAT 0x0439#define OMAP_MMC_REG_IE 0x0540#define OMAP_MMC_REG_CTO 0x0641#define OMAP_MMC_REG_DTO 0x0742#define OMAP_MMC_REG_DATA 0x0843#define OMAP_MMC_REG_BLEN 0x0944#define OMAP_MMC_REG_NBLK 0x0a45#define OMAP_MMC_REG_BUF 0x0b46#define OMAP_MMC_REG_SDIO 0x0d47#define OMAP_MMC_REG_REV 0x0f48#define OMAP_MMC_REG_RSP0 0x1049#define OMAP_MMC_REG_RSP1 0x1150#define OMAP_MMC_REG_RSP2 0x1251#define OMAP_MMC_REG_RSP3 0x1352#define OMAP_MMC_REG_RSP4 0x1453#define OMAP_MMC_REG_RSP5 0x1554#define OMAP_MMC_REG_RSP6 0x1655#define OMAP_MMC_REG_RSP7 0x1756#define OMAP_MMC_REG_IOSR 0x1857#define OMAP_MMC_REG_SYSC 0x1958#define OMAP_MMC_REG_SYSS 0x1a59 60#define OMAP_MMC_STAT_CARD_ERR (1 << 14)61#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)62#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)63#define OMAP_MMC_STAT_A_EMPTY (1 << 11)64#define OMAP_MMC_STAT_A_FULL (1 << 10)65#define OMAP_MMC_STAT_CMD_CRC (1 << 8)66#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)67#define OMAP_MMC_STAT_DATA_CRC (1 << 6)68#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)69#define OMAP_MMC_STAT_END_BUSY (1 << 4)70#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)71#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)72#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)73 74#define mmc_omap7xx() (host->features & MMC_OMAP7XX)75#define mmc_omap15xx() (host->features & MMC_OMAP15XX)76#define mmc_omap16xx() (host->features & MMC_OMAP16XX)77#define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)78#define mmc_omap1() (host->features & MMC_OMAP1_MASK)79#define mmc_omap2() (!mmc_omap1())80 81#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)82#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))83#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))84 85/*86 * Command types87 */88#define OMAP_MMC_CMDTYPE_BC 089#define OMAP_MMC_CMDTYPE_BCR 190#define OMAP_MMC_CMDTYPE_AC 291#define OMAP_MMC_CMDTYPE_ADTC 392 93#define DRIVER_NAME "mmci-omap"94 95/* Specifies how often in millisecs to poll for card status changes96 * when the cover switch is open */97#define OMAP_MMC_COVER_POLL_DELAY 50098 99struct mmc_omap_host;100 101struct mmc_omap_slot {102 int id;103 unsigned int vdd;104 u16 saved_con;105 u16 bus_mode;106 u16 power_mode;107 unsigned int fclk_freq;108 109 struct work_struct cover_bh_work;110 struct timer_list cover_timer;111 unsigned cover_open;112 113 struct mmc_request *mrq;114 struct mmc_omap_host *host;115 struct mmc_host *mmc;116 struct gpio_desc *vsd;117 struct gpio_desc *vio;118 struct gpio_desc *cover;119 struct omap_mmc_slot_data *pdata;120};121 122struct mmc_omap_host {123 int initialized;124 struct mmc_request * mrq;125 struct mmc_command * cmd;126 struct mmc_data * data;127 struct mmc_host * mmc;128 struct device * dev;129 unsigned char id; /* 16xx chips have 2 MMC blocks */130 struct clk * iclk;131 struct clk * fclk;132 struct dma_chan *dma_rx;133 u32 dma_rx_burst;134 struct dma_chan *dma_tx;135 u32 dma_tx_burst;136 void __iomem *virt_base;137 unsigned int phys_base;138 int irq;139 unsigned char bus_mode;140 unsigned int reg_shift;141 struct gpio_desc *slot_switch;142 143 struct work_struct cmd_abort_work;144 unsigned abort:1;145 struct timer_list cmd_abort_timer;146 147 struct work_struct slot_release_work;148 struct mmc_omap_slot *next_slot;149 struct work_struct send_stop_work;150 struct mmc_data *stop_data;151 152 struct sg_mapping_iter sg_miter;153 unsigned int sg_len;154 u32 total_bytes_left;155 156 unsigned features;157 unsigned brs_received:1, dma_done:1;158 unsigned dma_in_use:1;159 spinlock_t dma_lock;160 161 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];162 struct mmc_omap_slot *current_slot;163 spinlock_t slot_lock;164 wait_queue_head_t slot_wq;165 int nr_slots;166 167 struct timer_list clk_timer;168 spinlock_t clk_lock; /* for changing enabled state */169 unsigned int fclk_enabled:1;170 struct workqueue_struct *mmc_omap_wq;171 172 struct omap_mmc_platform_data *pdata;173};174 175 176static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)177{178 unsigned long tick_ns;179 180 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {181 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);182 ndelay(8 * tick_ns);183 }184}185 186static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)187{188 unsigned long flags;189 190 spin_lock_irqsave(&host->clk_lock, flags);191 if (host->fclk_enabled != enable) {192 host->fclk_enabled = enable;193 if (enable)194 clk_enable(host->fclk);195 else196 clk_disable(host->fclk);197 }198 spin_unlock_irqrestore(&host->clk_lock, flags);199}200 201static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)202{203 struct mmc_omap_host *host = slot->host;204 unsigned long flags;205 206 if (claimed)207 goto no_claim;208 spin_lock_irqsave(&host->slot_lock, flags);209 while (host->mmc != NULL) {210 spin_unlock_irqrestore(&host->slot_lock, flags);211 wait_event(host->slot_wq, host->mmc == NULL);212 spin_lock_irqsave(&host->slot_lock, flags);213 }214 host->mmc = slot->mmc;215 spin_unlock_irqrestore(&host->slot_lock, flags);216no_claim:217 del_timer(&host->clk_timer);218 if (host->current_slot != slot || !claimed)219 mmc_omap_fclk_offdelay(host->current_slot);220 221 if (host->current_slot != slot) {222 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);223 if (host->slot_switch)224 /*225 * With two slots and a simple GPIO switch, setting226 * the GPIO to 0 selects slot ID 0, setting it to 1227 * selects slot ID 1.228 */229 gpiod_set_value(host->slot_switch, slot->id);230 host->current_slot = slot;231 }232 233 if (claimed) {234 mmc_omap_fclk_enable(host, 1);235 236 /* Doing the dummy read here seems to work around some bug237 * at least in OMAP24xx silicon where the command would not238 * start after writing the CMD register. Sigh. */239 OMAP_MMC_READ(host, CON);240 241 OMAP_MMC_WRITE(host, CON, slot->saved_con);242 } else243 mmc_omap_fclk_enable(host, 0);244}245 246static void mmc_omap_start_request(struct mmc_omap_host *host,247 struct mmc_request *req);248 249static void mmc_omap_slot_release_work(struct work_struct *work)250{251 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,252 slot_release_work);253 struct mmc_omap_slot *next_slot = host->next_slot;254 struct mmc_request *rq;255 256 host->next_slot = NULL;257 mmc_omap_select_slot(next_slot, 1);258 259 rq = next_slot->mrq;260 next_slot->mrq = NULL;261 mmc_omap_start_request(host, rq);262}263 264static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)265{266 struct mmc_omap_host *host = slot->host;267 unsigned long flags;268 int i;269 270 BUG_ON(slot == NULL || host->mmc == NULL);271 272 if (clk_enabled)273 /* Keeps clock running for at least 8 cycles on valid freq */274 mod_timer(&host->clk_timer, jiffies + HZ/10);275 else {276 del_timer(&host->clk_timer);277 mmc_omap_fclk_offdelay(slot);278 mmc_omap_fclk_enable(host, 0);279 }280 281 spin_lock_irqsave(&host->slot_lock, flags);282 /* Check for any pending requests */283 for (i = 0; i < host->nr_slots; i++) {284 struct mmc_omap_slot *new_slot;285 286 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)287 continue;288 289 BUG_ON(host->next_slot != NULL);290 new_slot = host->slots[i];291 /* The current slot should not have a request in queue */292 BUG_ON(new_slot == host->current_slot);293 294 host->next_slot = new_slot;295 host->mmc = new_slot->mmc;296 spin_unlock_irqrestore(&host->slot_lock, flags);297 queue_work(host->mmc_omap_wq, &host->slot_release_work);298 return;299 }300 301 host->mmc = NULL;302 wake_up(&host->slot_wq);303 spin_unlock_irqrestore(&host->slot_lock, flags);304}305 306static inline307int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)308{309 /* If we have a GPIO then use that */310 if (slot->cover)311 return gpiod_get_value(slot->cover);312 if (slot->pdata->get_cover_state)313 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),314 slot->id);315 return 0;316}317 318static ssize_t319mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,320 char *buf)321{322 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);323 struct mmc_omap_slot *slot = mmc_priv(mmc);324 325 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :326 "closed");327}328 329static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);330 331static ssize_t332mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,333 char *buf)334{335 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);336 struct mmc_omap_slot *slot = mmc_priv(mmc);337 338 return sprintf(buf, "%s\n", slot->pdata->name);339}340 341static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);342 343static void344mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)345{346 u32 cmdreg;347 u32 resptype;348 u32 cmdtype;349 u16 irq_mask;350 351 host->cmd = cmd;352 353 resptype = 0;354 cmdtype = 0;355 356 /* Our hardware needs to know exact type */357 switch (mmc_resp_type(cmd)) {358 case MMC_RSP_NONE:359 break;360 case MMC_RSP_R1:361 case MMC_RSP_R1B:362 /* resp 1, 1b, 6, 7 */363 resptype = 1;364 break;365 case MMC_RSP_R2:366 resptype = 2;367 break;368 case MMC_RSP_R3:369 resptype = 3;370 break;371 default:372 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));373 break;374 }375 376 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {377 cmdtype = OMAP_MMC_CMDTYPE_ADTC;378 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {379 cmdtype = OMAP_MMC_CMDTYPE_BC;380 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {381 cmdtype = OMAP_MMC_CMDTYPE_BCR;382 } else {383 cmdtype = OMAP_MMC_CMDTYPE_AC;384 }385 386 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);387 388 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)389 cmdreg |= 1 << 6;390 391 if (cmd->flags & MMC_RSP_BUSY)392 cmdreg |= 1 << 11;393 394 if (host->data && !(host->data->flags & MMC_DATA_WRITE))395 cmdreg |= 1 << 15;396 397 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);398 399 OMAP_MMC_WRITE(host, CTO, 200);400 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);401 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);402 irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |403 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |404 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |405 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |406 OMAP_MMC_STAT_END_OF_DATA;407 if (cmd->opcode == MMC_ERASE)408 irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;409 OMAP_MMC_WRITE(host, IE, irq_mask);410 OMAP_MMC_WRITE(host, CMD, cmdreg);411}412 413static void414mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,415 int abort)416{417 enum dma_data_direction dma_data_dir;418 struct device *dev = mmc_dev(host->mmc);419 struct dma_chan *c;420 421 if (data->flags & MMC_DATA_WRITE) {422 dma_data_dir = DMA_TO_DEVICE;423 c = host->dma_tx;424 } else {425 dma_data_dir = DMA_FROM_DEVICE;426 c = host->dma_rx;427 }428 if (c) {429 if (data->error) {430 dmaengine_terminate_all(c);431 /* Claim nothing transferred on error... */432 data->bytes_xfered = 0;433 }434 dev = c->device->dev;435 }436 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);437}438 439static void mmc_omap_send_stop_work(struct work_struct *work)440{441 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,442 send_stop_work);443 struct mmc_omap_slot *slot = host->current_slot;444 struct mmc_data *data = host->stop_data;445 unsigned long tick_ns;446 447 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);448 ndelay(8*tick_ns);449 450 mmc_omap_start_command(host, data->stop);451}452 453static void454mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)455{456 if (host->dma_in_use)457 mmc_omap_release_dma(host, data, data->error);458 else459 sg_miter_stop(&host->sg_miter);460 461 host->data = NULL;462 host->sg_len = 0;463 464 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing465 * dozens of requests until the card finishes writing data.466 * It'd be cheaper to just wait till an EOFB interrupt arrives...467 */468 469 if (!data->stop) {470 struct mmc_host *mmc;471 472 host->mrq = NULL;473 mmc = host->mmc;474 mmc_omap_release_slot(host->current_slot, 1);475 mmc_request_done(mmc, data->mrq);476 return;477 }478 479 host->stop_data = data;480 queue_work(host->mmc_omap_wq, &host->send_stop_work);481}482 483static void484mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)485{486 struct mmc_omap_slot *slot = host->current_slot;487 unsigned int restarts, passes, timeout;488 u16 stat = 0;489 490 /* Sending abort takes 80 clocks. Have some extra and round up */491 timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);492 restarts = 0;493 while (restarts < maxloops) {494 OMAP_MMC_WRITE(host, STAT, 0xFFFF);495 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));496 497 passes = 0;498 while (passes < timeout) {499 stat = OMAP_MMC_READ(host, STAT);500 if (stat & OMAP_MMC_STAT_END_OF_CMD)501 goto out;502 udelay(1);503 passes++;504 }505 506 restarts++;507 }508out:509 OMAP_MMC_WRITE(host, STAT, stat);510}511 512static void513mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)514{515 if (host->dma_in_use)516 mmc_omap_release_dma(host, data, 1);517 518 host->data = NULL;519 host->sg_len = 0;520 521 mmc_omap_send_abort(host, 10000);522}523 524static void525mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)526{527 unsigned long flags;528 int done;529 530 if (!host->dma_in_use) {531 mmc_omap_xfer_done(host, data);532 return;533 }534 done = 0;535 spin_lock_irqsave(&host->dma_lock, flags);536 if (host->dma_done)537 done = 1;538 else539 host->brs_received = 1;540 spin_unlock_irqrestore(&host->dma_lock, flags);541 if (done)542 mmc_omap_xfer_done(host, data);543}544 545static void546mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)547{548 unsigned long flags;549 int done;550 551 done = 0;552 spin_lock_irqsave(&host->dma_lock, flags);553 if (host->brs_received)554 done = 1;555 else556 host->dma_done = 1;557 spin_unlock_irqrestore(&host->dma_lock, flags);558 if (done)559 mmc_omap_xfer_done(host, data);560}561 562static void563mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)564{565 host->cmd = NULL;566 567 del_timer(&host->cmd_abort_timer);568 569 if (cmd->flags & MMC_RSP_PRESENT) {570 if (cmd->flags & MMC_RSP_136) {571 /* response type 2 */572 cmd->resp[3] =573 OMAP_MMC_READ(host, RSP0) |574 (OMAP_MMC_READ(host, RSP1) << 16);575 cmd->resp[2] =576 OMAP_MMC_READ(host, RSP2) |577 (OMAP_MMC_READ(host, RSP3) << 16);578 cmd->resp[1] =579 OMAP_MMC_READ(host, RSP4) |580 (OMAP_MMC_READ(host, RSP5) << 16);581 cmd->resp[0] =582 OMAP_MMC_READ(host, RSP6) |583 (OMAP_MMC_READ(host, RSP7) << 16);584 } else {585 /* response types 1, 1b, 3, 4, 5, 6 */586 cmd->resp[0] =587 OMAP_MMC_READ(host, RSP6) |588 (OMAP_MMC_READ(host, RSP7) << 16);589 }590 }591 592 if (host->data == NULL || cmd->error) {593 struct mmc_host *mmc;594 595 if (host->data != NULL)596 mmc_omap_abort_xfer(host, host->data);597 host->mrq = NULL;598 mmc = host->mmc;599 mmc_omap_release_slot(host->current_slot, 1);600 mmc_request_done(mmc, cmd->mrq);601 }602}603 604/*605 * Abort stuck command. Can occur when card is removed while it is being606 * read.607 */608static void mmc_omap_abort_command(struct work_struct *work)609{610 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,611 cmd_abort_work);612 BUG_ON(!host->cmd);613 614 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",615 host->cmd->opcode);616 617 if (host->cmd->error == 0)618 host->cmd->error = -ETIMEDOUT;619 620 if (host->data == NULL) {621 struct mmc_command *cmd;622 struct mmc_host *mmc;623 624 cmd = host->cmd;625 host->cmd = NULL;626 mmc_omap_send_abort(host, 10000);627 628 host->mrq = NULL;629 mmc = host->mmc;630 mmc_omap_release_slot(host->current_slot, 1);631 mmc_request_done(mmc, cmd->mrq);632 } else633 mmc_omap_cmd_done(host, host->cmd);634 635 host->abort = 0;636 enable_irq(host->irq);637}638 639static void640mmc_omap_cmd_timer(struct timer_list *t)641{642 struct mmc_omap_host *host = from_timer(host, t, cmd_abort_timer);643 unsigned long flags;644 645 spin_lock_irqsave(&host->slot_lock, flags);646 if (host->cmd != NULL && !host->abort) {647 OMAP_MMC_WRITE(host, IE, 0);648 disable_irq(host->irq);649 host->abort = 1;650 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);651 }652 spin_unlock_irqrestore(&host->slot_lock, flags);653}654 655static void656mmc_omap_clk_timer(struct timer_list *t)657{658 struct mmc_omap_host *host = from_timer(host, t, clk_timer);659 660 mmc_omap_fclk_enable(host, 0);661}662 663/* PIO only */664static void665mmc_omap_xfer_data(struct mmc_omap_host *host, int write)666{667 struct sg_mapping_iter *sgm = &host->sg_miter;668 int n, nwords;669 u16 *buffer;670 671 if (!sg_miter_next(sgm)) {672 /* This should not happen */673 dev_err(mmc_dev(host->mmc), "ran out of scatterlist prematurely\n");674 return;675 }676 buffer = sgm->addr;677 678 n = 64;679 if (n > sgm->length)680 n = sgm->length;681 if (n > host->total_bytes_left)682 n = host->total_bytes_left;683 684 /* Round up to handle odd number of bytes to transfer */685 nwords = DIV_ROUND_UP(n, 2);686 687 sgm->consumed = n;688 host->total_bytes_left -= n;689 host->data->bytes_xfered += n;690 691 if (write) {692 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),693 buffer, nwords);694 } else {695 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),696 buffer, nwords);697 }698}699 700#ifdef CONFIG_MMC_DEBUG701static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)702{703 static const char *mmc_omap_status_bits[] = {704 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",705 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"706 };707 int i;708 char res[64], *buf = res;709 710 buf += sprintf(buf, "MMC IRQ 0x%x:", status);711 712 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)713 if (status & (1 << i))714 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);715 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);716}717#else718static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)719{720}721#endif722 723 724static irqreturn_t mmc_omap_irq(int irq, void *dev_id)725{726 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;727 u16 status;728 int end_command;729 int end_transfer;730 int transfer_error, cmd_error;731 732 if (host->cmd == NULL && host->data == NULL) {733 status = OMAP_MMC_READ(host, STAT);734 dev_info(mmc_dev(host->slots[0]->mmc),735 "Spurious IRQ 0x%04x\n", status);736 if (status != 0) {737 OMAP_MMC_WRITE(host, STAT, status);738 OMAP_MMC_WRITE(host, IE, 0);739 }740 return IRQ_HANDLED;741 }742 743 end_command = 0;744 end_transfer = 0;745 transfer_error = 0;746 cmd_error = 0;747 748 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {749 int cmd;750 751 OMAP_MMC_WRITE(host, STAT, status);752 if (host->cmd != NULL)753 cmd = host->cmd->opcode;754 else755 cmd = -1;756 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",757 status, cmd);758 mmc_omap_report_irq(host, status);759 760 if (host->total_bytes_left) {761 if ((status & OMAP_MMC_STAT_A_FULL) ||762 (status & OMAP_MMC_STAT_END_OF_DATA))763 mmc_omap_xfer_data(host, 0);764 if (status & OMAP_MMC_STAT_A_EMPTY)765 mmc_omap_xfer_data(host, 1);766 }767 768 if (status & OMAP_MMC_STAT_END_OF_DATA)769 end_transfer = 1;770 771 if (status & OMAP_MMC_STAT_DATA_TOUT) {772 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",773 cmd);774 if (host->data) {775 host->data->error = -ETIMEDOUT;776 transfer_error = 1;777 }778 }779 780 if (status & OMAP_MMC_STAT_DATA_CRC) {781 if (host->data) {782 host->data->error = -EILSEQ;783 dev_dbg(mmc_dev(host->mmc),784 "data CRC error, bytes left %d\n",785 host->total_bytes_left);786 transfer_error = 1;787 } else {788 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");789 }790 }791 792 if (status & OMAP_MMC_STAT_CMD_TOUT) {793 /* Timeouts are routine with some commands */794 if (host->cmd) {795 struct mmc_omap_slot *slot =796 host->current_slot;797 if (slot == NULL ||798 !mmc_omap_cover_is_open(slot))799 dev_err(mmc_dev(host->mmc),800 "command timeout (CMD%d)\n",801 cmd);802 host->cmd->error = -ETIMEDOUT;803 end_command = 1;804 cmd_error = 1;805 }806 }807 808 if (status & OMAP_MMC_STAT_CMD_CRC) {809 if (host->cmd) {810 dev_err(mmc_dev(host->mmc),811 "command CRC error (CMD%d, arg 0x%08x)\n",812 cmd, host->cmd->arg);813 host->cmd->error = -EILSEQ;814 end_command = 1;815 cmd_error = 1;816 } else817 dev_err(mmc_dev(host->mmc),818 "command CRC error without cmd?\n");819 }820 821 if (status & OMAP_MMC_STAT_CARD_ERR) {822 dev_dbg(mmc_dev(host->mmc),823 "ignoring card status error (CMD%d)\n",824 cmd);825 end_command = 1;826 }827 828 /*829 * NOTE: On 1610 the END_OF_CMD may come too early when830 * starting a write831 */832 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&833 (!(status & OMAP_MMC_STAT_A_EMPTY))) {834 end_command = 1;835 }836 }837 838 if (cmd_error && host->data) {839 del_timer(&host->cmd_abort_timer);840 host->abort = 1;841 OMAP_MMC_WRITE(host, IE, 0);842 disable_irq_nosync(host->irq);843 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);844 return IRQ_HANDLED;845 }846 847 if (end_command && host->cmd)848 mmc_omap_cmd_done(host, host->cmd);849 if (host->data != NULL) {850 if (transfer_error)851 mmc_omap_xfer_done(host, host->data);852 else if (end_transfer)853 mmc_omap_end_of_data(host, host->data);854 }855 856 return IRQ_HANDLED;857}858 859void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)860{861 int cover_open;862 struct mmc_omap_host *host = dev_get_drvdata(dev);863 struct mmc_omap_slot *slot = host->slots[num];864 865 BUG_ON(num >= host->nr_slots);866 867 /* Other subsystems can call in here before we're initialised. */868 if (host->nr_slots == 0 || !host->slots[num])869 return;870 871 cover_open = mmc_omap_cover_is_open(slot);872 if (cover_open != slot->cover_open) {873 slot->cover_open = cover_open;874 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");875 }876 877 queue_work(system_bh_highpri_wq, &slot->cover_bh_work);878}879 880static void mmc_omap_cover_timer(struct timer_list *t)881{882 struct mmc_omap_slot *slot = from_timer(slot, t, cover_timer);883 queue_work(system_bh_wq, &slot->cover_bh_work);884}885 886static void mmc_omap_cover_bh_handler(struct work_struct *t)887{888 struct mmc_omap_slot *slot = from_work(slot, t, cover_bh_work);889 int cover_open = mmc_omap_cover_is_open(slot);890 891 mmc_detect_change(slot->mmc, 0);892 if (!cover_open)893 return;894 895 /*896 * If no card is inserted, we postpone polling until897 * the cover has been closed.898 */899 if (slot->mmc->card == NULL)900 return;901 902 mod_timer(&slot->cover_timer,903 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));904}905 906static void mmc_omap_dma_callback(void *priv)907{908 struct mmc_omap_host *host = priv;909 struct mmc_data *data = host->data;910 911 /* If we got to the end of DMA, assume everything went well */912 data->bytes_xfered += data->blocks * data->blksz;913 914 mmc_omap_dma_done(host, data);915}916 917static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)918{919 u16 reg;920 921 reg = OMAP_MMC_READ(host, SDIO);922 reg &= ~(1 << 5);923 OMAP_MMC_WRITE(host, SDIO, reg);924 /* Set maximum timeout */925 OMAP_MMC_WRITE(host, CTO, 0xfd);926}927 928static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)929{930 unsigned int timeout, cycle_ns;931 u16 reg;932 933 cycle_ns = 1000000000 / host->current_slot->fclk_freq;934 timeout = req->data->timeout_ns / cycle_ns;935 timeout += req->data->timeout_clks;936 937 /* Check if we need to use timeout multiplier register */938 reg = OMAP_MMC_READ(host, SDIO);939 if (timeout > 0xffff) {940 reg |= (1 << 5);941 timeout /= 1024;942 } else943 reg &= ~(1 << 5);944 OMAP_MMC_WRITE(host, SDIO, reg);945 OMAP_MMC_WRITE(host, DTO, timeout);946}947 948static void949mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)950{951 unsigned int miter_flags = SG_MITER_ATOMIC; /* Used from IRQ */952 struct mmc_data *data = req->data;953 int i, use_dma = 1, block_size;954 struct scatterlist *sg;955 unsigned sg_len;956 957 host->data = data;958 if (data == NULL) {959 OMAP_MMC_WRITE(host, BLEN, 0);960 OMAP_MMC_WRITE(host, NBLK, 0);961 OMAP_MMC_WRITE(host, BUF, 0);962 host->dma_in_use = 0;963 set_cmd_timeout(host, req);964 return;965 }966 967 block_size = data->blksz;968 969 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);970 OMAP_MMC_WRITE(host, BLEN, block_size - 1);971 set_data_timeout(host, req);972 973 /* cope with calling layer confusion; it issues "single974 * block" writes using multi-block scatterlists.975 */976 sg_len = (data->blocks == 1) ? 1 : data->sg_len;977 978 /* Only do DMA for entire blocks */979 for_each_sg(data->sg, sg, sg_len, i) {980 if ((sg->length % block_size) != 0) {981 use_dma = 0;982 break;983 }984 }985 986 if (use_dma) {987 enum dma_data_direction dma_data_dir;988 struct dma_async_tx_descriptor *tx;989 struct dma_chan *c;990 u32 burst, *bp;991 u16 buf;992 993 /*994 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx995 * and 24xx. Use 16 or 32 word frames when the996 * blocksize is at least that large. Blocksize is997 * usually 512 bytes; but not for some SD reads.998 */999 burst = mmc_omap15xx() ? 32 : 64;1000 if (burst > data->blksz)1001 burst = data->blksz;1002 1003 burst >>= 1;1004 1005 if (data->flags & MMC_DATA_WRITE) {1006 c = host->dma_tx;1007 bp = &host->dma_tx_burst;1008 buf = 0x0f80 | (burst - 1) << 0;1009 dma_data_dir = DMA_TO_DEVICE;1010 } else {1011 c = host->dma_rx;1012 bp = &host->dma_rx_burst;1013 buf = 0x800f | (burst - 1) << 8;1014 dma_data_dir = DMA_FROM_DEVICE;1015 }1016 1017 if (!c)1018 goto use_pio;1019 1020 /* Only reconfigure if we have a different burst size */1021 if (*bp != burst) {1022 struct dma_slave_config cfg = {1023 .src_addr = host->phys_base +1024 OMAP_MMC_REG(host, DATA),1025 .dst_addr = host->phys_base +1026 OMAP_MMC_REG(host, DATA),1027 .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,1028 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,1029 .src_maxburst = burst,1030 .dst_maxburst = burst,1031 };1032 1033 if (dmaengine_slave_config(c, &cfg))1034 goto use_pio;1035 1036 *bp = burst;1037 }1038 1039 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,1040 dma_data_dir);1041 if (host->sg_len == 0)1042 goto use_pio;1043 1044 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,1045 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,1046 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);1047 if (!tx)1048 goto use_pio;1049 1050 OMAP_MMC_WRITE(host, BUF, buf);1051 1052 tx->callback = mmc_omap_dma_callback;1053 tx->callback_param = host;1054 dmaengine_submit(tx);1055 host->brs_received = 0;1056 host->dma_done = 0;1057 host->dma_in_use = 1;1058 return;1059 }1060 use_pio:1061 1062 /* Revert to PIO? */1063 OMAP_MMC_WRITE(host, BUF, 0x1f1f);1064 host->total_bytes_left = data->blocks * block_size;1065 host->sg_len = sg_len;1066 if (data->flags & MMC_DATA_READ)1067 miter_flags |= SG_MITER_TO_SG;1068 else1069 miter_flags |= SG_MITER_FROM_SG;1070 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, miter_flags);1071 host->dma_in_use = 0;1072}1073 1074static void mmc_omap_start_request(struct mmc_omap_host *host,1075 struct mmc_request *req)1076{1077 BUG_ON(host->mrq != NULL);1078 1079 host->mrq = req;1080 1081 /* only touch fifo AFTER the controller readies it */1082 mmc_omap_prepare_data(host, req);1083 mmc_omap_start_command(host, req->cmd);1084 if (host->dma_in_use) {1085 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?1086 host->dma_tx : host->dma_rx;1087 1088 dma_async_issue_pending(c);1089 }1090}1091 1092static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)1093{1094 struct mmc_omap_slot *slot = mmc_priv(mmc);1095 struct mmc_omap_host *host = slot->host;1096 unsigned long flags;1097 1098 spin_lock_irqsave(&host->slot_lock, flags);1099 if (host->mmc != NULL) {1100 BUG_ON(slot->mrq != NULL);1101 slot->mrq = req;1102 spin_unlock_irqrestore(&host->slot_lock, flags);1103 return;1104 } else1105 host->mmc = mmc;1106 spin_unlock_irqrestore(&host->slot_lock, flags);1107 mmc_omap_select_slot(slot, 1);1108 mmc_omap_start_request(host, req);1109}1110 1111static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,1112 int vdd)1113{1114 struct mmc_omap_host *host;1115 1116 host = slot->host;1117 1118 if (power_on) {1119 if (slot->vsd) {1120 gpiod_set_value(slot->vsd, power_on);1121 msleep(1);1122 }1123 if (slot->vio) {1124 gpiod_set_value(slot->vio, power_on);1125 msleep(1);1126 }1127 } else {1128 if (slot->vio) {1129 gpiod_set_value(slot->vio, power_on);1130 msleep(50);1131 }1132 if (slot->vsd) {1133 gpiod_set_value(slot->vsd, power_on);1134 msleep(50);1135 }1136 }1137 1138 if (slot->pdata->set_power != NULL)1139 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,1140 vdd);1141 if (mmc_omap2()) {1142 u16 w;1143 1144 if (power_on) {1145 w = OMAP_MMC_READ(host, CON);1146 OMAP_MMC_WRITE(host, CON, w | (1 << 11));1147 } else {1148 w = OMAP_MMC_READ(host, CON);1149 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));1150 }1151 }1152}1153 1154static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)1155{1156 struct mmc_omap_slot *slot = mmc_priv(mmc);1157 struct mmc_omap_host *host = slot->host;1158 int func_clk_rate = clk_get_rate(host->fclk);1159 int dsor;1160 1161 if (ios->clock == 0)1162 return 0;1163 1164 dsor = func_clk_rate / ios->clock;1165 if (dsor < 1)1166 dsor = 1;1167 1168 if (func_clk_rate / dsor > ios->clock)1169 dsor++;1170 1171 if (dsor > 250)1172 dsor = 250;1173 1174 slot->fclk_freq = func_clk_rate / dsor;1175 1176 if (ios->bus_width == MMC_BUS_WIDTH_4)1177 dsor |= 1 << 15;1178 1179 return dsor;1180}1181 1182static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)1183{1184 struct mmc_omap_slot *slot = mmc_priv(mmc);1185 struct mmc_omap_host *host = slot->host;1186 int i, dsor;1187 int clk_enabled, init_stream;1188 1189 mmc_omap_select_slot(slot, 0);1190 1191 dsor = mmc_omap_calc_divisor(mmc, ios);1192 1193 if (ios->vdd != slot->vdd)1194 slot->vdd = ios->vdd;1195 1196 clk_enabled = 0;1197 init_stream = 0;1198 switch (ios->power_mode) {1199 case MMC_POWER_OFF:1200 mmc_omap_set_power(slot, 0, ios->vdd);1201 break;1202 case MMC_POWER_UP:1203 /* Cannot touch dsor yet, just power up MMC */1204 mmc_omap_set_power(slot, 1, ios->vdd);1205 slot->power_mode = ios->power_mode;1206 goto exit;1207 case MMC_POWER_ON:1208 mmc_omap_fclk_enable(host, 1);1209 clk_enabled = 1;1210 dsor |= 1 << 11;1211 if (slot->power_mode != MMC_POWER_ON)1212 init_stream = 1;1213 break;1214 }1215 slot->power_mode = ios->power_mode;1216 1217 if (slot->bus_mode != ios->bus_mode) {1218 if (slot->pdata->set_bus_mode != NULL)1219 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,1220 ios->bus_mode);1221 slot->bus_mode = ios->bus_mode;1222 }1223 1224 /* On insanely high arm_per frequencies something sometimes1225 * goes somehow out of sync, and the POW bit is not being set,1226 * which results in the while loop below getting stuck.1227 * Writing to the CON register twice seems to do the trick. */1228 for (i = 0; i < 2; i++)1229 OMAP_MMC_WRITE(host, CON, dsor);1230 slot->saved_con = dsor;1231 if (init_stream) {1232 /* worst case at 400kHz, 80 cycles makes 200 microsecs */1233 int usecs = 250;1234 1235 /* Send clock cycles, poll completion */1236 OMAP_MMC_WRITE(host, IE, 0);1237 OMAP_MMC_WRITE(host, STAT, 0xffff);1238 OMAP_MMC_WRITE(host, CMD, 1 << 7);1239 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {1240 udelay(1);1241 usecs--;1242 }1243 OMAP_MMC_WRITE(host, STAT, 1);1244 }1245 1246exit:1247 mmc_omap_release_slot(slot, clk_enabled);1248}1249 1250static const struct mmc_host_ops mmc_omap_ops = {1251 .request = mmc_omap_request,1252 .set_ios = mmc_omap_set_ios,1253};1254 1255static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)1256{1257 struct mmc_omap_slot *slot = NULL;1258 struct mmc_host *mmc;1259 int r;1260 1261 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);1262 if (mmc == NULL)1263 return -ENOMEM;1264 1265 slot = mmc_priv(mmc);1266 slot->host = host;1267 slot->mmc = mmc;1268 slot->id = id;1269 slot->power_mode = MMC_POWER_UNDEFINED;1270 slot->pdata = &host->pdata->slots[id];1271 1272 /* Check for some optional GPIO controls */1273 slot->vsd = devm_gpiod_get_index_optional(host->dev, "vsd",1274 id, GPIOD_OUT_LOW);1275 if (IS_ERR(slot->vsd))1276 return dev_err_probe(host->dev, PTR_ERR(slot->vsd),1277 "error looking up VSD GPIO\n");1278 slot->vio = devm_gpiod_get_index_optional(host->dev, "vio",1279 id, GPIOD_OUT_LOW);1280 if (IS_ERR(slot->vio))1281 return dev_err_probe(host->dev, PTR_ERR(slot->vio),1282 "error looking up VIO GPIO\n");1283 slot->cover = devm_gpiod_get_index_optional(host->dev, "cover",1284 id, GPIOD_IN);1285 if (IS_ERR(slot->cover))1286 return dev_err_probe(host->dev, PTR_ERR(slot->cover),1287 "error looking up cover switch GPIO\n");1288 1289 host->slots[id] = slot;1290 1291 mmc->caps = 0;1292 if (host->pdata->slots[id].wires >= 4)1293 mmc->caps |= MMC_CAP_4_BIT_DATA;1294 1295 mmc->ops = &mmc_omap_ops;1296 mmc->f_min = 400000;1297 1298 if (mmc_omap2())1299 mmc->f_max = 48000000;1300 else1301 mmc->f_max = 24000000;1302 if (host->pdata->max_freq)1303 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);1304 mmc->ocr_avail = slot->pdata->ocr_mask;1305 1306 /* Use scatterlist DMA to reduce per-transfer costs.1307 * NOTE max_seg_size assumption that small blocks aren't1308 * normally used (except e.g. for reading SD registers).1309 */1310 mmc->max_segs = 32;1311 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */1312 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */1313 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;1314 mmc->max_seg_size = mmc->max_req_size;1315 1316 if (slot->pdata->get_cover_state != NULL) {1317 timer_setup(&slot->cover_timer, mmc_omap_cover_timer, 0);1318 INIT_WORK(&slot->cover_bh_work, mmc_omap_cover_bh_handler);1319 }1320 1321 r = mmc_add_host(mmc);1322 if (r < 0)1323 goto err_remove_host;1324 1325 if (slot->pdata->name != NULL) {1326 r = device_create_file(&mmc->class_dev,1327 &dev_attr_slot_name);1328 if (r < 0)1329 goto err_remove_host;1330 }1331 1332 if (slot->pdata->get_cover_state != NULL) {1333 r = device_create_file(&mmc->class_dev,1334 &dev_attr_cover_switch);1335 if (r < 0)1336 goto err_remove_slot_name;1337 queue_work(system_bh_wq, &slot->cover_bh_work);1338 }1339 1340 return 0;1341 1342err_remove_slot_name:1343 if (slot->pdata->name != NULL)1344 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);1345err_remove_host:1346 mmc_remove_host(mmc);1347 mmc_free_host(mmc);1348 return r;1349}1350 1351static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)1352{1353 struct mmc_host *mmc = slot->mmc;1354 1355 if (slot->pdata->name != NULL)1356 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);1357 if (slot->pdata->get_cover_state != NULL)1358 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);1359 1360 cancel_work_sync(&slot->cover_bh_work);1361 del_timer_sync(&slot->cover_timer);1362 flush_workqueue(slot->host->mmc_omap_wq);1363 1364 mmc_remove_host(mmc);1365 mmc_free_host(mmc);1366}1367 1368static int mmc_omap_probe(struct platform_device *pdev)1369{1370 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;1371 struct mmc_omap_host *host = NULL;1372 struct resource *res;1373 int i, ret = 0;1374 int irq;1375 1376 if (pdata == NULL) {1377 dev_err(&pdev->dev, "platform data missing\n");1378 return -ENXIO;1379 }1380 if (pdata->nr_slots == 0) {1381 dev_err(&pdev->dev, "no slots\n");1382 return -EPROBE_DEFER;1383 }1384 1385 host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),1386 GFP_KERNEL);1387 if (host == NULL)1388 return -ENOMEM;1389 1390 irq = platform_get_irq(pdev, 0);1391 if (irq < 0)1392 return irq;1393 1394 host->virt_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);1395 if (IS_ERR(host->virt_base))1396 return PTR_ERR(host->virt_base);1397 1398 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);1399 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);1400 1401 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);1402 timer_setup(&host->cmd_abort_timer, mmc_omap_cmd_timer, 0);1403 1404 spin_lock_init(&host->clk_lock);1405 timer_setup(&host->clk_timer, mmc_omap_clk_timer, 0);1406 1407 spin_lock_init(&host->dma_lock);1408 spin_lock_init(&host->slot_lock);1409 init_waitqueue_head(&host->slot_wq);1410 1411 host->pdata = pdata;1412 host->features = host->pdata->slots[0].features;1413 host->dev = &pdev->dev;1414 platform_set_drvdata(pdev, host);1415 1416 host->slot_switch = devm_gpiod_get_optional(host->dev, "switch",1417 GPIOD_OUT_LOW);1418 if (IS_ERR(host->slot_switch))1419 return dev_err_probe(host->dev, PTR_ERR(host->slot_switch),1420 "error looking up slot switch GPIO\n");1421 1422 host->id = pdev->id;1423 host->irq = irq;1424 host->phys_base = res->start;1425 host->iclk = clk_get(&pdev->dev, "ick");1426 if (IS_ERR(host->iclk))1427 return PTR_ERR(host->iclk);1428 clk_prepare_enable(host->iclk);1429 1430 host->fclk = clk_get(&pdev->dev, "fck");1431 if (IS_ERR(host->fclk)) {1432 ret = PTR_ERR(host->fclk);1433 goto err_free_iclk;1434 }1435 1436 ret = clk_prepare(host->fclk);1437 if (ret)1438 goto err_put_fclk;1439 1440 host->dma_tx_burst = -1;1441 host->dma_rx_burst = -1;1442 1443 host->dma_tx = dma_request_chan(&pdev->dev, "tx");1444 if (IS_ERR(host->dma_tx)) {1445 ret = PTR_ERR(host->dma_tx);1446 if (ret == -EPROBE_DEFER)1447 goto err_free_fclk;1448 1449 host->dma_tx = NULL;1450 dev_warn(host->dev, "TX DMA channel request failed\n");1451 }1452 1453 host->dma_rx = dma_request_chan(&pdev->dev, "rx");1454 if (IS_ERR(host->dma_rx)) {1455 ret = PTR_ERR(host->dma_rx);1456 if (ret == -EPROBE_DEFER) {1457 if (host->dma_tx)1458 dma_release_channel(host->dma_tx);1459 goto err_free_fclk;1460 }1461 1462 host->dma_rx = NULL;1463 dev_warn(host->dev, "RX DMA channel request failed\n");1464 }1465 1466 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);1467 if (ret)1468 goto err_free_dma;1469 1470 if (pdata->init != NULL) {1471 ret = pdata->init(&pdev->dev);1472 if (ret < 0)1473 goto err_free_irq;1474 }1475 1476 host->nr_slots = pdata->nr_slots;1477 host->reg_shift = (mmc_omap7xx() ? 1 : 2);1478 1479 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);1480 if (!host->mmc_omap_wq) {1481 ret = -ENOMEM;1482 goto err_plat_cleanup;1483 }1484 1485 for (i = 0; i < pdata->nr_slots; i++) {1486 ret = mmc_omap_new_slot(host, i);1487 if (ret < 0) {1488 while (--i >= 0)1489 mmc_omap_remove_slot(host->slots[i]);1490 1491 goto err_destroy_wq;1492 }1493 }1494 1495 return 0;1496 1497err_destroy_wq:1498 destroy_workqueue(host->mmc_omap_wq);1499err_plat_cleanup:1500 if (pdata->cleanup)1501 pdata->cleanup(&pdev->dev);1502err_free_irq:1503 free_irq(host->irq, host);1504err_free_dma:1505 if (host->dma_tx)1506 dma_release_channel(host->dma_tx);1507 if (host->dma_rx)1508 dma_release_channel(host->dma_rx);1509err_free_fclk:1510 clk_unprepare(host->fclk);1511err_put_fclk:1512 clk_put(host->fclk);1513err_free_iclk:1514 clk_disable_unprepare(host->iclk);1515 clk_put(host->iclk);1516 return ret;1517}1518 1519static void mmc_omap_remove(struct platform_device *pdev)1520{1521 struct mmc_omap_host *host = platform_get_drvdata(pdev);1522 int i;1523 1524 BUG_ON(host == NULL);1525 1526 for (i = 0; i < host->nr_slots; i++)1527 mmc_omap_remove_slot(host->slots[i]);1528 1529 if (host->pdata->cleanup)1530 host->pdata->cleanup(&pdev->dev);1531 1532 mmc_omap_fclk_enable(host, 0);1533 free_irq(host->irq, host);1534 clk_unprepare(host->fclk);1535 clk_put(host->fclk);1536 clk_disable_unprepare(host->iclk);1537 clk_put(host->iclk);1538 1539 if (host->dma_tx)1540 dma_release_channel(host->dma_tx);1541 if (host->dma_rx)1542 dma_release_channel(host->dma_rx);1543 1544 destroy_workqueue(host->mmc_omap_wq);1545}1546 1547#if IS_BUILTIN(CONFIG_OF)1548static const struct of_device_id mmc_omap_match[] = {1549 { .compatible = "ti,omap2420-mmc", },1550 { },1551};1552MODULE_DEVICE_TABLE(of, mmc_omap_match);1553#endif1554 1555static struct platform_driver mmc_omap_driver = {1556 .probe = mmc_omap_probe,1557 .remove_new = mmc_omap_remove,1558 .driver = {1559 .name = DRIVER_NAME,1560 .probe_type = PROBE_PREFER_ASYNCHRONOUS,1561 .of_match_table = of_match_ptr(mmc_omap_match),1562 },1563};1564 1565module_platform_driver(mmc_omap_driver);1566MODULE_DESCRIPTION("OMAP Multimedia Card driver");1567MODULE_LICENSE("GPL");1568MODULE_ALIAS("platform:" DRIVER_NAME);1569MODULE_AUTHOR("Juha Yrjölä");1570