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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's4 *5 * Copyright (C) 2015 Broadcom Corporation6 */7 8#include <linux/io.h>9#include <linux/iopoll.h>10#include <linux/mmc/host.h>11#include <linux/module.h>12#include <linux/of.h>13#include <linux/bitops.h>14#include <linux/delay.h>15 16#include "sdhci-cqhci.h"17#include "sdhci-pltfm.h"18#include "cqhci.h"19 20#define SDHCI_VENDOR 0x7821#define SDHCI_VENDOR_ENHANCED_STRB 0x122#define SDHCI_VENDOR_GATE_SDCLK_EN 0x223 24#define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0)25#define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1)26#define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE BIT(2)27#define BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY BIT(4)28 29#define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0)30#define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1)31 32#define SDHCI_ARASAN_CQE_BASE_ADDR 0x20033 34#define SDIO_CFG_CQ_CAPABILITY 0x4c35#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12)36 37#define SDIO_CFG_CTRL 0x038#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31)39#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30)40 41#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac42#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31)43#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0)44 45#define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V)46/* Select all SD UHS type I SDR speed above 50MB/s */47#define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)48 49struct sdhci_brcmstb_priv {50 void __iomem *cfg_regs;51 unsigned int flags;52 struct clk *base_clk;53 u32 base_freq_hz;54};55 56struct brcmstb_match_priv {57 void (*cfginit)(struct sdhci_host *host);58 void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);59 struct sdhci_ops *ops;60 const unsigned int flags;61};62 63static inline void enable_clock_gating(struct sdhci_host *host)64{65 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);66 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);67 u32 reg;68 69 if (!(priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK))70 return;71 72 reg = sdhci_readl(host, SDHCI_VENDOR);73 reg |= SDHCI_VENDOR_GATE_SDCLK_EN;74 sdhci_writel(host, reg, SDHCI_VENDOR);75}76 77static void brcmstb_reset(struct sdhci_host *host, u8 mask)78{79 sdhci_and_cqhci_reset(host, mask);80 81 /* Reset will clear this, so re-enable it */82 enable_clock_gating(host);83}84 85static void brcmstb_sdhci_reset_cmd_data(struct sdhci_host *host, u8 mask)86{87 u32 new_mask = (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) << 24;88 int ret;89 u32 reg;90 91 /*92 * SDHCI_CLOCK_CONTROL register CARD_EN and CLOCK_INT_EN bits shall93 * be set along with SOFTWARE_RESET register RESET_CMD or RESET_DATA94 * bits, hence access SDHCI_CLOCK_CONTROL register as 32-bit register95 */96 new_mask |= SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN;97 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);98 sdhci_writel(host, reg | new_mask, SDHCI_CLOCK_CONTROL);99 100 reg = sdhci_readb(host, SDHCI_SOFTWARE_RESET);101 102 ret = read_poll_timeout_atomic(sdhci_readb, reg, !(reg & mask),103 10, 10000, false,104 host, SDHCI_SOFTWARE_RESET);105 106 if (ret) {107 pr_err("%s: Reset 0x%x never completed.\n",108 mmc_hostname(host->mmc), (int)mask);109 sdhci_err_stats_inc(host, CTRL_TIMEOUT);110 sdhci_dumpregs(host);111 }112}113 114static void brcmstb_reset_74165b0(struct sdhci_host *host, u8 mask)115{116 /* take care of RESET_ALL as usual */117 if (mask & SDHCI_RESET_ALL)118 sdhci_and_cqhci_reset(host, SDHCI_RESET_ALL);119 120 /* cmd and/or data treated differently on this core */121 if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA))122 brcmstb_sdhci_reset_cmd_data(host, mask);123 124 /* Reset will clear this, so re-enable it */125 enable_clock_gating(host);126}127 128static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios)129{130 struct sdhci_host *host = mmc_priv(mmc);131 132 u32 reg;133 134 dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n",135 __func__);136 reg = readl(host->ioaddr + SDHCI_VENDOR);137 if (ios->enhanced_strobe)138 reg |= SDHCI_VENDOR_ENHANCED_STRB;139 else140 reg &= ~SDHCI_VENDOR_ENHANCED_STRB;141 writel(reg, host->ioaddr + SDHCI_VENDOR);142}143 144static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock)145{146 u16 clk;147 148 host->mmc->actual_clock = 0;149 150 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);151 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);152 153 if (clock == 0)154 return;155 156 sdhci_enable_clk(host, clk);157}158 159static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host,160 unsigned int timing)161{162 u16 ctrl_2;163 164 dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n",165 __func__, timing);166 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);167 /* Select Bus Speed Mode for host */168 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;169 if ((timing == MMC_TIMING_MMC_HS200) ||170 (timing == MMC_TIMING_UHS_SDR104))171 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;172 else if (timing == MMC_TIMING_UHS_SDR12)173 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;174 else if (timing == MMC_TIMING_SD_HS ||175 timing == MMC_TIMING_MMC_HS ||176 timing == MMC_TIMING_UHS_SDR25)177 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;178 else if (timing == MMC_TIMING_UHS_SDR50)179 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;180 else if ((timing == MMC_TIMING_UHS_DDR50) ||181 (timing == MMC_TIMING_MMC_DDR52))182 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;183 else if (timing == MMC_TIMING_MMC_HS400)184 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */185 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);186}187 188static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host)189{190 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);191 struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);192 u32 reg;193 194 /*195 * If we support a speed that requires tuning,196 * then select the delay line PHY as the clock source.197 */198 if ((host->mmc->caps & MMC_CAP_UHS_I_SDR_MASK) || (host->mmc->caps2 & MMC_CAP_HSE_MASK)) {199 reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE);200 reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE;201 reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE;202 writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE);203 }204 205 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||206 (host->mmc->caps & MMC_CAP_NEEDS_POLL)) {207 /* Force presence */208 reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL);209 reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV;210 reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN;211 writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL);212 }213}214 215static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc)216{217 sdhci_dumpregs(mmc_priv(mmc));218}219 220static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc)221{222 struct sdhci_host *host = mmc_priv(mmc);223 u32 reg;224 225 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);226 while (reg & SDHCI_DATA_AVAILABLE) {227 sdhci_readl(host, SDHCI_BUFFER);228 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);229 }230 231 sdhci_cqe_enable(mmc);232}233 234static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = {235 .enable = sdhci_brcmstb_cqe_enable,236 .disable = sdhci_cqe_disable,237 .dumpregs = sdhci_brcmstb_dumpregs,238};239 240static struct sdhci_ops sdhci_brcmstb_ops = {241 .set_clock = sdhci_set_clock,242 .set_bus_width = sdhci_set_bus_width,243 .reset = sdhci_reset,244 .set_uhs_signaling = sdhci_set_uhs_signaling,245};246 247static struct sdhci_ops sdhci_brcmstb_ops_2712 = {248 .set_clock = sdhci_set_clock,249 .set_power = sdhci_set_power_and_bus_voltage,250 .set_bus_width = sdhci_set_bus_width,251 .reset = sdhci_reset,252 .set_uhs_signaling = sdhci_set_uhs_signaling,253};254 255static struct sdhci_ops sdhci_brcmstb_ops_7216 = {256 .set_clock = sdhci_brcmstb_set_clock,257 .set_bus_width = sdhci_set_bus_width,258 .reset = brcmstb_reset,259 .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,260};261 262static struct sdhci_ops sdhci_brcmstb_ops_74165b0 = {263 .set_clock = sdhci_brcmstb_set_clock,264 .set_bus_width = sdhci_set_bus_width,265 .reset = brcmstb_reset_74165b0,266 .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,267};268 269static const struct brcmstb_match_priv match_priv_2712 = {270 .cfginit = sdhci_brcmstb_cfginit_2712,271 .ops = &sdhci_brcmstb_ops_2712,272};273 274static struct brcmstb_match_priv match_priv_7425 = {275 .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT |276 BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,277 .ops = &sdhci_brcmstb_ops,278};279 280static struct brcmstb_match_priv match_priv_7445 = {281 .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,282 .ops = &sdhci_brcmstb_ops,283};284 285static const struct brcmstb_match_priv match_priv_7216 = {286 .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,287 .hs400es = sdhci_brcmstb_hs400es,288 .ops = &sdhci_brcmstb_ops_7216,289};290 291static struct brcmstb_match_priv match_priv_74165b0 = {292 .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,293 .hs400es = sdhci_brcmstb_hs400es,294 .ops = &sdhci_brcmstb_ops_74165b0,295};296 297static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = {298 { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 },299 { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },300 { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },301 { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },302 { .compatible = "brcm,bcm74165b0-sdhci", .data = &match_priv_74165b0 },303 {},304};305 306static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask)307{308 int cmd_error = 0;309 int data_error = 0;310 311 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))312 return intmask;313 314 cqhci_irq(host->mmc, intmask, cmd_error, data_error);315 316 return 0;317}318 319static int sdhci_brcmstb_add_host(struct sdhci_host *host,320 struct sdhci_brcmstb_priv *priv)321{322 struct cqhci_host *cq_host;323 bool dma64;324 int ret;325 326 if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0)327 return sdhci_add_host(host);328 329 dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n");330 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;331 ret = sdhci_setup_host(host);332 if (ret)333 return ret;334 335 cq_host = devm_kzalloc(mmc_dev(host->mmc),336 sizeof(*cq_host), GFP_KERNEL);337 if (!cq_host) {338 ret = -ENOMEM;339 goto cleanup;340 }341 342 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;343 cq_host->ops = &sdhci_brcmstb_cqhci_ops;344 345 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;346 if (dma64) {347 dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n");348 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;349 }350 351 ret = cqhci_init(cq_host, host->mmc, dma64);352 if (ret)353 goto cleanup;354 355 ret = __sdhci_add_host(host);356 if (ret)357 goto cleanup;358 359 return 0;360 361cleanup:362 sdhci_cleanup_host(host);363 return ret;364}365 366static int sdhci_brcmstb_probe(struct platform_device *pdev)367{368 const struct brcmstb_match_priv *match_priv;369 struct sdhci_pltfm_data brcmstb_pdata;370 struct sdhci_pltfm_host *pltfm_host;371 const struct of_device_id *match;372 struct sdhci_brcmstb_priv *priv;373 u32 actual_clock_mhz;374 struct sdhci_host *host;375 struct clk *clk;376 struct clk *base_clk = NULL;377 int res;378 379 match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node);380 match_priv = match->data;381 382 dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible);383 384 clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);385 if (IS_ERR(clk))386 return dev_err_probe(&pdev->dev, PTR_ERR(clk),387 "Failed to get and enable clock from Device Tree\n");388 389 memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata));390 brcmstb_pdata.ops = match_priv->ops;391 host = sdhci_pltfm_init(pdev, &brcmstb_pdata,392 sizeof(struct sdhci_brcmstb_priv));393 if (IS_ERR(host))394 return PTR_ERR(host);395 396 pltfm_host = sdhci_priv(host);397 priv = sdhci_pltfm_priv(pltfm_host);398 if (device_property_read_bool(&pdev->dev, "supports-cqe")) {399 priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE;400 match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;401 }402 403 /* Map in the non-standard CFG registers */404 priv->cfg_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);405 if (IS_ERR(priv->cfg_regs)) {406 res = PTR_ERR(priv->cfg_regs);407 goto err;408 }409 410 sdhci_get_of_property(pdev);411 res = mmc_of_parse(host->mmc);412 if (res)413 goto err;414 415 /*416 * Automatic clock gating does not work for SD cards that may417 * voltage switch so only enable it for non-removable devices.418 */419 if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) &&420 (host->mmc->caps & MMC_CAP_NONREMOVABLE))421 priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK;422 423 /*424 * If the chip has enhanced strobe and it's enabled, add425 * callback426 */427 if (match_priv->hs400es &&428 (host->mmc->caps2 & MMC_CAP2_HS400_ES))429 host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es;430 431 if (match_priv->cfginit)432 match_priv->cfginit(host);433 434 /*435 * Supply the existing CAPS, but clear the UHS modes. This436 * will allow these modes to be specified by device tree437 * properties through mmc_of_parse().438 */439 sdhci_read_caps(host);440 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT)441 host->caps &= ~SDHCI_CAN_64BIT;442 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |443 SDHCI_SUPPORT_DDR50);444 445 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT)446 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;447 448 if (!(match_priv->flags & BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY))449 host->mmc_host_ops.card_busy = NULL;450 451 /* Change the base clock frequency if the DT property exists */452 if (device_property_read_u32(&pdev->dev, "clock-frequency",453 &priv->base_freq_hz) != 0)454 goto add_host;455 456 base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq");457 if (IS_ERR(base_clk)) {458 dev_warn(&pdev->dev, "Clock for \"sdio_freq\" not found\n");459 goto add_host;460 }461 462 res = clk_prepare_enable(base_clk);463 if (res)464 goto err;465 466 /* set improved clock rate */467 clk_set_rate(base_clk, priv->base_freq_hz);468 actual_clock_mhz = clk_get_rate(base_clk) / 1000000;469 470 host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK;471 host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT);472 /* Disable presets because they are now incorrect */473 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;474 475 dev_dbg(&pdev->dev, "Base Clock Frequency changed to %dMHz\n",476 actual_clock_mhz);477 priv->base_clk = base_clk;478 479add_host:480 res = sdhci_brcmstb_add_host(host, priv);481 if (res)482 goto err;483 484 pltfm_host->clk = clk;485 return res;486 487err:488 sdhci_pltfm_free(pdev);489 clk_disable_unprepare(base_clk);490 return res;491}492 493static void sdhci_brcmstb_shutdown(struct platform_device *pdev)494{495 sdhci_pltfm_suspend(&pdev->dev);496}497 498MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match);499 500#ifdef CONFIG_PM_SLEEP501static int sdhci_brcmstb_suspend(struct device *dev)502{503 struct sdhci_host *host = dev_get_drvdata(dev);504 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);505 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);506 507 clk_disable_unprepare(priv->base_clk);508 return sdhci_pltfm_suspend(dev);509}510 511static int sdhci_brcmstb_resume(struct device *dev)512{513 struct sdhci_host *host = dev_get_drvdata(dev);514 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);515 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);516 int ret;517 518 ret = sdhci_pltfm_resume(dev);519 if (!ret && priv->base_freq_hz) {520 ret = clk_prepare_enable(priv->base_clk);521 /*522 * Note: using clk_get_rate() below as clk_get_rate()523 * honors CLK_GET_RATE_NOCACHE attribute, but clk_set_rate()524 * may do implicit get_rate() calls that do not honor525 * CLK_GET_RATE_NOCACHE.526 */527 if (!ret &&528 (clk_get_rate(priv->base_clk) != priv->base_freq_hz))529 ret = clk_set_rate(priv->base_clk, priv->base_freq_hz);530 }531 532 return ret;533}534#endif535 536static const struct dev_pm_ops sdhci_brcmstb_pmops = {537 SET_SYSTEM_SLEEP_PM_OPS(sdhci_brcmstb_suspend, sdhci_brcmstb_resume)538};539 540static struct platform_driver sdhci_brcmstb_driver = {541 .driver = {542 .name = "sdhci-brcmstb",543 .probe_type = PROBE_PREFER_ASYNCHRONOUS,544 .pm = &sdhci_brcmstb_pmops,545 .of_match_table = of_match_ptr(sdhci_brcm_of_match),546 },547 .probe = sdhci_brcmstb_probe,548 .remove_new = sdhci_pltfm_remove,549 .shutdown = sdhci_brcmstb_shutdown,550};551 552module_platform_driver(sdhci_brcmstb_driver);553 554MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs");555MODULE_AUTHOR("Broadcom");556MODULE_LICENSE("GPL v2");557