110 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Freescale eSDHC controller driver generics for OF and pltfm.4 *5 * Copyright (c) 2007 Freescale Semiconductor, Inc.6 * Copyright (c) 2009 MontaVista Software, Inc.7 * Copyright (c) 2010 Pengutronix e.K.8 * Copyright 2020 NXP9 * Author: Wolfram Sang <kernel@pengutronix.de>10 */11 12#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H13#define _DRIVERS_MMC_SDHCI_ESDHC_H14 15/*16 * Ops and quirks for the Freescale eSDHC controller.17 */18 19#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \20 SDHCI_QUIRK_32BIT_DMA_ADDR | \21 SDHCI_QUIRK_NO_BUSY_IRQ | \22 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \23 SDHCI_QUIRK_PIO_NEEDS_DELAY | \24 SDHCI_QUIRK_NO_HISPD_BIT)25 26/* pltfm-specific */27#define ESDHC_HOST_CONTROL_LE 0x2028 29/*30 * eSDHC register definition31 */32 33/* Present State Register */34#define ESDHC_PRSSTAT 0x2435#define ESDHC_CLOCK_GATE_OFF 0x0000008036#define ESDHC_CLOCK_STABLE 0x0000000837 38/* Protocol Control Register */39#define ESDHC_PROCTL 0x2840#define ESDHC_VOLT_SEL 0x0000040041#define ESDHC_CTRL_4BITBUS (0x1 << 1)42#define ESDHC_CTRL_8BITBUS (0x2 << 1)43#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)44#define ESDHC_HOST_CONTROL_RES 0x0145 46/* System Control Register */47#define ESDHC_SYSTEM_CONTROL 0x2c48#define ESDHC_CLOCK_MASK 0x0000fff049#define ESDHC_PREDIV_SHIFT 850#define ESDHC_DIVIDER_SHIFT 451#define ESDHC_CLOCK_SDCLKEN 0x0000000852#define ESDHC_CLOCK_PEREN 0x0000000453#define ESDHC_CLOCK_HCKEN 0x0000000254#define ESDHC_CLOCK_IPGEN 0x0000000155 56/* System Control 2 Register */57#define ESDHC_SYSTEM_CONTROL_2 0x3c58#define ESDHC_SMPCLKSEL 0x0080000059#define ESDHC_EXTN 0x0040000060 61/* Host Controller Capabilities Register 2 */62#define ESDHC_CAPABILITIES_1 0x11463 64/* Tuning Block Control Register */65#define ESDHC_TBCTL 0x12066#define ESDHC_HS400_WNDW_ADJUST 0x0000004067#define ESDHC_HS400_MODE 0x0000001068#define ESDHC_TB_EN 0x0000000469#define ESDHC_TB_MODE_MASK 0x0000000370#define ESDHC_TB_MODE_SW 0x0000000371#define ESDHC_TB_MODE_3 0x0000000272 73#define ESDHC_TBSTAT 0x12474 75#define ESDHC_TBPTR 0x12876#define ESDHC_WNDW_STRT_PTR_SHIFT 877#define ESDHC_WNDW_STRT_PTR_MASK (0x7f << 8)78#define ESDHC_WNDW_END_PTR_MASK 0x7f79 80/* SD Clock Control Register */81#define ESDHC_SDCLKCTL 0x14482#define ESDHC_LPBK_CLK_SEL 0x8000000083#define ESDHC_CMD_CLK_CTL 0x0000800084 85/* SD Timing Control Register */86#define ESDHC_SDTIMNGCTL 0x14887#define ESDHC_FLW_CTL_BG 0x0000800088 89/* DLL Config 0 Register */90#define ESDHC_DLLCFG0 0x16091#define ESDHC_DLL_ENABLE 0x8000000092#define ESDHC_DLL_RESET 0x4000000093#define ESDHC_DLL_FREQ_SEL 0x0800000094 95/* DLL Config 1 Register */96#define ESDHC_DLLCFG1 0x16497#define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x8000000098 99/* DLL Status 0 Register */100#define ESDHC_DLLSTAT0 0x170101#define ESDHC_DLL_STS_SLV_LOCK 0x08000000102 103/* Control Register for DMA transfer */104#define ESDHC_DMA_SYSCTL 0x40c105#define ESDHC_PERIPHERAL_CLK_SEL 0x00080000106#define ESDHC_FLUSH_ASYNC_FIFO 0x00040000107#define ESDHC_DMA_SNOOP 0x00000040108 109#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */110