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1// SPDX-License-Identifier: GPL-2.0-or-later2/* Copyright (C) 2019 ASPEED Technology Inc. */3/* Copyright (C) 2019 IBM Corp. */4 5#include <linux/clk.h>6#include <linux/delay.h>7#include <linux/device.h>8#include <linux/io.h>9#include <linux/math64.h>10#include <linux/mmc/host.h>11#include <linux/module.h>12#include <linux/of_address.h>13#include <linux/of.h>14#include <linux/of_platform.h>15#include <linux/platform_device.h>16#include <linux/spinlock.h>17 18#include "sdhci-pltfm.h"19 20#define ASPEED_SDC_INFO 0x0021#define ASPEED_SDC_S1_MMC8 BIT(25)22#define ASPEED_SDC_S0_MMC8 BIT(24)23#define ASPEED_SDC_PHASE 0xf424#define ASPEED_SDC_S1_PHASE_IN GENMASK(25, 21)25#define ASPEED_SDC_S0_PHASE_IN GENMASK(20, 16)26#define ASPEED_SDC_S1_PHASE_OUT GENMASK(15, 11)27#define ASPEED_SDC_S1_PHASE_IN_EN BIT(10)28#define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8)29#define ASPEED_SDC_S0_PHASE_OUT GENMASK(7, 3)30#define ASPEED_SDC_S0_PHASE_IN_EN BIT(2)31#define ASPEED_SDC_S0_PHASE_OUT_EN GENMASK(1, 0)32#define ASPEED_SDC_PHASE_MAX 3133 34/* SDIO{10,20} */35#define ASPEED_SDC_CAP1_1_8V (0 * 32 + 26)36/* SDIO{14,24} */37#define ASPEED_SDC_CAP2_SDR104 (1 * 32 + 1)38 39struct aspeed_sdc {40 struct clk *clk;41 struct resource *res;42 43 spinlock_t lock;44 void __iomem *regs;45};46 47struct aspeed_sdhci_tap_param {48 bool valid;49 50#define ASPEED_SDHCI_TAP_PARAM_INVERT_CLK BIT(4)51 u8 in;52 u8 out;53};54 55struct aspeed_sdhci_tap_desc {56 u32 tap_mask;57 u32 enable_mask;58 u8 enable_value;59};60 61struct aspeed_sdhci_phase_desc {62 struct aspeed_sdhci_tap_desc in;63 struct aspeed_sdhci_tap_desc out;64};65 66struct aspeed_sdhci_pdata {67 unsigned int clk_div_start;68 const struct aspeed_sdhci_phase_desc *phase_desc;69 size_t nr_phase_descs;70};71 72struct aspeed_sdhci {73 const struct aspeed_sdhci_pdata *pdata;74 struct aspeed_sdc *parent;75 u32 width_mask;76 struct mmc_clk_phase_map phase_map;77 const struct aspeed_sdhci_phase_desc *phase_desc;78};79 80/*81 * The function sets the mirror register for updating82 * capbilities of the current slot.83 *84 * slot | capability | caps_reg | mirror_reg85 * -----|-------------|----------|------------86 * 0 | CAP1_1_8V | SDIO140 | SDIO1087 * 0 | CAP2_SDR104 | SDIO144 | SDIO1488 * 1 | CAP1_1_8V | SDIO240 | SDIO2089 * 1 | CAP2_SDR104 | SDIO244 | SDIO2490 */91static void aspeed_sdc_set_slot_capability(struct sdhci_host *host, struct aspeed_sdc *sdc,92 int capability, bool enable, u8 slot)93{94 u32 mirror_reg_offset;95 u32 cap_val;96 u8 cap_reg;97 98 if (slot > 1)99 return;100 101 cap_reg = capability / 32;102 cap_val = sdhci_readl(host, 0x40 + (cap_reg * 4));103 if (enable)104 cap_val |= BIT(capability % 32);105 else106 cap_val &= ~BIT(capability % 32);107 mirror_reg_offset = ((slot + 1) * 0x10) + (cap_reg * 4);108 writel(cap_val, sdc->regs + mirror_reg_offset);109}110 111static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc,112 struct aspeed_sdhci *sdhci,113 bool bus8)114{115 u32 info;116 117 /* Set/clear 8 bit mode */118 spin_lock(&sdc->lock);119 info = readl(sdc->regs + ASPEED_SDC_INFO);120 if (bus8)121 info |= sdhci->width_mask;122 else123 info &= ~sdhci->width_mask;124 writel(info, sdc->regs + ASPEED_SDC_INFO);125 spin_unlock(&sdc->lock);126}127 128static u32129aspeed_sdc_set_phase_tap(const struct aspeed_sdhci_tap_desc *desc,130 u8 tap, bool enable, u32 reg)131{132 reg &= ~(desc->enable_mask | desc->tap_mask);133 if (enable) {134 reg |= tap << __ffs(desc->tap_mask);135 reg |= desc->enable_value << __ffs(desc->enable_mask);136 }137 138 return reg;139}140 141static void142aspeed_sdc_set_phase_taps(struct aspeed_sdc *sdc,143 const struct aspeed_sdhci_phase_desc *desc,144 const struct aspeed_sdhci_tap_param *taps)145{146 u32 reg;147 148 spin_lock(&sdc->lock);149 reg = readl(sdc->regs + ASPEED_SDC_PHASE);150 151 reg = aspeed_sdc_set_phase_tap(&desc->in, taps->in, taps->valid, reg);152 reg = aspeed_sdc_set_phase_tap(&desc->out, taps->out, taps->valid, reg);153 154 writel(reg, sdc->regs + ASPEED_SDC_PHASE);155 spin_unlock(&sdc->lock);156}157 158#define PICOSECONDS_PER_SECOND 1000000000000ULL159#define ASPEED_SDHCI_NR_TAPS 15160/* Measured value with *handwave* environmentals and static loading */161#define ASPEED_SDHCI_MAX_TAP_DELAY_PS 1253162static int aspeed_sdhci_phase_to_tap(struct device *dev, unsigned long rate_hz,163 int phase_deg)164{165 u64 phase_period_ps;166 u64 prop_delay_ps;167 u64 clk_period_ps;168 unsigned int tap;169 u8 inverted;170 171 phase_deg %= 360;172 173 if (phase_deg >= 180) {174 inverted = ASPEED_SDHCI_TAP_PARAM_INVERT_CLK;175 phase_deg -= 180;176 dev_dbg(dev,177 "Inverting clock to reduce phase correction from %d to %d degrees\n",178 phase_deg + 180, phase_deg);179 } else {180 inverted = 0;181 }182 183 prop_delay_ps = ASPEED_SDHCI_MAX_TAP_DELAY_PS / ASPEED_SDHCI_NR_TAPS;184 clk_period_ps = div_u64(PICOSECONDS_PER_SECOND, (u64)rate_hz);185 phase_period_ps = div_u64((u64)phase_deg * clk_period_ps, 360ULL);186 187 tap = div_u64(phase_period_ps, prop_delay_ps);188 if (tap > ASPEED_SDHCI_NR_TAPS) {189 dev_dbg(dev,190 "Requested out of range phase tap %d for %d degrees of phase compensation at %luHz, clamping to tap %d\n",191 tap, phase_deg, rate_hz, ASPEED_SDHCI_NR_TAPS);192 tap = ASPEED_SDHCI_NR_TAPS;193 }194 195 return inverted | tap;196}197 198static void199aspeed_sdhci_phases_to_taps(struct device *dev, unsigned long rate,200 const struct mmc_clk_phase *phases,201 struct aspeed_sdhci_tap_param *taps)202{203 taps->valid = phases->valid;204 205 if (!phases->valid)206 return;207 208 taps->in = aspeed_sdhci_phase_to_tap(dev, rate, phases->in_deg);209 taps->out = aspeed_sdhci_phase_to_tap(dev, rate, phases->out_deg);210}211 212static void213aspeed_sdhci_configure_phase(struct sdhci_host *host, unsigned long rate)214{215 struct aspeed_sdhci_tap_param _taps = {0}, *taps = &_taps;216 struct mmc_clk_phase *params;217 struct aspeed_sdhci *sdhci;218 struct device *dev;219 220 dev = mmc_dev(host->mmc);221 sdhci = sdhci_pltfm_priv(sdhci_priv(host));222 223 if (!sdhci->phase_desc)224 return;225 226 params = &sdhci->phase_map.phase[host->timing];227 aspeed_sdhci_phases_to_taps(dev, rate, params, taps);228 aspeed_sdc_set_phase_taps(sdhci->parent, sdhci->phase_desc, taps);229 dev_dbg(dev,230 "Using taps [%d, %d] for [%d, %d] degrees of phase correction at %luHz (%d)\n",231 taps->in & ASPEED_SDHCI_NR_TAPS,232 taps->out & ASPEED_SDHCI_NR_TAPS,233 params->in_deg, params->out_deg, rate, host->timing);234}235 236static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)237{238 struct sdhci_pltfm_host *pltfm_host;239 unsigned long parent, bus;240 struct aspeed_sdhci *sdhci;241 int div;242 u16 clk;243 244 pltfm_host = sdhci_priv(host);245 sdhci = sdhci_pltfm_priv(pltfm_host);246 247 parent = clk_get_rate(pltfm_host->clk);248 249 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);250 251 if (clock == 0)252 return;253 254 if (WARN_ON(clock > host->max_clk))255 clock = host->max_clk;256 257 /*258 * Regarding the AST2600:259 *260 * If (EMMC12C[7:6], EMMC12C[15:8] == 0) then261 * period of SDCLK = period of SDMCLK.262 *263 * If (EMMC12C[7:6], EMMC12C[15:8] != 0) then264 * period of SDCLK = period of SDMCLK * 2 * (EMMC12C[7:6], EMMC[15:8])265 *266 * If you keep EMMC12C[7:6] = 0 and EMMC12C[15:8] as one-hot,267 * 0x1/0x2/0x4/etc, you will find it is compatible to AST2400 or AST2500268 *269 * Keep the one-hot behaviour for backwards compatibility except for270 * supporting the value 0 in (EMMC12C[7:6], EMMC12C[15:8]), and capture271 * the 0-value capability in clk_div_start.272 */273 for (div = sdhci->pdata->clk_div_start; div < 256; div *= 2) {274 bus = parent / div;275 if (bus <= clock)276 break;277 }278 279 div >>= 1;280 281 clk = div << SDHCI_DIVIDER_SHIFT;282 283 aspeed_sdhci_configure_phase(host, bus);284 285 sdhci_enable_clk(host, clk);286}287 288static unsigned int aspeed_sdhci_get_max_clock(struct sdhci_host *host)289{290 if (host->mmc->f_max)291 return host->mmc->f_max;292 293 return sdhci_pltfm_clk_get_max_clock(host);294}295 296static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width)297{298 struct sdhci_pltfm_host *pltfm_priv;299 struct aspeed_sdhci *aspeed_sdhci;300 struct aspeed_sdc *aspeed_sdc;301 u8 ctrl;302 303 pltfm_priv = sdhci_priv(host);304 aspeed_sdhci = sdhci_pltfm_priv(pltfm_priv);305 aspeed_sdc = aspeed_sdhci->parent;306 307 /* Set/clear 8-bit mode */308 aspeed_sdc_configure_8bit_mode(aspeed_sdc, aspeed_sdhci,309 width == MMC_BUS_WIDTH_8);310 311 /* Set/clear 1 or 4 bit mode */312 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);313 if (width == MMC_BUS_WIDTH_4)314 ctrl |= SDHCI_CTRL_4BITBUS;315 else316 ctrl &= ~SDHCI_CTRL_4BITBUS;317 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);318}319 320static u32 aspeed_sdhci_readl(struct sdhci_host *host, int reg)321{322 u32 val = readl(host->ioaddr + reg);323 324 if (unlikely(reg == SDHCI_PRESENT_STATE) &&325 (host->mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH))326 val ^= SDHCI_CARD_PRESENT;327 328 return val;329}330 331static const struct sdhci_ops aspeed_sdhci_ops = {332 .read_l = aspeed_sdhci_readl,333 .set_clock = aspeed_sdhci_set_clock,334 .get_max_clock = aspeed_sdhci_get_max_clock,335 .set_bus_width = aspeed_sdhci_set_bus_width,336 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,337 .reset = sdhci_reset,338 .set_uhs_signaling = sdhci_set_uhs_signaling,339};340 341static const struct sdhci_pltfm_data aspeed_sdhci_pdata = {342 .ops = &aspeed_sdhci_ops,343 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,344};345 346static inline int aspeed_sdhci_calculate_slot(struct aspeed_sdhci *dev,347 struct resource *res)348{349 resource_size_t delta;350 351 if (!res || resource_type(res) != IORESOURCE_MEM)352 return -EINVAL;353 354 if (res->start < dev->parent->res->start)355 return -EINVAL;356 357 delta = res->start - dev->parent->res->start;358 if (delta & (0x100 - 1))359 return -EINVAL;360 361 return (delta / 0x100) - 1;362}363 364static int aspeed_sdhci_probe(struct platform_device *pdev)365{366 const struct aspeed_sdhci_pdata *aspeed_pdata;367 struct device_node *np = pdev->dev.of_node;368 struct sdhci_pltfm_host *pltfm_host;369 struct aspeed_sdhci *dev;370 struct sdhci_host *host;371 struct resource *res;372 int slot;373 int ret;374 375 aspeed_pdata = of_device_get_match_data(&pdev->dev);376 if (!aspeed_pdata) {377 dev_err(&pdev->dev, "Missing platform configuration data\n");378 return -EINVAL;379 }380 381 host = sdhci_pltfm_init(pdev, &aspeed_sdhci_pdata, sizeof(*dev));382 if (IS_ERR(host))383 return PTR_ERR(host);384 385 pltfm_host = sdhci_priv(host);386 dev = sdhci_pltfm_priv(pltfm_host);387 dev->pdata = aspeed_pdata;388 dev->parent = dev_get_drvdata(pdev->dev.parent);389 390 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);391 slot = aspeed_sdhci_calculate_slot(dev, res);392 393 if (slot < 0)394 return slot;395 else if (slot >= 2)396 return -EINVAL;397 398 if (slot < dev->pdata->nr_phase_descs) {399 dev->phase_desc = &dev->pdata->phase_desc[slot];400 } else {401 dev_info(&pdev->dev,402 "Phase control not supported for slot %d\n", slot);403 dev->phase_desc = NULL;404 }405 406 dev->width_mask = !slot ? ASPEED_SDC_S0_MMC8 : ASPEED_SDC_S1_MMC8;407 408 dev_info(&pdev->dev, "Configured for slot %d\n", slot);409 410 sdhci_get_of_property(pdev);411 412 if (of_property_read_bool(np, "mmc-hs200-1_8v") ||413 of_property_read_bool(np, "sd-uhs-sdr104")) {414 aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP1_1_8V,415 true, slot);416 }417 418 if (of_property_read_bool(np, "sd-uhs-sdr104")) {419 aspeed_sdc_set_slot_capability(host, dev->parent, ASPEED_SDC_CAP2_SDR104,420 true, slot);421 }422 423 pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);424 if (IS_ERR(pltfm_host->clk))425 return PTR_ERR(pltfm_host->clk);426 427 ret = clk_prepare_enable(pltfm_host->clk);428 if (ret) {429 dev_err(&pdev->dev, "Unable to enable SDIO clock\n");430 goto err_pltfm_free;431 }432 433 ret = mmc_of_parse(host->mmc);434 if (ret)435 goto err_sdhci_add;436 437 if (dev->phase_desc)438 mmc_of_parse_clk_phase(&pdev->dev, &dev->phase_map);439 440 ret = sdhci_add_host(host);441 if (ret)442 goto err_sdhci_add;443 444 return 0;445 446err_sdhci_add:447 clk_disable_unprepare(pltfm_host->clk);448err_pltfm_free:449 sdhci_pltfm_free(pdev);450 return ret;451}452 453static void aspeed_sdhci_remove(struct platform_device *pdev)454{455 struct sdhci_pltfm_host *pltfm_host;456 struct sdhci_host *host;457 458 host = platform_get_drvdata(pdev);459 pltfm_host = sdhci_priv(host);460 461 sdhci_remove_host(host, 0);462 463 clk_disable_unprepare(pltfm_host->clk);464 465 sdhci_pltfm_free(pdev);466}467 468static const struct aspeed_sdhci_pdata ast2400_sdhci_pdata = {469 .clk_div_start = 2,470};471 472static const struct aspeed_sdhci_phase_desc ast2600_sdhci_phase[] = {473 /* SDHCI/Slot 0 */474 [0] = {475 .in = {476 .tap_mask = ASPEED_SDC_S0_PHASE_IN,477 .enable_mask = ASPEED_SDC_S0_PHASE_IN_EN,478 .enable_value = 1,479 },480 .out = {481 .tap_mask = ASPEED_SDC_S0_PHASE_OUT,482 .enable_mask = ASPEED_SDC_S0_PHASE_OUT_EN,483 .enable_value = 3,484 },485 },486 /* SDHCI/Slot 1 */487 [1] = {488 .in = {489 .tap_mask = ASPEED_SDC_S1_PHASE_IN,490 .enable_mask = ASPEED_SDC_S1_PHASE_IN_EN,491 .enable_value = 1,492 },493 .out = {494 .tap_mask = ASPEED_SDC_S1_PHASE_OUT,495 .enable_mask = ASPEED_SDC_S1_PHASE_OUT_EN,496 .enable_value = 3,497 },498 },499};500 501static const struct aspeed_sdhci_pdata ast2600_sdhci_pdata = {502 .clk_div_start = 1,503 .phase_desc = ast2600_sdhci_phase,504 .nr_phase_descs = ARRAY_SIZE(ast2600_sdhci_phase),505};506 507static const struct of_device_id aspeed_sdhci_of_match[] = {508 { .compatible = "aspeed,ast2400-sdhci", .data = &ast2400_sdhci_pdata, },509 { .compatible = "aspeed,ast2500-sdhci", .data = &ast2400_sdhci_pdata, },510 { .compatible = "aspeed,ast2600-sdhci", .data = &ast2600_sdhci_pdata, },511 { }512};513MODULE_DEVICE_TABLE(of, aspeed_sdhci_of_match);514 515static struct platform_driver aspeed_sdhci_driver = {516 .driver = {517 .name = "sdhci-aspeed",518 .probe_type = PROBE_PREFER_ASYNCHRONOUS,519 .of_match_table = aspeed_sdhci_of_match,520 },521 .probe = aspeed_sdhci_probe,522 .remove_new = aspeed_sdhci_remove,523};524 525static int aspeed_sdc_probe(struct platform_device *pdev)526 527{528 struct device_node *parent, *child;529 struct aspeed_sdc *sdc;530 int ret;531 532 sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);533 if (!sdc)534 return -ENOMEM;535 536 spin_lock_init(&sdc->lock);537 538 sdc->clk = devm_clk_get(&pdev->dev, NULL);539 if (IS_ERR(sdc->clk))540 return PTR_ERR(sdc->clk);541 542 ret = clk_prepare_enable(sdc->clk);543 if (ret) {544 dev_err(&pdev->dev, "Unable to enable SDCLK\n");545 return ret;546 }547 548 sdc->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &sdc->res);549 if (IS_ERR(sdc->regs)) {550 ret = PTR_ERR(sdc->regs);551 goto err_clk;552 }553 554 dev_set_drvdata(&pdev->dev, sdc);555 556 parent = pdev->dev.of_node;557 for_each_available_child_of_node(parent, child) {558 struct platform_device *cpdev;559 560 cpdev = of_platform_device_create(child, NULL, &pdev->dev);561 if (!cpdev) {562 of_node_put(child);563 ret = -ENODEV;564 goto err_clk;565 }566 }567 568 return 0;569 570err_clk:571 clk_disable_unprepare(sdc->clk);572 return ret;573}574 575static void aspeed_sdc_remove(struct platform_device *pdev)576{577 struct aspeed_sdc *sdc = dev_get_drvdata(&pdev->dev);578 579 clk_disable_unprepare(sdc->clk);580}581 582static const struct of_device_id aspeed_sdc_of_match[] = {583 { .compatible = "aspeed,ast2400-sd-controller", },584 { .compatible = "aspeed,ast2500-sd-controller", },585 { .compatible = "aspeed,ast2600-sd-controller", },586 { }587};588 589MODULE_DEVICE_TABLE(of, aspeed_sdc_of_match);590 591static struct platform_driver aspeed_sdc_driver = {592 .driver = {593 .name = "sd-controller-aspeed",594 .probe_type = PROBE_PREFER_ASYNCHRONOUS,595 .pm = &sdhci_pltfm_pmops,596 .of_match_table = aspeed_sdc_of_match,597 },598 .probe = aspeed_sdc_probe,599 .remove_new = aspeed_sdc_remove,600};601 602#if defined(CONFIG_MMC_SDHCI_OF_ASPEED_TEST)603#include "sdhci-of-aspeed-test.c"604#endif605 606static int __init aspeed_sdc_init(void)607{608 int rc;609 610 rc = platform_driver_register(&aspeed_sdhci_driver);611 if (rc < 0)612 return rc;613 614 rc = platform_driver_register(&aspeed_sdc_driver);615 if (rc < 0)616 platform_driver_unregister(&aspeed_sdhci_driver);617 618 return rc;619}620module_init(aspeed_sdc_init);621 622static void __exit aspeed_sdc_exit(void)623{624 platform_driver_unregister(&aspeed_sdc_driver);625 platform_driver_unregister(&aspeed_sdhci_driver);626}627module_exit(aspeed_sdc_exit);628 629MODULE_DESCRIPTION("Driver for the ASPEED SD/SDIO/SDHCI Controllers");630MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>");631MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>");632MODULE_LICENSE("GPL");633