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1// SPDX-License-Identifier: GPL-2.02/*3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller4 *5 * Copyright (C) 2018 Synaptics Incorporated6 *7 * Author: Jisheng Zhang <jszhang@kernel.org>8 */9 10#include <linux/acpi.h>11#include <linux/arm-smccc.h>12#include <linux/bitfield.h>13#include <linux/clk.h>14#include <linux/dma-mapping.h>15#include <linux/iopoll.h>16#include <linux/kernel.h>17#include <linux/module.h>18#include <linux/of.h>19#include <linux/platform_device.h>20#include <linux/pm_runtime.h>21#include <linux/reset.h>22#include <linux/sizes.h>23 24#include "sdhci-pltfm.h"25#include "cqhci.h"26 27#define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)28 29/* DWCMSHC specific Mode Select value */30#define DWCMSHC_CTRL_HS400 0x731 32/* DWC IP vendor area 1 pointer */33#define DWCMSHC_P_VENDOR_AREA1 0xe834#define DWCMSHC_AREA1_MASK GENMASK(11, 0)35/* Offset inside the vendor area 1 */36#define DWCMSHC_HOST_CTRL3 0x837#define DWCMSHC_EMMC_CONTROL 0x2c38#define DWCMSHC_CARD_IS_EMMC BIT(0)39#define DWCMSHC_ENHANCED_STROBE BIT(8)40#define DWCMSHC_EMMC_ATCTRL 0x4041/* Tuning and auto-tuning fields in AT_CTRL_R control register */42#define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */43#define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */44#define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */45#define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */46#define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */47#define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */48#define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */49#define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase code change */50#define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */51#define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */52#define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */53#define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */54#define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */55#define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */56 57/* DWC IP vendor area 2 pointer */58#define DWCMSHC_P_VENDOR_AREA2 0xea59 60/* Sophgo CV18XX specific Registers */61#define CV18XX_SDHCI_MSHC_CTRL 0x0062#define CV18XX_EMMC_FUNC_EN BIT(0)63#define CV18XX_LATANCY_1T BIT(1)64#define CV18XX_SDHCI_PHY_TX_RX_DLY 0x4065#define CV18XX_PHY_TX_DLY_MSK GENMASK(6, 0)66#define CV18XX_PHY_TX_SRC_MSK GENMASK(9, 8)67#define CV18XX_PHY_TX_SRC_INVERT_CLK_TX 0x168#define CV18XX_PHY_RX_DLY_MSK GENMASK(22, 16)69#define CV18XX_PHY_RX_SRC_MSK GENMASK(25, 24)70#define CV18XX_PHY_RX_SRC_INVERT_RX_CLK 0x171#define CV18XX_SDHCI_PHY_CONFIG 0x4c72#define CV18XX_PHY_TX_BPS BIT(0)73 74#define CV18XX_TUNE_MAX 12875#define CV18XX_TUNE_STEP 176#define CV18XX_RETRY_TUNING_MAX 5077 78/* Rockchip specific Registers */79#define DWCMSHC_EMMC_DLL_CTRL 0x80080#define DWCMSHC_EMMC_DLL_RXCLK 0x80481#define DWCMSHC_EMMC_DLL_TXCLK 0x80882#define DWCMSHC_EMMC_DLL_STRBIN 0x80c83#define DECMSHC_EMMC_DLL_CMDOUT 0x81084#define DWCMSHC_EMMC_DLL_STATUS0 0x84085#define DWCMSHC_EMMC_DLL_START BIT(0)86#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)87#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)88#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 2989#define DWCMSHC_EMMC_DLL_START_POINT 1690#define DWCMSHC_EMMC_DLL_INC 891#define DWCMSHC_EMMC_DLL_BYPASS BIT(24)92#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)93#define DLL_TXCLK_TAPNUM_DEFAULT 0x1094#define DLL_TXCLK_TAPNUM_90_DEGREES 0xA95#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)96#define DLL_STRBIN_TAPNUM_DEFAULT 0x897#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)98#define DLL_STRBIN_DELAY_NUM_SEL BIT(26)99#define DLL_STRBIN_DELAY_NUM_OFFSET 16100#define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16101#define DLL_RXCLK_NO_INVERTER 1102#define DLL_RXCLK_INVERTER 0103#define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8104#define DLL_RXCLK_ORI_GATE BIT(31)105#define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)106#define DLL_CMDOUT_SRC_CLK_NEG BIT(28)107#define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)108 109#define DLL_LOCK_WO_TMOUT(x) \110 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \111 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))112 113/* PHY register area pointer */114#define DWC_MSHC_PTR_PHY_R 0x300115 116/* PHY general configuration */117#define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00)118#define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */119#define PHY_CNFG_PHY_PWRGOOD_MASK BIT_MASK(1) /* bit [1] */120#define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */121#define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */122#define PHY_CNFG_PAD_SP_SG2042 0x09 /* PMOS TX drive strength for SG2042 */123#define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */124#define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */125#define PHY_CNFG_PAD_SN_SG2042 0x08 /* NMOS TX drive strength for SG2042 */126 127/* PHY command/response pad settings */128#define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04)129 130/* PHY data pad settings */131#define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06)132 133/* PHY clock pad settings */134#define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08)135 136/* PHY strobe pad settings */137#define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a)138 139/* PHY reset pad settings */140#define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c)141 142/* Bitfields are common for all pad settings */143#define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */144#define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */145 146#define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */147#define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */148#define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */149 150#define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */151#define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */152#define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */153#define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */154#define PHY_PAD_TXSLEW_CTRL_N_SG2042 0x2 /* Slew control for N-Type pad TX for SG2042 */155 156/* PHY CLK delay line settings */157#define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d)158#define PHY_SDCLKDL_CNFG_EXTDLY_EN BIT(0)159#define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */160 161/* PHY CLK delay line delay code */162#define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e)163#define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */164#define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */165#define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */166 167#define PHY_SMPLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x20)168#define PHY_SMPLDL_CNFG_BYPASS_EN BIT(1)169 170/* PHY drift_cclk_rx delay line configuration setting */171#define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21)172#define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */173#define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */174#define PHY_ATDL_CNFG_INPSEL_SG2042 0x2 /* delay line input source for SG2042 */175 176/* PHY DLL control settings */177#define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24)178#define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */179#define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */180 181/* PHY DLL configuration register 1 */182#define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25)183#define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */184#define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */185#define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */186 187/* PHY DLL configuration register 2 */188#define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26)189#define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */190 191/* PHY DLL master and slave delay line configuration settings */192#define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28)193#define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */194#define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */195 196#define FLAG_IO_FIXED_1V8 BIT(0)197 198#define BOUNDARY_OK(addr, len) \199 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))200 201#define DWCMSHC_SDHCI_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \202 SDHCI_TRNS_BLK_CNT_EN | \203 SDHCI_TRNS_DMA)204 205/* SMC call for BlueField-3 eMMC RST_N */206#define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007207 208enum dwcmshc_rk_type {209 DWCMSHC_RK3568,210 DWCMSHC_RK3588,211};212 213struct rk35xx_priv {214 struct reset_control *reset;215 enum dwcmshc_rk_type devtype;216 u8 txclk_tapnum;217};218 219#define DWCMSHC_MAX_OTHER_CLKS 3220 221struct dwcmshc_priv {222 struct clk *bus_clk;223 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA1 reg */224 int vendor_specific_area2; /* P_VENDOR_SPECIFIC_AREA2 reg */225 226 int num_other_clks;227 struct clk_bulk_data other_clks[DWCMSHC_MAX_OTHER_CLKS];228 229 void *priv; /* pointer to SoC private stuff */230 u16 delay_line;231 u16 flags;232};233 234struct dwcmshc_pltfm_data {235 const struct sdhci_pltfm_data pdata;236 int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv);237 void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv);238};239 240static int dwcmshc_get_enable_other_clks(struct device *dev,241 struct dwcmshc_priv *priv,242 int num_clks,243 const char * const clk_ids[])244{245 int err;246 247 if (num_clks > DWCMSHC_MAX_OTHER_CLKS)248 return -EINVAL;249 250 for (int i = 0; i < num_clks; i++)251 priv->other_clks[i].id = clk_ids[i];252 253 err = devm_clk_bulk_get_optional(dev, num_clks, priv->other_clks);254 if (err) {255 dev_err(dev, "failed to get clocks %d\n", err);256 return err;257 }258 259 err = clk_bulk_prepare_enable(num_clks, priv->other_clks);260 if (err)261 dev_err(dev, "failed to enable clocks %d\n", err);262 263 priv->num_other_clks = num_clks;264 265 return err;266}267 268/*269 * If DMA addr spans 128MB boundary, we split the DMA transfer into two270 * so that each DMA transfer doesn't exceed the boundary.271 */272static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,273 dma_addr_t addr, int len, unsigned int cmd)274{275 int tmplen, offset;276 277 if (likely(!len || BOUNDARY_OK(addr, len))) {278 sdhci_adma_write_desc(host, desc, addr, len, cmd);279 return;280 }281 282 offset = addr & (SZ_128M - 1);283 tmplen = SZ_128M - offset;284 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);285 286 addr += tmplen;287 len -= tmplen;288 sdhci_adma_write_desc(host, desc, addr, len, cmd);289}290 291static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)292{293 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);294 295 if (pltfm_host->clk)296 return sdhci_pltfm_clk_get_max_clock(host);297 else298 return pltfm_host->clock;299}300 301static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)302{303 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);304 305 return clk_round_rate(pltfm_host->clk, ULONG_MAX);306}307 308static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,309 struct mmc_request *mrq)310{311 struct sdhci_host *host = mmc_priv(mmc);312 313 /*314 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit315 * block count register which doesn't support stuff bits of316 * CMD23 argument on dwcmsch host controller.317 */318 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF))319 host->flags &= ~SDHCI_AUTO_CMD23;320 else321 host->flags |= SDHCI_AUTO_CMD23;322}323 324static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq)325{326 dwcmshc_check_auto_cmd23(mmc, mrq);327 328 sdhci_request(mmc, mrq);329}330 331static void dwcmshc_phy_1_8v_init(struct sdhci_host *host)332{333 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);334 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);335 u32 val;336 337 /* deassert phy reset & set tx drive strength */338 val = PHY_CNFG_RSTN_DEASSERT;339 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP);340 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN);341 sdhci_writel(host, val, PHY_CNFG_R);342 343 /* disable delay line */344 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);345 346 /* set delay line */347 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R);348 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);349 350 /* enable delay lane */351 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);352 val &= ~(PHY_SDCLKDL_CNFG_UPDATE);353 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);354 355 /* configure phy pads */356 val = PHY_PAD_RXSEL_1V8;357 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);358 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);359 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);360 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);361 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);362 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);363 364 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);365 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);366 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);367 368 val = PHY_PAD_RXSEL_1V8;369 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);370 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);371 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);372 sdhci_writew(host, val, PHY_STBPAD_CNFG_R);373 374 /* enable data strobe mode */375 sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL),376 PHY_DLLDL_CNFG_R);377 378 /* enable phy dll */379 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);380}381 382static void dwcmshc_phy_3_3v_init(struct sdhci_host *host)383{384 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);385 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);386 u32 val;387 388 /* deassert phy reset & set tx drive strength */389 val = PHY_CNFG_RSTN_DEASSERT;390 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP);391 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN);392 sdhci_writel(host, val, PHY_CNFG_R);393 394 /* disable delay line */395 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R);396 397 /* set delay line */398 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R);399 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R);400 401 /* enable delay lane */402 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);403 val &= ~(PHY_SDCLKDL_CNFG_UPDATE);404 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);405 406 /* configure phy pads */407 val = PHY_PAD_RXSEL_3V3;408 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);409 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);410 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);411 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);412 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);413 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);414 415 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);416 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);417 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);418 419 val = PHY_PAD_RXSEL_3V3;420 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);421 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);422 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N);423 sdhci_writew(host, val, PHY_STBPAD_CNFG_R);424 425 /* enable phy dll */426 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R);427}428 429static void th1520_sdhci_set_phy(struct sdhci_host *host)430{431 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);432 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);433 u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;434 u16 emmc_ctrl;435 436 /* Before power on, set PHY configs */437 if (priv->flags & FLAG_IO_FIXED_1V8)438 dwcmshc_phy_1_8v_init(host);439 else440 dwcmshc_phy_3_3v_init(host);441 442 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {443 emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);444 emmc_ctrl |= DWCMSHC_CARD_IS_EMMC;445 sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);446 }447 448 sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) |449 PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R);450}451 452static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,453 unsigned int timing)454{455 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);456 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);457 u16 ctrl, ctrl_2;458 459 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);460 /* Select Bus Speed Mode for host */461 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;462 if ((timing == MMC_TIMING_MMC_HS200) ||463 (timing == MMC_TIMING_UHS_SDR104))464 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;465 else if (timing == MMC_TIMING_UHS_SDR12)466 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;467 else if ((timing == MMC_TIMING_UHS_SDR25) ||468 (timing == MMC_TIMING_MMC_HS))469 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;470 else if (timing == MMC_TIMING_UHS_SDR50)471 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;472 else if ((timing == MMC_TIMING_UHS_DDR50) ||473 (timing == MMC_TIMING_MMC_DDR52))474 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;475 else if (timing == MMC_TIMING_MMC_HS400) {476 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */477 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);478 ctrl |= DWCMSHC_CARD_IS_EMMC;479 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);480 481 ctrl_2 |= DWCMSHC_CTRL_HS400;482 }483 484 if (priv->flags & FLAG_IO_FIXED_1V8)485 ctrl_2 |= SDHCI_CTRL_VDD_180;486 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);487}488 489static void th1520_set_uhs_signaling(struct sdhci_host *host,490 unsigned int timing)491{492 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);493 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);494 495 dwcmshc_set_uhs_signaling(host, timing);496 if (timing == MMC_TIMING_MMC_HS400)497 priv->delay_line = PHY_SDCLKDL_DC_HS400;498 else499 sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R);500 th1520_sdhci_set_phy(host);501}502 503static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc,504 struct mmc_ios *ios)505{506 u32 vendor;507 struct sdhci_host *host = mmc_priv(mmc);508 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);509 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);510 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;511 512 vendor = sdhci_readl(host, reg);513 if (ios->enhanced_strobe)514 vendor |= DWCMSHC_ENHANCED_STROBE;515 else516 vendor &= ~DWCMSHC_ENHANCED_STROBE;517 518 sdhci_writel(host, vendor, reg);519}520 521static int dwcmshc_execute_tuning(struct mmc_host *mmc, u32 opcode)522{523 int err = sdhci_execute_tuning(mmc, opcode);524 struct sdhci_host *host = mmc_priv(mmc);525 526 if (err)527 return err;528 529 /*530 * Tuning can leave the IP in an active state (Buffer Read Enable bit531 * set) which prevents the entry to low power states (i.e. S0i3). Data532 * reset will clear it.533 */534 sdhci_reset(host, SDHCI_RESET_DATA);535 536 return 0;537}538 539static u32 dwcmshc_cqe_irq_handler(struct sdhci_host *host, u32 intmask)540{541 int cmd_error = 0;542 int data_error = 0;543 544 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))545 return intmask;546 547 cqhci_irq(host->mmc, intmask, cmd_error, data_error);548 549 return 0;550}551 552static void dwcmshc_sdhci_cqe_enable(struct mmc_host *mmc)553{554 struct sdhci_host *host = mmc_priv(mmc);555 u8 ctrl;556 557 sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);558 559 sdhci_cqe_enable(mmc);560 561 /*562 * The "DesignWare Cores Mobile Storage Host Controller563 * DWC_mshc / DWC_mshc_lite Databook" says:564 * when Host Version 4 Enable" is 1 in Host Control 2 register,565 * SDHCI_CTRL_ADMA32 bit means ADMA2 is selected.566 * Selection of 32-bit/64-bit System Addressing:567 * either 32-bit or 64-bit system addressing is selected by568 * 64-bit Addressing bit in Host Control 2 register.569 *570 * On the other hand the "DesignWare Cores Mobile Storage Host571 * Controller DWC_mshc / DWC_mshc_lite User Guide" says, that we have to572 * set DMA_SEL to ADMA2 _only_ mode in the Host Control 2 register.573 */574 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);575 ctrl &= ~SDHCI_CTRL_DMA_MASK;576 ctrl |= SDHCI_CTRL_ADMA32;577 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);578}579 580static void dwcmshc_set_tran_desc(struct cqhci_host *cq_host, u8 **desc,581 dma_addr_t addr, int len, bool end, bool dma64)582{583 int tmplen, offset;584 585 if (likely(!len || BOUNDARY_OK(addr, len))) {586 cqhci_set_tran_desc(*desc, addr, len, end, dma64);587 return;588 }589 590 offset = addr & (SZ_128M - 1);591 tmplen = SZ_128M - offset;592 cqhci_set_tran_desc(*desc, addr, tmplen, false, dma64);593 594 addr += tmplen;595 len -= tmplen;596 *desc += cq_host->trans_desc_len;597 cqhci_set_tran_desc(*desc, addr, len, end, dma64);598}599 600static void dwcmshc_cqhci_dumpregs(struct mmc_host *mmc)601{602 sdhci_dumpregs(mmc_priv(mmc));603}604 605static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)606{607 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);608 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);609 struct rk35xx_priv *priv = dwc_priv->priv;610 u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;611 u32 extra, reg;612 int err;613 614 host->mmc->actual_clock = 0;615 616 if (clock == 0) {617 /* Disable interface clock at initial state. */618 sdhci_set_clock(host, clock);619 return;620 }621 622 /* Rockchip platform only support 375KHz for identify mode */623 if (clock <= 400000)624 clock = 375000;625 626 err = clk_set_rate(pltfm_host->clk, clock);627 if (err)628 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);629 630 sdhci_set_clock(host, clock);631 632 /* Disable cmd conflict check */633 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;634 extra = sdhci_readl(host, reg);635 extra &= ~BIT(0);636 sdhci_writel(host, extra, reg);637 638 if (clock <= 52000000) {639 /*640 * Disable DLL and reset both of sample and drive clock.641 * The bypass bit and start bit need to be set if DLL is not locked.642 */643 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);644 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);645 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);646 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);647 /*648 * Before switching to hs400es mode, the driver will enable649 * enhanced strobe first. PHY needs to configure the parameters650 * of enhanced strobe first.651 */652 extra = DWCMSHC_EMMC_DLL_DLYENA |653 DLL_STRBIN_DELAY_NUM_SEL |654 DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;655 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);656 return;657 }658 659 /* Reset DLL */660 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL);661 udelay(1);662 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);663 664 /*665 * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but666 * we must set it in higher speed mode.667 */668 extra = DWCMSHC_EMMC_DLL_DLYENA;669 if (priv->devtype == DWCMSHC_RK3568)670 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;671 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);672 673 /* Init DLL settings */674 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |675 0x2 << DWCMSHC_EMMC_DLL_INC |676 DWCMSHC_EMMC_DLL_START;677 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);678 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0,679 extra, DLL_LOCK_WO_TMOUT(extra), 1,680 500 * USEC_PER_MSEC);681 if (err) {682 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");683 return;684 }685 686 extra = 0x1 << 16 | /* tune clock stop en */687 0x3 << 17 | /* pre-change delay */688 0x3 << 19; /* post-change delay */689 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);690 691 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 ||692 host->mmc->ios.timing == MMC_TIMING_MMC_HS400)693 txclk_tapnum = priv->txclk_tapnum;694 695 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) {696 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES;697 698 extra = DLL_CMDOUT_SRC_CLK_NEG |699 DLL_CMDOUT_EN_SRC_CLK_NEG |700 DWCMSHC_EMMC_DLL_DLYENA |701 DLL_CMDOUT_TAPNUM_90_DEGREES |702 DLL_CMDOUT_TAPNUM_FROM_SW;703 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);704 }705 706 extra = DWCMSHC_EMMC_DLL_DLYENA |707 DLL_TXCLK_TAPNUM_FROM_SW |708 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL |709 txclk_tapnum;710 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);711 712 extra = DWCMSHC_EMMC_DLL_DLYENA |713 DLL_STRBIN_TAPNUM_DEFAULT |714 DLL_STRBIN_TAPNUM_FROM_SW;715 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);716}717 718static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)719{720 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);721 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);722 struct rk35xx_priv *priv = dwc_priv->priv;723 724 if (mask & SDHCI_RESET_ALL && priv->reset) {725 reset_control_assert(priv->reset);726 udelay(1);727 reset_control_deassert(priv->reset);728 }729 730 sdhci_reset(host, mask);731}732 733static int dwcmshc_rk35xx_init(struct device *dev, struct sdhci_host *host,734 struct dwcmshc_priv *dwc_priv)735{736 static const char * const clk_ids[] = {"axi", "block", "timer"};737 struct rk35xx_priv *priv;738 int err;739 740 priv = devm_kzalloc(dev, sizeof(struct rk35xx_priv), GFP_KERNEL);741 if (!priv)742 return -ENOMEM;743 744 if (of_device_is_compatible(dev->of_node, "rockchip,rk3588-dwcmshc"))745 priv->devtype = DWCMSHC_RK3588;746 else747 priv->devtype = DWCMSHC_RK3568;748 749 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));750 if (IS_ERR(priv->reset)) {751 err = PTR_ERR(priv->reset);752 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);753 return err;754 }755 756 err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,757 ARRAY_SIZE(clk_ids), clk_ids);758 if (err)759 return err;760 761 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",762 &priv->txclk_tapnum))763 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;764 765 /* Disable cmd conflict check */766 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);767 /* Reset previous settings */768 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);769 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);770 771 dwc_priv->priv = priv;772 773 return 0;774}775 776static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)777{778 /*779 * Don't support highspeed bus mode with low clk speed as we780 * cannot use DLL for this condition.781 */782 if (host->mmc->f_max <= 52000000) {783 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",784 host->mmc->f_max);785 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);786 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);787 }788}789 790static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode)791{792 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);793 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);794 u32 val = 0;795 796 if (host->flags & SDHCI_HS400_TUNING)797 return 0;798 799 sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL),800 PHY_ATDL_CNFG_R);801 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);802 803 /*804 * configure tuning settings:805 * - center phase select code driven in block gap interval806 * - disable reporting of framing errors807 * - disable software managed tuning808 * - disable user selection of sampling window edges,809 * instead tuning calculated edges are used810 */811 val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN |812 FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL));813 814 /*815 * configure tuning settings:816 * - enable auto-tuning817 * - enable sampling window threshold818 * - stop clocks during phase code change819 * - set max latency in cycles between tx and rx clocks820 * - set max latency in cycles to switch output phase821 * - set max sampling window threshold value822 */823 val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN;824 val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY);825 val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY);826 val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL);827 828 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);829 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);830 831 /* perform tuning */832 sdhci_start_tuning(host);833 host->tuning_loop_count = 128;834 host->tuning_err = __sdhci_execute_tuning(host, opcode);835 if (host->tuning_err) {836 /* disable auto-tuning upon tuning error */837 val &= ~AT_CTRL_AT_EN;838 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);839 dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err);840 return -EIO;841 }842 sdhci_end_tuning(host);843 844 return 0;845}846 847static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)848{849 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);850 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);851 u16 ctrl_2;852 853 sdhci_reset(host, mask);854 855 /* The T-Head 1520 SoC does not comply with the SDHCI specification856 * regarding the "Software Reset for CMD line should clear 'Command857 * Complete' in the Normal Interrupt Status Register." Clear the bit858 * here to compensate for this quirk.859 */860 if (mask & SDHCI_RESET_CMD)861 sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);862 863 if (priv->flags & FLAG_IO_FIXED_1V8) {864 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);865 if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) {866 ctrl_2 |= SDHCI_CTRL_VDD_180;867 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);868 }869 }870}871 872static int th1520_init(struct device *dev,873 struct sdhci_host *host,874 struct dwcmshc_priv *dwc_priv)875{876 dwc_priv->delay_line = PHY_SDCLKDL_DC_DEFAULT;877 878 if (device_property_read_bool(dev, "mmc-ddr-1_8v") ||879 device_property_read_bool(dev, "mmc-hs200-1_8v") ||880 device_property_read_bool(dev, "mmc-hs400-1_8v"))881 dwc_priv->flags |= FLAG_IO_FIXED_1V8;882 else883 dwc_priv->flags &= ~FLAG_IO_FIXED_1V8;884 885 /*886 * start_signal_voltage_switch() will try 3.3V first887 * then 1.8V. Use SDHCI_SIGNALING_180 rather than888 * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V889 * in sdhci_start_signal_voltage_switch().890 */891 if (dwc_priv->flags & FLAG_IO_FIXED_1V8) {892 host->flags &= ~SDHCI_SIGNALING_330;893 host->flags |= SDHCI_SIGNALING_180;894 }895 896 sdhci_enable_v4_mode(host);897 898 return 0;899}900 901static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask)902{903 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);904 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);905 u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;906 907 sdhci_reset(host, mask);908 909 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {910 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);911 val |= CV18XX_EMMC_FUNC_EN;912 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);913 }914 915 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);916 val |= CV18XX_LATANCY_1T;917 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);918 919 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);920 val |= CV18XX_PHY_TX_BPS;921 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);922 923 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) |924 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) |925 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, 0) |926 FIELD_PREP(CV18XX_PHY_RX_SRC_MSK, CV18XX_PHY_RX_SRC_INVERT_RX_CLK));927 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY);928}929 930static void cv18xx_sdhci_set_tap(struct sdhci_host *host, int tap)931{932 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);933 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);934 u16 clk;935 u32 val;936 937 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);938 clk &= ~SDHCI_CLOCK_CARD_EN;939 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);940 941 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);942 val &= ~CV18XX_LATANCY_1T;943 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);944 945 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) |946 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) |947 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, tap));948 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY);949 950 sdhci_writel(host, 0, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);951 952 clk |= SDHCI_CLOCK_CARD_EN;953 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);954 usleep_range(1000, 2000);955}956 957static int cv18xx_retry_tuning(struct mmc_host *mmc, u32 opcode, int *cmd_error)958{959 int ret, retry = 0;960 961 while (retry < CV18XX_RETRY_TUNING_MAX) {962 ret = mmc_send_tuning(mmc, opcode, NULL);963 if (ret)964 return ret;965 retry++;966 }967 968 return 0;969}970 971static void cv18xx_sdhci_post_tuning(struct sdhci_host *host)972{973 u32 val;974 975 val = sdhci_readl(host, SDHCI_INT_STATUS);976 val |= SDHCI_INT_DATA_AVAIL;977 sdhci_writel(host, val, SDHCI_INT_STATUS);978 979 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);980}981 982static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)983{984 int min, max, avg, ret;985 int win_length, target_min, target_max, target_win_length;986 987 min = max = 0;988 target_win_length = 0;989 990 sdhci_reset_tuning(host);991 992 while (max < CV18XX_TUNE_MAX) {993 /* find the mininum delay first which can pass tuning */994 while (min < CV18XX_TUNE_MAX) {995 cv18xx_sdhci_set_tap(host, min);996 if (!cv18xx_retry_tuning(host->mmc, opcode, NULL))997 break;998 min += CV18XX_TUNE_STEP;999 }1000 1001 /* find the maxinum delay which can not pass tuning */1002 max = min + CV18XX_TUNE_STEP;1003 while (max < CV18XX_TUNE_MAX) {1004 cv18xx_sdhci_set_tap(host, max);1005 if (cv18xx_retry_tuning(host->mmc, opcode, NULL)) {1006 max -= CV18XX_TUNE_STEP;1007 break;1008 }1009 max += CV18XX_TUNE_STEP;1010 }1011 1012 win_length = max - min + 1;1013 /* get the largest pass window */1014 if (win_length > target_win_length) {1015 target_win_length = win_length;1016 target_min = min;1017 target_max = max;1018 }1019 1020 /* continue to find the next pass window */1021 min = max + CV18XX_TUNE_STEP;1022 }1023 1024 cv18xx_sdhci_post_tuning(host);1025 1026 /* use average delay to get the best timing */1027 avg = (target_min + target_max) / 2;1028 cv18xx_sdhci_set_tap(host, avg);1029 ret = mmc_send_tuning(host->mmc, opcode, NULL);1030 1031 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",1032 ret ? "failed" : "passed", avg, ret);1033 1034 return ret;1035}1036 1037static inline void sg2042_sdhci_phy_init(struct sdhci_host *host)1038{1039 u32 val;1040 1041 /* Asset phy reset & set tx drive strength */1042 val = sdhci_readl(host, PHY_CNFG_R);1043 val &= ~PHY_CNFG_RSTN_DEASSERT;1044 val |= FIELD_PREP(PHY_CNFG_PHY_PWRGOOD_MASK, 1);1045 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP_SG2042);1046 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN_SG2042);1047 sdhci_writel(host, val, PHY_CNFG_R);1048 1049 /* Configure phy pads */1050 val = PHY_PAD_RXSEL_3V3;1051 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP);1052 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);1053 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042);1054 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R);1055 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R);1056 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R);1057 1058 val = PHY_PAD_RXSEL_3V3;1059 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);1060 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042);1061 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R);1062 1063 val = PHY_PAD_RXSEL_3V3;1064 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN);1065 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P);1066 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042);1067 sdhci_writew(host, val, PHY_STBPAD_CNFG_R);1068 1069 /* Configure delay line */1070 /* Enable fixed delay */1071 sdhci_writeb(host, PHY_SDCLKDL_CNFG_EXTDLY_EN, PHY_SDCLKDL_CNFG_R);1072 /*1073 * Set delay line.1074 * Its recommended that bit UPDATE_DC[4] is 1 when SDCLKDL_DC is being written.1075 * Ensure UPDATE_DC[4] is '0' when not updating code.1076 */1077 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);1078 val |= PHY_SDCLKDL_CNFG_UPDATE;1079 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);1080 /* Add 10 * 70ps = 0.7ns for output delay */1081 sdhci_writeb(host, 10, PHY_SDCLKDL_DC_R);1082 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R);1083 val &= ~(PHY_SDCLKDL_CNFG_UPDATE);1084 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R);1085 1086 /* Set SMPLDL_CNFG, Bypass */1087 sdhci_writeb(host, PHY_SMPLDL_CNFG_BYPASS_EN, PHY_SMPLDL_CNFG_R);1088 1089 /* Set ATDL_CNFG, tuning clk not use for init */1090 val = FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL_SG2042);1091 sdhci_writeb(host, val, PHY_ATDL_CNFG_R);1092 1093 /* Deasset phy reset */1094 val = sdhci_readl(host, PHY_CNFG_R);1095 val |= PHY_CNFG_RSTN_DEASSERT;1096 sdhci_writel(host, val, PHY_CNFG_R);1097}1098 1099static void sg2042_sdhci_reset(struct sdhci_host *host, u8 mask)1100{1101 sdhci_reset(host, mask);1102 1103 if (mask & SDHCI_RESET_ALL)1104 sg2042_sdhci_phy_init(host);1105}1106 1107static int sg2042_init(struct device *dev, struct sdhci_host *host,1108 struct dwcmshc_priv *dwc_priv)1109{1110 static const char * const clk_ids[] = {"timer"};1111 1112 return dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv,1113 ARRAY_SIZE(clk_ids), clk_ids);1114}1115 1116static const struct sdhci_ops sdhci_dwcmshc_ops = {1117 .set_clock = sdhci_set_clock,1118 .set_bus_width = sdhci_set_bus_width,1119 .set_uhs_signaling = dwcmshc_set_uhs_signaling,1120 .get_max_clock = dwcmshc_get_max_clock,1121 .reset = sdhci_reset,1122 .adma_write_desc = dwcmshc_adma_write_desc,1123 .irq = dwcmshc_cqe_irq_handler,1124};1125 1126#ifdef CONFIG_ACPI1127static void dwcmshc_bf3_hw_reset(struct sdhci_host *host)1128{1129 struct arm_smccc_res res = { 0 };1130 1131 arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0, &res);1132 1133 if (res.a0)1134 pr_err("%s: RST_N failed.\n", mmc_hostname(host->mmc));1135}1136 1137static const struct sdhci_ops sdhci_dwcmshc_bf3_ops = {1138 .set_clock = sdhci_set_clock,1139 .set_bus_width = sdhci_set_bus_width,1140 .set_uhs_signaling = dwcmshc_set_uhs_signaling,1141 .get_max_clock = dwcmshc_get_max_clock,1142 .reset = sdhci_reset,1143 .adma_write_desc = dwcmshc_adma_write_desc,1144 .irq = dwcmshc_cqe_irq_handler,1145 .hw_reset = dwcmshc_bf3_hw_reset,1146};1147#endif1148 1149static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {1150 .set_clock = dwcmshc_rk3568_set_clock,1151 .set_bus_width = sdhci_set_bus_width,1152 .set_uhs_signaling = dwcmshc_set_uhs_signaling,1153 .get_max_clock = rk35xx_get_max_clock,1154 .reset = rk35xx_sdhci_reset,1155 .adma_write_desc = dwcmshc_adma_write_desc,1156 .irq = dwcmshc_cqe_irq_handler,1157};1158 1159static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = {1160 .set_clock = sdhci_set_clock,1161 .set_bus_width = sdhci_set_bus_width,1162 .set_uhs_signaling = th1520_set_uhs_signaling,1163 .get_max_clock = dwcmshc_get_max_clock,1164 .reset = th1520_sdhci_reset,1165 .adma_write_desc = dwcmshc_adma_write_desc,1166 .voltage_switch = dwcmshc_phy_1_8v_init,1167 .platform_execute_tuning = th1520_execute_tuning,1168};1169 1170static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = {1171 .set_clock = sdhci_set_clock,1172 .set_bus_width = sdhci_set_bus_width,1173 .set_uhs_signaling = dwcmshc_set_uhs_signaling,1174 .get_max_clock = dwcmshc_get_max_clock,1175 .reset = cv18xx_sdhci_reset,1176 .adma_write_desc = dwcmshc_adma_write_desc,1177 .platform_execute_tuning = cv18xx_sdhci_execute_tuning,1178};1179 1180static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = {1181 .set_clock = sdhci_set_clock,1182 .set_bus_width = sdhci_set_bus_width,1183 .set_uhs_signaling = dwcmshc_set_uhs_signaling,1184 .get_max_clock = dwcmshc_get_max_clock,1185 .reset = sg2042_sdhci_reset,1186 .adma_write_desc = dwcmshc_adma_write_desc,1187 .platform_execute_tuning = th1520_execute_tuning,1188};1189 1190static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = {1191 .pdata = {1192 .ops = &sdhci_dwcmshc_ops,1193 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,1194 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,1195 },1196};1197 1198#ifdef CONFIG_ACPI1199static const struct dwcmshc_pltfm_data sdhci_dwcmshc_bf3_pdata = {1200 .pdata = {1201 .ops = &sdhci_dwcmshc_bf3_ops,1202 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,1203 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |1204 SDHCI_QUIRK2_ACMD23_BROKEN,1205 },1206};1207#endif1208 1209static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {1210 .pdata = {1211 .ops = &sdhci_dwcmshc_rk35xx_ops,1212 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |1213 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,1214 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |1215 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,1216 },1217 .init = dwcmshc_rk35xx_init,1218 .postinit = dwcmshc_rk35xx_postinit,1219};1220 1221static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = {1222 .pdata = {1223 .ops = &sdhci_dwcmshc_th1520_ops,1224 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,1225 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,1226 },1227 .init = th1520_init,1228};1229 1230static const struct dwcmshc_pltfm_data sdhci_dwcmshc_cv18xx_pdata = {1231 .pdata = {1232 .ops = &sdhci_dwcmshc_cv18xx_ops,1233 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,1234 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,1235 },1236};1237 1238static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = {1239 .pdata = {1240 .ops = &sdhci_dwcmshc_sg2042_ops,1241 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,1242 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,1243 },1244 .init = sg2042_init,1245};1246 1247static const struct cqhci_host_ops dwcmshc_cqhci_ops = {1248 .enable = dwcmshc_sdhci_cqe_enable,1249 .disable = sdhci_cqe_disable,1250 .dumpregs = dwcmshc_cqhci_dumpregs,1251 .set_tran_desc = dwcmshc_set_tran_desc,1252};1253 1254static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev)1255{1256 struct cqhci_host *cq_host;1257 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);1258 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);1259 bool dma64 = false;1260 u16 clk;1261 int err;1262 1263 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;1264 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);1265 if (!cq_host) {1266 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: not enough memory\n");1267 goto dsbl_cqe_caps;1268 }1269 1270 /*1271 * For dwcmshc host controller we have to enable internal clock1272 * before access to some registers from Vendor Specific Area 2.1273 */1274 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);1275 clk |= SDHCI_CLOCK_INT_EN;1276 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);1277 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);1278 if (!(clk & SDHCI_CLOCK_INT_EN)) {1279 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: internal clock enable error\n");1280 goto free_cq_host;1281 }1282 1283 cq_host->mmio = host->ioaddr + priv->vendor_specific_area2;1284 cq_host->ops = &dwcmshc_cqhci_ops;1285 1286 /* Enable using of 128-bit task descriptors */1287 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;1288 if (dma64) {1289 dev_dbg(mmc_dev(host->mmc), "128-bit task descriptors\n");1290 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;1291 }1292 err = cqhci_init(cq_host, host->mmc, dma64);1293 if (err) {1294 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: error %d\n", err);1295 goto int_clock_disable;1296 }1297 1298 dev_dbg(mmc_dev(host->mmc), "CQE init done\n");1299 1300 return;1301 1302int_clock_disable:1303 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);1304 clk &= ~SDHCI_CLOCK_INT_EN;1305 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);1306 1307free_cq_host:1308 devm_kfree(&pdev->dev, cq_host);1309 1310dsbl_cqe_caps:1311 host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD);1312}1313 1314static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {1315 {1316 .compatible = "rockchip,rk3588-dwcmshc",1317 .data = &sdhci_dwcmshc_rk35xx_pdata,1318 },1319 {1320 .compatible = "rockchip,rk3568-dwcmshc",1321 .data = &sdhci_dwcmshc_rk35xx_pdata,1322 },1323 {1324 .compatible = "snps,dwcmshc-sdhci",1325 .data = &sdhci_dwcmshc_pdata,1326 },1327 {1328 .compatible = "sophgo,cv1800b-dwcmshc",1329 .data = &sdhci_dwcmshc_cv18xx_pdata,1330 },1331 {1332 .compatible = "sophgo,sg2002-dwcmshc",1333 .data = &sdhci_dwcmshc_cv18xx_pdata,1334 },1335 {1336 .compatible = "thead,th1520-dwcmshc",1337 .data = &sdhci_dwcmshc_th1520_pdata,1338 },1339 {1340 .compatible = "sophgo,sg2042-dwcmshc",1341 .data = &sdhci_dwcmshc_sg2042_pdata,1342 },1343 {},1344};1345MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);1346 1347#ifdef CONFIG_ACPI1348static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {1349 {1350 .id = "MLNXBF30",1351 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata,1352 },1353 {}1354};1355MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids);1356#endif1357 1358static int dwcmshc_probe(struct platform_device *pdev)1359{1360 struct device *dev = &pdev->dev;1361 struct sdhci_pltfm_host *pltfm_host;1362 struct sdhci_host *host;1363 struct dwcmshc_priv *priv;1364 const struct dwcmshc_pltfm_data *pltfm_data;1365 int err;1366 u32 extra, caps;1367 1368 pltfm_data = device_get_match_data(&pdev->dev);1369 if (!pltfm_data) {1370 dev_err(&pdev->dev, "Error: No device match data found\n");1371 return -ENODEV;1372 }1373 1374 host = sdhci_pltfm_init(pdev, &pltfm_data->pdata,1375 sizeof(struct dwcmshc_priv));1376 if (IS_ERR(host))1377 return PTR_ERR(host);1378 1379 /*1380 * extra adma table cnt for cross 128M boundary handling.1381 */1382 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);1383 if (extra > SDHCI_MAX_SEGS)1384 extra = SDHCI_MAX_SEGS;1385 host->adma_table_cnt += extra;1386 1387 pltfm_host = sdhci_priv(host);1388 priv = sdhci_pltfm_priv(pltfm_host);1389 1390 if (dev->of_node) {1391 pltfm_host->clk = devm_clk_get(dev, "core");1392 if (IS_ERR(pltfm_host->clk)) {1393 err = PTR_ERR(pltfm_host->clk);1394 dev_err(dev, "failed to get core clk: %d\n", err);1395 goto free_pltfm;1396 }1397 err = clk_prepare_enable(pltfm_host->clk);1398 if (err)1399 goto free_pltfm;1400 1401 priv->bus_clk = devm_clk_get(dev, "bus");1402 if (!IS_ERR(priv->bus_clk))1403 clk_prepare_enable(priv->bus_clk);1404 }1405 1406 err = mmc_of_parse(host->mmc);1407 if (err)1408 goto err_clk;1409 1410 sdhci_get_of_property(pdev);1411 1412 priv->vendor_specific_area1 =1413 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;1414 1415 host->mmc_host_ops.request = dwcmshc_request;1416 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;1417 host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning;1418 1419 if (pltfm_data->init) {1420 err = pltfm_data->init(&pdev->dev, host, priv);1421 if (err)1422 goto err_clk;1423 }1424 1425#ifdef CONFIG_ACPI1426 if (pltfm_data == &sdhci_dwcmshc_bf3_pdata)1427 sdhci_enable_v4_mode(host);1428#endif1429 1430 caps = sdhci_readl(host, SDHCI_CAPABILITIES);1431 if (caps & SDHCI_CAN_64BIT_V4)1432 sdhci_enable_v4_mode(host);1433 1434 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;1435 1436 pm_runtime_get_noresume(dev);1437 pm_runtime_set_active(dev);1438 pm_runtime_enable(dev);1439 1440 err = sdhci_setup_host(host);1441 if (err)1442 goto err_rpm;1443 1444 /* Setup Command Queue Engine if enabled */1445 if (device_property_read_bool(&pdev->dev, "supports-cqe")) {1446 priv->vendor_specific_area2 =1447 sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2);1448 1449 dwcmshc_cqhci_init(host, pdev);1450 }1451 1452 if (pltfm_data->postinit)1453 pltfm_data->postinit(host, priv);1454 1455 err = __sdhci_add_host(host);1456 if (err)1457 goto err_setup_host;1458 1459 pm_runtime_put(dev);1460 1461 return 0;1462 1463err_setup_host:1464 sdhci_cleanup_host(host);1465err_rpm:1466 pm_runtime_disable(dev);1467 pm_runtime_put_noidle(dev);1468err_clk:1469 clk_disable_unprepare(pltfm_host->clk);1470 clk_disable_unprepare(priv->bus_clk);1471 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks);1472free_pltfm:1473 sdhci_pltfm_free(pdev);1474 return err;1475}1476 1477static void dwcmshc_disable_card_clk(struct sdhci_host *host)1478{1479 u16 ctrl;1480 1481 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);1482 if (ctrl & SDHCI_CLOCK_CARD_EN) {1483 ctrl &= ~SDHCI_CLOCK_CARD_EN;1484 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);1485 }1486}1487 1488static void dwcmshc_remove(struct platform_device *pdev)1489{1490 struct sdhci_host *host = platform_get_drvdata(pdev);1491 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);1492 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);1493 1494 pm_runtime_get_sync(&pdev->dev);1495 pm_runtime_disable(&pdev->dev);1496 pm_runtime_put_noidle(&pdev->dev);1497 1498 sdhci_remove_host(host, 0);1499 1500 dwcmshc_disable_card_clk(host);1501 1502 clk_disable_unprepare(pltfm_host->clk);1503 clk_disable_unprepare(priv->bus_clk);1504 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks);1505 sdhci_pltfm_free(pdev);1506}1507 1508#ifdef CONFIG_PM_SLEEP1509static int dwcmshc_suspend(struct device *dev)1510{1511 struct sdhci_host *host = dev_get_drvdata(dev);1512 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);1513 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);1514 int ret;1515 1516 pm_runtime_resume(dev);1517 1518 if (host->mmc->caps2 & MMC_CAP2_CQE) {1519 ret = cqhci_suspend(host->mmc);1520 if (ret)1521 return ret;1522 }1523 1524 ret = sdhci_suspend_host(host);1525 if (ret)1526 return ret;1527 1528 clk_disable_unprepare(pltfm_host->clk);1529 if (!IS_ERR(priv->bus_clk))1530 clk_disable_unprepare(priv->bus_clk);1531 1532 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks);1533 1534 return ret;1535}1536 1537static int dwcmshc_resume(struct device *dev)1538{1539 struct sdhci_host *host = dev_get_drvdata(dev);1540 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);1541 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);1542 int ret;1543 1544 ret = clk_prepare_enable(pltfm_host->clk);1545 if (ret)1546 return ret;1547 1548 if (!IS_ERR(priv->bus_clk)) {1549 ret = clk_prepare_enable(priv->bus_clk);1550 if (ret)1551 goto disable_clk;1552 }1553 1554 ret = clk_bulk_prepare_enable(priv->num_other_clks, priv->other_clks);1555 if (ret)1556 goto disable_bus_clk;1557 1558 ret = sdhci_resume_host(host);1559 if (ret)1560 goto disable_other_clks;1561 1562 if (host->mmc->caps2 & MMC_CAP2_CQE) {1563 ret = cqhci_resume(host->mmc);1564 if (ret)1565 goto disable_other_clks;1566 }1567 1568 return 0;1569 1570disable_other_clks:1571 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks);1572disable_bus_clk:1573 if (!IS_ERR(priv->bus_clk))1574 clk_disable_unprepare(priv->bus_clk);1575disable_clk:1576 clk_disable_unprepare(pltfm_host->clk);1577 return ret;1578}1579#endif1580 1581#ifdef CONFIG_PM1582 1583static void dwcmshc_enable_card_clk(struct sdhci_host *host)1584{1585 u16 ctrl;1586 1587 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);1588 if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) {1589 ctrl |= SDHCI_CLOCK_CARD_EN;1590 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);1591 }1592}1593 1594static int dwcmshc_runtime_suspend(struct device *dev)1595{1596 struct sdhci_host *host = dev_get_drvdata(dev);1597 1598 dwcmshc_disable_card_clk(host);1599 1600 return 0;1601}1602 1603static int dwcmshc_runtime_resume(struct device *dev)1604{1605 struct sdhci_host *host = dev_get_drvdata(dev);1606 1607 dwcmshc_enable_card_clk(host);1608 1609 return 0;1610}1611 1612#endif1613 1614static const struct dev_pm_ops dwcmshc_pmops = {1615 SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume)1616 SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend,1617 dwcmshc_runtime_resume, NULL)1618};1619 1620static struct platform_driver sdhci_dwcmshc_driver = {1621 .driver = {1622 .name = "sdhci-dwcmshc",1623 .probe_type = PROBE_PREFER_ASYNCHRONOUS,1624 .of_match_table = sdhci_dwcmshc_dt_ids,1625 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),1626 .pm = &dwcmshc_pmops,1627 },1628 .probe = dwcmshc_probe,1629 .remove_new = dwcmshc_remove,1630};1631module_platform_driver(sdhci_dwcmshc_driver);1632 1633MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");1634MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");1635MODULE_LICENSE("GPL v2");1636