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1// SPDX-License-Identifier: GPL-2.0+2/*3 * Copyright (C) 2019 Genesys Logic, Inc.4 *5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>6 *7 * Version: v0.9.0 (2019-08-08)8 */9 10#include <linux/bitfield.h>11#include <linux/bits.h>12#include <linux/pci.h>13#include <linux/mmc/mmc.h>14#include <linux/delay.h>15#include <linux/of.h>16#include <linux/iopoll.h>17#include "sdhci.h"18#include "sdhci-cqhci.h"19#include "sdhci-pci.h"20#include "cqhci.h"21 22/* Genesys Logic extra registers */23#define SDHCI_GLI_9750_WT 0x80024#define SDHCI_GLI_9750_WT_EN BIT(0)25#define GLI_9750_WT_EN_ON 0x126#define GLI_9750_WT_EN_OFF 0x027 28#define SDHCI_GLI_9750_CFG2 0x84829#define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24)30#define GLI_9750_CFG2_L1DLY_VALUE 0x1F31 32#define SDHCI_GLI_9750_DRIVING 0x86033#define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0)34#define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26)35#define GLI_9750_DRIVING_1_VALUE 0xFFF36#define GLI_9750_DRIVING_2_VALUE 0x337#define SDHCI_GLI_9750_SEL_1 BIT(29)38#define SDHCI_GLI_9750_SEL_2 BIT(31)39#define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30))40 41#define SDHCI_GLI_9750_PLL 0x86442#define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0)43#define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12)44#define SDHCI_GLI_9750_PLL_DIR BIT(15)45#define SDHCI_GLI_9750_PLL_TX2_INV BIT(23)46#define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20)47#define GLI_9750_PLL_TX2_INV_VALUE 0x148#define GLI_9750_PLL_TX2_DLY_VALUE 0x049#define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24)50#define SDHCI_GLI_9750_PLLSSC_EN BIT(31)51 52#define SDHCI_GLI_9750_PLLSSC 0x86C53#define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16)54 55#define SDHCI_GLI_9750_SW_CTRL 0x87456#define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6)57#define GLI_9750_SW_CTRL_4_VALUE 0x358 59#define SDHCI_GLI_9750_MISC 0x87860#define SDHCI_GLI_9750_MISC_TX1_INV BIT(2)61#define SDHCI_GLI_9750_MISC_RX_INV BIT(3)62#define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4)63#define GLI_9750_MISC_TX1_INV_VALUE 0x064#define GLI_9750_MISC_RX_INV_ON 0x165#define GLI_9750_MISC_RX_INV_OFF 0x066#define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF67#define GLI_9750_MISC_TX1_DLY_VALUE 0x568#define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26)69 70#define SDHCI_GLI_9750_TUNING_CONTROL 0x54071#define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4)72#define GLI_9750_TUNING_CONTROL_EN_ON 0x173#define GLI_9750_TUNING_CONTROL_EN_OFF 0x074#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16)75#define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19)76#define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x177#define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x278 79#define SDHCI_GLI_9750_TUNING_PARAMETERS 0x54480#define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0)81#define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x182 83#define SDHCI_GLI_9763E_CTRL_HS400 0x784 85#define SDHCI_GLI_9763E_HS400_ES_REG 0x52C86#define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8)87 88#define PCIE_GLI_9763E_VHS 0x88489#define GLI_9763E_VHS_REV GENMASK(19, 16)90#define GLI_9763E_VHS_REV_R 0x091#define GLI_9763E_VHS_REV_M 0x192#define GLI_9763E_VHS_REV_W 0x293#define PCIE_GLI_9763E_MB 0x88894#define GLI_9763E_MB_CMDQ_OFF BIT(19)95#define GLI_9763E_MB_ERP_ON BIT(7)96#define PCIE_GLI_9763E_SCR 0x8E097#define GLI_9763E_SCR_AXI_REQ BIT(9)98 99#define PCIE_GLI_9763E_CFG 0x8A0100#define GLI_9763E_CFG_LPSN_DIS BIT(12)101 102#define PCIE_GLI_9763E_CFG2 0x8A4103#define GLI_9763E_CFG2_L1DLY GENMASK(28, 19)104#define GLI_9763E_CFG2_L1DLY_MID 0x54105 106#define PCIE_GLI_9763E_MMC_CTRL 0x960107#define GLI_9763E_HS400_SLOW BIT(3)108 109#define PCIE_GLI_9763E_CLKRXDLY 0x934110#define GLI_9763E_HS400_RXDLY GENMASK(31, 28)111#define GLI_9763E_HS400_RXDLY_5 0x5112 113#define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200114#define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \115 SDHCI_TRNS_BLK_CNT_EN | \116 SDHCI_TRNS_DMA)117 118#define PCI_GLI_9755_WT 0x800119#define PCI_GLI_9755_WT_EN BIT(0)120#define GLI_9755_WT_EN_ON 0x1121#define GLI_9755_WT_EN_OFF 0x0122 123#define PCI_GLI_9755_PECONF 0x44124#define PCI_GLI_9755_LFCLK GENMASK(14, 12)125#define PCI_GLI_9755_DMACLK BIT(29)126#define PCI_GLI_9755_INVERT_CD BIT(30)127#define PCI_GLI_9755_INVERT_WP BIT(31)128 129#define PCI_GLI_9755_CFG2 0x48130#define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24)131#define GLI_9755_CFG2_L1DLY_VALUE 0x1F132 133#define PCI_GLI_9755_PLL 0x64134#define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0)135#define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12)136#define PCI_GLI_9755_PLL_DIR BIT(15)137#define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24)138#define PCI_GLI_9755_PLLSSC_EN BIT(31)139 140#define PCI_GLI_9755_PLLSSC 0x68141#define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0)142 143#define PCI_GLI_9755_SerDes 0x70144#define PCI_GLI_9755_SCP_DIS BIT(19)145 146#define PCI_GLI_9755_MISC 0x78147#define PCI_GLI_9755_MISC_SSC_OFF BIT(26)148 149#define SDHCI_GLI_9767_GM_BURST_SIZE 0x510150#define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8)151 152#define PCIE_GLI_9767_VHS 0x884153#define GLI_9767_VHS_REV GENMASK(19, 16)154#define GLI_9767_VHS_REV_R 0x0155#define GLI_9767_VHS_REV_M 0x1156#define GLI_9767_VHS_REV_W 0x2157 158#define PCIE_GLI_9767_COM_MAILBOX 0x888159#define PCIE_GLI_9767_COM_MAILBOX_SSC_EN BIT(1)160 161#define PCIE_GLI_9767_CFG 0x8A0162#define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12)163 164#define PCIE_GLI_9767_COMBO_MUX_CTL 0x8C8165#define PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN BIT(6)166#define PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN BIT(10)167 168#define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0169#define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0)170#define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12)171#define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE 0x7172#define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL GENMASK(29, 28)173#define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE 0x3174 175#define PCIE_GLI_9767_SCR 0x8E0176#define PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST BIT(6)177#define PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST BIT(7)178#define PCIE_GLI_9767_SCR_AXI_REQ BIT(9)179#define PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN BIT(10)180#define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 BIT(16)181#define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 BIT(17)182#define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21)183#define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30)184 185#define PCIE_GLI_9767_SDHC_CAP 0x91C186#define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5)187 188#define PCIE_GLI_9767_SD_PLL_CTL 0x938189#define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0)190#define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12)191#define PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN BIT(16)192#define PCIE_GLI_9767_SD_PLL_CTL_SSC_EN BIT(19)193#define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24)194 195#define PCIE_GLI_9767_SD_PLL_CTL2 0x93C196#define PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM GENMASK(31, 16)197 198#define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940199#define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0)200#define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1)201 202#define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944203#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16)204#define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64205 206#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950207#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0)208 209#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2 0x954210#define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN BIT(0)211 212#define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958213#define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0)214 215#define GLI_MAX_TUNING_LOOP 40216 217/* Genesys Logic chipset */218static inline void gl9750_wt_on(struct sdhci_host *host)219{220 u32 wt_value;221 u32 wt_enable;222 223 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);224 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);225 226 if (wt_enable == GLI_9750_WT_EN_ON)227 return;228 229 wt_value &= ~SDHCI_GLI_9750_WT_EN;230 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);231 232 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);233}234 235static inline void gl9750_wt_off(struct sdhci_host *host)236{237 u32 wt_value;238 u32 wt_enable;239 240 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);241 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);242 243 if (wt_enable == GLI_9750_WT_EN_OFF)244 return;245 246 wt_value &= ~SDHCI_GLI_9750_WT_EN;247 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);248 249 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);250}251 252static void gli_set_9750(struct sdhci_host *host)253{254 u32 driving_value;255 u32 pll_value;256 u32 sw_ctrl_value;257 u32 misc_value;258 u32 parameter_value;259 u32 control_value;260 u16 ctrl2;261 262 gl9750_wt_on(host);263 264 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);265 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);266 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);267 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);268 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);269 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);270 271 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);272 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);273 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,274 GLI_9750_DRIVING_1_VALUE);275 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,276 GLI_9750_DRIVING_2_VALUE);277 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);278 driving_value |= SDHCI_GLI_9750_SEL_2;279 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);280 281 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;282 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,283 GLI_9750_SW_CTRL_4_VALUE);284 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);285 286 /* reset the tuning flow after reinit and before starting tuning */287 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;288 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;289 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,290 GLI_9750_PLL_TX2_INV_VALUE);291 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,292 GLI_9750_PLL_TX2_DLY_VALUE);293 294 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;295 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;296 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;297 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,298 GLI_9750_MISC_TX1_INV_VALUE);299 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,300 GLI_9750_MISC_RX_INV_VALUE);301 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,302 GLI_9750_MISC_TX1_DLY_VALUE);303 304 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;305 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,306 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);307 308 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;309 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;310 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,311 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);312 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,313 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);314 315 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);316 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);317 318 /* disable tuned clk */319 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);320 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;321 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);322 323 /* enable tuning parameters control */324 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;325 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,326 GLI_9750_TUNING_CONTROL_EN_ON);327 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);328 329 /* write tuning parameters */330 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);331 332 /* disable tuning parameters control */333 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;334 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,335 GLI_9750_TUNING_CONTROL_EN_OFF);336 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);337 338 /* clear tuned clk */339 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);340 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;341 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);342 343 gl9750_wt_off(host);344}345 346static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)347{348 u32 misc_value;349 350 gl9750_wt_on(host);351 352 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);353 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;354 if (b) {355 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,356 GLI_9750_MISC_RX_INV_ON);357 } else {358 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,359 GLI_9750_MISC_RX_INV_OFF);360 }361 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);362 363 gl9750_wt_off(host);364}365 366static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)367{368 int i;369 int rx_inv;370 371 for (rx_inv = 0; rx_inv < 2; rx_inv++) {372 gli_set_9750_rx_inv(host, !!rx_inv);373 sdhci_start_tuning(host);374 375 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {376 u16 ctrl;377 378 sdhci_send_tuning(host, opcode);379 380 if (!host->tuning_done) {381 sdhci_abort_tuning(host, opcode);382 break;383 }384 385 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);386 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {387 if (ctrl & SDHCI_CTRL_TUNED_CLK)388 return 0; /* Success! */389 break;390 }391 }392 }393 if (!host->tuning_done) {394 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",395 mmc_hostname(host->mmc));396 return -ETIMEDOUT;397 }398 399 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",400 mmc_hostname(host->mmc));401 sdhci_reset_tuning(host);402 403 return -EAGAIN;404}405 406static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)407{408 host->mmc->retune_period = 0;409 if (host->tuning_mode == SDHCI_TUNING_MODE_1)410 host->mmc->retune_period = host->tuning_count;411 412 gli_set_9750(host);413 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);414 sdhci_end_tuning(host);415 416 return 0;417}418 419static void gl9750_disable_ssc_pll(struct sdhci_host *host)420{421 u32 pll;422 423 gl9750_wt_on(host);424 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);425 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);426 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);427 gl9750_wt_off(host);428}429 430static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)431{432 u32 pll;433 434 gl9750_wt_on(host);435 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);436 pll &= ~(SDHCI_GLI_9750_PLL_LDIV |437 SDHCI_GLI_9750_PLL_PDIV |438 SDHCI_GLI_9750_PLL_DIR);439 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |440 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |441 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);442 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);443 gl9750_wt_off(host);444 445 /* wait for pll stable */446 mdelay(1);447}448 449static bool gl9750_ssc_enable(struct sdhci_host *host)450{451 u32 misc;452 u8 off;453 454 gl9750_wt_on(host);455 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC);456 off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc);457 gl9750_wt_off(host);458 459 return !off;460}461 462static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)463{464 u32 pll;465 u32 ssc;466 467 gl9750_wt_on(host);468 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);469 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);470 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |471 SDHCI_GLI_9750_PLLSSC_EN);472 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;473 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |474 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);475 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);476 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);477 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);478 gl9750_wt_off(host);479}480 481static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)482{483 bool enable = gl9750_ssc_enable(host);484 485 /* set pll to 205MHz and ssc */486 gl9750_set_ssc(host, enable, 0xF, 0x5A1D);487 gl9750_set_pll(host, 0x1, 0x246, 0x0);488}489 490static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host)491{492 bool enable = gl9750_ssc_enable(host);493 494 /* set pll to 100MHz and ssc */495 gl9750_set_ssc(host, enable, 0xE, 0x51EC);496 gl9750_set_pll(host, 0x1, 0x244, 0x1);497}498 499static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host)500{501 bool enable = gl9750_ssc_enable(host);502 503 /* set pll to 50MHz and ssc */504 gl9750_set_ssc(host, enable, 0xE, 0x51EC);505 gl9750_set_pll(host, 0x1, 0x244, 0x3);506}507 508static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)509{510 struct mmc_ios *ios = &host->mmc->ios;511 u16 clk;512 513 host->mmc->actual_clock = 0;514 515 gl9750_disable_ssc_pll(host);516 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);517 518 if (clock == 0)519 return;520 521 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);522 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {523 host->mmc->actual_clock = 205000000;524 gl9750_set_ssc_pll_205mhz(host);525 } else if (clock == 100000000) {526 gl9750_set_ssc_pll_100mhz(host);527 } else if (clock == 50000000) {528 gl9750_set_ssc_pll_50mhz(host);529 }530 531 sdhci_enable_clk(host, clk);532}533 534static void gl9750_hw_setting(struct sdhci_host *host)535{536 struct sdhci_pci_slot *slot = sdhci_priv(host);537 struct pci_dev *pdev;538 int aer;539 u32 value;540 541 pdev = slot->chip->pdev;542 543 gl9750_wt_on(host);544 545 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);546 value &= ~SDHCI_GLI_9750_CFG2_L1DLY;547 /* set ASPM L1 entry delay to 7.9us */548 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY,549 GLI_9750_CFG2_L1DLY_VALUE);550 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2);551 552 /* toggle PM state to allow GL9750 to enter ASPM L1.2 */553 pci_set_power_state(pdev, PCI_D3hot);554 pci_set_power_state(pdev, PCI_D0);555 556 /* mask the replay timer timeout of AER */557 aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);558 if (aer) {559 pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);560 value |= PCI_ERR_COR_REP_TIMER;561 pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);562 }563 564 gl9750_wt_off(host);565}566 567static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)568{569 int ret;570 571 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,572 PCI_IRQ_MSI | PCI_IRQ_MSIX);573 if (ret < 0) {574 pr_warn("%s: enable PCI MSI failed, error=%d\n",575 mmc_hostname(slot->host->mmc), ret);576 return;577 }578 579 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);580}581 582static inline void gl9755_wt_on(struct pci_dev *pdev)583{584 u32 wt_value;585 u32 wt_enable;586 587 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);588 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);589 590 if (wt_enable == GLI_9755_WT_EN_ON)591 return;592 593 wt_value &= ~PCI_GLI_9755_WT_EN;594 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);595 596 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);597}598 599static inline void gl9755_wt_off(struct pci_dev *pdev)600{601 u32 wt_value;602 u32 wt_enable;603 604 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);605 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);606 607 if (wt_enable == GLI_9755_WT_EN_OFF)608 return;609 610 wt_value &= ~PCI_GLI_9755_WT_EN;611 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);612 613 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);614}615 616static void gl9755_disable_ssc_pll(struct pci_dev *pdev)617{618 u32 pll;619 620 gl9755_wt_on(pdev);621 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);622 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);623 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);624 gl9755_wt_off(pdev);625}626 627static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)628{629 u32 pll;630 631 gl9755_wt_on(pdev);632 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);633 pll &= ~(PCI_GLI_9755_PLL_LDIV |634 PCI_GLI_9755_PLL_PDIV |635 PCI_GLI_9755_PLL_DIR);636 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |637 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |638 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);639 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);640 gl9755_wt_off(pdev);641 642 /* wait for pll stable */643 mdelay(1);644}645 646static bool gl9755_ssc_enable(struct pci_dev *pdev)647{648 u32 misc;649 u8 off;650 651 gl9755_wt_on(pdev);652 pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc);653 off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc);654 gl9755_wt_off(pdev);655 656 return !off;657}658 659static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)660{661 u32 pll;662 u32 ssc;663 664 gl9755_wt_on(pdev);665 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);666 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);667 pll &= ~(PCI_GLI_9755_PLLSSC_STEP |668 PCI_GLI_9755_PLLSSC_EN);669 ssc &= ~PCI_GLI_9755_PLLSSC_PPM;670 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |671 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);672 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);673 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);674 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);675 gl9755_wt_off(pdev);676}677 678static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)679{680 bool enable = gl9755_ssc_enable(pdev);681 682 /* set pll to 205MHz and ssc */683 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D);684 gl9755_set_pll(pdev, 0x1, 0x246, 0x0);685}686 687static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev)688{689 bool enable = gl9755_ssc_enable(pdev);690 691 /* set pll to 100MHz and ssc */692 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);693 gl9755_set_pll(pdev, 0x1, 0x244, 0x1);694}695 696static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev)697{698 bool enable = gl9755_ssc_enable(pdev);699 700 /* set pll to 50MHz and ssc */701 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);702 gl9755_set_pll(pdev, 0x1, 0x244, 0x3);703}704 705static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)706{707 struct sdhci_pci_slot *slot = sdhci_priv(host);708 struct mmc_ios *ios = &host->mmc->ios;709 struct pci_dev *pdev;710 u16 clk;711 712 pdev = slot->chip->pdev;713 host->mmc->actual_clock = 0;714 715 gl9755_disable_ssc_pll(pdev);716 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);717 718 if (clock == 0)719 return;720 721 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);722 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {723 host->mmc->actual_clock = 205000000;724 gl9755_set_ssc_pll_205mhz(pdev);725 } else if (clock == 100000000) {726 gl9755_set_ssc_pll_100mhz(pdev);727 } else if (clock == 50000000) {728 gl9755_set_ssc_pll_50mhz(pdev);729 }730 731 sdhci_enable_clk(host, clk);732}733 734static void gl9755_hw_setting(struct sdhci_pci_slot *slot)735{736 struct pci_dev *pdev = slot->chip->pdev;737 int aer;738 u32 value;739 740 gl9755_wt_on(pdev);741 742 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);743 /*744 * Apple ARM64 platforms using these chips may have745 * inverted CD/WP detection.746 */747 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted"))748 value |= PCI_GLI_9755_INVERT_CD;749 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted"))750 value |= PCI_GLI_9755_INVERT_WP;751 value &= ~PCI_GLI_9755_LFCLK;752 value &= ~PCI_GLI_9755_DMACLK;753 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);754 755 /* enable short circuit protection */756 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value);757 value &= ~PCI_GLI_9755_SCP_DIS;758 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value);759 760 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value);761 value &= ~PCI_GLI_9755_CFG2_L1DLY;762 /* set ASPM L1 entry delay to 7.9us */763 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY,764 GLI_9755_CFG2_L1DLY_VALUE);765 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);766 767 /* toggle PM state to allow GL9755 to enter ASPM L1.2 */768 pci_set_power_state(pdev, PCI_D3hot);769 pci_set_power_state(pdev, PCI_D0);770 771 /* mask the replay timer timeout of AER */772 aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);773 if (aer) {774 pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);775 value |= PCI_ERR_COR_REP_TIMER;776 pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);777 }778 779 gl9755_wt_off(pdev);780}781 782static inline void gl9767_vhs_read(struct pci_dev *pdev)783{784 u32 vhs_enable;785 u32 vhs_value;786 787 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);788 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);789 790 if (vhs_enable == GLI_9767_VHS_REV_R)791 return;792 793 vhs_value &= ~GLI_9767_VHS_REV;794 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_R);795 796 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);797}798 799static inline void gl9767_vhs_write(struct pci_dev *pdev)800{801 u32 vhs_enable;802 u32 vhs_value;803 804 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);805 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);806 807 if (vhs_enable == GLI_9767_VHS_REV_W)808 return;809 810 vhs_value &= ~GLI_9767_VHS_REV;811 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_W);812 813 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);814}815 816static bool gl9767_ssc_enable(struct pci_dev *pdev)817{818 u32 value;819 u8 enable;820 821 gl9767_vhs_write(pdev);822 823 pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value);824 enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value);825 826 gl9767_vhs_read(pdev);827 828 return enable;829}830 831static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)832{833 u32 pll;834 u32 ssc;835 836 gl9767_vhs_write(pdev);837 838 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);839 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc);840 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING |841 PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);842 ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM;843 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) |844 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable);845 ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm);846 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc);847 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);848 849 gl9767_vhs_read(pdev);850}851 852static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)853{854 u32 pll;855 856 gl9767_vhs_write(pdev);857 858 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);859 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV |860 PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV |861 PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN);862 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) |863 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) |864 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir);865 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);866 867 gl9767_vhs_read(pdev);868 869 /* wait for pll stable */870 usleep_range(1000, 1100);871}872 873static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev)874{875 bool enable = gl9767_ssc_enable(pdev);876 877 /* set pll to 205MHz and ssc */878 gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3);879 gl9767_set_pll(pdev, 0x1, 0x246, 0x0);880}881 882static void gl9767_disable_ssc_pll(struct pci_dev *pdev)883{884 u32 pll;885 886 gl9767_vhs_write(pdev);887 888 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);889 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);890 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);891 892 gl9767_vhs_read(pdev);893}894 895static void gl9767_set_low_power_negotiation(struct pci_dev *pdev, bool enable)896{897 u32 value;898 899 gl9767_vhs_write(pdev);900 901 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);902 if (enable)903 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;904 else905 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;906 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);907 908 gl9767_vhs_read(pdev);909}910 911static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)912{913 struct sdhci_pci_slot *slot = sdhci_priv(host);914 struct mmc_ios *ios = &host->mmc->ios;915 struct pci_dev *pdev;916 u16 clk;917 918 pdev = slot->chip->pdev;919 host->mmc->actual_clock = 0;920 921 gl9767_set_low_power_negotiation(pdev, false);922 gl9767_disable_ssc_pll(pdev);923 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);924 925 if (clock == 0) {926 gl9767_set_low_power_negotiation(pdev, true);927 return;928 }929 930 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);931 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {932 host->mmc->actual_clock = 205000000;933 gl9767_set_ssc_pll_205mhz(pdev);934 }935 936 sdhci_enable_clk(host, clk);937 gl9767_set_low_power_negotiation(pdev, true);938}939 940static void gli_set_9767(struct sdhci_host *host)941{942 u32 value;943 944 value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE);945 value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET;946 sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE);947}948 949static void gl9767_hw_setting(struct sdhci_pci_slot *slot)950{951 struct pci_dev *pdev = slot->chip->pdev;952 u32 value;953 954 gl9767_vhs_write(pdev);955 956 pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value);957 value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |958 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE |959 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL);960 961 value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |962 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE,963 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE) |964 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL,965 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE);966 pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value);967 968 pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value);969 value &= ~(PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 |970 PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 |971 PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN);972 973 value |= PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST |974 PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST |975 PCIE_GLI_9767_SCR_AXI_REQ |976 PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN |977 PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF;978 pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value);979 980 gl9767_vhs_read(pdev);981}982 983static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask)984{985 sdhci_reset(host, mask);986 gli_set_9767(host);987}988 989static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)990{991 struct sdhci_host *host = mmc_priv(mmc);992 struct sdhci_pci_slot *slot = sdhci_priv(host);993 struct pci_dev *pdev;994 u32 value;995 int i;996 997 pdev = slot->chip->pdev;998 999 if (mmc->ops->get_ro(mmc)) {1000 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);1001 return 0;1002 }1003 1004 gl9767_vhs_write(pdev);1005 1006 pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value);1007 value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN);1008 pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value);1009 1010 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value);1011 value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME;1012 value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME,1013 PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE);1014 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value);1015 1016 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);1017 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE;1018 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value);1019 1020 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value);1021 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN;1022 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value);1023 1024 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value);1025 value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN;1026 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value);1027 1028 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);1029 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;1030 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);1031 1032 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);1033 value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);1034 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);1035 1036 value = sdhci_readb(host, SDHCI_POWER_CONTROL);1037 value |= (SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON);1038 sdhci_writeb(host, value, SDHCI_POWER_CONTROL);1039 1040 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);1041 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE;1042 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);1043 1044 for (i = 0; i < 2; i++) {1045 usleep_range(10000, 10100);1046 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);1047 if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) {1048 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2,1049 value);1050 break;1051 }1052 }1053 1054 pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value);1055 if (value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) {1056 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);1057 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE;1058 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);1059 } else {1060 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);1061 1062 value = sdhci_readb(host, SDHCI_POWER_CONTROL);1063 value &= ~(SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON);1064 sdhci_writeb(host, value, SDHCI_POWER_CONTROL);1065 1066 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);1067 value |= (SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);1068 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);1069 }1070 1071 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);1072 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;1073 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);1074 gl9767_vhs_read(pdev);1075 1076 return 0;1077}1078 1079static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)1080{1081 struct sdhci_host *host = slot->host;1082 1083 gl9750_hw_setting(host);1084 gli_pcie_enable_msi(slot);1085 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;1086 sdhci_enable_v4_mode(host);1087 1088 return 0;1089}1090 1091static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)1092{1093 struct sdhci_host *host = slot->host;1094 1095 gl9755_hw_setting(slot);1096 gli_pcie_enable_msi(slot);1097 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;1098 sdhci_enable_v4_mode(host);1099 1100 return 0;1101}1102 1103static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot)1104{1105 struct sdhci_host *host = slot->host;1106 1107 gli_set_9767(host);1108 gl9767_hw_setting(slot);1109 gli_pcie_enable_msi(slot);1110 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;1111 host->mmc->caps2 |= MMC_CAP2_SD_EXP;1112 host->mmc_host_ops.init_sd_express = gl9767_init_sd_express;1113 sdhci_enable_v4_mode(host);1114 1115 return 0;1116}1117 1118static void sdhci_gli_voltage_switch(struct sdhci_host *host)1119{1120 /*1121 * According to Section 3.6.1 signal voltage switch procedure in1122 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as1123 * follows:1124 * (6) Set 1.8V Signal Enable in the Host Control 2 register.1125 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this1126 * period.1127 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to1128 * step (12).1129 *1130 * Wait 5ms after set 1.8V signal enable in Host Control 2 register1131 * to ensure 1.8V signal enable bit is set by GL9750/GL9755.1132 *1133 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires1134 * slightly longer than 5ms before the control register reports that1135 * 1.8V is ready, and far longer still before the card will actually1136 * work reliably.1137 */1138 usleep_range(100000, 110000);1139}1140 1141static void sdhci_gl9767_voltage_switch(struct sdhci_host *host)1142{1143 /*1144 * According to Section 3.6.1 signal voltage switch procedure in1145 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as1146 * follows:1147 * (6) Set 1.8V Signal Enable in the Host Control 2 register.1148 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this1149 * period.1150 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to1151 * step (12).1152 *1153 * Wait 5ms after set 1.8V signal enable in Host Control 2 register1154 * to ensure 1.8V signal enable bit is set by GL9767.1155 *1156 */1157 usleep_range(5000, 5500);1158}1159 1160static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)1161{1162 sdhci_reset(host, mask);1163 gli_set_9750(host);1164}1165 1166static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)1167{1168 u32 value;1169 1170 value = readl(host->ioaddr + reg);1171 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))1172 value |= 0xc8;1173 1174 return value;1175}1176 1177static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,1178 struct mmc_ios *ios)1179{1180 struct sdhci_host *host = mmc_priv(mmc);1181 u32 val;1182 1183 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);1184 if (ios->enhanced_strobe)1185 val |= SDHCI_GLI_9763E_HS400_ES_BIT;1186 else1187 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;1188 1189 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);1190}1191 1192static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot,1193 bool enable)1194{1195 struct pci_dev *pdev = slot->chip->pdev;1196 u32 value;1197 1198 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);1199 value &= ~GLI_9763E_VHS_REV;1200 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);1201 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);1202 1203 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value);1204 1205 if (enable)1206 value &= ~GLI_9763E_CFG_LPSN_DIS;1207 else1208 value |= GLI_9763E_CFG_LPSN_DIS;1209 1210 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value);1211 1212 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);1213 value &= ~GLI_9763E_VHS_REV;1214 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);1215 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);1216}1217 1218static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,1219 unsigned int timing)1220{1221 u16 ctrl_2;1222 1223 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);1224 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;1225 if (timing == MMC_TIMING_MMC_HS200)1226 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;1227 else if (timing == MMC_TIMING_MMC_HS)1228 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;1229 else if (timing == MMC_TIMING_MMC_DDR52)1230 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;1231 else if (timing == MMC_TIMING_MMC_HS400)1232 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;1233 1234 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);1235}1236 1237static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)1238{1239 sdhci_dumpregs(mmc_priv(mmc));1240}1241 1242static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)1243{1244 struct cqhci_host *cq_host = mmc->cqe_private;1245 u32 value;1246 1247 value = cqhci_readl(cq_host, CQHCI_CFG);1248 value |= CQHCI_ENABLE;1249 cqhci_writel(cq_host, value, CQHCI_CFG);1250}1251 1252static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)1253{1254 struct sdhci_host *host = mmc_priv(mmc);1255 1256 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);1257 sdhci_cqe_enable(mmc);1258}1259 1260static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)1261{1262 int cmd_error = 0;1263 int data_error = 0;1264 1265 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))1266 return intmask;1267 1268 cqhci_irq(host->mmc, intmask, cmd_error, data_error);1269 1270 return 0;1271}1272 1273static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)1274{1275 struct sdhci_host *host = mmc_priv(mmc);1276 struct cqhci_host *cq_host = mmc->cqe_private;1277 u32 value;1278 1279 value = cqhci_readl(cq_host, CQHCI_CFG);1280 value &= ~CQHCI_ENABLE;1281 cqhci_writel(cq_host, value, CQHCI_CFG);1282 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);1283}1284 1285static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {1286 .enable = sdhci_gl9763e_cqe_enable,1287 .disable = sdhci_cqe_disable,1288 .dumpregs = sdhci_gl9763e_dumpregs,1289 .pre_enable = sdhci_gl9763e_cqe_pre_enable,1290 .post_disable = sdhci_gl9763e_cqe_post_disable,1291};1292 1293static int gl9763e_add_host(struct sdhci_pci_slot *slot)1294{1295 struct device *dev = &slot->chip->pdev->dev;1296 struct sdhci_host *host = slot->host;1297 struct cqhci_host *cq_host;1298 bool dma64;1299 int ret;1300 1301 ret = sdhci_setup_host(host);1302 if (ret)1303 return ret;1304 1305 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);1306 if (!cq_host) {1307 ret = -ENOMEM;1308 goto cleanup;1309 }1310 1311 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;1312 cq_host->ops = &sdhci_gl9763e_cqhci_ops;1313 1314 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;1315 if (dma64)1316 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;1317 1318 ret = cqhci_init(cq_host, host->mmc, dma64);1319 if (ret)1320 goto cleanup;1321 1322 ret = __sdhci_add_host(host);1323 if (ret)1324 goto cleanup;1325 1326 /* Disable LPM negotiation to avoid entering L1 state. */1327 gl9763e_set_low_power_negotiation(slot, false);1328 1329 return 0;1330 1331cleanup:1332 sdhci_cleanup_host(host);1333 return ret;1334}1335 1336static void gli_set_gl9763e(struct sdhci_pci_slot *slot)1337{1338 struct pci_dev *pdev = slot->chip->pdev;1339 u32 value;1340 1341 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);1342 value &= ~GLI_9763E_VHS_REV;1343 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);1344 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);1345 1346 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);1347 value |= GLI_9763E_SCR_AXI_REQ;1348 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);1349 1350 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);1351 value &= ~GLI_9763E_HS400_SLOW;1352 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);1353 1354 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);1355 value &= ~GLI_9763E_CFG2_L1DLY;1356 /* set ASPM L1 entry delay to 21us */1357 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);1358 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);1359 1360 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);1361 value &= ~GLI_9763E_HS400_RXDLY;1362 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);1363 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);1364 1365 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);1366 value &= ~GLI_9763E_VHS_REV;1367 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);1368 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);1369}1370 1371#ifdef CONFIG_PM1372static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip)1373{1374 struct sdhci_pci_slot *slot = chip->slots[0];1375 struct sdhci_host *host = slot->host;1376 u16 clock;1377 1378 /* Enable LPM negotiation to allow entering L1 state */1379 gl9763e_set_low_power_negotiation(slot, true);1380 1381 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);1382 clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN);1383 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);1384 1385 return 0;1386}1387 1388static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip)1389{1390 struct sdhci_pci_slot *slot = chip->slots[0];1391 struct sdhci_host *host = slot->host;1392 u16 clock;1393 1394 if (host->mmc->ios.power_mode != MMC_POWER_ON)1395 return 0;1396 1397 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);1398 1399 clock |= SDHCI_CLOCK_PLL_EN;1400 clock &= ~SDHCI_CLOCK_INT_STABLE;1401 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);1402 1403 /* Wait max 150 ms */1404 if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE),1405 1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) {1406 pr_err("%s: PLL clock never stabilised.\n",1407 mmc_hostname(host->mmc));1408 sdhci_dumpregs(host);1409 }1410 1411 clock |= SDHCI_CLOCK_CARD_EN;1412 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);1413 1414 /* Disable LPM negotiation to avoid entering L1 state. */1415 gl9763e_set_low_power_negotiation(slot, false);1416 1417 return 0;1418}1419#endif1420 1421#ifdef CONFIG_PM_SLEEP1422static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)1423{1424 struct sdhci_pci_slot *slot = chip->slots[0];1425 1426 pci_free_irq_vectors(slot->chip->pdev);1427 gli_pcie_enable_msi(slot);1428 1429 return sdhci_pci_resume_host(chip);1430}1431 1432static int gl9763e_resume(struct sdhci_pci_chip *chip)1433{1434 struct sdhci_pci_slot *slot = chip->slots[0];1435 int ret;1436 1437 ret = sdhci_pci_gli_resume(chip);1438 if (ret)1439 return ret;1440 1441 ret = cqhci_resume(slot->host->mmc);1442 if (ret)1443 return ret;1444 1445 /*1446 * Disable LPM negotiation to bring device back in sync1447 * with its runtime_pm state.1448 */1449 gl9763e_set_low_power_negotiation(slot, false);1450 1451 return 0;1452}1453 1454static int gl9763e_suspend(struct sdhci_pci_chip *chip)1455{1456 struct sdhci_pci_slot *slot = chip->slots[0];1457 int ret;1458 1459 /*1460 * Certain SoCs can suspend only with the bus in low-1461 * power state, notably x86 SoCs when using S0ix.1462 * Re-enable LPM negotiation to allow entering L1 state1463 * and entering system suspend.1464 */1465 gl9763e_set_low_power_negotiation(slot, true);1466 1467 ret = cqhci_suspend(slot->host->mmc);1468 if (ret)1469 goto err_suspend;1470 1471 ret = sdhci_suspend_host(slot->host);1472 if (ret)1473 goto err_suspend_host;1474 1475 return 0;1476 1477err_suspend_host:1478 cqhci_resume(slot->host->mmc);1479err_suspend:1480 gl9763e_set_low_power_negotiation(slot, false);1481 return ret;1482}1483#endif1484 1485static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)1486{1487 struct pci_dev *pdev = slot->chip->pdev;1488 struct sdhci_host *host = slot->host;1489 u32 value;1490 1491 host->mmc->caps |= MMC_CAP_8_BIT_DATA |1492 MMC_CAP_1_8V_DDR |1493 MMC_CAP_NONREMOVABLE;1494 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |1495 MMC_CAP2_HS400_1_8V |1496 MMC_CAP2_HS400_ES |1497 MMC_CAP2_NO_SDIO |1498 MMC_CAP2_NO_SD;1499 1500 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);1501 if (!(value & GLI_9763E_MB_CMDQ_OFF))1502 if (value & GLI_9763E_MB_ERP_ON)1503 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;1504 1505 gli_pcie_enable_msi(slot);1506 host->mmc_host_ops.hs400_enhanced_strobe =1507 gl9763e_hs400_enhanced_strobe;1508 gli_set_gl9763e(slot);1509 sdhci_enable_v4_mode(host);1510 1511 return 0;1512}1513 1514#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)1515 1516static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)1517{1518 u32 val = readl(host->ioaddr + (reg & ~3));1519 u16 word;1520 1521 word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;1522 return word;1523}1524 1525static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)1526{1527 u32 val = readl(host->ioaddr + (reg & ~3));1528 u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;1529 1530 return byte;1531}1532 1533static const struct sdhci_ops sdhci_gl9755_ops = {1534 .read_w = sdhci_gli_readw,1535 .read_b = sdhci_gli_readb,1536 .set_clock = sdhci_gl9755_set_clock,1537 .enable_dma = sdhci_pci_enable_dma,1538 .set_bus_width = sdhci_set_bus_width,1539 .reset = sdhci_reset,1540 .set_uhs_signaling = sdhci_set_uhs_signaling,1541 .voltage_switch = sdhci_gli_voltage_switch,1542};1543 1544const struct sdhci_pci_fixes sdhci_gl9755 = {1545 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,1546 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,1547 .probe_slot = gli_probe_slot_gl9755,1548 .ops = &sdhci_gl9755_ops,1549#ifdef CONFIG_PM_SLEEP1550 .resume = sdhci_pci_gli_resume,1551#endif1552};1553 1554static const struct sdhci_ops sdhci_gl9750_ops = {1555 .read_w = sdhci_gli_readw,1556 .read_b = sdhci_gli_readb,1557 .read_l = sdhci_gl9750_readl,1558 .set_clock = sdhci_gl9750_set_clock,1559 .enable_dma = sdhci_pci_enable_dma,1560 .set_bus_width = sdhci_set_bus_width,1561 .reset = sdhci_gl9750_reset,1562 .set_uhs_signaling = sdhci_set_uhs_signaling,1563 .voltage_switch = sdhci_gli_voltage_switch,1564 .platform_execute_tuning = gl9750_execute_tuning,1565};1566 1567const struct sdhci_pci_fixes sdhci_gl9750 = {1568 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,1569 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,1570 .probe_slot = gli_probe_slot_gl9750,1571 .ops = &sdhci_gl9750_ops,1572#ifdef CONFIG_PM_SLEEP1573 .resume = sdhci_pci_gli_resume,1574#endif1575};1576 1577static const struct sdhci_ops sdhci_gl9763e_ops = {1578 .set_clock = sdhci_set_clock,1579 .enable_dma = sdhci_pci_enable_dma,1580 .set_bus_width = sdhci_set_bus_width,1581 .reset = sdhci_and_cqhci_reset,1582 .set_uhs_signaling = sdhci_set_gl9763e_signaling,1583 .voltage_switch = sdhci_gli_voltage_switch,1584 .irq = sdhci_gl9763e_cqhci_irq,1585};1586 1587const struct sdhci_pci_fixes sdhci_gl9763e = {1588 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,1589 .probe_slot = gli_probe_slot_gl9763e,1590 .ops = &sdhci_gl9763e_ops,1591#ifdef CONFIG_PM_SLEEP1592 .resume = gl9763e_resume,1593 .suspend = gl9763e_suspend,1594#endif1595#ifdef CONFIG_PM1596 .runtime_suspend = gl9763e_runtime_suspend,1597 .runtime_resume = gl9763e_runtime_resume,1598 .allow_runtime_pm = true,1599#endif1600 .add_host = gl9763e_add_host,1601};1602 1603static const struct sdhci_ops sdhci_gl9767_ops = {1604 .set_clock = sdhci_gl9767_set_clock,1605 .enable_dma = sdhci_pci_enable_dma,1606 .set_bus_width = sdhci_set_bus_width,1607 .reset = sdhci_gl9767_reset,1608 .set_uhs_signaling = sdhci_set_uhs_signaling,1609 .voltage_switch = sdhci_gl9767_voltage_switch,1610};1611 1612const struct sdhci_pci_fixes sdhci_gl9767 = {1613 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,1614 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50,1615 .probe_slot = gli_probe_slot_gl9767,1616 .ops = &sdhci_gl9767_ops,1617#ifdef CONFIG_PM_SLEEP1618 .resume = sdhci_pci_gli_resume,1619#endif1620};1621