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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __SDHCI_PCI_H3#define __SDHCI_PCI_H4 5/*6 * PCI device IDs, sub IDs7 */8 9#define PCI_DEVICE_ID_O2_SDS0 0x842010#define PCI_DEVICE_ID_O2_SDS1 0x842111#define PCI_DEVICE_ID_O2_FUJIN2 0x852012#define PCI_DEVICE_ID_O2_SEABIRD0 0x862013#define PCI_DEVICE_ID_O2_SEABIRD1 0x862114#define PCI_DEVICE_ID_O2_GG8_9860 0x986015#define PCI_DEVICE_ID_O2_GG8_9861 0x986116#define PCI_DEVICE_ID_O2_GG8_9862 0x986217#define PCI_DEVICE_ID_O2_GG8_9863 0x986318 19#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x880920#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a21#define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f1422#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f1523#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f1624#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f5025#define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x229426#define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x229527#define PCI_DEVICE_ID_INTEL_BSW_SD 0x229628#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x119029#define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f930#define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa31#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb32#define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e533#define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e634#define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A735#define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b36#define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c37#define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d38#define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db39#define PCI_DEVICE_ID_INTEL_CDF_EMMC 0x18db40#define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca41#define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc42#define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad043#define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca44#define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc45#define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad046#define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca47#define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc48#define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad049#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca50#define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc51#define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d052#define PCI_DEVICE_ID_INTEL_CNP_EMMC 0x9dc453#define PCI_DEVICE_ID_INTEL_CNP_SD 0x9df554#define PCI_DEVICE_ID_INTEL_CNPH_SD 0xa37555#define PCI_DEVICE_ID_INTEL_ICP_EMMC 0x34c456#define PCI_DEVICE_ID_INTEL_ICP_SD 0x34f857#define PCI_DEVICE_ID_INTEL_EHL_EMMC 0x4b4758#define PCI_DEVICE_ID_INTEL_EHL_SD 0x4b4859#define PCI_DEVICE_ID_INTEL_CML_EMMC 0x02c460#define PCI_DEVICE_ID_INTEL_CML_SD 0x02f561#define PCI_DEVICE_ID_INTEL_CMLH_SD 0x06f562#define PCI_DEVICE_ID_INTEL_JSL_EMMC 0x4dc463#define PCI_DEVICE_ID_INTEL_JSL_SD 0x4df864#define PCI_DEVICE_ID_INTEL_LKF_EMMC 0x98c465#define PCI_DEVICE_ID_INTEL_LKF_SD 0x98f866#define PCI_DEVICE_ID_INTEL_ADL_EMMC 0x54c467 68#define PCI_DEVICE_ID_SYSKONNECT_8000 0x800069#define PCI_DEVICE_ID_VIA_95D0 0x95d070#define PCI_DEVICE_ID_REALTEK_5250 0x525071 72#define PCI_SUBDEVICE_ID_NI_7884 0x788473#define PCI_SUBDEVICE_ID_NI_78E3 0x78e374 75#define PCI_VENDOR_ID_ARASAN 0x16e676#define PCI_DEVICE_ID_ARASAN_PHY_EMMC 0x067077 78#define PCI_DEVICE_ID_SYNOPSYS_DWC_MSHC 0xc20279 80#define PCI_DEVICE_ID_GLI_9755 0x975581#define PCI_DEVICE_ID_GLI_9750 0x975082#define PCI_DEVICE_ID_GLI_9763E 0xe76383#define PCI_DEVICE_ID_GLI_9767 0x976784 85/*86 * PCI device class and mask87 */88 89#define SYSTEM_SDHCI (PCI_CLASS_SYSTEM_SDHCI << 8)90#define PCI_CLASS_MASK 0xFFFF0091 92/*93 * Macros for PCI device-description94 */95 96#define _PCI_VEND(vend) PCI_VENDOR_ID_##vend97#define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev98#define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev99 100#define SDHCI_PCI_DEVICE(vend, dev, cfg) { \101 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \102 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \103 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \104}105 106#define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \107 .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \108 .subvendor = _PCI_VEND(subvend), \109 .subdevice = _PCI_SUBDEV(subvend, subdev), \110 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \111}112 113#define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \114 .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \115 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \116 .class = (cl), .class_mask = (cl_msk), \117 .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \118}119 120/*121 * PCI registers122 */123 124#define PCI_SDHCI_IFPIO 0x00125#define PCI_SDHCI_IFDMA 0x01126#define PCI_SDHCI_IFVENDOR 0x02127 128#define PCI_SLOT_INFO 0x40 /* 8 bits */129#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)130#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07131 132#define MAX_SLOTS 8133 134struct sdhci_pci_chip;135struct sdhci_pci_slot;136 137struct sdhci_pci_fixes {138 unsigned int quirks;139 unsigned int quirks2;140 bool allow_runtime_pm;141 bool own_cd_for_runtime_pm;142 143 int (*probe) (struct sdhci_pci_chip *);144 145 int (*probe_slot) (struct sdhci_pci_slot *);146 int (*add_host) (struct sdhci_pci_slot *);147 void (*remove_slot) (struct sdhci_pci_slot *, int);148 149#ifdef CONFIG_PM_SLEEP150 int (*suspend) (struct sdhci_pci_chip *);151 int (*resume) (struct sdhci_pci_chip *);152#endif153#ifdef CONFIG_PM154 int (*runtime_suspend) (struct sdhci_pci_chip *);155 int (*runtime_resume) (struct sdhci_pci_chip *);156#endif157 158 const struct sdhci_ops *ops;159 size_t priv_size;160};161 162struct sdhci_pci_slot {163 struct sdhci_pci_chip *chip;164 struct sdhci_host *host;165 166 int cd_idx;167 bool cd_override_level;168 169 void (*hw_reset)(struct sdhci_host *host);170 unsigned long private[] ____cacheline_aligned;171};172 173struct sdhci_pci_chip {174 struct pci_dev *pdev;175 176 unsigned int quirks;177 unsigned int quirks2;178 bool allow_runtime_pm;179 bool pm_retune;180 bool rpm_retune;181 const struct sdhci_pci_fixes *fixes;182 183 int num_slots; /* Slots on controller */184 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */185};186 187static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot)188{189 return (void *)slot->private;190}191 192#ifdef CONFIG_PM_SLEEP193int sdhci_pci_resume_host(struct sdhci_pci_chip *chip);194#endif195int sdhci_pci_enable_dma(struct sdhci_host *host);196 197extern const struct sdhci_pci_fixes sdhci_arasan;198extern const struct sdhci_pci_fixes sdhci_snps;199extern const struct sdhci_pci_fixes sdhci_o2;200extern const struct sdhci_pci_fixes sdhci_gl9750;201extern const struct sdhci_pci_fixes sdhci_gl9755;202extern const struct sdhci_pci_fixes sdhci_gl9763e;203extern const struct sdhci_pci_fixes sdhci_gl9767;204 205#endif /* __SDHCI_PCI_H */206