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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright 2010 MontaVista Software, LLC.4 *5 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>6 */7 8#ifndef _DRIVERS_MMC_SDHCI_PLTFM_H9#define _DRIVERS_MMC_SDHCI_PLTFM_H10 11#include <linux/clk.h>12#include <linux/platform_device.h>13#include "sdhci.h"14 15struct sdhci_pltfm_data {16 const struct sdhci_ops *ops;17 unsigned int quirks;18 unsigned int quirks2;19};20 21struct sdhci_pltfm_host {22 struct clk *clk;23 24 /* migrate from sdhci_of_host */25 unsigned int clock;26 u16 xfer_mode_shadow;27 28 unsigned long private[] ____cacheline_aligned;29};30 31#ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER32/*33 * These accessors are designed for big endian hosts doing I/O to34 * little endian controllers incorporating a 32-bit hardware byte swapper.35 */36static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)37{38 return in_be32(host->ioaddr + reg);39}40 41static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)42{43 return in_be16(host->ioaddr + (reg ^ 0x2));44}45 46static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)47{48 return in_8(host->ioaddr + (reg ^ 0x3));49}50 51static inline void sdhci_be32bs_writel(struct sdhci_host *host,52 u32 val, int reg)53{54 out_be32(host->ioaddr + reg, val);55}56 57static inline void sdhci_be32bs_writew(struct sdhci_host *host,58 u16 val, int reg)59{60 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);61 int base = reg & ~0x3;62 int shift = (reg & 0x2) * 8;63 64 switch (reg) {65 case SDHCI_TRANSFER_MODE:66 /*67 * Postpone this write, we must do it together with a68 * command write that is down below.69 */70 pltfm_host->xfer_mode_shadow = val;71 return;72 case SDHCI_COMMAND:73 sdhci_be32bs_writel(host,74 val << 16 | pltfm_host->xfer_mode_shadow,75 SDHCI_TRANSFER_MODE);76 return;77 }78 clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);79}80 81static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)82{83 int base = reg & ~0x3;84 int shift = (reg & 0x3) * 8;85 86 clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);87}88#endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */89 90void sdhci_get_property(struct platform_device *pdev);91 92static inline void sdhci_get_of_property(struct platform_device *pdev)93{94 return sdhci_get_property(pdev);95}96 97extern struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,98 const struct sdhci_pltfm_data *pdata,99 size_t priv_size);100extern void sdhci_pltfm_free(struct platform_device *pdev);101 102extern int sdhci_pltfm_init_and_add_host(struct platform_device *pdev,103 const struct sdhci_pltfm_data *pdata,104 size_t priv_size);105extern void sdhci_pltfm_remove(struct platform_device *pdev);106 107extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);108 109static inline void *sdhci_pltfm_priv(struct sdhci_pltfm_host *host)110{111 return host->private;112}113 114extern const struct dev_pm_ops sdhci_pltfm_pmops;115#ifdef CONFIG_PM_SLEEP116int sdhci_pltfm_suspend(struct device *dev);117int sdhci_pltfm_resume(struct device *dev);118#else119static inline int sdhci_pltfm_suspend(struct device *dev) { return 0; }120static inline int sdhci_pltfm_resume(struct device *dev) { return 0; }121#endif122 123#endif /* _DRIVERS_MMC_SDHCI_PLTFM_H */124