879 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * PHY support for Xenon SDHC4 *5 * Copyright (C) 2016 Marvell, All Rights Reserved.6 *7 * Author: Hu Ziji <huziji@marvell.com>8 * Date: 2016-8-249 */10 11#include <linux/slab.h>12#include <linux/delay.h>13#include <linux/ktime.h>14#include <linux/iopoll.h>15#include <linux/of_address.h>16 17#include "sdhci-pltfm.h"18#include "sdhci-xenon.h"19 20/* Register base for eMMC PHY 5.0 Version */21#define XENON_EMMC_5_0_PHY_REG_BASE 0x016022/* Register base for eMMC PHY 5.1 Version */23#define XENON_EMMC_PHY_REG_BASE 0x017024 25#define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE26#define XENON_EMMC_5_0_PHY_TIMING_ADJUST XENON_EMMC_5_0_PHY_REG_BASE27#define XENON_TIMING_ADJUST_SLOW_MODE BIT(29)28#define XENON_TIMING_ADJUST_SDIO_MODE BIT(28)29#define XENON_SAMPL_INV_QSP_PHASE_SELECT BIT(18)30#define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT 1831#define XENON_PHY_INITIALIZAION BIT(31)32#define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF33#define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT 1234#define XENON_FC_SYNC_EN_DURATION_MASK 0xF35#define XENON_FC_SYNC_EN_DURATION_SHIFT 836#define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF37#define XENON_FC_SYNC_RST_EN_DURATION_SHIFT 438#define XENON_FC_SYNC_RST_DURATION_MASK 0xF39#define XENON_FC_SYNC_RST_DURATION_SHIFT 040 41#define XENON_EMMC_PHY_FUNC_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x4)42#define XENON_EMMC_5_0_PHY_FUNC_CONTROL \43 (XENON_EMMC_5_0_PHY_REG_BASE + 0x4)44#define XENON_ASYNC_DDRMODE_MASK BIT(23)45#define XENON_ASYNC_DDRMODE_SHIFT 2346#define XENON_CMD_DDR_MODE BIT(16)47#define XENON_DQ_DDR_MODE_SHIFT 848#define XENON_DQ_DDR_MODE_MASK 0xFF49#define XENON_DQ_ASYNC_MODE BIT(4)50 51#define XENON_EMMC_PHY_PAD_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x8)52#define XENON_EMMC_5_0_PHY_PAD_CONTROL \53 (XENON_EMMC_5_0_PHY_REG_BASE + 0x8)54#define XENON_REC_EN_SHIFT 2455#define XENON_REC_EN_MASK 0xF56#define XENON_FC_DQ_RECEN BIT(24)57#define XENON_FC_CMD_RECEN BIT(25)58#define XENON_FC_QSP_RECEN BIT(26)59#define XENON_FC_QSN_RECEN BIT(27)60#define XENON_OEN_QSN BIT(28)61#define XENON_AUTO_RECEN_CTRL BIT(30)62#define XENON_FC_ALL_CMOS_RECEIVER 0xF00063 64#define XENON_EMMC5_FC_QSP_PD BIT(18)65#define XENON_EMMC5_FC_QSP_PU BIT(22)66#define XENON_EMMC5_FC_CMD_PD BIT(17)67#define XENON_EMMC5_FC_CMD_PU BIT(21)68#define XENON_EMMC5_FC_DQ_PD BIT(16)69#define XENON_EMMC5_FC_DQ_PU BIT(20)70 71#define XENON_EMMC_PHY_PAD_CONTROL1 (XENON_EMMC_PHY_REG_BASE + 0xC)72#define XENON_EMMC5_1_FC_QSP_PD BIT(9)73#define XENON_EMMC5_1_FC_QSP_PU BIT(25)74#define XENON_EMMC5_1_FC_CMD_PD BIT(8)75#define XENON_EMMC5_1_FC_CMD_PU BIT(24)76#define XENON_EMMC5_1_FC_DQ_PD 0xFF77#define XENON_EMMC5_1_FC_DQ_PU (0xFF << 16)78 79#define XENON_EMMC_PHY_PAD_CONTROL2 (XENON_EMMC_PHY_REG_BASE + 0x10)80#define XENON_EMMC_5_0_PHY_PAD_CONTROL2 \81 (XENON_EMMC_5_0_PHY_REG_BASE + 0xC)82#define XENON_ZNR_MASK 0x1F83#define XENON_ZNR_SHIFT 884#define XENON_ZPR_MASK 0x1F85/* Preferred ZNR and ZPR value vary between different boards.86 * The specific ZNR and ZPR value should be defined here87 * according to board actual timing.88 */89#define XENON_ZNR_DEF_VALUE 0xF90#define XENON_ZPR_DEF_VALUE 0xF91 92#define XENON_EMMC_PHY_DLL_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x14)93#define XENON_EMMC_5_0_PHY_DLL_CONTROL \94 (XENON_EMMC_5_0_PHY_REG_BASE + 0x10)95#define XENON_DLL_ENABLE BIT(31)96#define XENON_DLL_UPDATE_STROBE_5_0 BIT(30)97#define XENON_DLL_REFCLK_SEL BIT(30)98#define XENON_DLL_UPDATE BIT(23)99#define XENON_DLL_PHSEL1_SHIFT 24100#define XENON_DLL_PHSEL0_SHIFT 16101#define XENON_DLL_PHASE_MASK 0x3F102#define XENON_DLL_PHASE_90_DEGREE 0x1F103#define XENON_DLL_FAST_LOCK BIT(5)104#define XENON_DLL_GAIN2X BIT(3)105#define XENON_DLL_BYPASS_EN BIT(0)106 107#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \108 (XENON_EMMC_5_0_PHY_REG_BASE + 0x14)109#define XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE 0x5A54110#define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18)111#define XENON_LOGIC_TIMING_VALUE 0x00AA8977112 113#define XENON_MAX_PHY_TIMEOUT_LOOPS 100114 115/*116 * List offset of PHY registers and some special register values117 * in eMMC PHY 5.0 or eMMC PHY 5.1118 */119struct xenon_emmc_phy_regs {120 /* Offset of Timing Adjust register */121 u16 timing_adj;122 /* Offset of Func Control register */123 u16 func_ctrl;124 /* Offset of Pad Control register */125 u16 pad_ctrl;126 /* Offset of Pad Control register 2 */127 u16 pad_ctrl2;128 /* Offset of DLL Control register */129 u16 dll_ctrl;130 /* Offset of Logic Timing Adjust register */131 u16 logic_timing_adj;132 /* DLL Update Enable bit */133 u32 dll_update;134 /* value in Logic Timing Adjustment register */135 u32 logic_timing_val;136};137 138static const char * const phy_types[] = {139 "emmc 5.0 phy",140 "emmc 5.1 phy"141};142 143enum xenon_phy_type_enum {144 EMMC_5_0_PHY,145 EMMC_5_1_PHY,146 NR_PHY_TYPES147};148 149enum soc_pad_ctrl_type {150 SOC_PAD_SD,151 SOC_PAD_FIXED_1_8V,152};153 154struct soc_pad_ctrl {155 /* Register address of SoC PHY PAD ctrl */156 void __iomem *reg;157 /* SoC PHY PAD ctrl type */158 enum soc_pad_ctrl_type pad_type;159 /* SoC specific operation to set SoC PHY PAD */160 void (*set_soc_pad)(struct sdhci_host *host,161 unsigned char signal_voltage);162};163 164static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs = {165 .timing_adj = XENON_EMMC_5_0_PHY_TIMING_ADJUST,166 .func_ctrl = XENON_EMMC_5_0_PHY_FUNC_CONTROL,167 .pad_ctrl = XENON_EMMC_5_0_PHY_PAD_CONTROL,168 .pad_ctrl2 = XENON_EMMC_5_0_PHY_PAD_CONTROL2,169 .dll_ctrl = XENON_EMMC_5_0_PHY_DLL_CONTROL,170 .logic_timing_adj = XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST,171 .dll_update = XENON_DLL_UPDATE_STROBE_5_0,172 .logic_timing_val = XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE,173};174 175static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs = {176 .timing_adj = XENON_EMMC_PHY_TIMING_ADJUST,177 .func_ctrl = XENON_EMMC_PHY_FUNC_CONTROL,178 .pad_ctrl = XENON_EMMC_PHY_PAD_CONTROL,179 .pad_ctrl2 = XENON_EMMC_PHY_PAD_CONTROL2,180 .dll_ctrl = XENON_EMMC_PHY_DLL_CONTROL,181 .logic_timing_adj = XENON_EMMC_PHY_LOGIC_TIMING_ADJUST,182 .dll_update = XENON_DLL_UPDATE,183 .logic_timing_val = XENON_LOGIC_TIMING_VALUE,184};185 186/*187 * eMMC PHY configuration and operations188 */189struct xenon_emmc_phy_params {190 bool slow_mode;191 192 u8 znr;193 u8 zpr;194 195 /* Nr of consecutive Sampling Points of a Valid Sampling Window */196 u8 nr_tun_times;197 /* Divider for calculating Tuning Step */198 u8 tun_step_divider;199 200 struct soc_pad_ctrl pad_ctrl;201};202 203static int xenon_alloc_emmc_phy(struct sdhci_host *host)204{205 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);206 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);207 struct xenon_emmc_phy_params *params;208 209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL);210 if (!params)211 return -ENOMEM;212 213 priv->phy_params = params;214 if (priv->phy_type == EMMC_5_0_PHY)215 priv->emmc_phy_regs = &xenon_emmc_5_0_phy_regs;216 else217 priv->emmc_phy_regs = &xenon_emmc_5_1_phy_regs;218 219 return 0;220}221 222static int xenon_check_stability_internal_clk(struct sdhci_host *host)223{224 u32 reg;225 int err;226 227 err = read_poll_timeout(sdhci_readw, reg, reg & SDHCI_CLOCK_INT_STABLE,228 1100, 20000, false, host, SDHCI_CLOCK_CONTROL);229 if (err)230 dev_err(mmc_dev(host->mmc), "phy_init: Internal clock never stabilized.\n");231 232 return err;233}234 235/*236 * eMMC 5.0/5.1 PHY init/re-init.237 * eMMC PHY init should be executed after:238 * 1. SDCLK frequency changes.239 * 2. SDCLK is stopped and re-enabled.240 * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl241 * are changed242 */243static int xenon_emmc_phy_init(struct sdhci_host *host)244{245 u32 reg;246 u32 wait, clock;247 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);248 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);249 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;250 251 int ret = xenon_check_stability_internal_clk(host);252 253 if (ret)254 return ret;255 256 reg = sdhci_readl(host, phy_regs->timing_adj);257 reg |= XENON_PHY_INITIALIZAION;258 sdhci_writel(host, reg, phy_regs->timing_adj);259 260 /* Add duration of FC_SYNC_RST */261 wait = ((reg >> XENON_FC_SYNC_RST_DURATION_SHIFT) &262 XENON_FC_SYNC_RST_DURATION_MASK);263 /* Add interval between FC_SYNC_EN and FC_SYNC_RST */264 wait += ((reg >> XENON_FC_SYNC_RST_EN_DURATION_SHIFT) &265 XENON_FC_SYNC_RST_EN_DURATION_MASK);266 /* Add duration of asserting FC_SYNC_EN */267 wait += ((reg >> XENON_FC_SYNC_EN_DURATION_SHIFT) &268 XENON_FC_SYNC_EN_DURATION_MASK);269 /* Add duration of waiting for PHY */270 wait += ((reg >> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT) &271 XENON_WAIT_CYCLE_BEFORE_USING_MASK);272 /* 4 additional bus clock and 4 AXI bus clock are required */273 wait += 8;274 wait <<= 20;275 276 clock = host->clock;277 if (!clock)278 /* Use the possibly slowest bus frequency value */279 clock = XENON_LOWEST_SDCLK_FREQ;280 /* get the wait time */281 wait /= clock;282 wait++;283 284 /*285 * AC5X spec says bit must be polled until zero.286 * We see cases in which timeout can take longer287 * than the standard calculation on AC5X, which is288 * expected following the spec comment above.289 * According to the spec, we must wait as long as290 * it takes for that bit to toggle on AC5X.291 * Cap that with 100 delay loops so we won't get292 * stuck here forever:293 */294 295 ret = read_poll_timeout(sdhci_readl, reg,296 !(reg & XENON_PHY_INITIALIZAION),297 wait, XENON_MAX_PHY_TIMEOUT_LOOPS * wait,298 false, host, phy_regs->timing_adj);299 if (ret)300 dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n",301 wait * XENON_MAX_PHY_TIMEOUT_LOOPS);302 303 return ret;304}305 306#define ARMADA_3700_SOC_PAD_1_8V 0x1307#define ARMADA_3700_SOC_PAD_3_3V 0x0308 309static void armada_3700_soc_pad_voltage_set(struct sdhci_host *host,310 unsigned char signal_voltage)311{312 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);313 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);314 struct xenon_emmc_phy_params *params = priv->phy_params;315 316 if (params->pad_ctrl.pad_type == SOC_PAD_FIXED_1_8V) {317 writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);318 } else if (params->pad_ctrl.pad_type == SOC_PAD_SD) {319 if (signal_voltage == MMC_SIGNAL_VOLTAGE_180)320 writel(ARMADA_3700_SOC_PAD_1_8V, params->pad_ctrl.reg);321 else if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)322 writel(ARMADA_3700_SOC_PAD_3_3V, params->pad_ctrl.reg);323 }324}325 326/*327 * Set SoC PHY voltage PAD control register,328 * according to the operation voltage on PAD.329 * The detailed operation depends on SoC implementation.330 */331static void xenon_emmc_phy_set_soc_pad(struct sdhci_host *host,332 unsigned char signal_voltage)333{334 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);335 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);336 struct xenon_emmc_phy_params *params = priv->phy_params;337 338 if (!params->pad_ctrl.reg)339 return;340 341 if (params->pad_ctrl.set_soc_pad)342 params->pad_ctrl.set_soc_pad(host, signal_voltage);343}344 345/*346 * Enable eMMC PHY HW DLL347 * DLL should be enabled and stable before HS200/SDR104 tuning,348 * and before HS400 data strobe setting.349 */350static int xenon_emmc_phy_enable_dll(struct sdhci_host *host)351{352 u32 reg;353 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);354 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);355 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;356 ktime_t timeout;357 358 if (WARN_ON(host->clock <= MMC_HIGH_52_MAX_DTR))359 return -EINVAL;360 361 reg = sdhci_readl(host, phy_regs->dll_ctrl);362 if (reg & XENON_DLL_ENABLE)363 return 0;364 365 /* Enable DLL */366 reg = sdhci_readl(host, phy_regs->dll_ctrl);367 reg |= (XENON_DLL_ENABLE | XENON_DLL_FAST_LOCK);368 369 /*370 * Set Phase as 90 degree, which is most common value.371 * Might set another value if necessary.372 * The granularity is 1 degree.373 */374 reg &= ~((XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL0_SHIFT) |375 (XENON_DLL_PHASE_MASK << XENON_DLL_PHSEL1_SHIFT));376 reg |= ((XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL0_SHIFT) |377 (XENON_DLL_PHASE_90_DEGREE << XENON_DLL_PHSEL1_SHIFT));378 379 reg &= ~XENON_DLL_BYPASS_EN;380 reg |= phy_regs->dll_update;381 if (priv->phy_type == EMMC_5_1_PHY)382 reg &= ~XENON_DLL_REFCLK_SEL;383 sdhci_writel(host, reg, phy_regs->dll_ctrl);384 385 /* Wait max 32 ms */386 timeout = ktime_add_ms(ktime_get(), 32);387 while (1) {388 bool timedout = ktime_after(ktime_get(), timeout);389 390 if (sdhci_readw(host, XENON_SLOT_EXT_PRESENT_STATE) &391 XENON_DLL_LOCK_STATE)392 break;393 if (timedout) {394 dev_err(mmc_dev(host->mmc), "Wait for DLL Lock time-out\n");395 return -ETIMEDOUT;396 }397 udelay(100);398 }399 return 0;400}401 402/*403 * Config to eMMC PHY to prepare for tuning.404 * Enable HW DLL and set the TUNING_STEP405 */406static int xenon_emmc_phy_config_tuning(struct sdhci_host *host)407{408 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);409 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);410 struct xenon_emmc_phy_params *params = priv->phy_params;411 u32 reg, tuning_step;412 int ret;413 414 if (host->clock <= MMC_HIGH_52_MAX_DTR)415 return -EINVAL;416 417 ret = xenon_emmc_phy_enable_dll(host);418 if (ret)419 return ret;420 421 /* Achieve TUNING_STEP with HW DLL help */422 reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL);423 tuning_step = reg / params->tun_step_divider;424 if (unlikely(tuning_step > XENON_TUNING_STEP_MASK)) {425 dev_warn(mmc_dev(host->mmc),426 "HS200 TUNING_STEP %d is larger than MAX value\n",427 tuning_step);428 tuning_step = XENON_TUNING_STEP_MASK;429 }430 431 /* Set TUNING_STEP for later tuning */432 reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL);433 reg &= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK <<434 XENON_TUN_CONSECUTIVE_TIMES_SHIFT);435 reg |= (params->nr_tun_times << XENON_TUN_CONSECUTIVE_TIMES_SHIFT);436 reg &= ~(XENON_TUNING_STEP_MASK << XENON_TUNING_STEP_SHIFT);437 reg |= (tuning_step << XENON_TUNING_STEP_SHIFT);438 sdhci_writel(host, reg, XENON_SLOT_OP_STATUS_CTRL);439 440 return 0;441}442 443static void xenon_emmc_phy_disable_strobe(struct sdhci_host *host)444{445 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);446 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);447 u32 reg;448 449 /* Disable both SDHC Data Strobe and Enhanced Strobe */450 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);451 reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE);452 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);453 454 /* Clear Strobe line Pull down or Pull up */455 if (priv->phy_type == EMMC_5_0_PHY) {456 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);457 reg &= ~(XENON_EMMC5_FC_QSP_PD | XENON_EMMC5_FC_QSP_PU);458 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);459 } else {460 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);461 reg &= ~(XENON_EMMC5_1_FC_QSP_PD | XENON_EMMC5_1_FC_QSP_PU);462 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);463 }464}465 466/* Set HS400 Data Strobe and Enhanced Strobe */467static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host *host)468{469 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);470 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);471 u32 reg;472 473 if (WARN_ON(host->timing != MMC_TIMING_MMC_HS400))474 return;475 476 if (host->clock <= MMC_HIGH_52_MAX_DTR)477 return;478 479 dev_dbg(mmc_dev(host->mmc), "starts HS400 strobe delay adjustment\n");480 481 xenon_emmc_phy_enable_dll(host);482 483 /* Enable SDHC Data Strobe */484 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL);485 reg |= XENON_ENABLE_DATA_STROBE;486 /*487 * Enable SDHC Enhanced Strobe if supported488 * Xenon Enhanced Strobe should be enabled only when489 * 1. card is in HS400 mode and490 * 2. SDCLK is higher than 52MHz491 * 3. DLL is enabled492 */493 if (host->mmc->ios.enhanced_strobe)494 reg |= XENON_ENABLE_RESP_STROBE;495 sdhci_writel(host, reg, XENON_SLOT_EMMC_CTRL);496 497 /* Set Data Strobe Pull down */498 if (priv->phy_type == EMMC_5_0_PHY) {499 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);500 reg |= XENON_EMMC5_FC_QSP_PD;501 reg &= ~XENON_EMMC5_FC_QSP_PU;502 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);503 } else {504 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);505 reg |= XENON_EMMC5_1_FC_QSP_PD;506 reg &= ~XENON_EMMC5_1_FC_QSP_PU;507 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);508 }509}510 511/*512 * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)513 * in SDR mode, enable Slow Mode to bypass eMMC PHY.514 * SDIO slower SDR mode also requires Slow Mode.515 *516 * If Slow Mode is enabled, return true.517 * Otherwise, return false.518 */519static bool xenon_emmc_phy_slow_mode(struct sdhci_host *host,520 unsigned char timing)521{522 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);523 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);524 struct xenon_emmc_phy_params *params = priv->phy_params;525 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;526 u32 reg;527 int ret;528 529 if (host->clock > MMC_HIGH_52_MAX_DTR)530 return false;531 532 reg = sdhci_readl(host, phy_regs->timing_adj);533 /* When in slower SDR mode, enable Slow Mode for SDIO534 * or when Slow Mode flag is set535 */536 switch (timing) {537 case MMC_TIMING_LEGACY:538 /*539 * If Slow Mode is required, enable Slow Mode by default540 * in early init phase to avoid any potential issue.541 */542 if (params->slow_mode) {543 reg |= XENON_TIMING_ADJUST_SLOW_MODE;544 ret = true;545 } else {546 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;547 ret = false;548 }549 break;550 case MMC_TIMING_UHS_SDR25:551 case MMC_TIMING_UHS_SDR12:552 case MMC_TIMING_SD_HS:553 case MMC_TIMING_MMC_HS:554 if ((priv->init_card_type == MMC_TYPE_SDIO) ||555 params->slow_mode) {556 reg |= XENON_TIMING_ADJUST_SLOW_MODE;557 ret = true;558 break;559 }560 fallthrough;561 default:562 reg &= ~XENON_TIMING_ADJUST_SLOW_MODE;563 ret = false;564 }565 566 sdhci_writel(host, reg, phy_regs->timing_adj);567 return ret;568}569 570/*571 * Set-up eMMC 5.0/5.1 PHY.572 * Specific configuration depends on the current speed mode in use.573 */574static void xenon_emmc_phy_set(struct sdhci_host *host,575 unsigned char timing)576{577 u32 reg;578 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);579 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);580 struct xenon_emmc_phy_params *params = priv->phy_params;581 struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs;582 583 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting starts\n");584 585 /* Setup pad, set bit[28] and bits[26:24] */586 reg = sdhci_readl(host, phy_regs->pad_ctrl);587 reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN |588 XENON_FC_QSP_RECEN | XENON_OEN_QSN);589 /* All FC_XX_RECEIVCE should be set as CMOS Type */590 reg |= XENON_FC_ALL_CMOS_RECEIVER;591 sdhci_writel(host, reg, phy_regs->pad_ctrl);592 593 /* Set CMD and DQ Pull Up */594 if (priv->phy_type == EMMC_5_0_PHY) {595 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL);596 reg |= (XENON_EMMC5_FC_CMD_PU | XENON_EMMC5_FC_DQ_PU);597 reg &= ~(XENON_EMMC5_FC_CMD_PD | XENON_EMMC5_FC_DQ_PD);598 sdhci_writel(host, reg, XENON_EMMC_5_0_PHY_PAD_CONTROL);599 } else {600 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1);601 reg |= (XENON_EMMC5_1_FC_CMD_PU | XENON_EMMC5_1_FC_DQ_PU);602 reg &= ~(XENON_EMMC5_1_FC_CMD_PD | XENON_EMMC5_1_FC_DQ_PD);603 sdhci_writel(host, reg, XENON_EMMC_PHY_PAD_CONTROL1);604 }605 606 if (timing == MMC_TIMING_LEGACY) {607 xenon_emmc_phy_slow_mode(host, timing);608 goto phy_init;609 }610 611 /*612 * If SDIO card, set SDIO Mode613 * Otherwise, clear SDIO Mode614 */615 reg = sdhci_readl(host, phy_regs->timing_adj);616 if (priv->init_card_type == MMC_TYPE_SDIO)617 reg |= XENON_TIMING_ADJUST_SDIO_MODE;618 else619 reg &= ~XENON_TIMING_ADJUST_SDIO_MODE;620 sdhci_writel(host, reg, phy_regs->timing_adj);621 622 if (xenon_emmc_phy_slow_mode(host, timing))623 goto phy_init;624 625 /*626 * Set preferred ZNR and ZPR value627 * The ZNR and ZPR value vary between different boards.628 * Define them both in sdhci-xenon-emmc-phy.h.629 */630 reg = sdhci_readl(host, phy_regs->pad_ctrl2);631 reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK);632 reg |= ((params->znr << XENON_ZNR_SHIFT) | params->zpr);633 sdhci_writel(host, reg, phy_regs->pad_ctrl2);634 635 /*636 * When setting EMMC_PHY_FUNC_CONTROL register,637 * SD clock should be disabled638 */639 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);640 reg &= ~SDHCI_CLOCK_CARD_EN;641 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);642 643 reg = sdhci_readl(host, phy_regs->func_ctrl);644 switch (timing) {645 case MMC_TIMING_MMC_HS400:646 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |647 XENON_CMD_DDR_MODE;648 reg &= ~XENON_DQ_ASYNC_MODE;649 break;650 case MMC_TIMING_UHS_DDR50:651 case MMC_TIMING_MMC_DDR52:652 reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |653 XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE;654 break;655 default:656 reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) |657 XENON_CMD_DDR_MODE);658 reg |= XENON_DQ_ASYNC_MODE;659 }660 sdhci_writel(host, reg, phy_regs->func_ctrl);661 662 /* Enable bus clock */663 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);664 reg |= SDHCI_CLOCK_CARD_EN;665 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);666 667 if (timing == MMC_TIMING_MMC_HS400)668 /* Hardware team recommend a value for HS400 */669 sdhci_writel(host, phy_regs->logic_timing_val,670 phy_regs->logic_timing_adj);671 else672 xenon_emmc_phy_disable_strobe(host);673 674phy_init:675 xenon_emmc_phy_init(host);676 677 dev_dbg(mmc_dev(host->mmc), "eMMC PHY setting completes\n");678}679 680static int get_dt_pad_ctrl_data(struct sdhci_host *host,681 struct device_node *np,682 struct xenon_emmc_phy_params *params)683{684 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);685 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);686 int ret = 0;687 const char *name;688 struct resource iomem;689 690 if (priv->hw_version == XENON_A3700)691 params->pad_ctrl.set_soc_pad = armada_3700_soc_pad_voltage_set;692 else693 return 0;694 695 if (of_address_to_resource(np, 1, &iomem)) {696 dev_err(mmc_dev(host->mmc), "Unable to find SoC PAD ctrl register address for %pOFn\n",697 np);698 return -EINVAL;699 }700 701 params->pad_ctrl.reg = devm_ioremap_resource(mmc_dev(host->mmc),702 &iomem);703 if (IS_ERR(params->pad_ctrl.reg))704 return PTR_ERR(params->pad_ctrl.reg);705 706 ret = of_property_read_string(np, "marvell,pad-type", &name);707 if (ret) {708 dev_err(mmc_dev(host->mmc), "Unable to determine SoC PHY PAD ctrl type\n");709 return ret;710 }711 if (!strcmp(name, "sd")) {712 params->pad_ctrl.pad_type = SOC_PAD_SD;713 } else if (!strcmp(name, "fixed-1-8v")) {714 params->pad_ctrl.pad_type = SOC_PAD_FIXED_1_8V;715 } else {716 dev_err(mmc_dev(host->mmc), "Unsupported SoC PHY PAD ctrl type %s\n",717 name);718 return -EINVAL;719 }720 721 return ret;722}723 724static int xenon_emmc_phy_parse_params(struct sdhci_host *host,725 struct device *dev,726 struct xenon_emmc_phy_params *params)727{728 u32 value;729 730 params->slow_mode = false;731 if (device_property_read_bool(dev, "marvell,xenon-phy-slow-mode"))732 params->slow_mode = true;733 734 params->znr = XENON_ZNR_DEF_VALUE;735 if (!device_property_read_u32(dev, "marvell,xenon-phy-znr", &value))736 params->znr = value & XENON_ZNR_MASK;737 738 params->zpr = XENON_ZPR_DEF_VALUE;739 if (!device_property_read_u32(dev, "marvell,xenon-phy-zpr", &value))740 params->zpr = value & XENON_ZPR_MASK;741 742 params->nr_tun_times = XENON_TUN_CONSECUTIVE_TIMES;743 if (!device_property_read_u32(dev, "marvell,xenon-phy-nr-success-tun",744 &value))745 params->nr_tun_times = value & XENON_TUN_CONSECUTIVE_TIMES_MASK;746 747 params->tun_step_divider = XENON_TUNING_STEP_DIVIDER;748 if (!device_property_read_u32(dev, "marvell,xenon-phy-tun-step-divider",749 &value))750 params->tun_step_divider = value & 0xFF;751 752 if (dev->of_node)753 return get_dt_pad_ctrl_data(host, dev->of_node, params);754 return 0;755}756 757/* Set SoC PHY Voltage PAD */758void xenon_soc_pad_ctrl(struct sdhci_host *host,759 unsigned char signal_voltage)760{761 xenon_emmc_phy_set_soc_pad(host, signal_voltage);762}763 764/*765 * Setting PHY when card is working in High Speed Mode.766 * HS400 set Data Strobe and Enhanced Strobe if it is supported.767 * HS200/SDR104 set tuning config to prepare for tuning.768 */769static int xenon_hs_delay_adj(struct sdhci_host *host)770{771 int ret = 0;772 773 if (WARN_ON(host->clock <= XENON_DEFAULT_SDCLK_FREQ))774 return -EINVAL;775 776 switch (host->timing) {777 case MMC_TIMING_MMC_HS400:778 xenon_emmc_phy_strobe_delay_adj(host);779 return 0;780 case MMC_TIMING_MMC_HS200:781 case MMC_TIMING_UHS_SDR104:782 return xenon_emmc_phy_config_tuning(host);783 case MMC_TIMING_MMC_DDR52:784 case MMC_TIMING_UHS_DDR50:785 /*786 * DDR Mode requires driver to scan Sampling Fixed Delay Line,787 * to find out a perfect operation sampling point.788 * It is hard to implement such a scan in host driver789 * since initiating commands by host driver is not safe.790 * Thus so far just keep PHY Sampling Fixed Delay in791 * default value of DDR mode.792 *793 * If any timing issue occurs in DDR mode on Marvell products,794 * please contact maintainer for internal support in Marvell.795 */796 dev_warn_once(mmc_dev(host->mmc), "Timing issue might occur in DDR mode\n");797 return 0;798 }799 800 return ret;801}802 803/*804 * Adjust PHY setting.805 * PHY setting should be adjusted when SDCLK frequency, Bus Width806 * or Speed Mode is changed.807 * Additional config are required when card is working in High Speed mode,808 * after leaving Legacy Mode.809 */810int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios)811{812 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);813 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);814 int ret = 0;815 816 if (!host->clock) {817 priv->clock = 0;818 return 0;819 }820 821 /*822 * The timing, frequency or bus width is changed,823 * better to set eMMC PHY based on current setting824 * and adjust Xenon SDHC delay.825 */826 if ((host->clock == priv->clock) &&827 (ios->bus_width == priv->bus_width) &&828 (ios->timing == priv->timing))829 return 0;830 831 xenon_emmc_phy_set(host, ios->timing);832 833 /* Update the record */834 priv->bus_width = ios->bus_width;835 836 priv->timing = ios->timing;837 priv->clock = host->clock;838 839 /* Legacy mode is a special case */840 if (ios->timing == MMC_TIMING_LEGACY)841 return 0;842 843 if (host->clock > XENON_DEFAULT_SDCLK_FREQ)844 ret = xenon_hs_delay_adj(host);845 return ret;846}847 848static int xenon_add_phy(struct device *dev, struct sdhci_host *host,849 const char *phy_name)850{851 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);852 struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host);853 int ret;854 855 priv->phy_type = match_string(phy_types, NR_PHY_TYPES, phy_name);856 if (priv->phy_type < 0) {857 dev_err(mmc_dev(host->mmc),858 "Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n",859 phy_name);860 priv->phy_type = EMMC_5_1_PHY;861 }862 863 ret = xenon_alloc_emmc_phy(host);864 if (ret)865 return ret;866 867 return xenon_emmc_phy_parse_params(host, dev, priv->phy_params);868}869 870int xenon_phy_parse_params(struct device *dev, struct sdhci_host *host)871{872 const char *phy_type = NULL;873 874 if (!device_property_read_string(dev, "marvell,xenon-phy-type", &phy_type))875 return xenon_add_phy(dev, host, phy_type);876 877 return xenon_add_phy(dev, host, "emmc 5.1 phy");878}879