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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2016 Marvell, All Rights Reserved.4 *5 * Author: Hu Ziji <huziji@marvell.com>6 * Date: 2016-8-247 */8#ifndef SDHCI_XENON_H_9#define SDHCI_XENON_H_10 11/* Register Offset of Xenon SDHC self-defined register */12#define XENON_SYS_CFG_INFO 0x010413#define XENON_SLOT_TYPE_SDIO_SHIFT 2414#define XENON_NR_SUPPORTED_SLOT_MASK 0x715 16#define XENON_SYS_OP_CTRL 0x010817#define XENON_AUTO_CLKGATE_DISABLE_MASK BIT(20)18#define XENON_SDCLK_IDLEOFF_ENABLE_SHIFT 819#define XENON_SLOT_ENABLE_SHIFT 020 21#define XENON_SYS_EXT_OP_CTRL 0x010C22#define XENON_MASK_CMD_CONFLICT_ERR BIT(8)23 24#define XENON_SLOT_OP_STATUS_CTRL 0x012825#define XENON_TUN_CONSECUTIVE_TIMES_SHIFT 1626#define XENON_TUN_CONSECUTIVE_TIMES_MASK 0x727#define XENON_TUN_CONSECUTIVE_TIMES 0x428#define XENON_TUNING_STEP_SHIFT 1229#define XENON_TUNING_STEP_MASK 0xF30#define XENON_TUNING_STEP_DIVIDER BIT(6)31 32#define XENON_SLOT_EMMC_CTRL 0x013033#define XENON_ENABLE_RESP_STROBE BIT(25)34#define XENON_ENABLE_DATA_STROBE BIT(24)35 36#define XENON_SLOT_RETUNING_REQ_CTRL 0x014437/* retuning compatible */38#define XENON_RETUNING_COMPATIBLE 0x139 40#define XENON_SLOT_EXT_PRESENT_STATE 0x014C41#define XENON_DLL_LOCK_STATE 0x142 43#define XENON_SLOT_DLL_CUR_DLY_VAL 0x015044 45/* Tuning Parameter */46#define XENON_TMR_RETUN_NO_PRESENT 0xF47#define XENON_DEF_TUNING_COUNT 0x948 49#define XENON_DEFAULT_SDCLK_FREQ 40000050#define XENON_LOWEST_SDCLK_FREQ 10000051 52/* Xenon specific Mode Select value */53#define XENON_CTRL_HS200 0x554#define XENON_CTRL_HS400 0x655 56enum xenon_variant {57 XENON_A3700,58 XENON_AP806,59 XENON_AP807,60 XENON_CP110,61 XENON_AC562};63 64struct xenon_priv {65 unsigned char tuning_count;66 /* idx of SDHC */67 u8 sdhc_id;68 69 /*70 * eMMC/SD/SDIO require different register settings.71 * Xenon driver has to recognize card type72 * before mmc_host->card is not available.73 * This field records the card type during init.74 * It is updated in xenon_init_card().75 *76 * It is only valid during initialization after it is updated.77 * Do not access this variable in normal transfers after78 * initialization completes.79 */80 unsigned int init_card_type;81 82 /*83 * The bus_width, timing, and clock fields in below84 * record the current ios setting of Xenon SDHC.85 * Driver will adjust PHY setting if any change to86 * ios affects PHY timing.87 */88 unsigned char bus_width;89 unsigned char timing;90 unsigned int clock;91 struct clk *axi_clk;92 93 int phy_type;94 /*95 * Contains board-specific PHY parameters96 * passed from device tree.97 */98 void *phy_params;99 struct xenon_emmc_phy_regs *emmc_phy_regs;100 bool restore_needed;101 enum xenon_variant hw_version;102};103 104int xenon_phy_adj(struct sdhci_host *host, struct mmc_ios *ios);105int xenon_phy_parse_params(struct device *dev,106 struct sdhci_host *host);107void xenon_soc_pad_ctrl(struct sdhci_host *host,108 unsigned char signal_voltage);109#endif110