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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver4 *5 * Header file for Host Controller registers and I/O accessors.6 *7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.8 */9#ifndef __SDHCI_HW_H10#define __SDHCI_HW_H11 12#include <linux/bits.h>13#include <linux/scatterlist.h>14#include <linux/compiler.h>15#include <linux/types.h>16#include <linux/io.h>17#include <linux/leds.h>18#include <linux/interrupt.h>19 20#include <linux/mmc/host.h>21 22/*23 * Controller registers24 */25 26#define SDHCI_DMA_ADDRESS 0x0027#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS28#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS29 30#define SDHCI_BLOCK_SIZE 0x0431#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))32 33#define SDHCI_BLOCK_COUNT 0x0634 35#define SDHCI_ARGUMENT 0x0836 37#define SDHCI_TRANSFER_MODE 0x0C38#define SDHCI_TRNS_DMA 0x0139#define SDHCI_TRNS_BLK_CNT_EN 0x0240#define SDHCI_TRNS_AUTO_CMD12 0x0441#define SDHCI_TRNS_AUTO_CMD23 0x0842#define SDHCI_TRNS_AUTO_SEL 0x0C43#define SDHCI_TRNS_READ 0x1044#define SDHCI_TRNS_MULTI 0x2045 46#define SDHCI_COMMAND 0x0E47#define SDHCI_CMD_RESP_MASK 0x0348#define SDHCI_CMD_CRC 0x0849#define SDHCI_CMD_INDEX 0x1050#define SDHCI_CMD_DATA 0x2051#define SDHCI_CMD_ABORTCMD 0xC052 53#define SDHCI_CMD_RESP_NONE 0x0054#define SDHCI_CMD_RESP_LONG 0x0155#define SDHCI_CMD_RESP_SHORT 0x0256#define SDHCI_CMD_RESP_SHORT_BUSY 0x0357 58#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))59#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)60 61#define SDHCI_RESPONSE 0x1062 63#define SDHCI_BUFFER 0x2064 65#define SDHCI_PRESENT_STATE 0x2466#define SDHCI_CMD_INHIBIT 0x0000000167#define SDHCI_DATA_INHIBIT 0x0000000268#define SDHCI_DOING_WRITE 0x0000010069#define SDHCI_DOING_READ 0x0000020070#define SDHCI_SPACE_AVAILABLE 0x0000040071#define SDHCI_DATA_AVAILABLE 0x0000080072#define SDHCI_CARD_PRESENT 0x0001000073#define SDHCI_CARD_PRES_SHIFT 1674#define SDHCI_CD_STABLE 0x0002000075#define SDHCI_CD_LVL 0x0004000076#define SDHCI_CD_LVL_SHIFT 1877#define SDHCI_WRITE_PROTECT 0x0008000078#define SDHCI_DATA_LVL_MASK 0x00F0000079#define SDHCI_DATA_LVL_SHIFT 2080#define SDHCI_DATA_0_LVL_MASK 0x0010000081#define SDHCI_CMD_LVL 0x0100000082 83#define SDHCI_HOST_CONTROL 0x2884#define SDHCI_CTRL_LED 0x0185#define SDHCI_CTRL_4BITBUS 0x0286#define SDHCI_CTRL_HISPD 0x0487#define SDHCI_CTRL_DMA_MASK 0x1888#define SDHCI_CTRL_SDMA 0x0089#define SDHCI_CTRL_ADMA1 0x0890#define SDHCI_CTRL_ADMA32 0x1091#define SDHCI_CTRL_ADMA64 0x1892#define SDHCI_CTRL_ADMA3 0x1893#define SDHCI_CTRL_8BITBUS 0x2094#define SDHCI_CTRL_CDTEST_INS 0x4095#define SDHCI_CTRL_CDTEST_EN 0x8096 97#define SDHCI_POWER_CONTROL 0x2998#define SDHCI_POWER_ON 0x0199#define SDHCI_POWER_180 0x0A100#define SDHCI_POWER_300 0x0C101#define SDHCI_POWER_330 0x0E102/*103 * VDD2 - UHS2 or PCIe/NVMe104 * VDD2 power on/off and voltage select105 */106#define SDHCI_VDD2_POWER_ON 0x10107#define SDHCI_VDD2_POWER_120 0x80108#define SDHCI_VDD2_POWER_180 0xA0109 110#define SDHCI_BLOCK_GAP_CONTROL 0x2A111 112#define SDHCI_WAKE_UP_CONTROL 0x2B113#define SDHCI_WAKE_ON_INT 0x01114#define SDHCI_WAKE_ON_INSERT 0x02115#define SDHCI_WAKE_ON_REMOVE 0x04116 117#define SDHCI_CLOCK_CONTROL 0x2C118#define SDHCI_DIVIDER_SHIFT 8119#define SDHCI_DIVIDER_HI_SHIFT 6120#define SDHCI_DIV_MASK 0xFF121#define SDHCI_DIV_MASK_LEN 8122#define SDHCI_DIV_HI_MASK 0x300123#define SDHCI_PROG_CLOCK_MODE 0x0020124#define SDHCI_CLOCK_CARD_EN 0x0004125#define SDHCI_CLOCK_PLL_EN 0x0008126#define SDHCI_CLOCK_INT_STABLE 0x0002127#define SDHCI_CLOCK_INT_EN 0x0001128 129#define SDHCI_TIMEOUT_CONTROL 0x2E130 131#define SDHCI_SOFTWARE_RESET 0x2F132#define SDHCI_RESET_ALL 0x01133#define SDHCI_RESET_CMD 0x02134#define SDHCI_RESET_DATA 0x04135 136#define SDHCI_INT_STATUS 0x30137#define SDHCI_INT_ENABLE 0x34138#define SDHCI_SIGNAL_ENABLE 0x38139#define SDHCI_INT_RESPONSE 0x00000001140#define SDHCI_INT_DATA_END 0x00000002141#define SDHCI_INT_BLK_GAP 0x00000004142#define SDHCI_INT_DMA_END 0x00000008143#define SDHCI_INT_SPACE_AVAIL 0x00000010144#define SDHCI_INT_DATA_AVAIL 0x00000020145#define SDHCI_INT_CARD_INSERT 0x00000040146#define SDHCI_INT_CARD_REMOVE 0x00000080147#define SDHCI_INT_CARD_INT 0x00000100148#define SDHCI_INT_RETUNE 0x00001000149#define SDHCI_INT_CQE 0x00004000150#define SDHCI_INT_ERROR 0x00008000151#define SDHCI_INT_TIMEOUT 0x00010000152#define SDHCI_INT_CRC 0x00020000153#define SDHCI_INT_END_BIT 0x00040000154#define SDHCI_INT_INDEX 0x00080000155#define SDHCI_INT_DATA_TIMEOUT 0x00100000156#define SDHCI_INT_DATA_CRC 0x00200000157#define SDHCI_INT_DATA_END_BIT 0x00400000158#define SDHCI_INT_BUS_POWER 0x00800000159#define SDHCI_INT_AUTO_CMD_ERR 0x01000000160#define SDHCI_INT_ADMA_ERROR 0x02000000161#define SDHCI_INT_TUNING_ERROR 0x04000000162 163#define SDHCI_INT_NORMAL_MASK 0x00007FFF164#define SDHCI_INT_ERROR_MASK 0xFFFF8000165 166#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \167 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \168 SDHCI_INT_AUTO_CMD_ERR)169#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \170 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \171 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \172 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \173 SDHCI_INT_BLK_GAP | SDHCI_INT_TUNING_ERROR)174#define SDHCI_INT_ALL_MASK ((unsigned int)-1)175 176#define SDHCI_CQE_INT_ERR_MASK ( \177 SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | \178 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | \179 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)180 181#define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)182 183#define SDHCI_AUTO_CMD_STATUS 0x3C184#define SDHCI_AUTO_CMD_TIMEOUT 0x00000002185#define SDHCI_AUTO_CMD_CRC 0x00000004186#define SDHCI_AUTO_CMD_END_BIT 0x00000008187#define SDHCI_AUTO_CMD_INDEX 0x00000010188 189#define SDHCI_HOST_CONTROL2 0x3E190#define SDHCI_CTRL_UHS_MASK 0x0007191#define SDHCI_CTRL_UHS_SDR12 0x0000192#define SDHCI_CTRL_UHS_SDR25 0x0001193#define SDHCI_CTRL_UHS_SDR50 0x0002194#define SDHCI_CTRL_UHS_SDR104 0x0003195#define SDHCI_CTRL_UHS_DDR50 0x0004196#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */197#define SDHCI_CTRL_VDD_180 0x0008198#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030199#define SDHCI_CTRL_DRV_TYPE_B 0x0000200#define SDHCI_CTRL_DRV_TYPE_A 0x0010201#define SDHCI_CTRL_DRV_TYPE_C 0x0020202#define SDHCI_CTRL_DRV_TYPE_D 0x0030203#define SDHCI_CTRL_EXEC_TUNING 0x0040204#define SDHCI_CTRL_TUNED_CLK 0x0080205#define SDHCI_CMD23_ENABLE 0x0800206#define SDHCI_CTRL_V4_MODE 0x1000207#define SDHCI_CTRL_64BIT_ADDR 0x2000208#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000209 210#define SDHCI_CAPABILITIES 0x40211#define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0)212#define SDHCI_TIMEOUT_CLK_SHIFT 0213#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080214#define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8)215#define SDHCI_CLOCK_BASE_SHIFT 8216#define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8)217#define SDHCI_MAX_BLOCK_MASK 0x00030000218#define SDHCI_MAX_BLOCK_SHIFT 16219#define SDHCI_CAN_DO_8BIT 0x00040000220#define SDHCI_CAN_DO_ADMA2 0x00080000221#define SDHCI_CAN_DO_ADMA1 0x00100000222#define SDHCI_CAN_DO_HISPD 0x00200000223#define SDHCI_CAN_DO_SDMA 0x00400000224#define SDHCI_CAN_DO_SUSPEND 0x00800000225#define SDHCI_CAN_VDD_330 0x01000000226#define SDHCI_CAN_VDD_300 0x02000000227#define SDHCI_CAN_VDD_180 0x04000000228#define SDHCI_CAN_64BIT_V4 0x08000000229#define SDHCI_CAN_64BIT 0x10000000230 231#define SDHCI_CAPABILITIES_1 0x44232#define SDHCI_SUPPORT_SDR50 0x00000001233#define SDHCI_SUPPORT_SDR104 0x00000002234#define SDHCI_SUPPORT_DDR50 0x00000004235#define SDHCI_DRIVER_TYPE_A 0x00000010236#define SDHCI_DRIVER_TYPE_C 0x00000020237#define SDHCI_DRIVER_TYPE_D 0x00000040238#define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8)239#define SDHCI_USE_SDR50_TUNING 0x00002000240#define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14)241#define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16)242#define SDHCI_CAN_DO_ADMA3 0x08000000243#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */244 245#define SDHCI_MAX_CURRENT 0x48246#define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0)247#define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0)248#define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8)249#define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16)250#define SDHCI_MAX_CURRENT_MULTIPLIER 4251 252/* 4C-4F reserved for more max current */253 254#define SDHCI_SET_ACMD12_ERROR 0x50255#define SDHCI_SET_INT_ERROR 0x52256 257#define SDHCI_ADMA_ERROR 0x54258 259/* 55-57 reserved */260 261#define SDHCI_ADMA_ADDRESS 0x58262#define SDHCI_ADMA_ADDRESS_HI 0x5C263 264/* 60-FB reserved */265 266#define SDHCI_PRESET_FOR_HIGH_SPEED 0x64267#define SDHCI_PRESET_FOR_SDR12 0x66268#define SDHCI_PRESET_FOR_SDR25 0x68269#define SDHCI_PRESET_FOR_SDR50 0x6A270#define SDHCI_PRESET_FOR_SDR104 0x6C271#define SDHCI_PRESET_FOR_DDR50 0x6E272#define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */273#define SDHCI_PRESET_DRV_MASK GENMASK(15, 14)274#define SDHCI_PRESET_CLKGEN_SEL BIT(10)275#define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0)276 277#define SDHCI_SLOT_INT_STATUS 0xFC278 279#define SDHCI_HOST_VERSION 0xFE280#define SDHCI_VENDOR_VER_MASK 0xFF00281#define SDHCI_VENDOR_VER_SHIFT 8282#define SDHCI_SPEC_VER_MASK 0x00FF283#define SDHCI_SPEC_VER_SHIFT 0284#define SDHCI_SPEC_100 0285#define SDHCI_SPEC_200 1286#define SDHCI_SPEC_300 2287#define SDHCI_SPEC_400 3288#define SDHCI_SPEC_410 4289#define SDHCI_SPEC_420 5290 291/*292 * End of controller registers.293 */294 295#define SDHCI_MAX_DIV_SPEC_200 256296#define SDHCI_MAX_DIV_SPEC_300 2046297 298/*299 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.300 */301#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)302#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)303 304/* ADMA2 32-bit DMA descriptor size */305#define SDHCI_ADMA2_32_DESC_SZ 8306 307/* ADMA2 32-bit descriptor */308struct sdhci_adma2_32_desc {309 __le16 cmd;310 __le16 len;311 __le32 addr;312} __packed __aligned(4);313 314/* ADMA2 data alignment */315#define SDHCI_ADMA2_ALIGN 4316#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)317 318/*319 * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte320 * alignment for the descriptor table even in 32-bit DMA mode. Memory321 * allocation is at least 8 byte aligned anyway, so just stipulate 8 always.322 */323#define SDHCI_ADMA2_DESC_ALIGN 8324 325/*326 * ADMA2 64-bit DMA descriptor size327 * According to SD Host Controller spec v4.10, there are two kinds of328 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit329 * Descriptor, if Host Version 4 Enable is set in the Host Control 2330 * register, 128-bit Descriptor will be selected.331 */332#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)333 334/*335 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte336 * aligned.337 */338struct sdhci_adma2_64_desc {339 __le16 cmd;340 __le16 len;341 __le32 addr_lo;342 __le32 addr_hi;343} __packed __aligned(4);344 345#define ADMA2_TRAN_VALID 0x21346#define ADMA2_NOP_END_VALID 0x3347#define ADMA2_END 0x2348 349/*350 * Maximum segments assuming a 512KiB maximum requisition size and a minimum351 * 4KiB page size. Note this also allows enough for multiple descriptors in352 * case of PAGE_SIZE >= 64KiB.353 */354#define SDHCI_MAX_SEGS 128355 356/* Allow for a command request and a data request at the same time */357#define SDHCI_MAX_MRQS 2358 359/*360 * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.361 * However since the start time of the command, the time between362 * command and response, and the time between response and start of data is363 * not known, set the command transfer time to 10ms.364 */365#define MMC_CMD_TRANSFER_TIME (10 * NSEC_PER_MSEC) /* max 10 ms */366 367#define sdhci_err_stats_inc(host, err_name) \368 mmc_debugfs_err_stats_inc((host)->mmc, MMC_ERR_##err_name)369 370enum sdhci_cookie {371 COOKIE_UNMAPPED,372 COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */373 COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */374};375 376struct sdhci_host {377 /* Data set by hardware interface driver */378 const char *hw_name; /* Hardware bus name */379 380 unsigned int quirks; /* Deviations from spec. */381 382/* Controller doesn't honor resets unless we touch the clock register */383#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)384/* Controller has bad caps bits, but really supports DMA */385#define SDHCI_QUIRK_FORCE_DMA (1<<1)386/* Controller doesn't like to be reset when there is no card inserted. */387#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)388/* Controller doesn't like clearing the power reg before a change */389#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)390/* Controller has an unusable DMA engine */391#define SDHCI_QUIRK_BROKEN_DMA (1<<5)392/* Controller has an unusable ADMA engine */393#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)394/* Controller can only DMA from 32-bit aligned addresses */395#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)396/* Controller can only DMA chunk sizes that are a multiple of 32 bits */397#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)398/* Controller can only ADMA chunks that are a multiple of 32 bits */399#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)400/* Controller needs to be reset after each request to stay stable */401#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)402/* Controller needs voltage and power writes to happen separately */403#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)404/* Controller provides an incorrect timeout value for transfers */405#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)406/* Controller has an issue with buffer bits for small transfers */407#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)408/* Controller does not provide transfer-complete interrupt when not busy */409#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)410/* Controller has unreliable card detection */411#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)412/* Controller reports inverted write-protect state */413#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)414/* Controller has unusable command queue engine */415#define SDHCI_QUIRK_BROKEN_CQE (1<<17)416/* Controller does not like fast PIO transfers */417#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)418/* Controller does not have a LED */419#define SDHCI_QUIRK_NO_LED (1<<19)420/* Controller has to be forced to use block size of 2048 bytes */421#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)422/* Controller cannot do multi-block transfers */423#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)424/* Controller can only handle 1-bit data transfers */425#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)426/* Controller needs 10ms delay between applying power and clock */427#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)428/* Controller uses SDCLK instead of TMCLK for data timeouts */429#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)430/* Controller reports wrong base clock capability */431#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)432/* Controller cannot support End Attribute in NOP ADMA descriptor */433#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)434/* Controller uses Auto CMD12 command to stop the transfer */435#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)436/* Controller doesn't have HISPD bit field in HI-SPEED SD card */437#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)438/* Controller treats ADMA descriptors with length 0000h incorrectly */439#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)440 441 unsigned int quirks2; /* More deviations from spec. */442 443#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)444#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)445/* The system physically doesn't support 1.8v, even if the host does */446#define SDHCI_QUIRK2_NO_1_8_V (1<<2)447#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)448#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)449/* Controller has a non-standard host control register */450#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)451/* Controller does not support HS200 */452#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)453/* Controller does not support DDR50 */454#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)455/* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */456#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)457/* Controller does not support 64-bit DMA */458#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)459/* need clear transfer mode register before send cmd */460#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)461/* Capability register bit-63 indicates HS400 support */462#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11)463/* forced tuned clock */464#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12)465/* disable the block count for single block transactions */466#define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13)467/* Controller broken with using ACMD23 */468#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)469/* Broken Clock divider zero in controller */470#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)471/* Controller has CRC in 136 bit Command Response */472#define SDHCI_QUIRK2_RSP_136_HAS_CRC (1<<16)473/*474 * Disable HW timeout if the requested timeout is more than the maximum475 * obtainable timeout.476 */477#define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17)478/*479 * 32-bit block count may not support eMMC where upper bits of CMD23 are used480 * for other purposes. Consequently we support 16-bit block count by default.481 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit482 * block count.483 */484#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18)485/* Issue CMD and DATA reset together */486#define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19)487 488 int irq; /* Device IRQ */489 void __iomem *ioaddr; /* Mapped address */490 phys_addr_t mapbase; /* physical address base */491 char *bounce_buffer; /* For packing SDMA reads/writes */492 dma_addr_t bounce_addr;493 unsigned int bounce_buffer_size;494 495 const struct sdhci_ops *ops; /* Low level hw interface */496 497 /* Internal data */498 struct mmc_host *mmc; /* MMC structure */499 struct mmc_host_ops mmc_host_ops; /* MMC host ops */500 u64 dma_mask; /* custom DMA mask */501 502#if IS_ENABLED(CONFIG_LEDS_CLASS)503 struct led_classdev led; /* LED control */504 char led_name[32];505#endif506 507 spinlock_t lock; /* Mutex */508 509 int flags; /* Host attributes */510#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */511#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */512#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */513#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */514#define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */515#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */516#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */517#define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */518#define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */519#define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */520#define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */521#define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */522#define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */523 524 unsigned int version; /* SDHCI spec. version */525 526 unsigned int max_clk; /* Max possible freq (MHz) */527 unsigned int timeout_clk; /* Timeout freq (KHz) */528 u8 max_timeout_count; /* Vendor specific max timeout count */529 unsigned int clk_mul; /* Clock Muliplier value */530 531 unsigned int clock; /* Current clock (MHz) */532 u8 pwr; /* Current voltage */533 u8 drv_type; /* Current UHS-I driver type */534 bool reinit_uhs; /* Force UHS-related re-initialization */535 536 bool runtime_suspended; /* Host is runtime suspended */537 bool bus_on; /* Bus power prevents runtime suspend */538 bool preset_enabled; /* Preset is enabled */539 bool pending_reset; /* Cmd/data reset is pending */540 bool irq_wake_enabled; /* IRQ wakeup is enabled */541 bool v4_mode; /* Host Version 4 Enable */542 bool use_external_dma; /* Host selects to use external DMA */543 bool always_defer_done; /* Always defer to complete requests */544 545 struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */546 struct mmc_command *cmd; /* Current command */547 struct mmc_command *data_cmd; /* Current data command */548 struct mmc_command *deferred_cmd; /* Deferred command */549 struct mmc_data *data; /* Current data request */550 unsigned int data_early:1; /* Data finished before cmd */551 552 struct sg_mapping_iter sg_miter; /* SG state for PIO */553 unsigned int blocks; /* remaining PIO blocks */554 555 int sg_count; /* Mapped sg entries */556 int max_adma; /* Max. length in ADMA descriptor */557 558 void *adma_table; /* ADMA descriptor table */559 void *align_buffer; /* Bounce buffer */560 561 size_t adma_table_sz; /* ADMA descriptor table size */562 size_t align_buffer_sz; /* Bounce buffer size */563 564 dma_addr_t adma_addr; /* Mapped ADMA descr. table */565 dma_addr_t align_addr; /* Mapped bounce buffer */566 567 unsigned int desc_sz; /* ADMA current descriptor size */568 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */569 570 struct workqueue_struct *complete_wq; /* Request completion wq */571 struct work_struct complete_work; /* Request completion work */572 573 struct timer_list timer; /* Timer for timeouts */574 struct timer_list data_timer; /* Timer for data timeouts */575 576#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)577 struct dma_chan *rx_chan;578 struct dma_chan *tx_chan;579#endif580 581 u32 caps; /* CAPABILITY_0 */582 u32 caps1; /* CAPABILITY_1 */583 bool read_caps; /* Capability flags have been read */584 585 bool sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */586 unsigned int ocr_avail_sdio; /* OCR bit masks */587 unsigned int ocr_avail_sd;588 unsigned int ocr_avail_mmc;589 u32 ocr_mask; /* available voltages */590 591 unsigned timing; /* Current timing */592 593 u32 thread_isr;594 595 /* cached registers */596 u32 ier;597 598 bool cqe_on; /* CQE is operating */599 u32 cqe_ier; /* CQE interrupt mask */600 u32 cqe_err_ier; /* CQE error interrupt mask */601 602 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */603 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */604 605 unsigned int tuning_count; /* Timer count for re-tuning */606 unsigned int tuning_mode; /* Re-tuning mode supported by host */607 unsigned int tuning_err; /* Error code for re-tuning */608#define SDHCI_TUNING_MODE_1 0609#define SDHCI_TUNING_MODE_2 1610#define SDHCI_TUNING_MODE_3 2611 /* Delay (ms) between tuning commands */612 int tuning_delay;613 int tuning_loop_count;614 615 /* Host SDMA buffer boundary. */616 u32 sdma_boundary;617 618 /* Host ADMA table count */619 u32 adma_table_cnt;620 621 u64 data_timeout;622 623 unsigned long private[] ____cacheline_aligned;624};625 626struct sdhci_ops {627#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS628 u32 (*read_l)(struct sdhci_host *host, int reg);629 u16 (*read_w)(struct sdhci_host *host, int reg);630 u8 (*read_b)(struct sdhci_host *host, int reg);631 void (*write_l)(struct sdhci_host *host, u32 val, int reg);632 void (*write_w)(struct sdhci_host *host, u16 val, int reg);633 void (*write_b)(struct sdhci_host *host, u8 val, int reg);634#endif635 636 void (*set_clock)(struct sdhci_host *host, unsigned int clock);637 void (*set_power)(struct sdhci_host *host, unsigned char mode,638 unsigned short vdd);639 640 u32 (*irq)(struct sdhci_host *host, u32 intmask);641 642 int (*set_dma_mask)(struct sdhci_host *host);643 int (*enable_dma)(struct sdhci_host *host);644 unsigned int (*get_max_clock)(struct sdhci_host *host);645 unsigned int (*get_min_clock)(struct sdhci_host *host);646 /* get_timeout_clock should return clk rate in unit of Hz */647 unsigned int (*get_timeout_clock)(struct sdhci_host *host);648 unsigned int (*get_max_timeout_count)(struct sdhci_host *host);649 void (*set_timeout)(struct sdhci_host *host,650 struct mmc_command *cmd);651 void (*set_bus_width)(struct sdhci_host *host, int width);652 void (*platform_send_init_74_clocks)(struct sdhci_host *host,653 u8 power_mode);654 unsigned int (*get_ro)(struct sdhci_host *host);655 void (*reset)(struct sdhci_host *host, u8 mask);656 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);657 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);658 void (*hw_reset)(struct sdhci_host *host);659 void (*adma_workaround)(struct sdhci_host *host, u32 intmask);660 void (*card_event)(struct sdhci_host *host);661 void (*voltage_switch)(struct sdhci_host *host);662 void (*adma_write_desc)(struct sdhci_host *host, void **desc,663 dma_addr_t addr, int len, unsigned int cmd);664 void (*copy_to_bounce_buffer)(struct sdhci_host *host,665 struct mmc_data *data,666 unsigned int length);667 void (*request_done)(struct sdhci_host *host,668 struct mmc_request *mrq);669 void (*dump_vendor_regs)(struct sdhci_host *host);670};671 672#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS673 674static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)675{676 if (unlikely(host->ops->write_l))677 host->ops->write_l(host, val, reg);678 else679 writel(val, host->ioaddr + reg);680}681 682static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)683{684 if (unlikely(host->ops->write_w))685 host->ops->write_w(host, val, reg);686 else687 writew(val, host->ioaddr + reg);688}689 690static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)691{692 if (unlikely(host->ops->write_b))693 host->ops->write_b(host, val, reg);694 else695 writeb(val, host->ioaddr + reg);696}697 698static inline u32 sdhci_readl(struct sdhci_host *host, int reg)699{700 if (unlikely(host->ops->read_l))701 return host->ops->read_l(host, reg);702 else703 return readl(host->ioaddr + reg);704}705 706static inline u16 sdhci_readw(struct sdhci_host *host, int reg)707{708 if (unlikely(host->ops->read_w))709 return host->ops->read_w(host, reg);710 else711 return readw(host->ioaddr + reg);712}713 714static inline u8 sdhci_readb(struct sdhci_host *host, int reg)715{716 if (unlikely(host->ops->read_b))717 return host->ops->read_b(host, reg);718 else719 return readb(host->ioaddr + reg);720}721 722#else723 724static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)725{726 writel(val, host->ioaddr + reg);727}728 729static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)730{731 writew(val, host->ioaddr + reg);732}733 734static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)735{736 writeb(val, host->ioaddr + reg);737}738 739static inline u32 sdhci_readl(struct sdhci_host *host, int reg)740{741 return readl(host->ioaddr + reg);742}743 744static inline u16 sdhci_readw(struct sdhci_host *host, int reg)745{746 return readw(host->ioaddr + reg);747}748 749static inline u8 sdhci_readb(struct sdhci_host *host, int reg)750{751 return readb(host->ioaddr + reg);752}753 754#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */755 756struct sdhci_host *sdhci_alloc_host(struct device *dev, size_t priv_size);757void sdhci_free_host(struct sdhci_host *host);758 759static inline void *sdhci_priv(struct sdhci_host *host)760{761 return host->private;762}763 764void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,765 const u32 *caps, const u32 *caps1);766int sdhci_setup_host(struct sdhci_host *host);767void sdhci_cleanup_host(struct sdhci_host *host);768int __sdhci_add_host(struct sdhci_host *host);769int sdhci_add_host(struct sdhci_host *host);770void sdhci_remove_host(struct sdhci_host *host, int dead);771 772static inline void sdhci_read_caps(struct sdhci_host *host)773{774 __sdhci_read_caps(host, NULL, NULL, NULL);775}776 777u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,778 unsigned int *actual_clock);779void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);780void sdhci_enable_clk(struct sdhci_host *host, u16 clk);781void sdhci_set_power(struct sdhci_host *host, unsigned char mode,782 unsigned short vdd);783void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,784 unsigned char mode,785 unsigned short vdd);786void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,787 unsigned short vdd);788int sdhci_get_cd_nogpio(struct mmc_host *mmc);789int sdhci_get_ro(struct mmc_host *mmc);790void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq);791int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq);792void sdhci_set_bus_width(struct sdhci_host *host, int width);793void sdhci_reset(struct sdhci_host *host, u8 mask);794void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);795int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);796int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode);797void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);798int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,799 struct mmc_ios *ios);800void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);801void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,802 dma_addr_t addr, int len, unsigned int cmd);803 804#ifdef CONFIG_PM805int sdhci_suspend_host(struct sdhci_host *host);806int sdhci_resume_host(struct sdhci_host *host);807int sdhci_runtime_suspend_host(struct sdhci_host *host);808int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);809#endif810 811void sdhci_cqe_enable(struct mmc_host *mmc);812void sdhci_cqe_disable(struct mmc_host *mmc, bool recovery);813bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,814 int *data_error);815 816void sdhci_dumpregs(struct sdhci_host *host);817void sdhci_enable_v4_mode(struct sdhci_host *host);818 819void sdhci_start_tuning(struct sdhci_host *host);820void sdhci_end_tuning(struct sdhci_host *host);821void sdhci_reset_tuning(struct sdhci_host *host);822void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);823void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode);824void sdhci_switch_external_dma(struct sdhci_host *host, bool en);825void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable);826void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);827 828#endif /* __SDHCI_HW_H */829