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1// SPDX-License-Identifier: GPL-2.02/*3 * MMCIF eMMC driver.4 *5 * Copyright (C) 2010 Renesas Solutions Corp.6 * Yusuke Goda <yusuke.goda.sx@renesas.com>7 */8 9/*10 * The MMCIF driver is now processing MMC requests asynchronously, according11 * to the Linux MMC API requirement.12 *13 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional14 * data, and optional stop. To achieve asynchronous processing each of these15 * stages is split into two halves: a top and a bottom half. The top half16 * initialises the hardware, installs a timeout handler to handle completion17 * timeouts, and returns. In case of the command stage this immediately returns18 * control to the caller, leaving all further processing to run asynchronously.19 * All further request processing is performed by the bottom halves.20 *21 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler22 * thread, a DMA completion callback, if DMA is used, a timeout work, and23 * request- and stage-specific handler methods.24 *25 * Each bottom half run begins with either a hardware interrupt, a DMA callback26 * invocation, or a timeout work run. In case of an error or a successful27 * processing completion, the MMC core is informed and the request processing is28 * finished. In case processing has to continue, i.e., if data has to be read29 * from or written to the card, or if a stop command has to be sent, the next30 * top half is called, which performs the necessary hardware handling and31 * reschedules the timeout work. This returns the driver state machine into the32 * bottom half waiting state.33 */34 35#include <linux/bitops.h>36#include <linux/clk.h>37#include <linux/completion.h>38#include <linux/delay.h>39#include <linux/dma-mapping.h>40#include <linux/dmaengine.h>41#include <linux/mmc/card.h>42#include <linux/mmc/core.h>43#include <linux/mmc/host.h>44#include <linux/mmc/mmc.h>45#include <linux/mmc/sdio.h>46#include <linux/mmc/slot-gpio.h>47#include <linux/mod_devicetable.h>48#include <linux/mutex.h>49#include <linux/pagemap.h>50#include <linux/platform_data/sh_mmcif.h>51#include <linux/platform_device.h>52#include <linux/pm_qos.h>53#include <linux/pm_runtime.h>54#include <linux/sh_dma.h>55#include <linux/spinlock.h>56#include <linux/module.h>57 58#define DRIVER_NAME "sh_mmcif"59 60/* CE_CMD_SET */61#define CMD_MASK 0x3f00000062#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))63#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */64#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */65#define CMD_SET_RBSY (1 << 21) /* R1b */66#define CMD_SET_CCSEN (1 << 20)67#define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */68#define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */69#define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */70#define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */71#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */72#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */73#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */74#define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/75#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/76#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/77#define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/78#define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */79#define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */80#define CMD_SET_OPDM (1 << 6) /* 1: open/drain */81#define CMD_SET_CCSH (1 << 5)82#define CMD_SET_DARS (1 << 2) /* Dual Data Rate */83#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */84#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */85#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */86 87/* CE_CMD_CTRL */88#define CMD_CTRL_BREAK (1 << 0)89 90/* CE_BLOCK_SET */91#define BLOCK_SIZE_MASK 0x0000ffff92 93/* CE_INT */94#define INT_CCSDE (1 << 29)95#define INT_CMD12DRE (1 << 26)96#define INT_CMD12RBE (1 << 25)97#define INT_CMD12CRE (1 << 24)98#define INT_DTRANE (1 << 23)99#define INT_BUFRE (1 << 22)100#define INT_BUFWEN (1 << 21)101#define INT_BUFREN (1 << 20)102#define INT_CCSRCV (1 << 19)103#define INT_RBSYE (1 << 17)104#define INT_CRSPE (1 << 16)105#define INT_CMDVIO (1 << 15)106#define INT_BUFVIO (1 << 14)107#define INT_WDATERR (1 << 11)108#define INT_RDATERR (1 << 10)109#define INT_RIDXERR (1 << 9)110#define INT_RSPERR (1 << 8)111#define INT_CCSTO (1 << 5)112#define INT_CRCSTO (1 << 4)113#define INT_WDATTO (1 << 3)114#define INT_RDATTO (1 << 2)115#define INT_RBSYTO (1 << 1)116#define INT_RSPTO (1 << 0)117#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \118 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \119 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \120 INT_RDATTO | INT_RBSYTO | INT_RSPTO)121 122#define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \123 INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \124 INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE)125 126#define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE)127 128/* CE_INT_MASK */129#define MASK_ALL 0x00000000130#define MASK_MCCSDE (1 << 29)131#define MASK_MCMD12DRE (1 << 26)132#define MASK_MCMD12RBE (1 << 25)133#define MASK_MCMD12CRE (1 << 24)134#define MASK_MDTRANE (1 << 23)135#define MASK_MBUFRE (1 << 22)136#define MASK_MBUFWEN (1 << 21)137#define MASK_MBUFREN (1 << 20)138#define MASK_MCCSRCV (1 << 19)139#define MASK_MRBSYE (1 << 17)140#define MASK_MCRSPE (1 << 16)141#define MASK_MCMDVIO (1 << 15)142#define MASK_MBUFVIO (1 << 14)143#define MASK_MWDATERR (1 << 11)144#define MASK_MRDATERR (1 << 10)145#define MASK_MRIDXERR (1 << 9)146#define MASK_MRSPERR (1 << 8)147#define MASK_MCCSTO (1 << 5)148#define MASK_MCRCSTO (1 << 4)149#define MASK_MWDATTO (1 << 3)150#define MASK_MRDATTO (1 << 2)151#define MASK_MRBSYTO (1 << 1)152#define MASK_MRSPTO (1 << 0)153 154#define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \155 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \156 MASK_MCRCSTO | MASK_MWDATTO | \157 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)158 159#define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \160 MASK_MBUFREN | MASK_MBUFWEN | \161 MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \162 MASK_MCMD12RBE | MASK_MCMD12CRE)163 164/* CE_HOST_STS1 */165#define STS1_CMDSEQ (1 << 31)166 167/* CE_HOST_STS2 */168#define STS2_CRCSTE (1 << 31)169#define STS2_CRC16E (1 << 30)170#define STS2_AC12CRCE (1 << 29)171#define STS2_RSPCRC7E (1 << 28)172#define STS2_CRCSTEBE (1 << 27)173#define STS2_RDATEBE (1 << 26)174#define STS2_AC12REBE (1 << 25)175#define STS2_RSPEBE (1 << 24)176#define STS2_AC12IDXE (1 << 23)177#define STS2_RSPIDXE (1 << 22)178#define STS2_CCSTO (1 << 15)179#define STS2_RDATTO (1 << 14)180#define STS2_DATBSYTO (1 << 13)181#define STS2_CRCSTTO (1 << 12)182#define STS2_AC12BSYTO (1 << 11)183#define STS2_RSPBSYTO (1 << 10)184#define STS2_AC12RSPTO (1 << 9)185#define STS2_RSPTO (1 << 8)186#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \187 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)188#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \189 STS2_DATBSYTO | STS2_CRCSTTO | \190 STS2_AC12BSYTO | STS2_RSPBSYTO | \191 STS2_AC12RSPTO | STS2_RSPTO)192 193#define CLKDEV_EMMC_DATA 52000000 /* 52 MHz */194#define CLKDEV_MMC_DATA 20000000 /* 20 MHz */195#define CLKDEV_INIT 400000 /* 400 kHz */196 197enum sh_mmcif_state {198 STATE_IDLE,199 STATE_REQUEST,200 STATE_IOS,201 STATE_TIMEOUT,202};203 204enum sh_mmcif_wait_for {205 MMCIF_WAIT_FOR_REQUEST,206 MMCIF_WAIT_FOR_CMD,207 MMCIF_WAIT_FOR_MREAD,208 MMCIF_WAIT_FOR_MWRITE,209 MMCIF_WAIT_FOR_READ,210 MMCIF_WAIT_FOR_WRITE,211 MMCIF_WAIT_FOR_READ_END,212 MMCIF_WAIT_FOR_WRITE_END,213 MMCIF_WAIT_FOR_STOP,214};215 216/*217 * difference for each SoC218 */219struct sh_mmcif_host {220 struct mmc_host *mmc;221 struct mmc_request *mrq;222 struct platform_device *pd;223 struct clk *clk;224 int bus_width;225 unsigned char timing;226 bool sd_error;227 bool dying;228 long timeout;229 void __iomem *addr;230 spinlock_t lock; /* protect sh_mmcif_host::state */231 enum sh_mmcif_state state;232 enum sh_mmcif_wait_for wait_for;233 struct delayed_work timeout_work;234 size_t blocksize;235 struct sg_mapping_iter sg_miter;236 bool power;237 bool ccs_enable; /* Command Completion Signal support */238 bool clk_ctrl2_enable;239 struct mutex thread_lock;240 u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */241 242 /* DMA support */243 struct dma_chan *chan_rx;244 struct dma_chan *chan_tx;245 struct completion dma_complete;246 bool dma_active;247};248 249static const struct of_device_id sh_mmcif_of_match[] = {250 { .compatible = "renesas,sh-mmcif" },251 { }252};253MODULE_DEVICE_TABLE(of, sh_mmcif_of_match);254 255#define sh_mmcif_host_to_dev(host) (&host->pd->dev)256 257static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,258 unsigned int reg, u32 val)259{260 writel(val | readl(host->addr + reg), host->addr + reg);261}262 263static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,264 unsigned int reg, u32 val)265{266 writel(~val & readl(host->addr + reg), host->addr + reg);267}268 269static void sh_mmcif_dma_complete(void *arg)270{271 struct sh_mmcif_host *host = arg;272 struct mmc_request *mrq = host->mrq;273 struct device *dev = sh_mmcif_host_to_dev(host);274 275 dev_dbg(dev, "Command completed\n");276 277 if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n",278 dev_name(dev)))279 return;280 281 complete(&host->dma_complete);282}283 284static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)285{286 struct mmc_data *data = host->mrq->data;287 struct scatterlist *sg = data->sg;288 struct dma_async_tx_descriptor *desc = NULL;289 struct dma_chan *chan = host->chan_rx;290 struct device *dev = sh_mmcif_host_to_dev(host);291 dma_cookie_t cookie = -EINVAL;292 int ret;293 294 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,295 DMA_FROM_DEVICE);296 if (ret > 0) {297 host->dma_active = true;298 desc = dmaengine_prep_slave_sg(chan, sg, ret,299 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);300 }301 302 if (desc) {303 desc->callback = sh_mmcif_dma_complete;304 desc->callback_param = host;305 cookie = dmaengine_submit(desc);306 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);307 dma_async_issue_pending(chan);308 }309 dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n",310 __func__, data->sg_len, ret, cookie);311 312 if (!desc) {313 /* DMA failed, fall back to PIO */314 if (ret >= 0)315 ret = -EIO;316 host->chan_rx = NULL;317 host->dma_active = false;318 dma_release_channel(chan);319 /* Free the Tx channel too */320 chan = host->chan_tx;321 if (chan) {322 host->chan_tx = NULL;323 dma_release_channel(chan);324 }325 dev_warn(dev,326 "DMA failed: %d, falling back to PIO\n", ret);327 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);328 }329 330 dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,331 desc, cookie, data->sg_len);332}333 334static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)335{336 struct mmc_data *data = host->mrq->data;337 struct scatterlist *sg = data->sg;338 struct dma_async_tx_descriptor *desc = NULL;339 struct dma_chan *chan = host->chan_tx;340 struct device *dev = sh_mmcif_host_to_dev(host);341 dma_cookie_t cookie = -EINVAL;342 int ret;343 344 ret = dma_map_sg(chan->device->dev, sg, data->sg_len,345 DMA_TO_DEVICE);346 if (ret > 0) {347 host->dma_active = true;348 desc = dmaengine_prep_slave_sg(chan, sg, ret,349 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);350 }351 352 if (desc) {353 desc->callback = sh_mmcif_dma_complete;354 desc->callback_param = host;355 cookie = dmaengine_submit(desc);356 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);357 dma_async_issue_pending(chan);358 }359 dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n",360 __func__, data->sg_len, ret, cookie);361 362 if (!desc) {363 /* DMA failed, fall back to PIO */364 if (ret >= 0)365 ret = -EIO;366 host->chan_tx = NULL;367 host->dma_active = false;368 dma_release_channel(chan);369 /* Free the Rx channel too */370 chan = host->chan_rx;371 if (chan) {372 host->chan_rx = NULL;373 dma_release_channel(chan);374 }375 dev_warn(dev,376 "DMA failed: %d, falling back to PIO\n", ret);377 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);378 }379 380 dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__,381 desc, cookie);382}383 384static struct dma_chan *385sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id)386{387 dma_cap_mask_t mask;388 389 dma_cap_zero(mask);390 dma_cap_set(DMA_SLAVE, mask);391 if (slave_id <= 0)392 return NULL;393 394 return dma_request_channel(mask, shdma_chan_filter, (void *)slave_id);395}396 397static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host,398 struct dma_chan *chan,399 enum dma_transfer_direction direction)400{401 struct resource *res;402 struct dma_slave_config cfg = { 0, };403 404 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);405 if (!res)406 return -EINVAL;407 408 cfg.direction = direction;409 410 if (direction == DMA_DEV_TO_MEM) {411 cfg.src_addr = res->start + MMCIF_CE_DATA;412 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;413 } else {414 cfg.dst_addr = res->start + MMCIF_CE_DATA;415 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;416 }417 418 return dmaengine_slave_config(chan, &cfg);419}420 421static void sh_mmcif_request_dma(struct sh_mmcif_host *host)422{423 struct device *dev = sh_mmcif_host_to_dev(host);424 host->dma_active = false;425 426 /* We can only either use DMA for both Tx and Rx or not use it at all */427 if (IS_ENABLED(CONFIG_SUPERH) && dev->platform_data) {428 struct sh_mmcif_plat_data *pdata = dev->platform_data;429 430 host->chan_tx = sh_mmcif_request_dma_pdata(host,431 pdata->slave_id_tx);432 host->chan_rx = sh_mmcif_request_dma_pdata(host,433 pdata->slave_id_rx);434 } else {435 host->chan_tx = dma_request_chan(dev, "tx");436 if (IS_ERR(host->chan_tx))437 host->chan_tx = NULL;438 host->chan_rx = dma_request_chan(dev, "rx");439 if (IS_ERR(host->chan_rx))440 host->chan_rx = NULL;441 }442 dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx,443 host->chan_rx);444 445 if (!host->chan_tx || !host->chan_rx ||446 sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) ||447 sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM))448 goto error;449 450 return;451 452error:453 if (host->chan_tx)454 dma_release_channel(host->chan_tx);455 if (host->chan_rx)456 dma_release_channel(host->chan_rx);457 host->chan_tx = host->chan_rx = NULL;458}459 460static void sh_mmcif_release_dma(struct sh_mmcif_host *host)461{462 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);463 /* Descriptors are freed automatically */464 if (host->chan_tx) {465 struct dma_chan *chan = host->chan_tx;466 host->chan_tx = NULL;467 dma_release_channel(chan);468 }469 if (host->chan_rx) {470 struct dma_chan *chan = host->chan_rx;471 host->chan_rx = NULL;472 dma_release_channel(chan);473 }474 475 host->dma_active = false;476}477 478static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)479{480 struct device *dev = sh_mmcif_host_to_dev(host);481 struct sh_mmcif_plat_data *p = dev->platform_data;482 bool sup_pclk = p ? p->sup_pclk : false;483 unsigned int current_clk = clk_get_rate(host->clk);484 unsigned int clkdiv;485 486 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);487 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);488 489 if (!clk)490 return;491 492 if (host->clkdiv_map) {493 unsigned int freq, best_freq, myclk, div, diff_min, diff;494 int i;495 496 clkdiv = 0;497 diff_min = ~0;498 best_freq = 0;499 for (i = 31; i >= 0; i--) {500 if (!((1 << i) & host->clkdiv_map))501 continue;502 503 /*504 * clk = parent_freq / div505 * -> parent_freq = clk x div506 */507 508 div = 1 << (i + 1);509 freq = clk_round_rate(host->clk, clk * div);510 myclk = freq / div;511 diff = (myclk > clk) ? myclk - clk : clk - myclk;512 513 if (diff <= diff_min) {514 best_freq = freq;515 clkdiv = i;516 diff_min = diff;517 }518 }519 520 dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n",521 (best_freq >> (clkdiv + 1)), clk, best_freq, clkdiv);522 523 clk_set_rate(host->clk, best_freq);524 clkdiv = clkdiv << 16;525 } else if (sup_pclk && clk == current_clk) {526 clkdiv = CLK_SUP_PCLK;527 } else {528 clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16;529 }530 531 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv);532 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);533}534 535static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)536{537 u32 tmp;538 539 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);540 541 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);542 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);543 if (host->ccs_enable)544 tmp |= SCCSTO_29;545 if (host->clk_ctrl2_enable)546 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000);547 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |548 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);549 /* byte swap on */550 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);551}552 553static int sh_mmcif_error_manage(struct sh_mmcif_host *host)554{555 struct device *dev = sh_mmcif_host_to_dev(host);556 u32 state1, state2;557 int ret, timeout;558 559 host->sd_error = false;560 561 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);562 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);563 dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1);564 dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2);565 566 if (state1 & STS1_CMDSEQ) {567 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);568 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);569 for (timeout = 10000; timeout; timeout--) {570 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)571 & STS1_CMDSEQ))572 break;573 mdelay(1);574 }575 if (!timeout) {576 dev_err(dev,577 "Forced end of command sequence timeout err\n");578 return -EIO;579 }580 sh_mmcif_sync_reset(host);581 dev_dbg(dev, "Forced end of command sequence\n");582 return -EIO;583 }584 585 if (state2 & STS2_CRC_ERR) {586 dev_err(dev, " CRC error: state %u, wait %u\n",587 host->state, host->wait_for);588 ret = -EIO;589 } else if (state2 & STS2_TIMEOUT_ERR) {590 dev_err(dev, " Timeout: state %u, wait %u\n",591 host->state, host->wait_for);592 ret = -ETIMEDOUT;593 } else {594 dev_dbg(dev, " End/Index error: state %u, wait %u\n",595 host->state, host->wait_for);596 ret = -EIO;597 }598 return ret;599}600 601static void sh_mmcif_single_read(struct sh_mmcif_host *host,602 struct mmc_request *mrq)603{604 struct mmc_data *data = mrq->data;605 606 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &607 BLOCK_SIZE_MASK) + 3;608 609 sg_miter_start(&host->sg_miter, data->sg, data->sg_len,610 SG_MITER_TO_SG);611 612 host->wait_for = MMCIF_WAIT_FOR_READ;613 614 /* buf read enable */615 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);616}617 618static bool sh_mmcif_read_block(struct sh_mmcif_host *host)619{620 struct sg_mapping_iter *sgm = &host->sg_miter;621 struct device *dev = sh_mmcif_host_to_dev(host);622 struct mmc_data *data = host->mrq->data;623 u32 *p;624 int i;625 626 if (host->sd_error) {627 sg_miter_stop(sgm);628 data->error = sh_mmcif_error_manage(host);629 dev_dbg(dev, "%s(): %d\n", __func__, data->error);630 return false;631 }632 633 if (!sg_miter_next(sgm)) {634 /* This should not happen on single blocks */635 sg_miter_stop(sgm);636 return false;637 }638 639 p = sgm->addr;640 641 for (i = 0; i < host->blocksize / 4; i++)642 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);643 644 sg_miter_stop(&host->sg_miter);645 646 /* buffer read end */647 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);648 host->wait_for = MMCIF_WAIT_FOR_READ_END;649 650 return true;651}652 653static void sh_mmcif_multi_read(struct sh_mmcif_host *host,654 struct mmc_request *mrq)655{656 struct sg_mapping_iter *sgm = &host->sg_miter;657 struct mmc_data *data = mrq->data;658 659 if (!data->sg_len || !data->sg->length)660 return;661 662 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &663 BLOCK_SIZE_MASK;664 665 sg_miter_start(sgm, data->sg, data->sg_len,666 SG_MITER_TO_SG);667 668 /* Advance to the first sglist entry */669 if (!sg_miter_next(sgm)) {670 sg_miter_stop(sgm);671 return;672 }673 674 host->wait_for = MMCIF_WAIT_FOR_MREAD;675 676 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);677}678 679static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)680{681 struct sg_mapping_iter *sgm = &host->sg_miter;682 struct device *dev = sh_mmcif_host_to_dev(host);683 struct mmc_data *data = host->mrq->data;684 u32 *p;685 int i;686 687 if (host->sd_error) {688 sg_miter_stop(sgm);689 data->error = sh_mmcif_error_manage(host);690 dev_dbg(dev, "%s(): %d\n", __func__, data->error);691 return false;692 }693 694 p = sgm->addr;695 696 for (i = 0; i < host->blocksize / 4; i++)697 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);698 699 sgm->consumed = host->blocksize;700 701 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);702 703 if (!sg_miter_next(sgm)) {704 sg_miter_stop(sgm);705 return false;706 }707 708 return true;709}710 711static void sh_mmcif_single_write(struct sh_mmcif_host *host,712 struct mmc_request *mrq)713{714 struct mmc_data *data = mrq->data;715 716 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &717 BLOCK_SIZE_MASK) + 3;718 719 sg_miter_start(&host->sg_miter, data->sg, data->sg_len,720 SG_MITER_FROM_SG);721 722 host->wait_for = MMCIF_WAIT_FOR_WRITE;723 724 /* buf write enable */725 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);726}727 728static bool sh_mmcif_write_block(struct sh_mmcif_host *host)729{730 struct sg_mapping_iter *sgm = &host->sg_miter;731 struct device *dev = sh_mmcif_host_to_dev(host);732 struct mmc_data *data = host->mrq->data;733 u32 *p;734 int i;735 736 if (host->sd_error) {737 sg_miter_stop(sgm);738 data->error = sh_mmcif_error_manage(host);739 dev_dbg(dev, "%s(): %d\n", __func__, data->error);740 return false;741 }742 743 if (!sg_miter_next(sgm)) {744 /* This should not happen on single blocks */745 sg_miter_stop(sgm);746 return false;747 }748 749 p = sgm->addr;750 751 for (i = 0; i < host->blocksize / 4; i++)752 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);753 754 sg_miter_stop(&host->sg_miter);755 756 /* buffer write end */757 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);758 host->wait_for = MMCIF_WAIT_FOR_WRITE_END;759 760 return true;761}762 763static void sh_mmcif_multi_write(struct sh_mmcif_host *host,764 struct mmc_request *mrq)765{766 struct sg_mapping_iter *sgm = &host->sg_miter;767 struct mmc_data *data = mrq->data;768 769 if (!data->sg_len || !data->sg->length)770 return;771 772 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &773 BLOCK_SIZE_MASK;774 775 sg_miter_start(sgm, data->sg, data->sg_len,776 SG_MITER_FROM_SG);777 778 /* Advance to the first sglist entry */779 if (!sg_miter_next(sgm)) {780 sg_miter_stop(sgm);781 return;782 }783 784 host->wait_for = MMCIF_WAIT_FOR_MWRITE;785 786 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);787}788 789static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)790{791 struct sg_mapping_iter *sgm = &host->sg_miter;792 struct device *dev = sh_mmcif_host_to_dev(host);793 struct mmc_data *data = host->mrq->data;794 u32 *p;795 int i;796 797 if (host->sd_error) {798 sg_miter_stop(sgm);799 data->error = sh_mmcif_error_manage(host);800 dev_dbg(dev, "%s(): %d\n", __func__, data->error);801 return false;802 }803 804 p = sgm->addr;805 806 for (i = 0; i < host->blocksize / 4; i++)807 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);808 809 sgm->consumed = host->blocksize;810 811 if (!sg_miter_next(sgm)) {812 sg_miter_stop(sgm);813 return false;814 }815 816 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);817 818 return true;819}820 821static void sh_mmcif_get_response(struct sh_mmcif_host *host,822 struct mmc_command *cmd)823{824 if (cmd->flags & MMC_RSP_136) {825 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);826 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);827 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);828 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);829 } else830 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);831}832 833static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,834 struct mmc_command *cmd)835{836 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);837}838 839static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,840 struct mmc_request *mrq)841{842 struct device *dev = sh_mmcif_host_to_dev(host);843 struct mmc_data *data = mrq->data;844 struct mmc_command *cmd = mrq->cmd;845 u32 opc = cmd->opcode;846 u32 tmp = 0;847 848 /* Response Type check */849 switch (mmc_resp_type(cmd)) {850 case MMC_RSP_NONE:851 tmp |= CMD_SET_RTYP_NO;852 break;853 case MMC_RSP_R1:854 case MMC_RSP_R3:855 tmp |= CMD_SET_RTYP_6B;856 break;857 case MMC_RSP_R1B:858 tmp |= CMD_SET_RBSY | CMD_SET_RTYP_6B;859 break;860 case MMC_RSP_R2:861 tmp |= CMD_SET_RTYP_17B;862 break;863 default:864 dev_err(dev, "Unsupported response type.\n");865 break;866 }867 868 /* WDAT / DATW */869 if (data) {870 tmp |= CMD_SET_WDAT;871 switch (host->bus_width) {872 case MMC_BUS_WIDTH_1:873 tmp |= CMD_SET_DATW_1;874 break;875 case MMC_BUS_WIDTH_4:876 tmp |= CMD_SET_DATW_4;877 break;878 case MMC_BUS_WIDTH_8:879 tmp |= CMD_SET_DATW_8;880 break;881 default:882 dev_err(dev, "Unsupported bus width.\n");883 break;884 }885 switch (host->timing) {886 case MMC_TIMING_MMC_DDR52:887 /*888 * MMC core will only set this timing, if the host889 * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR890 * capability. MMCIF implementations with this891 * capability, e.g. sh73a0, will have to set it892 * in their platform data.893 */894 tmp |= CMD_SET_DARS;895 break;896 }897 }898 /* DWEN */899 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)900 tmp |= CMD_SET_DWEN;901 /* CMLTE/CMD12EN */902 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {903 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;904 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,905 data->blocks << 16);906 }907 /* RIDXC[1:0] check bits */908 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||909 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)910 tmp |= CMD_SET_RIDXC_BITS;911 /* RCRC7C[1:0] check bits */912 if (opc == MMC_SEND_OP_COND)913 tmp |= CMD_SET_CRC7C_BITS;914 /* RCRC7C[1:0] internal CRC7 */915 if (opc == MMC_ALL_SEND_CID ||916 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)917 tmp |= CMD_SET_CRC7C_INTERNAL;918 919 return (opc << 24) | tmp;920}921 922static int sh_mmcif_data_trans(struct sh_mmcif_host *host,923 struct mmc_request *mrq, u32 opc)924{925 struct device *dev = sh_mmcif_host_to_dev(host);926 927 switch (opc) {928 case MMC_READ_MULTIPLE_BLOCK:929 sh_mmcif_multi_read(host, mrq);930 return 0;931 case MMC_WRITE_MULTIPLE_BLOCK:932 sh_mmcif_multi_write(host, mrq);933 return 0;934 case MMC_WRITE_BLOCK:935 sh_mmcif_single_write(host, mrq);936 return 0;937 case MMC_READ_SINGLE_BLOCK:938 case MMC_SEND_EXT_CSD:939 sh_mmcif_single_read(host, mrq);940 return 0;941 default:942 dev_err(dev, "Unsupported CMD%d\n", opc);943 return -EINVAL;944 }945}946 947static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,948 struct mmc_request *mrq)949{950 struct mmc_command *cmd = mrq->cmd;951 u32 opc;952 u32 mask = 0;953 unsigned long flags;954 955 if (cmd->flags & MMC_RSP_BUSY)956 mask = MASK_START_CMD | MASK_MRBSYE;957 else958 mask = MASK_START_CMD | MASK_MCRSPE;959 960 if (host->ccs_enable)961 mask |= MASK_MCCSTO;962 963 if (mrq->data) {964 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);965 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,966 mrq->data->blksz);967 }968 opc = sh_mmcif_set_cmd(host, mrq);969 970 if (host->ccs_enable)971 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);972 else973 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS);974 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);975 /* set arg */976 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);977 /* set cmd */978 spin_lock_irqsave(&host->lock, flags);979 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);980 981 host->wait_for = MMCIF_WAIT_FOR_CMD;982 schedule_delayed_work(&host->timeout_work, host->timeout);983 spin_unlock_irqrestore(&host->lock, flags);984}985 986static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,987 struct mmc_request *mrq)988{989 struct device *dev = sh_mmcif_host_to_dev(host);990 991 switch (mrq->cmd->opcode) {992 case MMC_READ_MULTIPLE_BLOCK:993 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);994 break;995 case MMC_WRITE_MULTIPLE_BLOCK:996 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);997 break;998 default:999 dev_err(dev, "unsupported stop cmd\n");1000 mrq->stop->error = sh_mmcif_error_manage(host);1001 return;1002 }1003 1004 host->wait_for = MMCIF_WAIT_FOR_STOP;1005}1006 1007static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)1008{1009 struct sh_mmcif_host *host = mmc_priv(mmc);1010 struct device *dev = sh_mmcif_host_to_dev(host);1011 unsigned long flags;1012 1013 spin_lock_irqsave(&host->lock, flags);1014 if (host->state != STATE_IDLE) {1015 dev_dbg(dev, "%s() rejected, state %u\n",1016 __func__, host->state);1017 spin_unlock_irqrestore(&host->lock, flags);1018 mrq->cmd->error = -EAGAIN;1019 mmc_request_done(mmc, mrq);1020 return;1021 }1022 1023 host->state = STATE_REQUEST;1024 spin_unlock_irqrestore(&host->lock, flags);1025 1026 host->mrq = mrq;1027 1028 sh_mmcif_start_cmd(host, mrq);1029}1030 1031static void sh_mmcif_clk_setup(struct sh_mmcif_host *host)1032{1033 struct device *dev = sh_mmcif_host_to_dev(host);1034 1035 if (host->mmc->f_max) {1036 unsigned int f_max, f_min = 0, f_min_old;1037 1038 f_max = host->mmc->f_max;1039 for (f_min_old = f_max; f_min_old > 2;) {1040 f_min = clk_round_rate(host->clk, f_min_old / 2);1041 if (f_min == f_min_old)1042 break;1043 f_min_old = f_min;1044 }1045 1046 /*1047 * This driver assumes this SoC is R-Car Gen2 or later1048 */1049 host->clkdiv_map = 0x3ff;1050 1051 host->mmc->f_max = f_max >> ffs(host->clkdiv_map);1052 host->mmc->f_min = f_min >> fls(host->clkdiv_map);1053 } else {1054 unsigned int clk = clk_get_rate(host->clk);1055 1056 host->mmc->f_max = clk / 2;1057 host->mmc->f_min = clk / 512;1058 }1059 1060 dev_dbg(dev, "clk max/min = %d/%d\n",1061 host->mmc->f_max, host->mmc->f_min);1062}1063 1064static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)1065{1066 struct sh_mmcif_host *host = mmc_priv(mmc);1067 struct device *dev = sh_mmcif_host_to_dev(host);1068 unsigned long flags;1069 1070 spin_lock_irqsave(&host->lock, flags);1071 if (host->state != STATE_IDLE) {1072 dev_dbg(dev, "%s() rejected, state %u\n",1073 __func__, host->state);1074 spin_unlock_irqrestore(&host->lock, flags);1075 return;1076 }1077 1078 host->state = STATE_IOS;1079 spin_unlock_irqrestore(&host->lock, flags);1080 1081 switch (ios->power_mode) {1082 case MMC_POWER_UP:1083 if (!IS_ERR(mmc->supply.vmmc))1084 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);1085 if (!host->power) {1086 clk_prepare_enable(host->clk);1087 pm_runtime_get_sync(dev);1088 sh_mmcif_sync_reset(host);1089 sh_mmcif_request_dma(host);1090 host->power = true;1091 }1092 break;1093 case MMC_POWER_OFF:1094 if (!IS_ERR(mmc->supply.vmmc))1095 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);1096 if (host->power) {1097 sh_mmcif_clock_control(host, 0);1098 sh_mmcif_release_dma(host);1099 pm_runtime_put(dev);1100 clk_disable_unprepare(host->clk);1101 host->power = false;1102 }1103 break;1104 case MMC_POWER_ON:1105 sh_mmcif_clock_control(host, ios->clock);1106 break;1107 }1108 1109 host->timing = ios->timing;1110 host->bus_width = ios->bus_width;1111 host->state = STATE_IDLE;1112}1113 1114static const struct mmc_host_ops sh_mmcif_ops = {1115 .request = sh_mmcif_request,1116 .set_ios = sh_mmcif_set_ios,1117 .get_cd = mmc_gpio_get_cd,1118};1119 1120static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)1121{1122 struct mmc_command *cmd = host->mrq->cmd;1123 struct mmc_data *data = host->mrq->data;1124 struct device *dev = sh_mmcif_host_to_dev(host);1125 long time;1126 1127 if (host->sd_error) {1128 switch (cmd->opcode) {1129 case MMC_ALL_SEND_CID:1130 case MMC_SELECT_CARD:1131 case MMC_APP_CMD:1132 cmd->error = -ETIMEDOUT;1133 break;1134 default:1135 cmd->error = sh_mmcif_error_manage(host);1136 break;1137 }1138 dev_dbg(dev, "CMD%d error %d\n",1139 cmd->opcode, cmd->error);1140 host->sd_error = false;1141 return false;1142 }1143 if (!(cmd->flags & MMC_RSP_PRESENT)) {1144 cmd->error = 0;1145 return false;1146 }1147 1148 sh_mmcif_get_response(host, cmd);1149 1150 if (!data)1151 return false;1152 1153 /*1154 * Completion can be signalled from DMA callback and error, so, have to1155 * reset here, before setting .dma_active1156 */1157 init_completion(&host->dma_complete);1158 1159 if (data->flags & MMC_DATA_READ) {1160 if (host->chan_rx)1161 sh_mmcif_start_dma_rx(host);1162 } else {1163 if (host->chan_tx)1164 sh_mmcif_start_dma_tx(host);1165 }1166 1167 if (!host->dma_active) {1168 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);1169 return !data->error;1170 }1171 1172 /* Running in the IRQ thread, can sleep */1173 time = wait_for_completion_interruptible_timeout(&host->dma_complete,1174 host->timeout);1175 1176 if (data->flags & MMC_DATA_READ)1177 dma_unmap_sg(host->chan_rx->device->dev,1178 data->sg, data->sg_len,1179 DMA_FROM_DEVICE);1180 else1181 dma_unmap_sg(host->chan_tx->device->dev,1182 data->sg, data->sg_len,1183 DMA_TO_DEVICE);1184 1185 if (host->sd_error) {1186 dev_err(host->mmc->parent,1187 "Error IRQ while waiting for DMA completion!\n");1188 /* Woken up by an error IRQ: abort DMA */1189 data->error = sh_mmcif_error_manage(host);1190 } else if (!time) {1191 dev_err(host->mmc->parent, "DMA timeout!\n");1192 data->error = -ETIMEDOUT;1193 } else if (time < 0) {1194 dev_err(host->mmc->parent,1195 "wait_for_completion_...() error %ld!\n", time);1196 data->error = time;1197 }1198 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,1199 BUF_ACC_DMAREN | BUF_ACC_DMAWEN);1200 host->dma_active = false;1201 1202 if (data->error) {1203 data->bytes_xfered = 0;1204 /* Abort DMA */1205 if (data->flags & MMC_DATA_READ)1206 dmaengine_terminate_sync(host->chan_rx);1207 else1208 dmaengine_terminate_sync(host->chan_tx);1209 }1210 1211 return false;1212}1213 1214static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)1215{1216 struct sh_mmcif_host *host = dev_id;1217 struct mmc_request *mrq;1218 struct device *dev = sh_mmcif_host_to_dev(host);1219 bool wait = false;1220 unsigned long flags;1221 int wait_work;1222 1223 spin_lock_irqsave(&host->lock, flags);1224 wait_work = host->wait_for;1225 spin_unlock_irqrestore(&host->lock, flags);1226 1227 cancel_delayed_work_sync(&host->timeout_work);1228 1229 mutex_lock(&host->thread_lock);1230 1231 mrq = host->mrq;1232 if (!mrq) {1233 dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n",1234 host->state, host->wait_for);1235 mutex_unlock(&host->thread_lock);1236 return IRQ_HANDLED;1237 }1238 1239 /*1240 * All handlers return true, if processing continues, and false, if the1241 * request has to be completed - successfully or not1242 */1243 switch (wait_work) {1244 case MMCIF_WAIT_FOR_REQUEST:1245 /* We're too late, the timeout has already kicked in */1246 mutex_unlock(&host->thread_lock);1247 return IRQ_HANDLED;1248 case MMCIF_WAIT_FOR_CMD:1249 /* Wait for data? */1250 wait = sh_mmcif_end_cmd(host);1251 break;1252 case MMCIF_WAIT_FOR_MREAD:1253 /* Wait for more data? */1254 wait = sh_mmcif_mread_block(host);1255 break;1256 case MMCIF_WAIT_FOR_READ:1257 /* Wait for data end? */1258 wait = sh_mmcif_read_block(host);1259 break;1260 case MMCIF_WAIT_FOR_MWRITE:1261 /* Wait data to write? */1262 wait = sh_mmcif_mwrite_block(host);1263 break;1264 case MMCIF_WAIT_FOR_WRITE:1265 /* Wait for data end? */1266 wait = sh_mmcif_write_block(host);1267 break;1268 case MMCIF_WAIT_FOR_STOP:1269 if (host->sd_error) {1270 mrq->stop->error = sh_mmcif_error_manage(host);1271 dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error);1272 break;1273 }1274 sh_mmcif_get_cmd12response(host, mrq->stop);1275 mrq->stop->error = 0;1276 break;1277 case MMCIF_WAIT_FOR_READ_END:1278 case MMCIF_WAIT_FOR_WRITE_END:1279 if (host->sd_error) {1280 mrq->data->error = sh_mmcif_error_manage(host);1281 dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error);1282 }1283 break;1284 default:1285 BUG();1286 }1287 1288 if (wait) {1289 schedule_delayed_work(&host->timeout_work, host->timeout);1290 /* Wait for more data */1291 mutex_unlock(&host->thread_lock);1292 return IRQ_HANDLED;1293 }1294 1295 if (host->wait_for != MMCIF_WAIT_FOR_STOP) {1296 struct mmc_data *data = mrq->data;1297 if (!mrq->cmd->error && data && !data->error)1298 data->bytes_xfered =1299 data->blocks * data->blksz;1300 1301 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {1302 sh_mmcif_stop_cmd(host, mrq);1303 if (!mrq->stop->error) {1304 schedule_delayed_work(&host->timeout_work, host->timeout);1305 mutex_unlock(&host->thread_lock);1306 return IRQ_HANDLED;1307 }1308 }1309 }1310 1311 host->wait_for = MMCIF_WAIT_FOR_REQUEST;1312 host->state = STATE_IDLE;1313 host->mrq = NULL;1314 mmc_request_done(host->mmc, mrq);1315 1316 mutex_unlock(&host->thread_lock);1317 1318 return IRQ_HANDLED;1319}1320 1321static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)1322{1323 struct sh_mmcif_host *host = dev_id;1324 struct device *dev = sh_mmcif_host_to_dev(host);1325 u32 state, mask;1326 1327 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);1328 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK);1329 if (host->ccs_enable)1330 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask));1331 else1332 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask));1333 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN);1334 1335 if (state & ~MASK_CLEAN)1336 dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n",1337 state);1338 1339 if (state & INT_ERR_STS || state & ~INT_ALL) {1340 host->sd_error = true;1341 dev_dbg(dev, "int err state = 0x%08x\n", state);1342 }1343 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {1344 if (!host->mrq)1345 dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state);1346 if (!host->dma_active)1347 return IRQ_WAKE_THREAD;1348 else if (host->sd_error)1349 sh_mmcif_dma_complete(host);1350 } else {1351 dev_dbg(dev, "Unexpected IRQ 0x%x\n", state);1352 }1353 1354 return IRQ_HANDLED;1355}1356 1357static void sh_mmcif_timeout_work(struct work_struct *work)1358{1359 struct delayed_work *d = to_delayed_work(work);1360 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);1361 struct mmc_request *mrq = host->mrq;1362 struct device *dev = sh_mmcif_host_to_dev(host);1363 unsigned long flags;1364 1365 if (host->dying)1366 /* Don't run after mmc_remove_host() */1367 return;1368 1369 spin_lock_irqsave(&host->lock, flags);1370 if (host->state == STATE_IDLE) {1371 spin_unlock_irqrestore(&host->lock, flags);1372 return;1373 }1374 1375 dev_err(dev, "Timeout waiting for %u on CMD%u\n",1376 host->wait_for, mrq->cmd->opcode);1377 1378 host->state = STATE_TIMEOUT;1379 spin_unlock_irqrestore(&host->lock, flags);1380 1381 /*1382 * Handle races with cancel_delayed_work(), unless1383 * cancel_delayed_work_sync() is used1384 */1385 switch (host->wait_for) {1386 case MMCIF_WAIT_FOR_CMD:1387 mrq->cmd->error = sh_mmcif_error_manage(host);1388 break;1389 case MMCIF_WAIT_FOR_STOP:1390 mrq->stop->error = sh_mmcif_error_manage(host);1391 break;1392 case MMCIF_WAIT_FOR_MREAD:1393 case MMCIF_WAIT_FOR_MWRITE:1394 case MMCIF_WAIT_FOR_READ:1395 case MMCIF_WAIT_FOR_WRITE:1396 case MMCIF_WAIT_FOR_READ_END:1397 case MMCIF_WAIT_FOR_WRITE_END:1398 mrq->data->error = sh_mmcif_error_manage(host);1399 break;1400 default:1401 BUG();1402 }1403 1404 host->state = STATE_IDLE;1405 host->wait_for = MMCIF_WAIT_FOR_REQUEST;1406 host->mrq = NULL;1407 mmc_request_done(host->mmc, mrq);1408}1409 1410static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)1411{1412 struct device *dev = sh_mmcif_host_to_dev(host);1413 struct sh_mmcif_plat_data *pd = dev->platform_data;1414 struct mmc_host *mmc = host->mmc;1415 1416 mmc_regulator_get_supply(mmc);1417 1418 if (!pd)1419 return;1420 1421 if (!mmc->ocr_avail)1422 mmc->ocr_avail = pd->ocr;1423 else if (pd->ocr)1424 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");1425}1426 1427static int sh_mmcif_probe(struct platform_device *pdev)1428{1429 int ret = 0, irq[2];1430 struct mmc_host *mmc;1431 struct sh_mmcif_host *host;1432 struct device *dev = &pdev->dev;1433 struct sh_mmcif_plat_data *pd = dev->platform_data;1434 void __iomem *reg;1435 const char *name;1436 1437 irq[0] = platform_get_irq(pdev, 0);1438 irq[1] = platform_get_irq_optional(pdev, 1);1439 if (irq[0] < 0)1440 return irq[0];1441 1442 reg = devm_platform_ioremap_resource(pdev, 0);1443 if (IS_ERR(reg))1444 return PTR_ERR(reg);1445 1446 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev);1447 if (!mmc)1448 return -ENOMEM;1449 1450 ret = mmc_of_parse(mmc);1451 if (ret < 0)1452 goto err_host;1453 1454 host = mmc_priv(mmc);1455 host->mmc = mmc;1456 host->addr = reg;1457 host->timeout = msecs_to_jiffies(10000);1458 host->ccs_enable = true;1459 host->clk_ctrl2_enable = false;1460 1461 host->pd = pdev;1462 1463 spin_lock_init(&host->lock);1464 1465 mmc->ops = &sh_mmcif_ops;1466 sh_mmcif_init_ocr(host);1467 1468 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;1469 mmc->caps2 |= MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;1470 mmc->max_busy_timeout = 10000;1471 1472 if (pd && pd->caps)1473 mmc->caps |= pd->caps;1474 mmc->max_segs = 32;1475 mmc->max_blk_size = 512;1476 mmc->max_req_size = PAGE_SIZE * mmc->max_segs;1477 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;1478 mmc->max_seg_size = mmc->max_req_size;1479 1480 platform_set_drvdata(pdev, host);1481 1482 host->clk = devm_clk_get(dev, NULL);1483 if (IS_ERR(host->clk)) {1484 ret = PTR_ERR(host->clk);1485 dev_err(dev, "cannot get clock: %d\n", ret);1486 goto err_host;1487 }1488 1489 ret = clk_prepare_enable(host->clk);1490 if (ret < 0)1491 goto err_host;1492 1493 sh_mmcif_clk_setup(host);1494 1495 pm_runtime_enable(dev);1496 host->power = false;1497 1498 ret = pm_runtime_get_sync(dev);1499 if (ret < 0)1500 goto err_clk;1501 1502 INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work);1503 1504 sh_mmcif_sync_reset(host);1505 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);1506 1507 name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error";1508 ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr,1509 sh_mmcif_irqt, 0, name, host);1510 if (ret) {1511 dev_err(dev, "request_irq error (%s)\n", name);1512 goto err_clk;1513 }1514 if (irq[1] >= 0) {1515 ret = devm_request_threaded_irq(dev, irq[1],1516 sh_mmcif_intr, sh_mmcif_irqt,1517 0, "sh_mmc:int", host);1518 if (ret) {1519 dev_err(dev, "request_irq error (sh_mmc:int)\n");1520 goto err_clk;1521 }1522 }1523 1524 mutex_init(&host->thread_lock);1525 1526 ret = mmc_add_host(mmc);1527 if (ret < 0)1528 goto err_clk;1529 1530 dev_pm_qos_expose_latency_limit(dev, 100);1531 1532 dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n",1533 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff,1534 clk_get_rate(host->clk) / 1000000UL);1535 1536 pm_runtime_put(dev);1537 clk_disable_unprepare(host->clk);1538 return ret;1539 1540err_clk:1541 clk_disable_unprepare(host->clk);1542 pm_runtime_put_sync(dev);1543 pm_runtime_disable(dev);1544err_host:1545 mmc_free_host(mmc);1546 return ret;1547}1548 1549static void sh_mmcif_remove(struct platform_device *pdev)1550{1551 struct sh_mmcif_host *host = platform_get_drvdata(pdev);1552 1553 host->dying = true;1554 clk_prepare_enable(host->clk);1555 pm_runtime_get_sync(&pdev->dev);1556 1557 dev_pm_qos_hide_latency_limit(&pdev->dev);1558 1559 mmc_remove_host(host->mmc);1560 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);1561 1562 /*1563 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the1564 * mmc_remove_host() call above. But swapping order doesn't help either1565 * (a query on the linux-mmc mailing list didn't bring any replies).1566 */1567 cancel_delayed_work_sync(&host->timeout_work);1568 1569 clk_disable_unprepare(host->clk);1570 mmc_free_host(host->mmc);1571 pm_runtime_put_sync(&pdev->dev);1572 pm_runtime_disable(&pdev->dev);1573}1574 1575#ifdef CONFIG_PM_SLEEP1576static int sh_mmcif_suspend(struct device *dev)1577{1578 struct sh_mmcif_host *host = dev_get_drvdata(dev);1579 1580 pm_runtime_get_sync(dev);1581 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);1582 pm_runtime_put(dev);1583 1584 return 0;1585}1586 1587static int sh_mmcif_resume(struct device *dev)1588{1589 return 0;1590}1591#endif1592 1593static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {1594 SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume)1595};1596 1597static struct platform_driver sh_mmcif_driver = {1598 .probe = sh_mmcif_probe,1599 .remove_new = sh_mmcif_remove,1600 .driver = {1601 .name = DRIVER_NAME,1602 .probe_type = PROBE_PREFER_ASYNCHRONOUS,1603 .pm = &sh_mmcif_dev_pm_ops,1604 .of_match_table = sh_mmcif_of_match,1605 },1606};1607 1608module_platform_driver(sh_mmcif_driver);1609 1610MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");1611MODULE_LICENSE("GPL v2");1612MODULE_ALIAS("platform:" DRIVER_NAME);1613MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");1614