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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Driver for sunxi SD/MMC host controllers4 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.5 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>6 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>7 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch>8 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com>9 * (C) Copyright 2017 Sootech SA10 */11 12#include <linux/clk.h>13#include <linux/clk/sunxi-ng.h>14#include <linux/delay.h>15#include <linux/device.h>16#include <linux/dma-mapping.h>17#include <linux/err.h>18#include <linux/interrupt.h>19#include <linux/io.h>20#include <linux/kernel.h>21#include <linux/mmc/card.h>22#include <linux/mmc/core.h>23#include <linux/mmc/host.h>24#include <linux/mmc/mmc.h>25#include <linux/mmc/sd.h>26#include <linux/mmc/sdio.h>27#include <linux/mmc/slot-gpio.h>28#include <linux/module.h>29#include <linux/mod_devicetable.h>30#include <linux/of_address.h>31#include <linux/of_platform.h>32#include <linux/platform_device.h>33#include <linux/pm_runtime.h>34#include <linux/regulator/consumer.h>35#include <linux/reset.h>36#include <linux/scatterlist.h>37#include <linux/slab.h>38#include <linux/spinlock.h>39 40/* register offset definitions */41#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */42#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */43#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */44#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */45#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */46#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */47#define SDXC_REG_CMDR (0x18) /* SMC Command Register */48#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */49#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */50#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */51#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */52#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */53#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */54#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */55#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */56#define SDXC_REG_STAS (0x3C) /* SMC Status Register */57#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */58#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */59#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */60#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */61#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */62#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */63#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */64#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */65#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */66#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */67#define SDXC_REG_CHDA (0x90)68#define SDXC_REG_CBDA (0x94)69 70/* New registers introduced in A64 */71#define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */72#define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */73#define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */74#define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */75#define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */76 77#define mmc_readl(host, reg) \78 readl((host)->reg_base + SDXC_##reg)79#define mmc_writel(host, reg, value) \80 writel((value), (host)->reg_base + SDXC_##reg)81 82/* global control register bits */83#define SDXC_SOFT_RESET BIT(0)84#define SDXC_FIFO_RESET BIT(1)85#define SDXC_DMA_RESET BIT(2)86#define SDXC_INTERRUPT_ENABLE_BIT BIT(4)87#define SDXC_DMA_ENABLE_BIT BIT(5)88#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)89#define SDXC_POSEDGE_LATCH_DATA BIT(9)90#define SDXC_DDR_MODE BIT(10)91#define SDXC_MEMORY_ACCESS_DONE BIT(29)92#define SDXC_ACCESS_DONE_DIRECT BIT(30)93#define SDXC_ACCESS_BY_AHB BIT(31)94#define SDXC_ACCESS_BY_DMA (0 << 31)95#define SDXC_HARDWARE_RESET \96 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)97 98/* clock control bits */99#define SDXC_MASK_DATA0 BIT(31)100#define SDXC_CARD_CLOCK_ON BIT(16)101#define SDXC_LOW_POWER_ON BIT(17)102 103/* bus width */104#define SDXC_WIDTH1 0105#define SDXC_WIDTH4 1106#define SDXC_WIDTH8 2107 108/* smc command bits */109#define SDXC_RESP_EXPIRE BIT(6)110#define SDXC_LONG_RESPONSE BIT(7)111#define SDXC_CHECK_RESPONSE_CRC BIT(8)112#define SDXC_DATA_EXPIRE BIT(9)113#define SDXC_WRITE BIT(10)114#define SDXC_SEQUENCE_MODE BIT(11)115#define SDXC_SEND_AUTO_STOP BIT(12)116#define SDXC_WAIT_PRE_OVER BIT(13)117#define SDXC_STOP_ABORT_CMD BIT(14)118#define SDXC_SEND_INIT_SEQUENCE BIT(15)119#define SDXC_UPCLK_ONLY BIT(21)120#define SDXC_READ_CEATA_DEV BIT(22)121#define SDXC_CCS_EXPIRE BIT(23)122#define SDXC_ENABLE_BIT_BOOT BIT(24)123#define SDXC_ALT_BOOT_OPTIONS BIT(25)124#define SDXC_BOOT_ACK_EXPIRE BIT(26)125#define SDXC_BOOT_ABORT BIT(27)126#define SDXC_VOLTAGE_SWITCH BIT(28)127#define SDXC_USE_HOLD_REGISTER BIT(29)128#define SDXC_START BIT(31)129 130/* interrupt bits */131#define SDXC_RESP_ERROR BIT(1)132#define SDXC_COMMAND_DONE BIT(2)133#define SDXC_DATA_OVER BIT(3)134#define SDXC_TX_DATA_REQUEST BIT(4)135#define SDXC_RX_DATA_REQUEST BIT(5)136#define SDXC_RESP_CRC_ERROR BIT(6)137#define SDXC_DATA_CRC_ERROR BIT(7)138#define SDXC_RESP_TIMEOUT BIT(8)139#define SDXC_DATA_TIMEOUT BIT(9)140#define SDXC_VOLTAGE_CHANGE_DONE BIT(10)141#define SDXC_FIFO_RUN_ERROR BIT(11)142#define SDXC_HARD_WARE_LOCKED BIT(12)143#define SDXC_START_BIT_ERROR BIT(13)144#define SDXC_AUTO_COMMAND_DONE BIT(14)145#define SDXC_END_BIT_ERROR BIT(15)146#define SDXC_SDIO_INTERRUPT BIT(16)147#define SDXC_CARD_INSERT BIT(30)148#define SDXC_CARD_REMOVE BIT(31)149#define SDXC_INTERRUPT_ERROR_BIT \150 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \151 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \152 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR)153#define SDXC_INTERRUPT_DONE_BIT \154 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \155 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)156 157/* status */158#define SDXC_RXWL_FLAG BIT(0)159#define SDXC_TXWL_FLAG BIT(1)160#define SDXC_FIFO_EMPTY BIT(2)161#define SDXC_FIFO_FULL BIT(3)162#define SDXC_CARD_PRESENT BIT(8)163#define SDXC_CARD_DATA_BUSY BIT(9)164#define SDXC_DATA_FSM_BUSY BIT(10)165#define SDXC_DMA_REQUEST BIT(31)166#define SDXC_FIFO_SIZE 16167 168/* Function select */169#define SDXC_CEATA_ON (0xceaa << 16)170#define SDXC_SEND_IRQ_RESPONSE BIT(0)171#define SDXC_SDIO_READ_WAIT BIT(1)172#define SDXC_ABORT_READ_DATA BIT(2)173#define SDXC_SEND_CCSD BIT(8)174#define SDXC_SEND_AUTO_STOPCCSD BIT(9)175#define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10)176 177/* IDMA controller bus mod bit field */178#define SDXC_IDMAC_SOFT_RESET BIT(0)179#define SDXC_IDMAC_FIX_BURST BIT(1)180#define SDXC_IDMAC_IDMA_ON BIT(7)181#define SDXC_IDMAC_REFETCH_DES BIT(31)182 183/* IDMA status bit field */184#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)185#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)186#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)187#define SDXC_IDMAC_DESTINATION_INVALID BIT(4)188#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)189#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)190#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)191#define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10)192#define SDXC_IDMAC_IDLE (0 << 13)193#define SDXC_IDMAC_SUSPEND (1 << 13)194#define SDXC_IDMAC_DESC_READ (2 << 13)195#define SDXC_IDMAC_DESC_CHECK (3 << 13)196#define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13)197#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13)198#define SDXC_IDMAC_READ (6 << 13)199#define SDXC_IDMAC_WRITE (7 << 13)200#define SDXC_IDMAC_DESC_CLOSE (8 << 13)201 202/*203* If the idma-des-size-bits of property is ie 13, bufsize bits are:204* Bits 0-12: buf1 size205* Bits 13-25: buf2 size206* Bits 26-31: not used207* Since we only ever set buf1 size, we can simply store it directly.208*/209#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */210#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */211#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */212#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */213#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */214#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */215#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */216 217#define SDXC_CLK_400K 0218#define SDXC_CLK_25M 1219#define SDXC_CLK_50M 2220#define SDXC_CLK_50M_DDR 3221#define SDXC_CLK_50M_DDR_8BIT 4222 223#define SDXC_2X_TIMING_MODE BIT(31)224 225#define SDXC_CAL_START BIT(15)226#define SDXC_CAL_DONE BIT(14)227#define SDXC_CAL_DL_SHIFT 8228#define SDXC_CAL_DL_SW_EN BIT(7)229#define SDXC_CAL_DL_SW_SHIFT 0230#define SDXC_CAL_DL_MASK 0x3f231 232#define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/233 234struct sunxi_mmc_clk_delay {235 u32 output;236 u32 sample;237};238 239struct sunxi_idma_des {240 __le32 config;241 __le32 buf_size;242 __le32 buf_addr_ptr1;243 __le32 buf_addr_ptr2;244};245 246struct sunxi_mmc_cfg {247 u32 idma_des_size_bits;248 u32 idma_des_shift;249 const struct sunxi_mmc_clk_delay *clk_delays;250 251 /* does the IP block support autocalibration? */252 bool can_calibrate;253 254 /* Does DATA0 needs to be masked while the clock is updated */255 bool mask_data0;256 257 /*258 * hardware only supports new timing mode, either due to lack of259 * a mode switch in the clock controller, or the mmc controller260 * is permanently configured in the new timing mode, without the261 * NTSR mode switch.262 */263 bool needs_new_timings;264 265 /* clock hardware can switch between old and new timing modes */266 bool ccu_has_timings_switch;267};268 269struct sunxi_mmc_host {270 struct device *dev;271 struct mmc_host *mmc;272 struct reset_control *reset;273 const struct sunxi_mmc_cfg *cfg;274 275 /* IO mapping base */276 void __iomem *reg_base;277 278 /* clock management */279 struct clk *clk_ahb;280 struct clk *clk_mmc;281 struct clk *clk_sample;282 struct clk *clk_output;283 284 /* irq */285 spinlock_t lock;286 int irq;287 u32 int_sum;288 u32 sdio_imask;289 290 /* dma */291 dma_addr_t sg_dma;292 void *sg_cpu;293 bool wait_dma;294 295 struct mmc_request *mrq;296 struct mmc_request *manual_stop_mrq;297 int ferror;298 299 /* vqmmc */300 bool vqmmc_enabled;301 302 /* timings */303 bool use_new_timings;304};305 306static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)307{308 unsigned long expire = jiffies + msecs_to_jiffies(250);309 u32 rval;310 311 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET);312 do {313 rval = mmc_readl(host, REG_GCTRL);314 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET));315 316 if (rval & SDXC_HARDWARE_RESET) {317 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n");318 return -EIO;319 }320 321 return 0;322}323 324static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)325{326 u32 rval;327 328 if (sunxi_mmc_reset_host(host))329 return -EIO;330 331 /*332 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8333 *334 * TODO: sun9i has a larger FIFO and supports higher trigger values335 */336 mmc_writel(host, REG_FTRGL, 0x20070008);337 /* Maximum timeout value */338 mmc_writel(host, REG_TMOUT, 0xffffffff);339 /* Unmask SDIO interrupt if needed */340 mmc_writel(host, REG_IMASK, host->sdio_imask);341 /* Clear all pending interrupts */342 mmc_writel(host, REG_RINTR, 0xffffffff);343 /* Debug register? undocumented */344 mmc_writel(host, REG_DBGC, 0xdeb);345 /* Enable CEATA support */346 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);347 /* Set DMA descriptor list base address */348 mmc_writel(host, REG_DLBA, host->sg_dma >> host->cfg->idma_des_shift);349 350 rval = mmc_readl(host, REG_GCTRL);351 rval |= SDXC_INTERRUPT_ENABLE_BIT;352 /* Undocumented, but found in Allwinner code */353 rval &= ~SDXC_ACCESS_DONE_DIRECT;354 mmc_writel(host, REG_GCTRL, rval);355 356 return 0;357}358 359static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,360 struct mmc_data *data)361{362 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;363 dma_addr_t next_desc = host->sg_dma;364 int i, max_len = (1 << host->cfg->idma_des_size_bits);365 366 for (i = 0; i < data->sg_len; i++) {367 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |368 SDXC_IDMAC_DES0_OWN |369 SDXC_IDMAC_DES0_DIC);370 371 if (data->sg[i].length == max_len)372 pdes[i].buf_size = 0; /* 0 == max_len */373 else374 pdes[i].buf_size = cpu_to_le32(data->sg[i].length);375 376 next_desc += sizeof(struct sunxi_idma_des);377 pdes[i].buf_addr_ptr1 =378 cpu_to_le32(sg_dma_address(&data->sg[i]) >>379 host->cfg->idma_des_shift);380 pdes[i].buf_addr_ptr2 =381 cpu_to_le32(next_desc >>382 host->cfg->idma_des_shift);383 }384 385 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);386 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD |387 SDXC_IDMAC_DES0_ER);388 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC);389 pdes[i - 1].buf_addr_ptr2 = 0;390 391 /*392 * Avoid the io-store starting the idmac hitting io-mem before the393 * descriptors hit the main-mem.394 */395 wmb();396}397 398static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host,399 struct mmc_data *data)400{401 u32 i, dma_len;402 struct scatterlist *sg;403 404 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,405 mmc_get_dma_dir(data));406 if (dma_len == 0) {407 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");408 return -ENOMEM;409 }410 411 for_each_sg(data->sg, sg, data->sg_len, i) {412 if (sg->offset & 3 || sg->length & 3) {413 dev_err(mmc_dev(host->mmc),414 "unaligned scatterlist: os %x length %d\n",415 sg->offset, sg->length);416 return -EINVAL;417 }418 }419 420 return 0;421}422 423static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host,424 struct mmc_data *data)425{426 u32 rval;427 428 sunxi_mmc_init_idma_des(host, data);429 430 rval = mmc_readl(host, REG_GCTRL);431 rval |= SDXC_DMA_ENABLE_BIT;432 mmc_writel(host, REG_GCTRL, rval);433 rval |= SDXC_DMA_RESET;434 mmc_writel(host, REG_GCTRL, rval);435 436 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);437 438 if (!(data->flags & MMC_DATA_WRITE))439 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);440 441 mmc_writel(host, REG_DMAC,442 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);443}444 445static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,446 struct mmc_request *req)447{448 u32 arg, cmd_val, ri;449 unsigned long expire = jiffies + msecs_to_jiffies(1000);450 451 cmd_val = SDXC_START | SDXC_RESP_EXPIRE |452 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC;453 454 if (req->cmd->opcode == SD_IO_RW_EXTENDED) {455 cmd_val |= SD_IO_RW_DIRECT;456 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |457 ((req->cmd->arg >> 28) & 0x7);458 } else {459 cmd_val |= MMC_STOP_TRANSMISSION;460 arg = 0;461 }462 463 mmc_writel(host, REG_CARG, arg);464 mmc_writel(host, REG_CMDR, cmd_val);465 466 do {467 ri = mmc_readl(host, REG_RINTR);468 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&469 time_before(jiffies, expire));470 471 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) {472 dev_err(mmc_dev(host->mmc), "send stop command failed\n");473 if (req->stop)474 req->stop->resp[0] = -ETIMEDOUT;475 } else {476 if (req->stop)477 req->stop->resp[0] = mmc_readl(host, REG_RESP0);478 }479 480 mmc_writel(host, REG_RINTR, 0xffff);481}482 483static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host)484{485 struct mmc_command *cmd = host->mrq->cmd;486 struct mmc_data *data = host->mrq->data;487 488 /* For some cmds timeout is normal with sd/mmc cards */489 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) ==490 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND ||491 cmd->opcode == SD_IO_RW_DIRECT))492 return;493 494 dev_dbg(mmc_dev(host->mmc),495 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",496 host->mmc->index, cmd->opcode,497 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",498 host->int_sum & SDXC_RESP_ERROR ? " RE" : "",499 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "",500 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",501 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "",502 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",503 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",504 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",505 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",506 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""507 );508}509 510/* Called in interrupt context! */511static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)512{513 struct mmc_request *mrq = host->mrq;514 struct mmc_data *data = mrq->data;515 u32 rval;516 517 mmc_writel(host, REG_IMASK, host->sdio_imask);518 mmc_writel(host, REG_IDIE, 0);519 520 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {521 sunxi_mmc_dump_errinfo(host);522 mrq->cmd->error = -ETIMEDOUT;523 524 if (data) {525 data->error = -ETIMEDOUT;526 host->manual_stop_mrq = mrq;527 }528 529 if (mrq->stop)530 mrq->stop->error = -ETIMEDOUT;531 } else {532 if (mrq->cmd->flags & MMC_RSP_136) {533 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3);534 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2);535 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1);536 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0);537 } else {538 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0);539 }540 541 if (data)542 data->bytes_xfered = data->blocks * data->blksz;543 }544 545 if (data) {546 mmc_writel(host, REG_IDST, 0x337);547 mmc_writel(host, REG_DMAC, 0);548 rval = mmc_readl(host, REG_GCTRL);549 rval |= SDXC_DMA_RESET;550 mmc_writel(host, REG_GCTRL, rval);551 rval &= ~SDXC_DMA_ENABLE_BIT;552 mmc_writel(host, REG_GCTRL, rval);553 rval |= SDXC_FIFO_RESET;554 mmc_writel(host, REG_GCTRL, rval);555 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,556 mmc_get_dma_dir(data));557 }558 559 mmc_writel(host, REG_RINTR, 0xffff);560 561 host->mrq = NULL;562 host->int_sum = 0;563 host->wait_dma = false;564 565 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED;566}567 568static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)569{570 struct sunxi_mmc_host *host = dev_id;571 struct mmc_request *mrq;572 u32 msk_int, idma_int;573 bool finalize = false;574 bool sdio_int = false;575 irqreturn_t ret = IRQ_HANDLED;576 577 spin_lock(&host->lock);578 579 idma_int = mmc_readl(host, REG_IDST);580 msk_int = mmc_readl(host, REG_MISTA);581 582 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",583 host->mrq, msk_int, idma_int);584 585 mrq = host->mrq;586 if (mrq) {587 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)588 host->wait_dma = false;589 590 host->int_sum |= msk_int;591 592 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */593 if ((host->int_sum & SDXC_RESP_TIMEOUT) &&594 !(host->int_sum & SDXC_COMMAND_DONE))595 mmc_writel(host, REG_IMASK,596 host->sdio_imask | SDXC_COMMAND_DONE);597 /* Don't wait for dma on error */598 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)599 finalize = true;600 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) &&601 !host->wait_dma)602 finalize = true;603 }604 605 if (msk_int & SDXC_SDIO_INTERRUPT)606 sdio_int = true;607 608 mmc_writel(host, REG_RINTR, msk_int);609 mmc_writel(host, REG_IDST, idma_int);610 611 if (finalize)612 ret = sunxi_mmc_finalize_request(host);613 614 spin_unlock(&host->lock);615 616 if (finalize && ret == IRQ_HANDLED)617 mmc_request_done(host->mmc, mrq);618 619 if (sdio_int)620 mmc_signal_sdio_irq(host->mmc);621 622 return ret;623}624 625static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id)626{627 struct sunxi_mmc_host *host = dev_id;628 struct mmc_request *mrq;629 unsigned long iflags;630 631 spin_lock_irqsave(&host->lock, iflags);632 mrq = host->manual_stop_mrq;633 spin_unlock_irqrestore(&host->lock, iflags);634 635 if (!mrq) {636 dev_err(mmc_dev(host->mmc), "no request for manual stop\n");637 return IRQ_HANDLED;638 }639 640 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n");641 642 /*643 * We will never have more than one outstanding request,644 * and we do not complete the request until after645 * we've cleared host->manual_stop_mrq so we do not need to646 * spin lock this function.647 * Additionally we have wait states within this function648 * so having it in a lock is a very bad idea.649 */650 sunxi_mmc_send_manual_stop(host, mrq);651 652 spin_lock_irqsave(&host->lock, iflags);653 host->manual_stop_mrq = NULL;654 spin_unlock_irqrestore(&host->lock, iflags);655 656 mmc_request_done(host->mmc, mrq);657 658 return IRQ_HANDLED;659}660 661static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)662{663 unsigned long expire = jiffies + msecs_to_jiffies(750);664 u32 rval;665 666 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n",667 oclk_en ? "en" : "dis");668 669 rval = mmc_readl(host, REG_CLKCR);670 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);671 672 if (oclk_en)673 rval |= SDXC_CARD_CLOCK_ON;674 if (host->cfg->mask_data0)675 rval |= SDXC_MASK_DATA0;676 677 mmc_writel(host, REG_CLKCR, rval);678 679 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;680 mmc_writel(host, REG_CMDR, rval);681 682 do {683 rval = mmc_readl(host, REG_CMDR);684 } while (time_before(jiffies, expire) && (rval & SDXC_START));685 686 /* clear irq status bits set by the command */687 mmc_writel(host, REG_RINTR,688 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);689 690 if (rval & SDXC_START) {691 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");692 return -EIO;693 }694 695 if (host->cfg->mask_data0) {696 rval = mmc_readl(host, REG_CLKCR);697 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);698 }699 700 return 0;701}702 703static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off)704{705 if (!host->cfg->can_calibrate)706 return 0;707 708 /*709 * FIXME:710 * This is not clear how the calibration is supposed to work711 * yet. The best rate have been obtained by simply setting the712 * delay to 0, as Allwinner does in its BSP.713 *714 * The only mode that doesn't have such a delay is HS400, that715 * is in itself a TODO.716 */717 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off);718 719 return 0;720}721 722static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,723 struct mmc_ios *ios, u32 rate)724{725 int index;726 727 /* clk controller delays not used under new timings mode */728 if (host->use_new_timings)729 return 0;730 731 /* some old controllers don't support delays */732 if (!host->cfg->clk_delays)733 return 0;734 735 /* determine delays */736 if (rate <= 400000) {737 index = SDXC_CLK_400K;738 } else if (rate <= 25000000) {739 index = SDXC_CLK_25M;740 } else if (rate <= 52000000) {741 if (ios->timing != MMC_TIMING_UHS_DDR50 &&742 ios->timing != MMC_TIMING_MMC_DDR52) {743 index = SDXC_CLK_50M;744 } else if (ios->bus_width == MMC_BUS_WIDTH_8) {745 index = SDXC_CLK_50M_DDR_8BIT;746 } else {747 index = SDXC_CLK_50M_DDR;748 }749 } else {750 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n");751 return -EINVAL;752 }753 754 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample);755 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output);756 757 return 0;758}759 760static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,761 struct mmc_ios *ios)762{763 struct mmc_host *mmc = host->mmc;764 long rate;765 u32 rval, clock = ios->clock, div = 1;766 int ret;767 768 ret = sunxi_mmc_oclk_onoff(host, 0);769 if (ret)770 return ret;771 772 /* Our clock is gated now */773 mmc->actual_clock = 0;774 775 if (!ios->clock)776 return 0;777 778 /*779 * Under the old timing mode, 8 bit DDR requires the module780 * clock to be double the card clock. Under the new timing781 * mode, all DDR modes require a doubled module clock.782 *783 * We currently only support the standard MMC DDR52 mode.784 * This block should be updated once support for other DDR785 * modes is added.786 */787 if (ios->timing == MMC_TIMING_MMC_DDR52 &&788 (host->use_new_timings ||789 ios->bus_width == MMC_BUS_WIDTH_8)) {790 div = 2;791 clock <<= 1;792 }793 794 if (host->use_new_timings && host->cfg->ccu_has_timings_switch) {795 ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);796 if (ret) {797 dev_err(mmc_dev(mmc),798 "error setting new timing mode\n");799 return ret;800 }801 }802 803 rate = clk_round_rate(host->clk_mmc, clock);804 if (rate < 0) {805 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",806 clock, rate);807 return rate;808 }809 dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n",810 clock, rate);811 812 /* setting clock rate */813 ret = clk_set_rate(host->clk_mmc, rate);814 if (ret) {815 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n",816 rate, ret);817 return ret;818 }819 820 /* set internal divider */821 rval = mmc_readl(host, REG_CLKCR);822 rval &= ~0xff;823 rval |= div - 1;824 mmc_writel(host, REG_CLKCR, rval);825 826 /* update card clock rate to account for internal divider */827 rate /= div;828 829 /*830 * Configure the controller to use the new timing mode if needed.831 * On controllers that only support the new timing mode, such as832 * the eMMC controller on the A64, this register does not exist,833 * and any writes to it are ignored.834 */835 if (host->use_new_timings) {836 /* Don't touch the delay bits */837 rval = mmc_readl(host, REG_SD_NTSR);838 rval |= SDXC_2X_TIMING_MODE;839 mmc_writel(host, REG_SD_NTSR, rval);840 }841 842 /* sunxi_mmc_clk_set_phase expects the actual card clock rate */843 ret = sunxi_mmc_clk_set_phase(host, ios, rate);844 if (ret)845 return ret;846 847 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG);848 if (ret)849 return ret;850 851 /*852 * FIXME:853 *854 * In HS400 we'll also need to calibrate the data strobe855 * signal. This should only happen on the MMC2 controller (at856 * least on the A64).857 */858 859 ret = sunxi_mmc_oclk_onoff(host, 1);860 if (ret)861 return ret;862 863 /* And we just enabled our clock back */864 mmc->actual_clock = rate;865 866 return 0;867}868 869static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host,870 unsigned char width)871{872 switch (width) {873 case MMC_BUS_WIDTH_1:874 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1);875 break;876 case MMC_BUS_WIDTH_4:877 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4);878 break;879 case MMC_BUS_WIDTH_8:880 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8);881 break;882 }883}884 885static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios)886{887 u32 rval;888 889 /* set ddr mode */890 rval = mmc_readl(host, REG_GCTRL);891 if (ios->timing == MMC_TIMING_UHS_DDR50 ||892 ios->timing == MMC_TIMING_MMC_DDR52)893 rval |= SDXC_DDR_MODE;894 else895 rval &= ~SDXC_DDR_MODE;896 mmc_writel(host, REG_GCTRL, rval);897 898 host->ferror = sunxi_mmc_clk_set_rate(host, ios);899 /* Android code had a usleep_range(50000, 55000); here */900}901 902static void sunxi_mmc_card_power(struct sunxi_mmc_host *host,903 struct mmc_ios *ios)904{905 struct mmc_host *mmc = host->mmc;906 907 switch (ios->power_mode) {908 case MMC_POWER_UP:909 dev_dbg(mmc_dev(mmc), "Powering card up\n");910 911 if (!IS_ERR(mmc->supply.vmmc)) {912 host->ferror = mmc_regulator_set_ocr(mmc,913 mmc->supply.vmmc,914 ios->vdd);915 if (host->ferror)916 return;917 }918 919 if (!IS_ERR(mmc->supply.vqmmc)) {920 host->ferror = regulator_enable(mmc->supply.vqmmc);921 if (host->ferror) {922 dev_err(mmc_dev(mmc),923 "failed to enable vqmmc\n");924 return;925 }926 host->vqmmc_enabled = true;927 }928 break;929 930 case MMC_POWER_OFF:931 dev_dbg(mmc_dev(mmc), "Powering card off\n");932 933 if (!IS_ERR(mmc->supply.vmmc))934 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);935 936 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled)937 regulator_disable(mmc->supply.vqmmc);938 939 host->vqmmc_enabled = false;940 break;941 942 default:943 dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n");944 break;945 }946}947 948static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)949{950 struct sunxi_mmc_host *host = mmc_priv(mmc);951 952 sunxi_mmc_card_power(host, ios);953 sunxi_mmc_set_bus_width(host, ios->bus_width);954 sunxi_mmc_set_clk(host, ios);955}956 957static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)958{959 int ret;960 961 /* vqmmc regulator is available */962 if (!IS_ERR(mmc->supply.vqmmc)) {963 ret = mmc_regulator_set_vqmmc(mmc, ios);964 return ret < 0 ? ret : 0;965 }966 967 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */968 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330)969 return 0;970 971 return -EINVAL;972}973 974static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)975{976 struct sunxi_mmc_host *host = mmc_priv(mmc);977 unsigned long flags;978 u32 imask;979 980 if (enable)981 pm_runtime_get_noresume(host->dev);982 983 spin_lock_irqsave(&host->lock, flags);984 985 imask = mmc_readl(host, REG_IMASK);986 if (enable) {987 host->sdio_imask = SDXC_SDIO_INTERRUPT;988 imask |= SDXC_SDIO_INTERRUPT;989 } else {990 host->sdio_imask = 0;991 imask &= ~SDXC_SDIO_INTERRUPT;992 }993 mmc_writel(host, REG_IMASK, imask);994 spin_unlock_irqrestore(&host->lock, flags);995 996 if (!enable)997 pm_runtime_put_noidle(host->mmc->parent);998}999 1000static void sunxi_mmc_hw_reset(struct mmc_host *mmc)1001{1002 struct sunxi_mmc_host *host = mmc_priv(mmc);1003 mmc_writel(host, REG_HWRST, 0);1004 udelay(10);1005 mmc_writel(host, REG_HWRST, 1);1006 udelay(300);1007}1008 1009static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)1010{1011 struct sunxi_mmc_host *host = mmc_priv(mmc);1012 struct mmc_command *cmd = mrq->cmd;1013 struct mmc_data *data = mrq->data;1014 unsigned long iflags;1015 u32 imask = SDXC_INTERRUPT_ERROR_BIT;1016 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);1017 bool wait_dma = host->wait_dma;1018 int ret;1019 1020 /* Check for set_ios errors (should never happen) */1021 if (host->ferror) {1022 mrq->cmd->error = host->ferror;1023 mmc_request_done(mmc, mrq);1024 return;1025 }1026 1027 if (data) {1028 ret = sunxi_mmc_map_dma(host, data);1029 if (ret < 0) {1030 dev_err(mmc_dev(mmc), "map DMA failed\n");1031 cmd->error = ret;1032 data->error = ret;1033 mmc_request_done(mmc, mrq);1034 return;1035 }1036 }1037 1038 if (cmd->opcode == MMC_GO_IDLE_STATE) {1039 cmd_val |= SDXC_SEND_INIT_SEQUENCE;1040 imask |= SDXC_COMMAND_DONE;1041 }1042 1043 if (cmd->flags & MMC_RSP_PRESENT) {1044 cmd_val |= SDXC_RESP_EXPIRE;1045 if (cmd->flags & MMC_RSP_136)1046 cmd_val |= SDXC_LONG_RESPONSE;1047 if (cmd->flags & MMC_RSP_CRC)1048 cmd_val |= SDXC_CHECK_RESPONSE_CRC;1049 1050 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {1051 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;1052 1053 if (cmd->data->stop) {1054 imask |= SDXC_AUTO_COMMAND_DONE;1055 cmd_val |= SDXC_SEND_AUTO_STOP;1056 } else {1057 imask |= SDXC_DATA_OVER;1058 }1059 1060 if (cmd->data->flags & MMC_DATA_WRITE)1061 cmd_val |= SDXC_WRITE;1062 else1063 wait_dma = true;1064 } else {1065 imask |= SDXC_COMMAND_DONE;1066 }1067 } else {1068 imask |= SDXC_COMMAND_DONE;1069 }1070 1071 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",1072 cmd_val & 0x3f, cmd_val, cmd->arg, imask,1073 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);1074 1075 spin_lock_irqsave(&host->lock, iflags);1076 1077 if (host->mrq || host->manual_stop_mrq) {1078 spin_unlock_irqrestore(&host->lock, iflags);1079 1080 if (data)1081 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,1082 mmc_get_dma_dir(data));1083 1084 dev_err(mmc_dev(mmc), "request already pending\n");1085 mrq->cmd->error = -EBUSY;1086 mmc_request_done(mmc, mrq);1087 return;1088 }1089 1090 if (data) {1091 mmc_writel(host, REG_BLKSZ, data->blksz);1092 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks);1093 sunxi_mmc_start_dma(host, data);1094 }1095 1096 host->mrq = mrq;1097 host->wait_dma = wait_dma;1098 mmc_writel(host, REG_IMASK, host->sdio_imask | imask);1099 mmc_writel(host, REG_CARG, cmd->arg);1100 mmc_writel(host, REG_CMDR, cmd_val);1101 1102 spin_unlock_irqrestore(&host->lock, iflags);1103}1104 1105static int sunxi_mmc_card_busy(struct mmc_host *mmc)1106{1107 struct sunxi_mmc_host *host = mmc_priv(mmc);1108 1109 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY);1110}1111 1112static const struct mmc_host_ops sunxi_mmc_ops = {1113 .request = sunxi_mmc_request,1114 .set_ios = sunxi_mmc_set_ios,1115 .get_ro = mmc_gpio_get_ro,1116 .get_cd = mmc_gpio_get_cd,1117 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,1118 .start_signal_voltage_switch = sunxi_mmc_volt_switch,1119 .card_hw_reset = sunxi_mmc_hw_reset,1120 .card_busy = sunxi_mmc_card_busy,1121};1122 1123static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {1124 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },1125 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },1126 [SDXC_CLK_50M] = { .output = 90, .sample = 120 },1127 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 },1128 /* Value from A83T "new timing mode". Works but might not be right. */1129 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 },1130};1131 1132static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {1133 [SDXC_CLK_400K] = { .output = 180, .sample = 180 },1134 [SDXC_CLK_25M] = { .output = 180, .sample = 75 },1135 [SDXC_CLK_50M] = { .output = 150, .sample = 120 },1136 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 },1137 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 },1138};1139 1140static const struct sunxi_mmc_cfg sun4i_a10_cfg = {1141 .idma_des_size_bits = 13,1142 .clk_delays = NULL,1143 .can_calibrate = false,1144};1145 1146static const struct sunxi_mmc_cfg sun5i_a13_cfg = {1147 .idma_des_size_bits = 16,1148 .clk_delays = NULL,1149 .can_calibrate = false,1150};1151 1152static const struct sunxi_mmc_cfg sun7i_a20_cfg = {1153 .idma_des_size_bits = 16,1154 .clk_delays = sunxi_mmc_clk_delays,1155 .can_calibrate = false,1156};1157 1158static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = {1159 .idma_des_size_bits = 16,1160 .clk_delays = sunxi_mmc_clk_delays,1161 .can_calibrate = false,1162 .ccu_has_timings_switch = true,1163};1164 1165static const struct sunxi_mmc_cfg sun9i_a80_cfg = {1166 .idma_des_size_bits = 16,1167 .clk_delays = sun9i_mmc_clk_delays,1168 .can_calibrate = false,1169};1170 1171static const struct sunxi_mmc_cfg sun20i_d1_cfg = {1172 .idma_des_size_bits = 13,1173 .idma_des_shift = 2,1174 .can_calibrate = true,1175 .mask_data0 = true,1176 .needs_new_timings = true,1177};1178 1179static const struct sunxi_mmc_cfg sun50i_a64_cfg = {1180 .idma_des_size_bits = 16,1181 .clk_delays = NULL,1182 .can_calibrate = true,1183 .mask_data0 = true,1184 .needs_new_timings = true,1185};1186 1187static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {1188 .idma_des_size_bits = 13,1189 .clk_delays = NULL,1190 .can_calibrate = true,1191 .needs_new_timings = true,1192};1193 1194static const struct sunxi_mmc_cfg sun50i_h616_cfg = {1195 .idma_des_size_bits = 16,1196 .idma_des_shift = 2,1197 .can_calibrate = true,1198 .mask_data0 = true,1199 .needs_new_timings = true,1200};1201 1202static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = {1203 .idma_des_size_bits = 13,1204 .idma_des_shift = 2,1205 .clk_delays = NULL,1206 .can_calibrate = true,1207 .needs_new_timings = true,1208};1209 1210static const struct of_device_id sunxi_mmc_of_match[] = {1211 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },1212 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },1213 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },1214 { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg },1215 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },1216 { .compatible = "allwinner,sun20i-d1-mmc", .data = &sun20i_d1_cfg },1217 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg },1218 { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },1219 { .compatible = "allwinner,sun50i-a100-mmc", .data = &sun20i_d1_cfg },1220 { .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },1221 { .compatible = "allwinner,sun50i-h616-mmc", .data = &sun50i_h616_cfg },1222 { /* sentinel */ }1223};1224MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);1225 1226static int sunxi_mmc_enable(struct sunxi_mmc_host *host)1227{1228 int ret;1229 1230 if (!IS_ERR(host->reset)) {1231 ret = reset_control_reset(host->reset);1232 if (ret) {1233 dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n",1234 ret);1235 return ret;1236 }1237 }1238 1239 ret = clk_prepare_enable(host->clk_ahb);1240 if (ret) {1241 dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret);1242 goto error_assert_reset;1243 }1244 1245 ret = clk_prepare_enable(host->clk_mmc);1246 if (ret) {1247 dev_err(host->dev, "Enable mmc clk err %d\n", ret);1248 goto error_disable_clk_ahb;1249 }1250 1251 ret = clk_prepare_enable(host->clk_output);1252 if (ret) {1253 dev_err(host->dev, "Enable output clk err %d\n", ret);1254 goto error_disable_clk_mmc;1255 }1256 1257 ret = clk_prepare_enable(host->clk_sample);1258 if (ret) {1259 dev_err(host->dev, "Enable sample clk err %d\n", ret);1260 goto error_disable_clk_output;1261 }1262 1263 /*1264 * Sometimes the controller asserts the irq on boot for some reason,1265 * make sure the controller is in a sane state before enabling irqs.1266 */1267 ret = sunxi_mmc_reset_host(host);1268 if (ret)1269 goto error_disable_clk_sample;1270 1271 return 0;1272 1273error_disable_clk_sample:1274 clk_disable_unprepare(host->clk_sample);1275error_disable_clk_output:1276 clk_disable_unprepare(host->clk_output);1277error_disable_clk_mmc:1278 clk_disable_unprepare(host->clk_mmc);1279error_disable_clk_ahb:1280 clk_disable_unprepare(host->clk_ahb);1281error_assert_reset:1282 if (!IS_ERR(host->reset))1283 reset_control_assert(host->reset);1284 return ret;1285}1286 1287static void sunxi_mmc_disable(struct sunxi_mmc_host *host)1288{1289 sunxi_mmc_reset_host(host);1290 1291 clk_disable_unprepare(host->clk_sample);1292 clk_disable_unprepare(host->clk_output);1293 clk_disable_unprepare(host->clk_mmc);1294 clk_disable_unprepare(host->clk_ahb);1295 1296 if (!IS_ERR(host->reset))1297 reset_control_assert(host->reset);1298}1299 1300static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,1301 struct platform_device *pdev)1302{1303 int ret;1304 1305 host->cfg = of_device_get_match_data(&pdev->dev);1306 if (!host->cfg)1307 return -EINVAL;1308 1309 ret = mmc_regulator_get_supply(host->mmc);1310 if (ret)1311 return ret;1312 1313 host->reg_base = devm_platform_ioremap_resource(pdev, 0);1314 if (IS_ERR(host->reg_base))1315 return PTR_ERR(host->reg_base);1316 1317 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");1318 if (IS_ERR(host->clk_ahb)) {1319 dev_err(&pdev->dev, "Could not get ahb clock\n");1320 return PTR_ERR(host->clk_ahb);1321 }1322 1323 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc");1324 if (IS_ERR(host->clk_mmc)) {1325 dev_err(&pdev->dev, "Could not get mmc clock\n");1326 return PTR_ERR(host->clk_mmc);1327 }1328 1329 if (host->cfg->clk_delays) {1330 host->clk_output = devm_clk_get(&pdev->dev, "output");1331 if (IS_ERR(host->clk_output)) {1332 dev_err(&pdev->dev, "Could not get output clock\n");1333 return PTR_ERR(host->clk_output);1334 }1335 1336 host->clk_sample = devm_clk_get(&pdev->dev, "sample");1337 if (IS_ERR(host->clk_sample)) {1338 dev_err(&pdev->dev, "Could not get sample clock\n");1339 return PTR_ERR(host->clk_sample);1340 }1341 }1342 1343 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,1344 "ahb");1345 if (PTR_ERR(host->reset) == -EPROBE_DEFER)1346 return PTR_ERR(host->reset);1347 1348 ret = sunxi_mmc_enable(host);1349 if (ret)1350 return ret;1351 1352 host->irq = platform_get_irq(pdev, 0);1353 if (host->irq < 0) {1354 ret = host->irq;1355 goto error_disable_mmc;1356 }1357 1358 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq,1359 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host);1360 1361error_disable_mmc:1362 sunxi_mmc_disable(host);1363 return ret;1364}1365 1366static int sunxi_mmc_probe(struct platform_device *pdev)1367{1368 struct sunxi_mmc_host *host;1369 struct mmc_host *mmc;1370 int ret;1371 1372 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);1373 if (!mmc) {1374 dev_err(&pdev->dev, "mmc alloc host failed\n");1375 return -ENOMEM;1376 }1377 platform_set_drvdata(pdev, mmc);1378 1379 host = mmc_priv(mmc);1380 host->dev = &pdev->dev;1381 host->mmc = mmc;1382 spin_lock_init(&host->lock);1383 1384 ret = sunxi_mmc_resource_request(host, pdev);1385 if (ret)1386 goto error_free_host;1387 1388 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,1389 &host->sg_dma, GFP_KERNEL);1390 if (!host->sg_cpu) {1391 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");1392 ret = -ENOMEM;1393 goto error_free_host;1394 }1395 1396 if (host->cfg->ccu_has_timings_switch) {1397 /*1398 * Supports both old and new timing modes.1399 * Try setting the clk to new timing mode.1400 */1401 sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);1402 1403 /* And check the result */1404 ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc);1405 if (ret < 0) {1406 /*1407 * For whatever reason we were not able to get1408 * the current active mode. Default to old mode.1409 */1410 dev_warn(&pdev->dev, "MMC clk timing mode unknown\n");1411 host->use_new_timings = false;1412 } else {1413 host->use_new_timings = !!ret;1414 }1415 } else if (host->cfg->needs_new_timings) {1416 /* Supports new timing mode only */1417 host->use_new_timings = true;1418 }1419 1420 mmc->ops = &sunxi_mmc_ops;1421 mmc->max_blk_count = 8192;1422 mmc->max_blk_size = 4096;1423 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);1424 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);1425 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;1426 /* 400kHz ~ 52MHz */1427 mmc->f_min = 400000;1428 mmc->f_max = 52000000;1429 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |1430 MMC_CAP_SDIO_IRQ;1431 1432 /*1433 * Some H5 devices do not have signal traces precise enough to1434 * use HS DDR mode for their eMMC chips.1435 *1436 * We still enable HS DDR modes for all the other controller1437 * variants that support them.1438 */1439 if ((host->cfg->clk_delays || host->use_new_timings) &&1440 !of_device_is_compatible(pdev->dev.of_node,1441 "allwinner,sun50i-h5-emmc"))1442 mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;1443 1444 ret = mmc_of_parse(mmc);1445 if (ret)1446 goto error_free_dma;1447 1448 /*1449 * If we don't support delay chains in the SoC, we can't use any1450 * of the higher speed modes. Mask them out in case the device1451 * tree specifies the properties for them, which gets added to1452 * the caps by mmc_of_parse() above.1453 */1454 if (!(host->cfg->clk_delays || host->use_new_timings)) {1455 mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR |1456 MMC_CAP_1_2V_DDR | MMC_CAP_UHS);1457 mmc->caps2 &= ~MMC_CAP2_HS200;1458 }1459 1460 /* TODO: This driver doesn't support HS400 mode yet */1461 mmc->caps2 &= ~MMC_CAP2_HS400;1462 1463 ret = sunxi_mmc_init_host(host);1464 if (ret)1465 goto error_free_dma;1466 1467 pm_runtime_set_active(&pdev->dev);1468 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);1469 pm_runtime_use_autosuspend(&pdev->dev);1470 pm_runtime_enable(&pdev->dev);1471 1472 ret = mmc_add_host(mmc);1473 if (ret)1474 goto error_free_dma;1475 1476 dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n",1477 mmc->max_req_size >> 10,1478 host->use_new_timings ? ", uses new timings mode" : "");1479 1480 return 0;1481 1482error_free_dma:1483 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);1484error_free_host:1485 mmc_free_host(mmc);1486 return ret;1487}1488 1489static void sunxi_mmc_remove(struct platform_device *pdev)1490{1491 struct mmc_host *mmc = platform_get_drvdata(pdev);1492 struct sunxi_mmc_host *host = mmc_priv(mmc);1493 1494 mmc_remove_host(mmc);1495 pm_runtime_disable(&pdev->dev);1496 if (!pm_runtime_status_suspended(&pdev->dev)) {1497 disable_irq(host->irq);1498 sunxi_mmc_disable(host);1499 }1500 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);1501 mmc_free_host(mmc);1502}1503 1504#ifdef CONFIG_PM1505static int sunxi_mmc_runtime_resume(struct device *dev)1506{1507 struct mmc_host *mmc = dev_get_drvdata(dev);1508 struct sunxi_mmc_host *host = mmc_priv(mmc);1509 int ret;1510 1511 ret = sunxi_mmc_enable(host);1512 if (ret)1513 return ret;1514 1515 sunxi_mmc_init_host(host);1516 sunxi_mmc_set_bus_width(host, mmc->ios.bus_width);1517 sunxi_mmc_set_clk(host, &mmc->ios);1518 enable_irq(host->irq);1519 1520 return 0;1521}1522 1523static int sunxi_mmc_runtime_suspend(struct device *dev)1524{1525 struct mmc_host *mmc = dev_get_drvdata(dev);1526 struct sunxi_mmc_host *host = mmc_priv(mmc);1527 1528 /*1529 * When clocks are off, it's possible receiving1530 * fake interrupts, which will stall the system.1531 * Disabling the irq will prevent this.1532 */1533 disable_irq(host->irq);1534 sunxi_mmc_reset_host(host);1535 sunxi_mmc_disable(host);1536 1537 return 0;1538}1539#endif1540 1541static const struct dev_pm_ops sunxi_mmc_pm_ops = {1542 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,1543 pm_runtime_force_resume)1544 SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend,1545 sunxi_mmc_runtime_resume,1546 NULL)1547};1548 1549static struct platform_driver sunxi_mmc_driver = {1550 .driver = {1551 .name = "sunxi-mmc",1552 .probe_type = PROBE_PREFER_ASYNCHRONOUS,1553 .of_match_table = sunxi_mmc_of_match,1554 .pm = &sunxi_mmc_pm_ops,1555 },1556 .probe = sunxi_mmc_probe,1557 .remove_new = sunxi_mmc_remove,1558};1559module_platform_driver(sunxi_mmc_driver);1560 1561MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");1562MODULE_LICENSE("GPL v2");1563MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>");1564MODULE_ALIAS("platform:sunxi-mmc");1565