173 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Toshiba PCI Secure Digital Host Controller Interface driver4 *5 * Copyright (C) 2014 Ondrej Zary6 * Copyright (C) 2007 Richard Betts, All Rights Reserved.7 *8 * Based on asic3_mmc.c Copyright (c) 2005 SDG Systems, LLC9 */10 11#define HCLK 33000000 /* 33 MHz (PCI clock) */12 13#define SD_PCICFG_CLKSTOP 0x40 /* 0x1f = clock controller, 0 = stop */14#define SD_PCICFG_GATEDCLK 0x41 /* Gated clock */15#define SD_PCICFG_CLKMODE 0x42 /* Control clock of SD controller */16#define SD_PCICFG_PINSTATUS 0x44 /* R/O: read status of SD pins */17#define SD_PCICFG_POWER1 0x4818#define SD_PCICFG_POWER2 0x4919#define SD_PCICFG_POWER3 0x4a20#define SD_PCICFG_CARDDETECT 0x4c21#define SD_PCICFG_SLOTS 0x50 /* R/O: define support slot number */22#define SD_PCICFG_EXTGATECLK1 0xf0 /* Could be used for gated clock */23#define SD_PCICFG_EXTGATECLK2 0xf1 /* Could be used for gated clock */24#define SD_PCICFG_EXTGATECLK3 0xf9 /* Bit 1: double buffer/single buffer */25#define SD_PCICFG_SDLED_ENABLE1 0xfa26#define SD_PCICFG_SDLED_ENABLE2 0xfe27 28#define SD_PCICFG_CLKMODE_DIV_DISABLE BIT(0)29#define SD_PCICFG_CLKSTOP_ENABLE_ALL 0x1f30#define SD_PCICFG_LED_ENABLE1_START 0x1231#define SD_PCICFG_LED_ENABLE2_START 0x8032 33#define SD_PCICFG_PWR1_33V 0x08 /* Set for 3.3 volts */34#define SD_PCICFG_PWR1_OFF 0x00 /* Turn off power */35#define SD_PCICFG_PWR2_AUTO 0x0236 37#define SD_CMD 0x00 /* also for SDIO */38#define SD_ARG0 0x04 /* also for SDIO */39#define SD_ARG1 0x06 /* also for SDIO */40#define SD_STOPINTERNAL 0x0841#define SD_BLOCKCOUNT 0x0a /* also for SDIO */42#define SD_RESPONSE0 0x0c /* also for SDIO */43#define SD_RESPONSE1 0x0e /* also for SDIO */44#define SD_RESPONSE2 0x10 /* also for SDIO */45#define SD_RESPONSE3 0x12 /* also for SDIO */46#define SD_RESPONSE4 0x14 /* also for SDIO */47#define SD_RESPONSE5 0x16 /* also for SDIO */48#define SD_RESPONSE6 0x18 /* also for SDIO */49#define SD_RESPONSE7 0x1a /* also for SDIO */50#define SD_CARDSTATUS 0x1c /* also for SDIO */51#define SD_BUFFERCTRL 0x1e /* also for SDIO */52#define SD_INTMASKCARD 0x20 /* also for SDIO */53#define SD_INTMASKBUFFER 0x22 /* also for SDIO */54#define SD_CARDCLOCKCTRL 0x2455#define SD_CARDXFERDATALEN 0x26 /* also for SDIO */56#define SD_CARDOPTIONSETUP 0x28 /* also for SDIO */57#define SD_ERRORSTATUS0 0x2c /* also for SDIO */58#define SD_ERRORSTATUS1 0x2e /* also for SDIO */59#define SD_DATAPORT 0x30 /* also for SDIO */60#define SD_TRANSACTIONCTRL 0x34 /* also for SDIO */61#define SD_SOFTWARERESET 0xe0 /* also for SDIO */62 63/* registers above marked "also for SDIO" and all SDIO registers below can be64 * accessed at SDIO_BASE + reg address */65#define SDIO_BASE 0x10066 67#define SDIO_CARDPORTSEL 0x0268#define SDIO_CARDINTCTRL 0x3669#define SDIO_CLOCKNWAITCTRL 0x3870#define SDIO_HOSTINFORMATION 0x3a71#define SDIO_ERRORCTRL 0x3c72#define SDIO_LEDCTRL 0x3e73 74#define SD_TRANSCTL_SET BIT(8)75 76#define SD_CARDCLK_DIV_DISABLE BIT(15)77#define SD_CARDCLK_ENABLE_CLOCK BIT(8)78#define SD_CARDCLK_CLK_DIV_512 BIT(7)79#define SD_CARDCLK_CLK_DIV_256 BIT(6)80#define SD_CARDCLK_CLK_DIV_128 BIT(5)81#define SD_CARDCLK_CLK_DIV_64 BIT(4)82#define SD_CARDCLK_CLK_DIV_32 BIT(3)83#define SD_CARDCLK_CLK_DIV_16 BIT(2)84#define SD_CARDCLK_CLK_DIV_8 BIT(1)85#define SD_CARDCLK_CLK_DIV_4 BIT(0)86#define SD_CARDCLK_CLK_DIV_2 087 88#define SD_CARDOPT_REQUIRED 0x000e89#define SD_CARDOPT_DATA_RESP_TIMEOUT(x) (((x) & 0x0f) << 4) /* 4 bits */90#define SD_CARDOPT_C2_MODULE_ABSENT BIT(14)91#define SD_CARDOPT_DATA_XFR_WIDTH_1 (1 << 15)92#define SD_CARDOPT_DATA_XFR_WIDTH_4 (0 << 15)93 94#define SD_CMD_TYPE_CMD (0 << 6)95#define SD_CMD_TYPE_ACMD (1 << 6)96#define SD_CMD_TYPE_AUTHEN (2 << 6)97#define SD_CMD_RESP_TYPE_NONE (3 << 8)98#define SD_CMD_RESP_TYPE_EXT_R1 (4 << 8)99#define SD_CMD_RESP_TYPE_EXT_R1B (5 << 8)100#define SD_CMD_RESP_TYPE_EXT_R2 (6 << 8)101#define SD_CMD_RESP_TYPE_EXT_R3 (7 << 8)102#define SD_CMD_RESP_TYPE_EXT_R6 (4 << 8)103#define SD_CMD_RESP_TYPE_EXT_R7 (4 << 8)104#define SD_CMD_DATA_PRESENT BIT(11)105#define SD_CMD_TRANSFER_READ BIT(12)106#define SD_CMD_MULTI_BLOCK BIT(13)107#define SD_CMD_SECURITY_CMD BIT(14)108 109#define SD_STOPINT_ISSUE_CMD12 BIT(0)110#define SD_STOPINT_AUTO_ISSUE_CMD12 BIT(8)111 112#define SD_CARD_RESP_END BIT(0)113#define SD_CARD_RW_END BIT(2)114#define SD_CARD_CARD_REMOVED_0 BIT(3)115#define SD_CARD_CARD_INSERTED_0 BIT(4)116#define SD_CARD_PRESENT_0 BIT(5)117#define SD_CARD_UNK6 BIT(6)118#define SD_CARD_WRITE_PROTECT BIT(7)119#define SD_CARD_CARD_REMOVED_3 BIT(8)120#define SD_CARD_CARD_INSERTED_3 BIT(9)121#define SD_CARD_PRESENT_3 BIT(10)122 123#define SD_BUF_CMD_INDEX_ERR BIT(16)124#define SD_BUF_CRC_ERR BIT(17)125#define SD_BUF_STOP_BIT_END_ERR BIT(18)126#define SD_BUF_DATA_TIMEOUT BIT(19)127#define SD_BUF_OVERFLOW BIT(20)128#define SD_BUF_UNDERFLOW BIT(21)129#define SD_BUF_CMD_TIMEOUT BIT(22)130#define SD_BUF_UNK7 BIT(23)131#define SD_BUF_READ_ENABLE BIT(24)132#define SD_BUF_WRITE_ENABLE BIT(25)133#define SD_BUF_ILLEGAL_FUNCTION BIT(29)134#define SD_BUF_CMD_BUSY BIT(30)135#define SD_BUF_ILLEGAL_ACCESS BIT(31)136 137#define SD_ERR0_RESP_CMD_ERR BIT(0)138#define SD_ERR0_RESP_NON_CMD12_END_BIT_ERR BIT(2)139#define SD_ERR0_RESP_CMD12_END_BIT_ERR BIT(3)140#define SD_ERR0_READ_DATA_END_BIT_ERR BIT(4)141#define SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR BIT(5)142#define SD_ERR0_RESP_NON_CMD12_CRC_ERR BIT(8)143#define SD_ERR0_RESP_CMD12_CRC_ERR BIT(9)144#define SD_ERR0_READ_DATA_CRC_ERR BIT(10)145#define SD_ERR0_WRITE_CMD_CRC_ERR BIT(11)146 147#define SD_ERR1_NO_CMD_RESP BIT(16)148#define SD_ERR1_TIMEOUT_READ_DATA BIT(20)149#define SD_ERR1_TIMEOUT_CRS_STATUS BIT(21)150#define SD_ERR1_TIMEOUT_CRC_BUSY BIT(22)151 152#define IRQ_DONT_CARE_BITS (SD_CARD_PRESENT_3 \153 | SD_CARD_WRITE_PROTECT \154 | SD_CARD_UNK6 \155 | SD_CARD_PRESENT_0 \156 | SD_BUF_UNK7 \157 | SD_BUF_CMD_BUSY)158 159struct toshsd_host {160 struct pci_dev *pdev;161 struct mmc_host *mmc;162 163 spinlock_t lock;164 165 struct mmc_request *mrq;/* Current request */166 struct mmc_command *cmd;/* Current command */167 struct mmc_data *data; /* Current data request */168 169 struct sg_mapping_iter sg_miter; /* for PIO */170 171 void __iomem *ioaddr; /* mapped address */172};173