182 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * linux/drivers/mmc/host/wbsd.h - Winbond W83L51xD SD/MMC driver4 *5 * Copyright (C) 2004-2007 Pierre Ossman, All Rights Reserved.6 */7 8#define LOCK_CODE 0xAA9 10#define WBSD_CONF_SWRST 0x0211#define WBSD_CONF_DEVICE 0x0712#define WBSD_CONF_ID_HI 0x2013#define WBSD_CONF_ID_LO 0x2114#define WBSD_CONF_POWER 0x2215#define WBSD_CONF_PME 0x2316#define WBSD_CONF_PMES 0x2417 18#define WBSD_CONF_ENABLE 0x3019#define WBSD_CONF_PORT_HI 0x6020#define WBSD_CONF_PORT_LO 0x6121#define WBSD_CONF_IRQ 0x7022#define WBSD_CONF_DRQ 0x7423 24#define WBSD_CONF_PINS 0xF025 26#define DEVICE_SD 0x0327 28#define WBSD_PINS_DAT3_HI 0x2029#define WBSD_PINS_DAT3_OUT 0x1030#define WBSD_PINS_GP11_HI 0x0431#define WBSD_PINS_DETECT_GP11 0x0232#define WBSD_PINS_DETECT_DAT3 0x0133 34#define WBSD_CMDR 0x0035#define WBSD_DFR 0x0136#define WBSD_EIR 0x0237#define WBSD_ISR 0x0338#define WBSD_FSR 0x0439#define WBSD_IDXR 0x0540#define WBSD_DATAR 0x0641#define WBSD_CSR 0x0742 43#define WBSD_EINT_CARD 0x4044#define WBSD_EINT_FIFO_THRE 0x2045#define WBSD_EINT_CRC 0x1046#define WBSD_EINT_TIMEOUT 0x0847#define WBSD_EINT_PROGEND 0x0448#define WBSD_EINT_BUSYEND 0x0249#define WBSD_EINT_TC 0x0150 51#define WBSD_INT_PENDING 0x8052#define WBSD_INT_CARD 0x4053#define WBSD_INT_FIFO_THRE 0x2054#define WBSD_INT_CRC 0x1055#define WBSD_INT_TIMEOUT 0x0856#define WBSD_INT_PROGEND 0x0457#define WBSD_INT_BUSYEND 0x0258#define WBSD_INT_TC 0x0159 60#define WBSD_FIFO_EMPTY 0x8061#define WBSD_FIFO_FULL 0x4062#define WBSD_FIFO_EMTHRE 0x2063#define WBSD_FIFO_FUTHRE 0x1064#define WBSD_FIFO_SZMASK 0x0F65 66#define WBSD_MSLED 0x2067#define WBSD_POWER_N 0x1068#define WBSD_WRPT 0x0469#define WBSD_CARDPRESENT 0x0170 71#define WBSD_IDX_CLK 0x0172#define WBSD_IDX_PBSMSB 0x0273#define WBSD_IDX_TAAC 0x0374#define WBSD_IDX_NSAC 0x0475#define WBSD_IDX_PBSLSB 0x0576#define WBSD_IDX_SETUP 0x0677#define WBSD_IDX_DMA 0x0778#define WBSD_IDX_FIFOEN 0x0879#define WBSD_IDX_STATUS 0x1080#define WBSD_IDX_RSPLEN 0x1E81#define WBSD_IDX_RESP0 0x1F82#define WBSD_IDX_RESP1 0x2083#define WBSD_IDX_RESP2 0x2184#define WBSD_IDX_RESP3 0x2285#define WBSD_IDX_RESP4 0x2386#define WBSD_IDX_RESP5 0x2487#define WBSD_IDX_RESP6 0x2588#define WBSD_IDX_RESP7 0x2689#define WBSD_IDX_RESP8 0x2790#define WBSD_IDX_RESP9 0x2891#define WBSD_IDX_RESP10 0x2992#define WBSD_IDX_RESP11 0x2A93#define WBSD_IDX_RESP12 0x2B94#define WBSD_IDX_RESP13 0x2C95#define WBSD_IDX_RESP14 0x2D96#define WBSD_IDX_RESP15 0x2E97#define WBSD_IDX_RESP16 0x2F98#define WBSD_IDX_CRCSTATUS 0x3099#define WBSD_IDX_ISR 0x3F100 101#define WBSD_CLK_375K 0x00102#define WBSD_CLK_12M 0x01103#define WBSD_CLK_16M 0x02104#define WBSD_CLK_24M 0x03105 106#define WBSD_DATA_WIDTH 0x01107 108#define WBSD_DAT3_H 0x08109#define WBSD_FIFO_RESET 0x04110#define WBSD_SOFT_RESET 0x02111#define WBSD_INC_INDEX 0x01112 113#define WBSD_DMA_SINGLE 0x02114#define WBSD_DMA_ENABLE 0x01115 116#define WBSD_FIFOEN_EMPTY 0x20117#define WBSD_FIFOEN_FULL 0x10118#define WBSD_FIFO_THREMASK 0x0F119 120#define WBSD_BLOCK_READ 0x80121#define WBSD_BLOCK_WRITE 0x40122#define WBSD_BUSY 0x20123#define WBSD_CARDTRAFFIC 0x04124#define WBSD_SENDCMD 0x02125#define WBSD_RECVRES 0x01126 127#define WBSD_RSP_SHORT 0x00128#define WBSD_RSP_LONG 0x01129 130#define WBSD_CRC_MASK 0x1F131#define WBSD_CRC_OK 0x05 /* S010E (00101) */132#define WBSD_CRC_FAIL 0x0B /* S101E (01011) */133 134#define WBSD_DMA_SIZE 65536135 136struct wbsd_host137{138 struct mmc_host* mmc; /* MMC structure */139 140 spinlock_t lock; /* Mutex */141 142 int flags; /* Driver states */143 144#define WBSD_FCARD_PRESENT (1<<0) /* Card is present */145#define WBSD_FIGNORE_DETECT (1<<1) /* Ignore card detection */146 147 struct mmc_request* mrq; /* Current request */148 149 u8 isr; /* Accumulated ISR */150 151 struct scatterlist* cur_sg; /* Current SG entry */152 unsigned int num_sg; /* Number of entries left */153 154 unsigned int offset; /* Offset into current entry */155 unsigned int remain; /* Data left in curren entry */156 157 char* dma_buffer; /* ISA DMA buffer */158 dma_addr_t dma_addr; /* Physical address for same */159 160 int firsterr; /* See fifo functions */161 162 u8 clk; /* Current clock speed */163 unsigned char bus_width; /* Current bus width */164 165 int config; /* Config port */166 u8 unlock_code; /* Code to unlock config */167 168 int chip_id; /* ID of controller */169 170 int base; /* I/O port base */171 int irq; /* Interrupt */172 int dma; /* DMA channel */173 174 struct work_struct card_bh_work; /* Work structures */175 struct work_struct fifo_bh_work;176 struct work_struct crc_bh_work;177 struct work_struct timeout_bh_work;178 struct work_struct finish_bh_work;179 180 struct timer_list ignore_timer; /* Ignore detection timer */181};182