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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * amd76xrom.c4 *5 * Normal mappings of chips in physical memory6 */7 8#include <linux/module.h>9#include <linux/types.h>10#include <linux/kernel.h>11#include <linux/init.h>12#include <linux/slab.h>13#include <asm/io.h>14#include <linux/mtd/mtd.h>15#include <linux/mtd/map.h>16#include <linux/mtd/cfi.h>17#include <linux/mtd/flashchip.h>18#include <linux/pci.h>19#include <linux/pci_ids.h>20#include <linux/list.h>21 22 23#define xstr(s) str(s)24#define str(s) #s25#define MOD_NAME xstr(KBUILD_BASENAME)26 27#define ADDRESS_NAME_LEN 1828 29#define ROM_PROBE_STEP_SIZE (64*1024) /* 64KiB */30 31struct amd76xrom_window {32 void __iomem *virt;33 unsigned long phys;34 unsigned long size;35 struct list_head maps;36 struct resource rsrc;37 struct pci_dev *pdev;38};39 40struct amd76xrom_map_info {41 struct list_head list;42 struct map_info map;43 struct mtd_info *mtd;44 struct resource rsrc;45 char map_name[sizeof(MOD_NAME) + 2 + ADDRESS_NAME_LEN];46};47 48/* The 2 bits controlling the window size are often set to allow reading49 * the BIOS, but too small to allow writing, since the lock registers are50 * 4MiB lower in the address space than the data.51 *52 * This is intended to prevent flashing the bios, perhaps accidentally.53 *54 * This parameter allows the normal driver to over-ride the BIOS settings.55 *56 * The bits are 6 and 7. If both bits are set, it is a 5MiB window.57 * If only the 7 Bit is set, it is a 4MiB window. Otherwise, a58 * 64KiB window.59 *60 */61static uint win_size_bits;62module_param(win_size_bits, uint, 0);63MODULE_PARM_DESC(win_size_bits, "ROM window size bits override for 0x43 byte, normally set by BIOS.");64 65static struct amd76xrom_window amd76xrom_window = {66 .maps = LIST_HEAD_INIT(amd76xrom_window.maps),67};68 69static void amd76xrom_cleanup(struct amd76xrom_window *window)70{71 struct amd76xrom_map_info *map, *scratch;72 u8 byte;73 74 if (window->pdev) {75 /* Disable writes through the rom window */76 pci_read_config_byte(window->pdev, 0x40, &byte);77 pci_write_config_byte(window->pdev, 0x40, byte & ~1);78 pci_dev_put(window->pdev);79 }80 81 /* Free all of the mtd devices */82 list_for_each_entry_safe(map, scratch, &window->maps, list) {83 if (map->rsrc.parent) {84 release_resource(&map->rsrc);85 }86 mtd_device_unregister(map->mtd);87 map_destroy(map->mtd);88 list_del(&map->list);89 kfree(map);90 }91 if (window->rsrc.parent)92 release_resource(&window->rsrc);93 94 if (window->virt) {95 iounmap(window->virt);96 window->virt = NULL;97 window->phys = 0;98 window->size = 0;99 window->pdev = NULL;100 }101}102 103 104static int amd76xrom_init_one(struct pci_dev *pdev,105 const struct pci_device_id *ent)106{107 static char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL };108 u8 byte;109 struct amd76xrom_window *window = &amd76xrom_window;110 struct amd76xrom_map_info *map = NULL;111 unsigned long map_top;112 113 /* Remember the pci dev I find the window in - already have a ref */114 window->pdev = pdev;115 116 /* Enable the selected rom window. This is often incorrectly117 * set up by the BIOS, and the 4MiB offset for the lock registers118 * requires the full 5MiB of window space.119 *120 * This 'write, then read' approach leaves the bits for121 * other uses of the hardware info.122 */123 pci_read_config_byte(pdev, 0x43, &byte);124 pci_write_config_byte(pdev, 0x43, byte | win_size_bits );125 126 /* Assume the rom window is properly setup, and find it's size */127 pci_read_config_byte(pdev, 0x43, &byte);128 if ((byte & ((1<<7)|(1<<6))) == ((1<<7)|(1<<6))) {129 window->phys = 0xffb00000; /* 5MiB */130 }131 else if ((byte & (1<<7)) == (1<<7)) {132 window->phys = 0xffc00000; /* 4MiB */133 }134 else {135 window->phys = 0xffff0000; /* 64KiB */136 }137 window->size = 0xffffffffUL - window->phys + 1UL;138 139 /*140 * Try to reserve the window mem region. If this fails then141 * it is likely due to a fragment of the window being142 * "reserved" by the BIOS. In the case that the143 * request_mem_region() fails then once the rom size is144 * discovered we will try to reserve the unreserved fragment.145 */146 window->rsrc.name = MOD_NAME;147 window->rsrc.start = window->phys;148 window->rsrc.end = window->phys + window->size - 1;149 window->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;150 if (request_resource(&iomem_resource, &window->rsrc)) {151 window->rsrc.parent = NULL;152 printk(KERN_ERR MOD_NAME153 " %s(): Unable to register resource %pR - kernel bug?\n",154 __func__, &window->rsrc);155 return -EBUSY;156 }157 158 159 /* Enable writes through the rom window */160 pci_read_config_byte(pdev, 0x40, &byte);161 pci_write_config_byte(pdev, 0x40, byte | 1);162 163 /* FIXME handle registers 0x80 - 0x8C the bios region locks */164 165 /* For write accesses caches are useless */166 window->virt = ioremap(window->phys, window->size);167 if (!window->virt) {168 printk(KERN_ERR MOD_NAME ": ioremap(%08lx, %08lx) failed\n",169 window->phys, window->size);170 goto out;171 }172 173 /* Get the first address to look for an rom chip at */174 map_top = window->phys;175#if 1176 /* The probe sequence run over the firmware hub lock177 * registers sets them to 0x7 (no access).178 * Probe at most the last 4M of the address space.179 */180 if (map_top < 0xffc00000) {181 map_top = 0xffc00000;182 }183#endif184 /* Loop through and look for rom chips */185 while((map_top - 1) < 0xffffffffUL) {186 struct cfi_private *cfi;187 unsigned long offset;188 int i;189 190 if (!map) {191 map = kmalloc(sizeof(*map), GFP_KERNEL);192 if (!map)193 goto out;194 }195 memset(map, 0, sizeof(*map));196 INIT_LIST_HEAD(&map->list);197 map->map.name = map->map_name;198 map->map.phys = map_top;199 offset = map_top - window->phys;200 map->map.virt = (void __iomem *)201 (((unsigned long)(window->virt)) + offset);202 map->map.size = 0xffffffffUL - map_top + 1UL;203 /* Set the name of the map to the address I am trying */204 sprintf(map->map_name, "%s @%08Lx",205 MOD_NAME, (unsigned long long)map->map.phys);206 207 /* There is no generic VPP support */208 for(map->map.bankwidth = 32; map->map.bankwidth;209 map->map.bankwidth >>= 1)210 {211 char **probe_type;212 /* Skip bankwidths that are not supported */213 if (!map_bankwidth_supported(map->map.bankwidth))214 continue;215 216 /* Setup the map methods */217 simple_map_init(&map->map);218 219 /* Try all of the probe methods */220 probe_type = rom_probe_types;221 for(; *probe_type; probe_type++) {222 map->mtd = do_map_probe(*probe_type, &map->map);223 if (map->mtd)224 goto found;225 }226 }227 map_top += ROM_PROBE_STEP_SIZE;228 continue;229 found:230 /* Trim the size if we are larger than the map */231 if (map->mtd->size > map->map.size) {232 printk(KERN_WARNING MOD_NAME233 " rom(%llu) larger than window(%lu). fixing...\n",234 (unsigned long long)map->mtd->size, map->map.size);235 map->mtd->size = map->map.size;236 }237 if (window->rsrc.parent) {238 /*239 * Registering the MTD device in iomem may not be possible240 * if there is a BIOS "reserved" and BUSY range. If this241 * fails then continue anyway.242 */243 map->rsrc.name = map->map_name;244 map->rsrc.start = map->map.phys;245 map->rsrc.end = map->map.phys + map->mtd->size - 1;246 map->rsrc.flags = IORESOURCE_MEM | IORESOURCE_BUSY;247 if (request_resource(&window->rsrc, &map->rsrc)) {248 printk(KERN_ERR MOD_NAME249 ": cannot reserve MTD resource\n");250 map->rsrc.parent = NULL;251 }252 }253 254 /* Make the whole region visible in the map */255 map->map.virt = window->virt;256 map->map.phys = window->phys;257 cfi = map->map.fldrv_priv;258 for(i = 0; i < cfi->numchips; i++) {259 cfi->chips[i].start += offset;260 }261 262 /* Now that the mtd devices is complete claim and export it */263 map->mtd->owner = THIS_MODULE;264 if (mtd_device_register(map->mtd, NULL, 0)) {265 map_destroy(map->mtd);266 map->mtd = NULL;267 goto out;268 }269 270 271 /* Calculate the new value of map_top */272 map_top += map->mtd->size;273 274 /* File away the map structure */275 list_add(&map->list, &window->maps);276 map = NULL;277 }278 279 out:280 /* Free any left over map structures */281 kfree(map);282 /* See if I have any map structures */283 if (list_empty(&window->maps)) {284 amd76xrom_cleanup(window);285 return -ENODEV;286 }287 return 0;288}289 290 291static void amd76xrom_remove_one(struct pci_dev *pdev)292{293 struct amd76xrom_window *window = &amd76xrom_window;294 295 amd76xrom_cleanup(window);296}297 298static const struct pci_device_id amd76xrom_pci_tbl[] = {299 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410,300 PCI_ANY_ID, PCI_ANY_ID, },301 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7440,302 PCI_ANY_ID, PCI_ANY_ID, },303 { PCI_VENDOR_ID_AMD, 0x7468 }, /* amd8111 support */304 { 0, }305};306 307MODULE_DEVICE_TABLE(pci, amd76xrom_pci_tbl);308 309#if 0310static struct pci_driver amd76xrom_driver = {311 .name = MOD_NAME,312 .id_table = amd76xrom_pci_tbl,313 .probe = amd76xrom_init_one,314 .remove = amd76xrom_remove_one,315};316#endif317 318static int __init init_amd76xrom(void)319{320 struct pci_dev *pdev;321 const struct pci_device_id *id;322 pdev = NULL;323 for(id = amd76xrom_pci_tbl; id->vendor; id++) {324 pdev = pci_get_device(id->vendor, id->device, NULL);325 if (pdev) {326 break;327 }328 }329 if (pdev) {330 return amd76xrom_init_one(pdev, &amd76xrom_pci_tbl[0]);331 }332 return -ENXIO;333#if 0334 return pci_register_driver(&amd76xrom_driver);335#endif336}337 338static void __exit cleanup_amd76xrom(void)339{340 amd76xrom_remove_one(amd76xrom_window.pdev);341}342 343module_init(init_amd76xrom);344module_exit(cleanup_amd76xrom);345 346MODULE_LICENSE("GPL");347MODULE_AUTHOR("Eric Biederman <ebiederman@lnxi.com>");348MODULE_DESCRIPTION("MTD map driver for BIOS chips on the AMD76X southbridge");349