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1// SPDX-License-Identifier: GPL-2.02/*3 * Arasan NAND Flash Controller Driver4 *5 * Copyright (C) 2014 - 2020 Xilinx, Inc.6 * Author:7 * Miquel Raynal <miquel.raynal@bootlin.com>8 * Original work (fully rewritten):9 * Punnaiah Choudary Kalluri <punnaia@xilinx.com>10 * Naga Sureshkumar Relli <nagasure@xilinx.com>11 */12 13#include <linux/bch.h>14#include <linux/bitfield.h>15#include <linux/clk.h>16#include <linux/delay.h>17#include <linux/dma-mapping.h>18#include <linux/gpio/consumer.h>19#include <linux/interrupt.h>20#include <linux/iopoll.h>21#include <linux/module.h>22#include <linux/mtd/mtd.h>23#include <linux/mtd/partitions.h>24#include <linux/mtd/rawnand.h>25#include <linux/of.h>26#include <linux/platform_device.h>27#include <linux/slab.h>28 29#define PKT_REG 0x0030#define PKT_SIZE(x) FIELD_PREP(GENMASK(10, 0), (x))31#define PKT_STEPS(x) FIELD_PREP(GENMASK(23, 12), (x))32 33#define MEM_ADDR1_REG 0x0434 35#define MEM_ADDR2_REG 0x0836#define ADDR2_STRENGTH(x) FIELD_PREP(GENMASK(27, 25), (x))37#define ADDR2_CS(x) FIELD_PREP(GENMASK(31, 30), (x))38 39#define CMD_REG 0x0C40#define CMD_1(x) FIELD_PREP(GENMASK(7, 0), (x))41#define CMD_2(x) FIELD_PREP(GENMASK(15, 8), (x))42#define CMD_PAGE_SIZE(x) FIELD_PREP(GENMASK(25, 23), (x))43#define CMD_DMA_ENABLE BIT(27)44#define CMD_NADDRS(x) FIELD_PREP(GENMASK(30, 28), (x))45#define CMD_ECC_ENABLE BIT(31)46 47#define PROG_REG 0x1048#define PROG_PGRD BIT(0)49#define PROG_ERASE BIT(2)50#define PROG_STATUS BIT(3)51#define PROG_PGPROG BIT(4)52#define PROG_RDID BIT(6)53#define PROG_RDPARAM BIT(7)54#define PROG_RST BIT(8)55#define PROG_GET_FEATURE BIT(9)56#define PROG_SET_FEATURE BIT(10)57#define PROG_CHG_RD_COL_ENH BIT(14)58 59#define INTR_STS_EN_REG 0x1460#define INTR_SIG_EN_REG 0x1861#define INTR_STS_REG 0x1C62#define WRITE_READY BIT(0)63#define READ_READY BIT(1)64#define XFER_COMPLETE BIT(2)65#define DMA_BOUNDARY BIT(6)66#define EVENT_MASK GENMASK(7, 0)67 68#define READY_STS_REG 0x2069 70#define DMA_ADDR0_REG 0x5071#define DMA_ADDR1_REG 0x2472 73#define FLASH_STS_REG 0x2874 75#define TIMING_REG 0x2C76#define TCCS_TIME_500NS 077#define TCCS_TIME_300NS 378#define TCCS_TIME_200NS 279#define TCCS_TIME_100NS 180#define FAST_TCAD BIT(2)81#define DQS_BUFF_SEL_IN(x) FIELD_PREP(GENMASK(6, 3), (x))82#define DQS_BUFF_SEL_OUT(x) FIELD_PREP(GENMASK(18, 15), (x))83 84#define DATA_PORT_REG 0x3085 86#define ECC_CONF_REG 0x3487#define ECC_CONF_COL(x) FIELD_PREP(GENMASK(15, 0), (x))88#define ECC_CONF_LEN(x) FIELD_PREP(GENMASK(26, 16), (x))89#define ECC_CONF_BCH_EN BIT(27)90 91#define ECC_ERR_CNT_REG 0x3892#define GET_PKT_ERR_CNT(x) FIELD_GET(GENMASK(7, 0), (x))93#define GET_PAGE_ERR_CNT(x) FIELD_GET(GENMASK(16, 8), (x))94 95#define ECC_SP_REG 0x3C96#define ECC_SP_CMD1(x) FIELD_PREP(GENMASK(7, 0), (x))97#define ECC_SP_CMD2(x) FIELD_PREP(GENMASK(15, 8), (x))98#define ECC_SP_ADDRS(x) FIELD_PREP(GENMASK(30, 28), (x))99 100#define ECC_1ERR_CNT_REG 0x40101#define ECC_2ERR_CNT_REG 0x44102 103#define DATA_INTERFACE_REG 0x6C104#define DIFACE_SDR_MODE(x) FIELD_PREP(GENMASK(2, 0), (x))105#define DIFACE_DDR_MODE(x) FIELD_PREP(GENMASK(5, 3), (x))106#define DIFACE_SDR 0107#define DIFACE_NVDDR BIT(9)108 109#define ANFC_MAX_CS 2110#define ANFC_DFLT_TIMEOUT_US 1000000111#define ANFC_MAX_CHUNK_SIZE SZ_1M112#define ANFC_MAX_PARAM_SIZE SZ_4K113#define ANFC_MAX_STEPS SZ_2K114#define ANFC_MAX_PKT_SIZE (SZ_2K - 1)115#define ANFC_MAX_ADDR_CYC 5U116#define ANFC_RSVD_ECC_BYTES 21117 118#define ANFC_XLNX_SDR_DFLT_CORE_CLK 100000000119#define ANFC_XLNX_SDR_HS_CORE_CLK 80000000120 121static struct gpio_desc *anfc_default_cs_array[2] = {NULL, NULL};122 123/**124 * struct anfc_op - Defines how to execute an operation125 * @pkt_reg: Packet register126 * @addr1_reg: Memory address 1 register127 * @addr2_reg: Memory address 2 register128 * @cmd_reg: Command register129 * @prog_reg: Program register130 * @steps: Number of "packets" to read/write131 * @rdy_timeout_ms: Timeout for waits on Ready/Busy pin132 * @len: Data transfer length133 * @read: Data transfer direction from the controller point of view134 * @buf: Data buffer135 */136struct anfc_op {137 u32 pkt_reg;138 u32 addr1_reg;139 u32 addr2_reg;140 u32 cmd_reg;141 u32 prog_reg;142 int steps;143 unsigned int rdy_timeout_ms;144 unsigned int len;145 bool read;146 u8 *buf;147};148 149/**150 * struct anand - Defines the NAND chip related information151 * @node: Used to store NAND chips into a list152 * @chip: NAND chip information structure153 * @rb: Ready-busy line154 * @page_sz: Register value of the page_sz field to use155 * @clk: Expected clock frequency to use156 * @data_iface: Data interface timing mode to use157 * @timings: NV-DDR specific timings to use158 * @ecc_conf: Hardware ECC configuration value159 * @strength: Register value of the ECC strength160 * @raddr_cycles: Row address cycle information161 * @caddr_cycles: Column address cycle information162 * @ecc_bits: Exact number of ECC bits per syndrome163 * @ecc_total: Total number of ECC bytes164 * @errloc: Array of errors located with soft BCH165 * @hw_ecc: Buffer to store syndromes computed by hardware166 * @bch: BCH structure167 * @cs_idx: Array of chip-select for this device, values are indexes168 * of the controller structure @gpio_cs array169 * @ncs_idx: Size of the @cs_idx array170 */171struct anand {172 struct list_head node;173 struct nand_chip chip;174 unsigned int rb;175 unsigned int page_sz;176 unsigned long clk;177 u32 data_iface;178 u32 timings;179 u32 ecc_conf;180 u32 strength;181 u16 raddr_cycles;182 u16 caddr_cycles;183 unsigned int ecc_bits;184 unsigned int ecc_total;185 unsigned int *errloc;186 u8 *hw_ecc;187 struct bch_control *bch;188 int *cs_idx;189 int ncs_idx;190};191 192/**193 * struct arasan_nfc - Defines the Arasan NAND flash controller driver instance194 * @dev: Pointer to the device structure195 * @base: Remapped register area196 * @controller_clk: Pointer to the system clock197 * @bus_clk: Pointer to the flash clock198 * @controller: Base controller structure199 * @chips: List of all NAND chips attached to the controller200 * @cur_clk: Current clock rate201 * @cs_array: CS array. Native CS are left empty, the other cells are202 * populated with their corresponding GPIO descriptor.203 * @ncs: Size of @cs_array204 * @cur_cs: Index in @cs_array of the currently in use CS205 * @native_cs: Currently selected native CS206 * @spare_cs: Native CS that is not wired (may be selected when a GPIO207 * CS is in use)208 */209struct arasan_nfc {210 struct device *dev;211 void __iomem *base;212 struct clk *controller_clk;213 struct clk *bus_clk;214 struct nand_controller controller;215 struct list_head chips;216 unsigned int cur_clk;217 struct gpio_desc **cs_array;218 unsigned int ncs;219 int cur_cs;220 unsigned int native_cs;221 unsigned int spare_cs;222};223 224static struct anand *to_anand(struct nand_chip *nand)225{226 return container_of(nand, struct anand, chip);227}228 229static struct arasan_nfc *to_anfc(struct nand_controller *ctrl)230{231 return container_of(ctrl, struct arasan_nfc, controller);232}233 234static int anfc_wait_for_event(struct arasan_nfc *nfc, unsigned int event)235{236 u32 val;237 int ret;238 239 ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val,240 val & event, 0,241 ANFC_DFLT_TIMEOUT_US);242 if (ret) {243 dev_err(nfc->dev, "Timeout waiting for event 0x%x\n", event);244 return -ETIMEDOUT;245 }246 247 writel_relaxed(event, nfc->base + INTR_STS_REG);248 249 return 0;250}251 252static int anfc_wait_for_rb(struct arasan_nfc *nfc, struct nand_chip *chip,253 unsigned int timeout_ms)254{255 struct anand *anand = to_anand(chip);256 u32 val;257 int ret;258 259 /* There is no R/B interrupt, we must poll a register */260 ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val,261 val & BIT(anand->rb),262 1, timeout_ms * 1000);263 if (ret) {264 dev_err(nfc->dev, "Timeout waiting for R/B 0x%x\n",265 readl_relaxed(nfc->base + READY_STS_REG));266 return -ETIMEDOUT;267 }268 269 return 0;270}271 272static void anfc_trigger_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)273{274 writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG);275 writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG);276 writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG);277 writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG);278 writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG);279}280 281static int anfc_pkt_len_config(unsigned int len, unsigned int *steps,282 unsigned int *pktsize)283{284 unsigned int nb, sz;285 286 for (nb = 1; nb < ANFC_MAX_STEPS; nb *= 2) {287 sz = len / nb;288 if (sz <= ANFC_MAX_PKT_SIZE)289 break;290 }291 292 if (sz * nb != len)293 return -ENOTSUPP;294 295 if (steps)296 *steps = nb;297 298 if (pktsize)299 *pktsize = sz;300 301 return 0;302}303 304static bool anfc_is_gpio_cs(struct arasan_nfc *nfc, int nfc_cs)305{306 return nfc_cs >= 0 && nfc->cs_array[nfc_cs];307}308 309static int anfc_relative_to_absolute_cs(struct anand *anand, int num)310{311 return anand->cs_idx[num];312}313 314static void anfc_assert_cs(struct arasan_nfc *nfc, unsigned int nfc_cs_idx)315{316 /* CS did not change: do nothing */317 if (nfc->cur_cs == nfc_cs_idx)318 return;319 320 /* Deassert the previous CS if it was a GPIO */321 if (anfc_is_gpio_cs(nfc, nfc->cur_cs))322 gpiod_set_value_cansleep(nfc->cs_array[nfc->cur_cs], 1);323 324 /* Assert the new one */325 if (anfc_is_gpio_cs(nfc, nfc_cs_idx)) {326 nfc->native_cs = nfc->spare_cs;327 gpiod_set_value_cansleep(nfc->cs_array[nfc_cs_idx], 0);328 } else {329 nfc->native_cs = nfc_cs_idx;330 }331 332 nfc->cur_cs = nfc_cs_idx;333}334 335static int anfc_select_target(struct nand_chip *chip, int target)336{337 struct anand *anand = to_anand(chip);338 struct arasan_nfc *nfc = to_anfc(chip->controller);339 unsigned int nfc_cs_idx = anfc_relative_to_absolute_cs(anand, target);340 int ret;341 342 anfc_assert_cs(nfc, nfc_cs_idx);343 344 /* Update the controller timings and the potential ECC configuration */345 writel_relaxed(anand->data_iface, nfc->base + DATA_INTERFACE_REG);346 writel_relaxed(anand->timings, nfc->base + TIMING_REG);347 348 /* Update clock frequency */349 if (nfc->cur_clk != anand->clk) {350 clk_disable_unprepare(nfc->bus_clk);351 ret = clk_set_rate(nfc->bus_clk, anand->clk);352 if (ret) {353 dev_err(nfc->dev, "Failed to change clock rate\n");354 return ret;355 }356 357 ret = clk_prepare_enable(nfc->bus_clk);358 if (ret) {359 dev_err(nfc->dev,360 "Failed to re-enable the bus clock\n");361 return ret;362 }363 364 nfc->cur_clk = anand->clk;365 }366 367 return 0;368}369 370/*371 * When using the embedded hardware ECC engine, the controller is in charge of372 * feeding the engine with, first, the ECC residue present in the data array.373 * A typical read operation is:374 * 1/ Assert the read operation by sending the relevant command/address cycles375 * but targeting the column of the first ECC bytes in the OOB area instead of376 * the main data directly.377 * 2/ After having read the relevant number of ECC bytes, the controller uses378 * the RNDOUT/RNDSTART commands which are set into the "ECC Spare Command379 * Register" to move the pointer back at the beginning of the main data.380 * 3/ It will read the content of the main area for a given size (pktsize) and381 * will feed the ECC engine with this buffer again.382 * 4/ The ECC engine derives the ECC bytes for the given data and compare them383 * with the ones already received. It eventually trigger status flags and384 * then set the "Buffer Read Ready" flag.385 * 5/ The corrected data is then available for reading from the data port386 * register.387 *388 * The hardware BCH ECC engine is known to be inconstent in BCH mode and never389 * reports uncorrectable errors. Because of this bug, we have to use the390 * software BCH implementation in the read path.391 */392static int anfc_read_page_hw_ecc(struct nand_chip *chip, u8 *buf,393 int oob_required, int page)394{395 struct arasan_nfc *nfc = to_anfc(chip->controller);396 struct mtd_info *mtd = nand_to_mtd(chip);397 struct anand *anand = to_anand(chip);398 unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0);399 unsigned int max_bitflips = 0;400 dma_addr_t dma_addr;401 int step, ret;402 struct anfc_op nfc_op = {403 .pkt_reg =404 PKT_SIZE(chip->ecc.size) |405 PKT_STEPS(chip->ecc.steps),406 .addr1_reg =407 (page & 0xFF) << (8 * (anand->caddr_cycles)) |408 (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))),409 .addr2_reg =410 ((page >> 16) & 0xFF) |411 ADDR2_STRENGTH(anand->strength) |412 ADDR2_CS(nfc->native_cs),413 .cmd_reg =414 CMD_1(NAND_CMD_READ0) |415 CMD_2(NAND_CMD_READSTART) |416 CMD_PAGE_SIZE(anand->page_sz) |417 CMD_DMA_ENABLE |418 CMD_NADDRS(anand->caddr_cycles +419 anand->raddr_cycles),420 .prog_reg = PROG_PGRD,421 };422 423 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_FROM_DEVICE);424 if (dma_mapping_error(nfc->dev, dma_addr)) {425 dev_err(nfc->dev, "Buffer mapping error");426 return -EIO;427 }428 429 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);430 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);431 432 anfc_trigger_op(nfc, &nfc_op);433 434 ret = anfc_wait_for_event(nfc, XFER_COMPLETE);435 dma_unmap_single(nfc->dev, dma_addr, len, DMA_FROM_DEVICE);436 if (ret) {437 dev_err(nfc->dev, "Error reading page %d\n", page);438 return ret;439 }440 441 /* Store the raw OOB bytes as well */442 ret = nand_change_read_column_op(chip, mtd->writesize, chip->oob_poi,443 mtd->oobsize, 0);444 if (ret)445 return ret;446 447 /*448 * For each step, compute by softare the BCH syndrome over the raw data.449 * Compare the theoretical amount of errors and compare with the450 * hardware engine feedback.451 */452 for (step = 0; step < chip->ecc.steps; step++) {453 u8 *raw_buf = &buf[step * chip->ecc.size];454 unsigned int bit, byte;455 int bf, i;456 457 /* Extract the syndrome, it is not necessarily aligned */458 memset(anand->hw_ecc, 0, chip->ecc.bytes);459 nand_extract_bits(anand->hw_ecc, 0,460 &chip->oob_poi[mtd->oobsize - anand->ecc_total],461 anand->ecc_bits * step, anand->ecc_bits);462 463 bf = bch_decode(anand->bch, raw_buf, chip->ecc.size,464 anand->hw_ecc, NULL, NULL, anand->errloc);465 if (!bf) {466 continue;467 } else if (bf > 0) {468 for (i = 0; i < bf; i++) {469 /* Only correct the data, not the syndrome */470 if (anand->errloc[i] < (chip->ecc.size * 8)) {471 bit = BIT(anand->errloc[i] & 7);472 byte = anand->errloc[i] >> 3;473 raw_buf[byte] ^= bit;474 }475 }476 477 mtd->ecc_stats.corrected += bf;478 max_bitflips = max_t(unsigned int, max_bitflips, bf);479 480 continue;481 }482 483 bf = nand_check_erased_ecc_chunk(raw_buf, chip->ecc.size,484 anand->hw_ecc, chip->ecc.bytes, NULL, 0,485 chip->ecc.strength);486 if (bf > 0) {487 mtd->ecc_stats.corrected += bf;488 max_bitflips = max_t(unsigned int, max_bitflips, bf);489 memset(raw_buf, 0xFF, chip->ecc.size);490 } else if (bf < 0) {491 mtd->ecc_stats.failed++;492 }493 }494 495 return 0;496}497 498static int anfc_sel_read_page_hw_ecc(struct nand_chip *chip, u8 *buf,499 int oob_required, int page)500{501 int ret;502 503 ret = anfc_select_target(chip, chip->cur_cs);504 if (ret)505 return ret;506 507 return anfc_read_page_hw_ecc(chip, buf, oob_required, page);508};509 510static int anfc_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf,511 int oob_required, int page)512{513 struct anand *anand = to_anand(chip);514 struct arasan_nfc *nfc = to_anfc(chip->controller);515 struct mtd_info *mtd = nand_to_mtd(chip);516 unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0);517 dma_addr_t dma_addr;518 u8 status;519 int ret;520 struct anfc_op nfc_op = {521 .pkt_reg =522 PKT_SIZE(chip->ecc.size) |523 PKT_STEPS(chip->ecc.steps),524 .addr1_reg =525 (page & 0xFF) << (8 * (anand->caddr_cycles)) |526 (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))),527 .addr2_reg =528 ((page >> 16) & 0xFF) |529 ADDR2_STRENGTH(anand->strength) |530 ADDR2_CS(nfc->native_cs),531 .cmd_reg =532 CMD_1(NAND_CMD_SEQIN) |533 CMD_2(NAND_CMD_PAGEPROG) |534 CMD_PAGE_SIZE(anand->page_sz) |535 CMD_DMA_ENABLE |536 CMD_NADDRS(anand->caddr_cycles +537 anand->raddr_cycles) |538 CMD_ECC_ENABLE,539 .prog_reg = PROG_PGPROG,540 };541 542 writel_relaxed(anand->ecc_conf, nfc->base + ECC_CONF_REG);543 writel_relaxed(ECC_SP_CMD1(NAND_CMD_RNDIN) |544 ECC_SP_ADDRS(anand->caddr_cycles),545 nfc->base + ECC_SP_REG);546 547 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_TO_DEVICE);548 if (dma_mapping_error(nfc->dev, dma_addr)) {549 dev_err(nfc->dev, "Buffer mapping error");550 return -EIO;551 }552 553 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);554 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG);555 556 anfc_trigger_op(nfc, &nfc_op);557 ret = anfc_wait_for_event(nfc, XFER_COMPLETE);558 dma_unmap_single(nfc->dev, dma_addr, len, DMA_TO_DEVICE);559 if (ret) {560 dev_err(nfc->dev, "Error writing page %d\n", page);561 return ret;562 }563 564 /* Spare data is not protected */565 if (oob_required) {566 ret = nand_write_oob_std(chip, page);567 if (ret)568 return ret;569 }570 571 /* Check write status on the chip side */572 ret = nand_status_op(chip, &status);573 if (ret)574 return ret;575 576 if (status & NAND_STATUS_FAIL)577 return -EIO;578 579 return 0;580}581 582static int anfc_sel_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf,583 int oob_required, int page)584{585 int ret;586 587 ret = anfc_select_target(chip, chip->cur_cs);588 if (ret)589 return ret;590 591 return anfc_write_page_hw_ecc(chip, buf, oob_required, page);592};593 594/* NAND framework ->exec_op() hooks and related helpers */595static int anfc_parse_instructions(struct nand_chip *chip,596 const struct nand_subop *subop,597 struct anfc_op *nfc_op)598{599 struct arasan_nfc *nfc = to_anfc(chip->controller);600 struct anand *anand = to_anand(chip);601 const struct nand_op_instr *instr = NULL;602 bool first_cmd = true;603 unsigned int op_id;604 int ret, i;605 606 memset(nfc_op, 0, sizeof(*nfc_op));607 nfc_op->addr2_reg = ADDR2_CS(nfc->native_cs);608 nfc_op->cmd_reg = CMD_PAGE_SIZE(anand->page_sz);609 610 for (op_id = 0; op_id < subop->ninstrs; op_id++) {611 unsigned int offset, naddrs, pktsize;612 const u8 *addrs;613 u8 *buf;614 615 instr = &subop->instrs[op_id];616 617 switch (instr->type) {618 case NAND_OP_CMD_INSTR:619 if (first_cmd)620 nfc_op->cmd_reg |= CMD_1(instr->ctx.cmd.opcode);621 else622 nfc_op->cmd_reg |= CMD_2(instr->ctx.cmd.opcode);623 624 first_cmd = false;625 break;626 627 case NAND_OP_ADDR_INSTR:628 offset = nand_subop_get_addr_start_off(subop, op_id);629 naddrs = nand_subop_get_num_addr_cyc(subop, op_id);630 addrs = &instr->ctx.addr.addrs[offset];631 nfc_op->cmd_reg |= CMD_NADDRS(naddrs);632 633 for (i = 0; i < min(ANFC_MAX_ADDR_CYC, naddrs); i++) {634 if (i < 4)635 nfc_op->addr1_reg |= (u32)addrs[i] << i * 8;636 else637 nfc_op->addr2_reg |= addrs[i];638 }639 640 break;641 case NAND_OP_DATA_IN_INSTR:642 nfc_op->read = true;643 fallthrough;644 case NAND_OP_DATA_OUT_INSTR:645 offset = nand_subop_get_data_start_off(subop, op_id);646 buf = instr->ctx.data.buf.in;647 nfc_op->buf = &buf[offset];648 nfc_op->len = nand_subop_get_data_len(subop, op_id);649 ret = anfc_pkt_len_config(nfc_op->len, &nfc_op->steps,650 &pktsize);651 if (ret)652 return ret;653 654 /*655 * Number of DATA cycles must be aligned on 4, this656 * means the controller might read/write more than657 * requested. This is harmless most of the time as extra658 * DATA are discarded in the write path and read pointer659 * adjusted in the read path.660 *661 * FIXME: The core should mark operations where662 * reading/writing more is allowed so the exec_op()663 * implementation can take the right decision when the664 * alignment constraint is not met: adjust the number of665 * DATA cycles when it's allowed, reject the operation666 * otherwise.667 */668 nfc_op->pkt_reg |= PKT_SIZE(round_up(pktsize, 4)) |669 PKT_STEPS(nfc_op->steps);670 break;671 case NAND_OP_WAITRDY_INSTR:672 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms;673 break;674 }675 }676 677 return 0;678}679 680static int anfc_rw_pio_op(struct arasan_nfc *nfc, struct anfc_op *nfc_op)681{682 unsigned int dwords = (nfc_op->len / 4) / nfc_op->steps;683 unsigned int last_len = nfc_op->len % 4;684 unsigned int offset, dir;685 u8 *buf = nfc_op->buf;686 int ret, i;687 688 for (i = 0; i < nfc_op->steps; i++) {689 dir = nfc_op->read ? READ_READY : WRITE_READY;690 ret = anfc_wait_for_event(nfc, dir);691 if (ret) {692 dev_err(nfc->dev, "PIO %s ready signal not received\n",693 nfc_op->read ? "Read" : "Write");694 return ret;695 }696 697 offset = i * (dwords * 4);698 if (nfc_op->read)699 ioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset],700 dwords);701 else702 iowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset],703 dwords);704 }705 706 if (last_len) {707 u32 remainder;708 709 offset = nfc_op->len - last_len;710 711 if (nfc_op->read) {712 remainder = readl_relaxed(nfc->base + DATA_PORT_REG);713 memcpy(&buf[offset], &remainder, last_len);714 } else {715 memcpy(&remainder, &buf[offset], last_len);716 writel_relaxed(remainder, nfc->base + DATA_PORT_REG);717 }718 }719 720 return anfc_wait_for_event(nfc, XFER_COMPLETE);721}722 723static int anfc_misc_data_type_exec(struct nand_chip *chip,724 const struct nand_subop *subop,725 u32 prog_reg)726{727 struct arasan_nfc *nfc = to_anfc(chip->controller);728 struct anfc_op nfc_op = {};729 int ret;730 731 ret = anfc_parse_instructions(chip, subop, &nfc_op);732 if (ret)733 return ret;734 735 nfc_op.prog_reg = prog_reg;736 anfc_trigger_op(nfc, &nfc_op);737 738 if (nfc_op.rdy_timeout_ms) {739 ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);740 if (ret)741 return ret;742 }743 744 return anfc_rw_pio_op(nfc, &nfc_op);745}746 747static int anfc_param_read_type_exec(struct nand_chip *chip,748 const struct nand_subop *subop)749{750 return anfc_misc_data_type_exec(chip, subop, PROG_RDPARAM);751}752 753static int anfc_data_read_type_exec(struct nand_chip *chip,754 const struct nand_subop *subop)755{756 u32 prog_reg = PROG_PGRD;757 758 /*759 * Experience shows that while in SDR mode sending a CHANGE READ COLUMN760 * command through the READ PAGE "type" always works fine, when in761 * NV-DDR mode the same command simply fails. However, it was also762 * spotted that any CHANGE READ COLUMN command sent through the CHANGE763 * READ COLUMN ENHANCED "type" would correctly work in both cases (SDR764 * and NV-DDR). So, for simplicity, let's program the controller with765 * the CHANGE READ COLUMN ENHANCED "type" whenever we are requested to766 * perform a CHANGE READ COLUMN operation.767 */768 if (subop->instrs[0].ctx.cmd.opcode == NAND_CMD_RNDOUT &&769 subop->instrs[2].ctx.cmd.opcode == NAND_CMD_RNDOUTSTART)770 prog_reg = PROG_CHG_RD_COL_ENH;771 772 return anfc_misc_data_type_exec(chip, subop, prog_reg);773}774 775static int anfc_param_write_type_exec(struct nand_chip *chip,776 const struct nand_subop *subop)777{778 return anfc_misc_data_type_exec(chip, subop, PROG_SET_FEATURE);779}780 781static int anfc_data_write_type_exec(struct nand_chip *chip,782 const struct nand_subop *subop)783{784 return anfc_misc_data_type_exec(chip, subop, PROG_PGPROG);785}786 787static int anfc_misc_zerolen_type_exec(struct nand_chip *chip,788 const struct nand_subop *subop,789 u32 prog_reg)790{791 struct arasan_nfc *nfc = to_anfc(chip->controller);792 struct anfc_op nfc_op = {};793 int ret;794 795 ret = anfc_parse_instructions(chip, subop, &nfc_op);796 if (ret)797 return ret;798 799 nfc_op.prog_reg = prog_reg;800 anfc_trigger_op(nfc, &nfc_op);801 802 ret = anfc_wait_for_event(nfc, XFER_COMPLETE);803 if (ret)804 return ret;805 806 if (nfc_op.rdy_timeout_ms)807 ret = anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);808 809 return ret;810}811 812static int anfc_status_type_exec(struct nand_chip *chip,813 const struct nand_subop *subop)814{815 struct arasan_nfc *nfc = to_anfc(chip->controller);816 u32 tmp;817 int ret;818 819 /* See anfc_check_op() for details about this constraint */820 if (subop->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS)821 return -ENOTSUPP;822 823 ret = anfc_misc_zerolen_type_exec(chip, subop, PROG_STATUS);824 if (ret)825 return ret;826 827 tmp = readl_relaxed(nfc->base + FLASH_STS_REG);828 memcpy(subop->instrs[1].ctx.data.buf.in, &tmp, 1);829 830 return 0;831}832 833static int anfc_reset_type_exec(struct nand_chip *chip,834 const struct nand_subop *subop)835{836 return anfc_misc_zerolen_type_exec(chip, subop, PROG_RST);837}838 839static int anfc_erase_type_exec(struct nand_chip *chip,840 const struct nand_subop *subop)841{842 return anfc_misc_zerolen_type_exec(chip, subop, PROG_ERASE);843}844 845static int anfc_wait_type_exec(struct nand_chip *chip,846 const struct nand_subop *subop)847{848 struct arasan_nfc *nfc = to_anfc(chip->controller);849 struct anfc_op nfc_op = {};850 int ret;851 852 ret = anfc_parse_instructions(chip, subop, &nfc_op);853 if (ret)854 return ret;855 856 return anfc_wait_for_rb(nfc, chip, nfc_op.rdy_timeout_ms);857}858 859static const struct nand_op_parser anfc_op_parser = NAND_OP_PARSER(860 NAND_OP_PARSER_PATTERN(861 anfc_param_read_type_exec,862 NAND_OP_PARSER_PAT_CMD_ELEM(false),863 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),864 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),865 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, ANFC_MAX_CHUNK_SIZE)),866 NAND_OP_PARSER_PATTERN(867 anfc_param_write_type_exec,868 NAND_OP_PARSER_PAT_CMD_ELEM(false),869 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),870 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, ANFC_MAX_PARAM_SIZE)),871 NAND_OP_PARSER_PATTERN(872 anfc_data_read_type_exec,873 NAND_OP_PARSER_PAT_CMD_ELEM(false),874 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),875 NAND_OP_PARSER_PAT_CMD_ELEM(false),876 NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),877 NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, ANFC_MAX_CHUNK_SIZE)),878 NAND_OP_PARSER_PATTERN(879 anfc_data_write_type_exec,880 NAND_OP_PARSER_PAT_CMD_ELEM(false),881 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),882 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, ANFC_MAX_CHUNK_SIZE),883 NAND_OP_PARSER_PAT_CMD_ELEM(false)),884 NAND_OP_PARSER_PATTERN(885 anfc_reset_type_exec,886 NAND_OP_PARSER_PAT_CMD_ELEM(false),887 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),888 NAND_OP_PARSER_PATTERN(889 anfc_erase_type_exec,890 NAND_OP_PARSER_PAT_CMD_ELEM(false),891 NAND_OP_PARSER_PAT_ADDR_ELEM(false, ANFC_MAX_ADDR_CYC),892 NAND_OP_PARSER_PAT_CMD_ELEM(false),893 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),894 NAND_OP_PARSER_PATTERN(895 anfc_status_type_exec,896 NAND_OP_PARSER_PAT_CMD_ELEM(false),897 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, ANFC_MAX_CHUNK_SIZE)),898 NAND_OP_PARSER_PATTERN(899 anfc_wait_type_exec,900 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),901 );902 903static int anfc_check_op(struct nand_chip *chip,904 const struct nand_operation *op)905{906 const struct nand_op_instr *instr;907 int op_id;908 909 /*910 * The controller abstracts all the NAND operations and do not support911 * data only operations.912 *913 * TODO: The nand_op_parser framework should be extended to914 * support custom checks on DATA instructions.915 */916 for (op_id = 0; op_id < op->ninstrs; op_id++) {917 instr = &op->instrs[op_id];918 919 switch (instr->type) {920 case NAND_OP_ADDR_INSTR:921 if (instr->ctx.addr.naddrs > ANFC_MAX_ADDR_CYC)922 return -ENOTSUPP;923 924 break;925 case NAND_OP_DATA_IN_INSTR:926 case NAND_OP_DATA_OUT_INSTR:927 if (instr->ctx.data.len > ANFC_MAX_CHUNK_SIZE)928 return -ENOTSUPP;929 930 if (anfc_pkt_len_config(instr->ctx.data.len, NULL, NULL))931 return -ENOTSUPP;932 933 break;934 default:935 break;936 }937 }938 939 /*940 * The controller does not allow to proceed with a CMD+DATA_IN cycle941 * manually on the bus by reading data from the data register. Instead,942 * the controller abstract a status read operation with its own status943 * register after ordering a read status operation. Hence, we cannot944 * support any CMD+DATA_IN operation other than a READ STATUS.945 *946 * TODO: The nand_op_parser() framework should be extended to describe947 * fixed patterns instead of open-coding this check here.948 */949 if (op->ninstrs == 2 &&950 op->instrs[0].type == NAND_OP_CMD_INSTR &&951 op->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS &&952 op->instrs[1].type == NAND_OP_DATA_IN_INSTR)953 return -ENOTSUPP;954 955 return nand_op_parser_exec_op(chip, &anfc_op_parser, op, true);956}957 958static int anfc_exec_op(struct nand_chip *chip,959 const struct nand_operation *op,960 bool check_only)961{962 int ret;963 964 if (check_only)965 return anfc_check_op(chip, op);966 967 ret = anfc_select_target(chip, op->cs);968 if (ret)969 return ret;970 971 return nand_op_parser_exec_op(chip, &anfc_op_parser, op, check_only);972}973 974static int anfc_setup_interface(struct nand_chip *chip, int target,975 const struct nand_interface_config *conf)976{977 struct anand *anand = to_anand(chip);978 struct arasan_nfc *nfc = to_anfc(chip->controller);979 struct device_node *np = nfc->dev->of_node;980 const struct nand_sdr_timings *sdr;981 const struct nand_nvddr_timings *nvddr;982 unsigned int tccs_min, dqs_mode, fast_tcad;983 984 if (nand_interface_is_nvddr(conf)) {985 nvddr = nand_get_nvddr_timings(conf);986 if (IS_ERR(nvddr))987 return PTR_ERR(nvddr);988 } else {989 sdr = nand_get_sdr_timings(conf);990 if (IS_ERR(sdr))991 return PTR_ERR(sdr);992 }993 994 if (target < 0)995 return 0;996 997 if (nand_interface_is_sdr(conf)) {998 anand->data_iface = DIFACE_SDR |999 DIFACE_SDR_MODE(conf->timings.mode);1000 anand->timings = 0;1001 } else {1002 anand->data_iface = DIFACE_NVDDR |1003 DIFACE_DDR_MODE(conf->timings.mode);1004 1005 if (conf->timings.nvddr.tCCS_min <= 100000)1006 tccs_min = TCCS_TIME_100NS;1007 else if (conf->timings.nvddr.tCCS_min <= 200000)1008 tccs_min = TCCS_TIME_200NS;1009 else if (conf->timings.nvddr.tCCS_min <= 300000)1010 tccs_min = TCCS_TIME_300NS;1011 else1012 tccs_min = TCCS_TIME_500NS;1013 1014 fast_tcad = 0;1015 if (conf->timings.nvddr.tCAD_min < 45000)1016 fast_tcad = FAST_TCAD;1017 1018 switch (conf->timings.mode) {1019 case 5:1020 case 4:1021 dqs_mode = 2;1022 break;1023 case 3:1024 dqs_mode = 3;1025 break;1026 case 2:1027 dqs_mode = 4;1028 break;1029 case 1:1030 dqs_mode = 5;1031 break;1032 case 0:1033 default:1034 dqs_mode = 6;1035 break;1036 }1037 1038 anand->timings = tccs_min | fast_tcad |1039 DQS_BUFF_SEL_IN(dqs_mode) |1040 DQS_BUFF_SEL_OUT(dqs_mode);1041 }1042 1043 if (nand_interface_is_sdr(conf)) {1044 anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;1045 } else {1046 /* ONFI timings are defined in picoseconds */1047 anand->clk = div_u64((u64)NSEC_PER_SEC * 1000,1048 conf->timings.nvddr.tCK_min);1049 }1050 1051 /*1052 * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work1053 * with f > 90MHz (default clock is 100MHz) but signals are unstable1054 * with higher modes. Hence we decrease a little bit the clock rate to1055 * 80MHz when using SDR modes 2-5 with this SoC.1056 */1057 if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") &&1058 nand_interface_is_sdr(conf) && conf->timings.mode >= 2)1059 anand->clk = ANFC_XLNX_SDR_HS_CORE_CLK;1060 1061 return 0;1062}1063 1064static int anfc_calc_hw_ecc_bytes(int step_size, int strength)1065{1066 unsigned int bch_gf_mag, ecc_bits;1067 1068 switch (step_size) {1069 case SZ_512:1070 bch_gf_mag = 13;1071 break;1072 case SZ_1K:1073 bch_gf_mag = 14;1074 break;1075 default:1076 return -EINVAL;1077 }1078 1079 ecc_bits = bch_gf_mag * strength;1080 1081 return DIV_ROUND_UP(ecc_bits, 8);1082}1083 1084static const int anfc_hw_ecc_512_strengths[] = {4, 8, 12};1085 1086static const int anfc_hw_ecc_1024_strengths[] = {24};1087 1088static const struct nand_ecc_step_info anfc_hw_ecc_step_infos[] = {1089 {1090 .stepsize = SZ_512,1091 .strengths = anfc_hw_ecc_512_strengths,1092 .nstrengths = ARRAY_SIZE(anfc_hw_ecc_512_strengths),1093 },1094 {1095 .stepsize = SZ_1K,1096 .strengths = anfc_hw_ecc_1024_strengths,1097 .nstrengths = ARRAY_SIZE(anfc_hw_ecc_1024_strengths),1098 },1099};1100 1101static const struct nand_ecc_caps anfc_hw_ecc_caps = {1102 .stepinfos = anfc_hw_ecc_step_infos,1103 .nstepinfos = ARRAY_SIZE(anfc_hw_ecc_step_infos),1104 .calc_ecc_bytes = anfc_calc_hw_ecc_bytes,1105};1106 1107static int anfc_init_hw_ecc_controller(struct arasan_nfc *nfc,1108 struct nand_chip *chip)1109{1110 struct anand *anand = to_anand(chip);1111 struct mtd_info *mtd = nand_to_mtd(chip);1112 struct nand_ecc_ctrl *ecc = &chip->ecc;1113 unsigned int bch_prim_poly = 0, bch_gf_mag = 0, ecc_offset;1114 int ret;1115 1116 switch (mtd->writesize) {1117 case SZ_512:1118 case SZ_2K:1119 case SZ_4K:1120 case SZ_8K:1121 case SZ_16K:1122 break;1123 default:1124 dev_err(nfc->dev, "Unsupported page size %d\n", mtd->writesize);1125 return -EINVAL;1126 }1127 1128 ret = nand_ecc_choose_conf(chip, &anfc_hw_ecc_caps, mtd->oobsize);1129 if (ret)1130 return ret;1131 1132 switch (ecc->strength) {1133 case 12:1134 anand->strength = 0x1;1135 break;1136 case 8:1137 anand->strength = 0x2;1138 break;1139 case 4:1140 anand->strength = 0x3;1141 break;1142 case 24:1143 anand->strength = 0x4;1144 break;1145 default:1146 dev_err(nfc->dev, "Unsupported strength %d\n", ecc->strength);1147 return -EINVAL;1148 }1149 1150 switch (ecc->size) {1151 case SZ_512:1152 bch_gf_mag = 13;1153 bch_prim_poly = 0x201b;1154 break;1155 case SZ_1K:1156 bch_gf_mag = 14;1157 bch_prim_poly = 0x4443;1158 break;1159 default:1160 dev_err(nfc->dev, "Unsupported step size %d\n", ecc->strength);1161 return -EINVAL;1162 }1163 1164 mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());1165 1166 ecc->steps = mtd->writesize / ecc->size;1167 ecc->algo = NAND_ECC_ALGO_BCH;1168 anand->ecc_bits = bch_gf_mag * ecc->strength;1169 ecc->bytes = DIV_ROUND_UP(anand->ecc_bits, 8);1170 anand->ecc_total = DIV_ROUND_UP(anand->ecc_bits * ecc->steps, 8);1171 ecc_offset = mtd->writesize + mtd->oobsize - anand->ecc_total;1172 anand->ecc_conf = ECC_CONF_COL(ecc_offset) |1173 ECC_CONF_LEN(anand->ecc_total) |1174 ECC_CONF_BCH_EN;1175 1176 anand->errloc = devm_kmalloc_array(nfc->dev, ecc->strength,1177 sizeof(*anand->errloc), GFP_KERNEL);1178 if (!anand->errloc)1179 return -ENOMEM;1180 1181 anand->hw_ecc = devm_kmalloc(nfc->dev, ecc->bytes, GFP_KERNEL);1182 if (!anand->hw_ecc)1183 return -ENOMEM;1184 1185 /* Enforce bit swapping to fit the hardware */1186 anand->bch = bch_init(bch_gf_mag, ecc->strength, bch_prim_poly, true);1187 if (!anand->bch)1188 return -EINVAL;1189 1190 ecc->read_page = anfc_sel_read_page_hw_ecc;1191 ecc->write_page = anfc_sel_write_page_hw_ecc;1192 1193 return 0;1194}1195 1196static int anfc_attach_chip(struct nand_chip *chip)1197{1198 struct anand *anand = to_anand(chip);1199 struct arasan_nfc *nfc = to_anfc(chip->controller);1200 struct mtd_info *mtd = nand_to_mtd(chip);1201 int ret = 0;1202 1203 if (mtd->writesize <= SZ_512)1204 anand->caddr_cycles = 1;1205 else1206 anand->caddr_cycles = 2;1207 1208 if (chip->options & NAND_ROW_ADDR_3)1209 anand->raddr_cycles = 3;1210 else1211 anand->raddr_cycles = 2;1212 1213 switch (mtd->writesize) {1214 case 512:1215 anand->page_sz = 0;1216 break;1217 case 1024:1218 anand->page_sz = 5;1219 break;1220 case 2048:1221 anand->page_sz = 1;1222 break;1223 case 4096:1224 anand->page_sz = 2;1225 break;1226 case 8192:1227 anand->page_sz = 3;1228 break;1229 case 16384:1230 anand->page_sz = 4;1231 break;1232 default:1233 return -EINVAL;1234 }1235 1236 /* These hooks are valid for all ECC providers */1237 chip->ecc.read_page_raw = nand_monolithic_read_page_raw;1238 chip->ecc.write_page_raw = nand_monolithic_write_page_raw;1239 1240 switch (chip->ecc.engine_type) {1241 case NAND_ECC_ENGINE_TYPE_NONE:1242 case NAND_ECC_ENGINE_TYPE_SOFT:1243 case NAND_ECC_ENGINE_TYPE_ON_DIE:1244 break;1245 case NAND_ECC_ENGINE_TYPE_ON_HOST:1246 ret = anfc_init_hw_ecc_controller(nfc, chip);1247 break;1248 default:1249 dev_err(nfc->dev, "Unsupported ECC mode: %d\n",1250 chip->ecc.engine_type);1251 return -EINVAL;1252 }1253 1254 return ret;1255}1256 1257static void anfc_detach_chip(struct nand_chip *chip)1258{1259 struct anand *anand = to_anand(chip);1260 1261 if (anand->bch)1262 bch_free(anand->bch);1263}1264 1265static const struct nand_controller_ops anfc_ops = {1266 .exec_op = anfc_exec_op,1267 .setup_interface = anfc_setup_interface,1268 .attach_chip = anfc_attach_chip,1269 .detach_chip = anfc_detach_chip,1270};1271 1272static int anfc_chip_init(struct arasan_nfc *nfc, struct device_node *np)1273{1274 struct anand *anand;1275 struct nand_chip *chip;1276 struct mtd_info *mtd;1277 int rb, ret, i;1278 1279 anand = devm_kzalloc(nfc->dev, sizeof(*anand), GFP_KERNEL);1280 if (!anand)1281 return -ENOMEM;1282 1283 /* Chip-select init */1284 anand->ncs_idx = of_property_count_elems_of_size(np, "reg", sizeof(u32));1285 if (anand->ncs_idx <= 0 || anand->ncs_idx > nfc->ncs) {1286 dev_err(nfc->dev, "Invalid reg property\n");1287 return -EINVAL;1288 }1289 1290 anand->cs_idx = devm_kcalloc(nfc->dev, anand->ncs_idx,1291 sizeof(*anand->cs_idx), GFP_KERNEL);1292 if (!anand->cs_idx)1293 return -ENOMEM;1294 1295 for (i = 0; i < anand->ncs_idx; i++) {1296 ret = of_property_read_u32_index(np, "reg", i,1297 &anand->cs_idx[i]);1298 if (ret) {1299 dev_err(nfc->dev, "invalid CS property: %d\n", ret);1300 return ret;1301 }1302 }1303 1304 /* Ready-busy init */1305 ret = of_property_read_u32(np, "nand-rb", &rb);1306 if (ret)1307 return ret;1308 1309 if (rb >= ANFC_MAX_CS) {1310 dev_err(nfc->dev, "Wrong RB %d\n", rb);1311 return -EINVAL;1312 }1313 1314 anand->rb = rb;1315 1316 chip = &anand->chip;1317 mtd = nand_to_mtd(chip);1318 mtd->dev.parent = nfc->dev;1319 chip->controller = &nfc->controller;1320 chip->options = NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE |1321 NAND_USES_DMA;1322 1323 nand_set_flash_node(chip, np);1324 if (!mtd->name) {1325 dev_err(nfc->dev, "NAND label property is mandatory\n");1326 return -EINVAL;1327 }1328 1329 ret = nand_scan(chip, anand->ncs_idx);1330 if (ret) {1331 dev_err(nfc->dev, "Scan operation failed\n");1332 return ret;1333 }1334 1335 ret = mtd_device_register(mtd, NULL, 0);1336 if (ret) {1337 nand_cleanup(chip);1338 return ret;1339 }1340 1341 list_add_tail(&anand->node, &nfc->chips);1342 1343 return 0;1344}1345 1346static void anfc_chips_cleanup(struct arasan_nfc *nfc)1347{1348 struct anand *anand, *tmp;1349 struct nand_chip *chip;1350 int ret;1351 1352 list_for_each_entry_safe(anand, tmp, &nfc->chips, node) {1353 chip = &anand->chip;1354 ret = mtd_device_unregister(nand_to_mtd(chip));1355 WARN_ON(ret);1356 nand_cleanup(chip);1357 list_del(&anand->node);1358 }1359}1360 1361static int anfc_chips_init(struct arasan_nfc *nfc)1362{1363 struct device_node *np = nfc->dev->of_node;1364 int nchips = of_get_child_count(np);1365 int ret;1366 1367 if (!nchips) {1368 dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n",1369 nchips);1370 return -EINVAL;1371 }1372 1373 for_each_child_of_node_scoped(np, nand_np) {1374 ret = anfc_chip_init(nfc, nand_np);1375 if (ret) {1376 anfc_chips_cleanup(nfc);1377 break;1378 }1379 }1380 1381 return ret;1382}1383 1384static void anfc_reset(struct arasan_nfc *nfc)1385{1386 /* Disable interrupt signals */1387 writel_relaxed(0, nfc->base + INTR_SIG_EN_REG);1388 1389 /* Enable interrupt status */1390 writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG);1391 1392 nfc->cur_cs = -1;1393}1394 1395static int anfc_parse_cs(struct arasan_nfc *nfc)1396{1397 int ret;1398 1399 /* Check the gpio-cs property */1400 ret = rawnand_dt_parse_gpio_cs(nfc->dev, &nfc->cs_array, &nfc->ncs);1401 if (ret)1402 return ret;1403 1404 /*1405 * The controller native CS cannot be both disabled at the same time.1406 * Hence, only one native CS can be used if GPIO CS are needed, so that1407 * the other is selected when a non-native CS must be asserted (not1408 * wired physically or configured as GPIO instead of NAND CS). In this1409 * case, the "not" chosen CS is assigned to nfc->spare_cs and selected1410 * whenever a GPIO CS must be asserted.1411 */1412 if (nfc->cs_array && nfc->ncs > 2) {1413 if (!nfc->cs_array[0] && !nfc->cs_array[1]) {1414 dev_err(nfc->dev,1415 "Assign a single native CS when using GPIOs\n");1416 return -EINVAL;1417 }1418 1419 if (nfc->cs_array[0])1420 nfc->spare_cs = 0;1421 else1422 nfc->spare_cs = 1;1423 }1424 1425 if (!nfc->cs_array) {1426 nfc->cs_array = anfc_default_cs_array;1427 nfc->ncs = ANFC_MAX_CS;1428 return 0;1429 }1430 1431 return 0;1432}1433 1434static int anfc_probe(struct platform_device *pdev)1435{1436 struct arasan_nfc *nfc;1437 int ret;1438 1439 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);1440 if (!nfc)1441 return -ENOMEM;1442 1443 nfc->dev = &pdev->dev;1444 nand_controller_init(&nfc->controller);1445 nfc->controller.ops = &anfc_ops;1446 INIT_LIST_HEAD(&nfc->chips);1447 1448 nfc->base = devm_platform_ioremap_resource(pdev, 0);1449 if (IS_ERR(nfc->base))1450 return PTR_ERR(nfc->base);1451 1452 anfc_reset(nfc);1453 1454 nfc->controller_clk = devm_clk_get_enabled(&pdev->dev, "controller");1455 if (IS_ERR(nfc->controller_clk))1456 return PTR_ERR(nfc->controller_clk);1457 1458 nfc->bus_clk = devm_clk_get_enabled(&pdev->dev, "bus");1459 if (IS_ERR(nfc->bus_clk))1460 return PTR_ERR(nfc->bus_clk);1461 1462 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));1463 if (ret)1464 return ret;1465 1466 ret = anfc_parse_cs(nfc);1467 if (ret)1468 return ret;1469 1470 ret = anfc_chips_init(nfc);1471 if (ret)1472 return ret;1473 1474 platform_set_drvdata(pdev, nfc);1475 1476 return 0;1477}1478 1479static void anfc_remove(struct platform_device *pdev)1480{1481 struct arasan_nfc *nfc = platform_get_drvdata(pdev);1482 1483 anfc_chips_cleanup(nfc);1484}1485 1486static const struct of_device_id anfc_ids[] = {1487 {1488 .compatible = "xlnx,zynqmp-nand-controller",1489 },1490 {1491 .compatible = "arasan,nfc-v3p10",1492 },1493 {}1494};1495MODULE_DEVICE_TABLE(of, anfc_ids);1496 1497static struct platform_driver anfc_driver = {1498 .driver = {1499 .name = "arasan-nand-controller",1500 .of_match_table = anfc_ids,1501 },1502 .probe = anfc_probe,1503 .remove_new = anfc_remove,1504};1505module_platform_driver(anfc_driver);1506 1507MODULE_LICENSE("GPL v2");1508MODULE_AUTHOR("Punnaiah Choudary Kalluri <punnaia@xilinx.com>");1509MODULE_AUTHOR("Naga Sureshkumar Relli <nagasure@xilinx.com>");1510MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");1511MODULE_DESCRIPTION("Arasan NAND Flash Controller Driver");1512