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1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright 2017 ATMEL4 * Copyright 2017 Free Electrons5 *6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>7 *8 * Derived from the atmel_nand.c driver which contained the following9 * copyrights:10 *11 * Copyright 2003 Rick Bronson12 *13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)14 * Copyright 2001 Thomas Gleixner (gleixner@autronix.de)15 *16 * Derived from drivers/mtd/spia.c (removed in v3.8)17 * Copyright 2000 Steven J. Hill (sjhill@cotw.com)18 *19 *20 * Add Hardware ECC support for AT91SAM9260 / AT91SAM926321 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 200722 *23 * Derived from Das U-Boot source code24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)25 * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas26 *27 * Add Programmable Multibit ECC support for various AT91 SoC28 * Copyright 2012 ATMEL, Hong Xu29 *30 * Add Nand Flash Controller support for SAMA5 SoC31 * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)32 *33 * A few words about the naming convention in this file. This convention34 * applies to structure and function names.35 *36 * Prefixes:37 *38 * - atmel_nand_: all generic structures/functions39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface40 * (at91sam9 and avr32 SoCs)41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface42 * (sama5 SoCs and later)43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block44 * that is available in the HSMC block45 * - <soc>_nand_: all SoC specific structures/functions46 */47 48#include <linux/clk.h>49#include <linux/dma-mapping.h>50#include <linux/dmaengine.h>51#include <linux/genalloc.h>52#include <linux/gpio/consumer.h>53#include <linux/interrupt.h>54#include <linux/mfd/syscon.h>55#include <linux/mfd/syscon/atmel-matrix.h>56#include <linux/mfd/syscon/atmel-smc.h>57#include <linux/module.h>58#include <linux/mtd/rawnand.h>59#include <linux/of_address.h>60#include <linux/of_irq.h>61#include <linux/of_platform.h>62#include <linux/iopoll.h>63#include <linux/platform_device.h>64#include <linux/regmap.h>65#include <soc/at91/atmel-sfr.h>66 67#include "pmecc.h"68 69#define ATMEL_HSMC_NFC_CFG 0x070#define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24)71#define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)72#define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20))73#define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16)74#define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13)75#define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12)76#define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9)77#define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8)78#define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0)79#define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)80 81#define ATMEL_HSMC_NFC_CTRL 0x482#define ATMEL_HSMC_NFC_CTRL_EN BIT(0)83#define ATMEL_HSMC_NFC_CTRL_DIS BIT(1)84 85#define ATMEL_HSMC_NFC_SR 0x886#define ATMEL_HSMC_NFC_IER 0xc87#define ATMEL_HSMC_NFC_IDR 0x1088#define ATMEL_HSMC_NFC_IMR 0x1489#define ATMEL_HSMC_NFC_SR_ENABLED BIT(1)90#define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4)91#define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5)92#define ATMEL_HSMC_NFC_SR_BUSY BIT(8)93#define ATMEL_HSMC_NFC_SR_WR BIT(11)94#define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12)95#define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16)96#define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17)97#define ATMEL_HSMC_NFC_SR_DTOE BIT(20)98#define ATMEL_HSMC_NFC_SR_UNDEF BIT(21)99#define ATMEL_HSMC_NFC_SR_AWB BIT(22)100#define ATMEL_HSMC_NFC_SR_NFCASE BIT(23)101#define ATMEL_HSMC_NFC_SR_ERRORS (ATMEL_HSMC_NFC_SR_DTOE | \102 ATMEL_HSMC_NFC_SR_UNDEF | \103 ATMEL_HSMC_NFC_SR_AWB | \104 ATMEL_HSMC_NFC_SR_NFCASE)105#define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24)106 107#define ATMEL_HSMC_NFC_ADDR 0x18108#define ATMEL_HSMC_NFC_BANK 0x1c109 110#define ATMEL_NFC_MAX_RB_ID 7111 112#define ATMEL_NFC_SRAM_SIZE 0x2400113 114#define ATMEL_NFC_CMD(pos, cmd) ((cmd) << (((pos) * 8) + 2))115#define ATMEL_NFC_VCMD2 BIT(18)116#define ATMEL_NFC_ACYCLE(naddrs) ((naddrs) << 19)117#define ATMEL_NFC_CSID(cs) ((cs) << 22)118#define ATMEL_NFC_DATAEN BIT(25)119#define ATMEL_NFC_NFCWR BIT(26)120 121#define ATMEL_NFC_MAX_ADDR_CYCLES 5122 123#define ATMEL_NAND_ALE_OFFSET BIT(21)124#define ATMEL_NAND_CLE_OFFSET BIT(22)125 126#define DEFAULT_TIMEOUT_MS 1000127#define MIN_DMA_LEN 128128 129static bool atmel_nand_avoid_dma __read_mostly;130 131MODULE_PARM_DESC(avoiddma, "Avoid using DMA");132module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);133 134enum atmel_nand_rb_type {135 ATMEL_NAND_NO_RB,136 ATMEL_NAND_NATIVE_RB,137 ATMEL_NAND_GPIO_RB,138};139 140struct atmel_nand_rb {141 enum atmel_nand_rb_type type;142 union {143 struct gpio_desc *gpio;144 int id;145 };146};147 148struct atmel_nand_cs {149 int id;150 struct atmel_nand_rb rb;151 struct gpio_desc *csgpio;152 struct {153 void __iomem *virt;154 dma_addr_t dma;155 } io;156 157 struct atmel_smc_cs_conf smcconf;158};159 160struct atmel_nand {161 struct list_head node;162 struct device *dev;163 struct nand_chip base;164 struct atmel_nand_cs *activecs;165 struct atmel_pmecc_user *pmecc;166 struct gpio_desc *cdgpio;167 int numcs;168 struct atmel_nand_cs cs[] __counted_by(numcs);169};170 171static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)172{173 return container_of(chip, struct atmel_nand, base);174}175 176enum atmel_nfc_data_xfer {177 ATMEL_NFC_NO_DATA,178 ATMEL_NFC_READ_DATA,179 ATMEL_NFC_WRITE_DATA,180};181 182struct atmel_nfc_op {183 u8 cs;184 u8 ncmds;185 u8 cmds[2];186 u8 naddrs;187 u8 addrs[5];188 enum atmel_nfc_data_xfer data;189 u32 wait;190 u32 errors;191};192 193struct atmel_nand_controller;194struct atmel_nand_controller_caps;195 196struct atmel_nand_controller_ops {197 int (*probe)(struct platform_device *pdev,198 const struct atmel_nand_controller_caps *caps);199 int (*remove)(struct atmel_nand_controller *nc);200 void (*nand_init)(struct atmel_nand_controller *nc,201 struct atmel_nand *nand);202 int (*ecc_init)(struct nand_chip *chip);203 int (*setup_interface)(struct atmel_nand *nand, int csline,204 const struct nand_interface_config *conf);205 int (*exec_op)(struct atmel_nand *nand,206 const struct nand_operation *op, bool check_only);207};208 209struct atmel_nand_controller_caps {210 bool has_dma;211 bool legacy_of_bindings;212 u32 ale_offs;213 u32 cle_offs;214 const char *ebi_csa_regmap_name;215 const struct atmel_nand_controller_ops *ops;216};217 218struct atmel_nand_controller {219 struct nand_controller base;220 const struct atmel_nand_controller_caps *caps;221 struct device *dev;222 struct regmap *smc;223 struct dma_chan *dmac;224 struct atmel_pmecc *pmecc;225 struct list_head chips;226 struct clk *mck;227};228 229static inline struct atmel_nand_controller *230to_nand_controller(struct nand_controller *ctl)231{232 return container_of(ctl, struct atmel_nand_controller, base);233}234 235struct atmel_smc_nand_ebi_csa_cfg {236 u32 offs;237 u32 nfd0_on_d16;238};239 240struct atmel_smc_nand_controller {241 struct atmel_nand_controller base;242 struct regmap *ebi_csa_regmap;243 struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;244};245 246static inline struct atmel_smc_nand_controller *247to_smc_nand_controller(struct nand_controller *ctl)248{249 return container_of(to_nand_controller(ctl),250 struct atmel_smc_nand_controller, base);251}252 253struct atmel_hsmc_nand_controller {254 struct atmel_nand_controller base;255 struct {256 struct gen_pool *pool;257 void __iomem *virt;258 dma_addr_t dma;259 } sram;260 const struct atmel_hsmc_reg_layout *hsmc_layout;261 struct regmap *io;262 struct atmel_nfc_op op;263 struct completion complete;264 u32 cfg;265 int irq;266 267 /* Only used when instantiating from legacy DT bindings. */268 struct clk *clk;269};270 271static inline struct atmel_hsmc_nand_controller *272to_hsmc_nand_controller(struct nand_controller *ctl)273{274 return container_of(to_nand_controller(ctl),275 struct atmel_hsmc_nand_controller, base);276}277 278static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)279{280 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;281 op->wait ^= status & op->wait;282 283 return !op->wait || op->errors;284}285 286static irqreturn_t atmel_nfc_interrupt(int irq, void *data)287{288 struct atmel_hsmc_nand_controller *nc = data;289 u32 sr, rcvd;290 bool done;291 292 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);293 294 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);295 done = atmel_nfc_op_done(&nc->op, sr);296 297 if (rcvd)298 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);299 300 if (done)301 complete(&nc->complete);302 303 return rcvd ? IRQ_HANDLED : IRQ_NONE;304}305 306static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,307 unsigned int timeout_ms)308{309 int ret;310 311 if (!timeout_ms)312 timeout_ms = DEFAULT_TIMEOUT_MS;313 314 if (poll) {315 u32 status;316 317 ret = regmap_read_poll_timeout(nc->base.smc,318 ATMEL_HSMC_NFC_SR, status,319 atmel_nfc_op_done(&nc->op,320 status),321 0, timeout_ms * 1000);322 } else {323 init_completion(&nc->complete);324 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,325 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);326 ret = wait_for_completion_timeout(&nc->complete,327 msecs_to_jiffies(timeout_ms));328 if (!ret)329 ret = -ETIMEDOUT;330 else331 ret = 0;332 333 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);334 }335 336 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {337 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");338 ret = -ETIMEDOUT;339 }340 341 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {342 dev_err(nc->base.dev, "Access to an undefined area\n");343 ret = -EIO;344 }345 346 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {347 dev_err(nc->base.dev, "Access while busy\n");348 ret = -EIO;349 }350 351 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {352 dev_err(nc->base.dev, "Wrong access size\n");353 ret = -EIO;354 }355 356 return ret;357}358 359static void atmel_nand_dma_transfer_finished(void *data)360{361 struct completion *finished = data;362 363 complete(finished);364}365 366static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,367 void *buf, dma_addr_t dev_dma, size_t len,368 enum dma_data_direction dir)369{370 DECLARE_COMPLETION_ONSTACK(finished);371 dma_addr_t src_dma, dst_dma, buf_dma;372 struct dma_async_tx_descriptor *tx;373 dma_cookie_t cookie;374 375 buf_dma = dma_map_single(nc->dev, buf, len, dir);376 if (dma_mapping_error(nc->dev, dev_dma)) {377 dev_err(nc->dev,378 "Failed to prepare a buffer for DMA access\n");379 goto err;380 }381 382 if (dir == DMA_FROM_DEVICE) {383 src_dma = dev_dma;384 dst_dma = buf_dma;385 } else {386 src_dma = buf_dma;387 dst_dma = dev_dma;388 }389 390 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,391 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);392 if (!tx) {393 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");394 goto err_unmap;395 }396 397 tx->callback = atmel_nand_dma_transfer_finished;398 tx->callback_param = &finished;399 400 cookie = dmaengine_submit(tx);401 if (dma_submit_error(cookie)) {402 dev_err(nc->dev, "Failed to do DMA tx_submit\n");403 goto err_unmap;404 }405 406 dma_async_issue_pending(nc->dmac);407 wait_for_completion(&finished);408 dma_unmap_single(nc->dev, buf_dma, len, dir);409 410 return 0;411 412err_unmap:413 dma_unmap_single(nc->dev, buf_dma, len, dir);414 415err:416 dev_dbg(nc->dev, "Fall back to CPU I/O\n");417 418 return -EIO;419}420 421static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)422{423 u8 *addrs = nc->op.addrs;424 unsigned int op = 0;425 u32 addr, val;426 int i, ret;427 428 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;429 430 for (i = 0; i < nc->op.ncmds; i++)431 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);432 433 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)434 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);435 436 op |= ATMEL_NFC_CSID(nc->op.cs) |437 ATMEL_NFC_ACYCLE(nc->op.naddrs);438 439 if (nc->op.ncmds > 1)440 op |= ATMEL_NFC_VCMD2;441 442 addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |443 (addrs[3] << 24);444 445 if (nc->op.data != ATMEL_NFC_NO_DATA) {446 op |= ATMEL_NFC_DATAEN;447 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;448 449 if (nc->op.data == ATMEL_NFC_WRITE_DATA)450 op |= ATMEL_NFC_NFCWR;451 }452 453 /* Clear all flags. */454 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);455 456 /* Send the command. */457 regmap_write(nc->io, op, addr);458 459 ret = atmel_nfc_wait(nc, poll, 0);460 if (ret)461 dev_err(nc->base.dev,462 "Failed to send NAND command (err = %d)!",463 ret);464 465 /* Reset the op state. */466 memset(&nc->op, 0, sizeof(nc->op));467 468 return ret;469}470 471static void atmel_nand_data_in(struct atmel_nand *nand, void *buf,472 unsigned int len, bool force_8bit)473{474 struct atmel_nand_controller *nc;475 476 nc = to_nand_controller(nand->base.controller);477 478 /*479 * If the controller supports DMA, the buffer address is DMA-able and480 * len is long enough to make DMA transfers profitable, let's trigger481 * a DMA transfer. If it fails, fallback to PIO mode.482 */483 if (nc->dmac && virt_addr_valid(buf) &&484 len >= MIN_DMA_LEN && !force_8bit &&485 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,486 DMA_FROM_DEVICE))487 return;488 489 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)490 ioread16_rep(nand->activecs->io.virt, buf, len / 2);491 else492 ioread8_rep(nand->activecs->io.virt, buf, len);493}494 495static void atmel_nand_data_out(struct atmel_nand *nand, const void *buf,496 unsigned int len, bool force_8bit)497{498 struct atmel_nand_controller *nc;499 500 nc = to_nand_controller(nand->base.controller);501 502 /*503 * If the controller supports DMA, the buffer address is DMA-able and504 * len is long enough to make DMA transfers profitable, let's trigger505 * a DMA transfer. If it fails, fallback to PIO mode.506 */507 if (nc->dmac && virt_addr_valid(buf) &&508 len >= MIN_DMA_LEN && !force_8bit &&509 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,510 len, DMA_TO_DEVICE))511 return;512 513 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)514 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);515 else516 iowrite8_rep(nand->activecs->io.virt, buf, len);517}518 519static int atmel_nand_waitrdy(struct atmel_nand *nand, unsigned int timeout_ms)520{521 if (nand->activecs->rb.type == ATMEL_NAND_NO_RB)522 return nand_soft_waitrdy(&nand->base, timeout_ms);523 524 return nand_gpio_waitrdy(&nand->base, nand->activecs->rb.gpio,525 timeout_ms);526}527 528static int atmel_hsmc_nand_waitrdy(struct atmel_nand *nand,529 unsigned int timeout_ms)530{531 struct atmel_hsmc_nand_controller *nc;532 u32 status, mask;533 534 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)535 return atmel_nand_waitrdy(nand, timeout_ms);536 537 nc = to_hsmc_nand_controller(nand->base.controller);538 mask = ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);539 return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR,540 status, status & mask,541 10, timeout_ms * 1000);542}543 544static void atmel_nand_select_target(struct atmel_nand *nand,545 unsigned int cs)546{547 nand->activecs = &nand->cs[cs];548}549 550static void atmel_hsmc_nand_select_target(struct atmel_nand *nand,551 unsigned int cs)552{553 struct mtd_info *mtd = nand_to_mtd(&nand->base);554 struct atmel_hsmc_nand_controller *nc;555 u32 cfg = ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |556 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |557 ATMEL_HSMC_NFC_CFG_RSPARE;558 559 nand->activecs = &nand->cs[cs];560 nc = to_hsmc_nand_controller(nand->base.controller);561 if (nc->cfg == cfg)562 return;563 564 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,565 ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |566 ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |567 ATMEL_HSMC_NFC_CFG_RSPARE |568 ATMEL_HSMC_NFC_CFG_WSPARE,569 cfg);570 nc->cfg = cfg;571}572 573static int atmel_smc_nand_exec_instr(struct atmel_nand *nand,574 const struct nand_op_instr *instr)575{576 struct atmel_nand_controller *nc;577 unsigned int i;578 579 nc = to_nand_controller(nand->base.controller);580 switch (instr->type) {581 case NAND_OP_CMD_INSTR:582 writeb(instr->ctx.cmd.opcode,583 nand->activecs->io.virt + nc->caps->cle_offs);584 return 0;585 case NAND_OP_ADDR_INSTR:586 for (i = 0; i < instr->ctx.addr.naddrs; i++)587 writeb(instr->ctx.addr.addrs[i],588 nand->activecs->io.virt + nc->caps->ale_offs);589 return 0;590 case NAND_OP_DATA_IN_INSTR:591 atmel_nand_data_in(nand, instr->ctx.data.buf.in,592 instr->ctx.data.len,593 instr->ctx.data.force_8bit);594 return 0;595 case NAND_OP_DATA_OUT_INSTR:596 atmel_nand_data_out(nand, instr->ctx.data.buf.out,597 instr->ctx.data.len,598 instr->ctx.data.force_8bit);599 return 0;600 case NAND_OP_WAITRDY_INSTR:601 return atmel_nand_waitrdy(nand,602 instr->ctx.waitrdy.timeout_ms);603 default:604 break;605 }606 607 return -EINVAL;608}609 610static int atmel_smc_nand_exec_op(struct atmel_nand *nand,611 const struct nand_operation *op,612 bool check_only)613{614 unsigned int i;615 int ret = 0;616 617 if (check_only)618 return 0;619 620 atmel_nand_select_target(nand, op->cs);621 gpiod_set_value(nand->activecs->csgpio, 0);622 for (i = 0; i < op->ninstrs; i++) {623 ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]);624 if (ret)625 break;626 }627 gpiod_set_value(nand->activecs->csgpio, 1);628 629 return ret;630}631 632static int atmel_hsmc_exec_cmd_addr(struct nand_chip *chip,633 const struct nand_subop *subop)634{635 struct atmel_nand *nand = to_atmel_nand(chip);636 struct atmel_hsmc_nand_controller *nc;637 unsigned int i, j;638 639 nc = to_hsmc_nand_controller(chip->controller);640 641 nc->op.cs = nand->activecs->id;642 for (i = 0; i < subop->ninstrs; i++) {643 const struct nand_op_instr *instr = &subop->instrs[i];644 645 if (instr->type == NAND_OP_CMD_INSTR) {646 nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode;647 continue;648 }649 650 for (j = nand_subop_get_addr_start_off(subop, i);651 j < nand_subop_get_num_addr_cyc(subop, i); j++) {652 nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j];653 nc->op.naddrs++;654 }655 }656 657 return atmel_nfc_exec_op(nc, true);658}659 660static int atmel_hsmc_exec_rw(struct nand_chip *chip,661 const struct nand_subop *subop)662{663 const struct nand_op_instr *instr = subop->instrs;664 struct atmel_nand *nand = to_atmel_nand(chip);665 666 if (instr->type == NAND_OP_DATA_IN_INSTR)667 atmel_nand_data_in(nand, instr->ctx.data.buf.in,668 instr->ctx.data.len,669 instr->ctx.data.force_8bit);670 else671 atmel_nand_data_out(nand, instr->ctx.data.buf.out,672 instr->ctx.data.len,673 instr->ctx.data.force_8bit);674 675 return 0;676}677 678static int atmel_hsmc_exec_waitrdy(struct nand_chip *chip,679 const struct nand_subop *subop)680{681 const struct nand_op_instr *instr = subop->instrs;682 struct atmel_nand *nand = to_atmel_nand(chip);683 684 return atmel_hsmc_nand_waitrdy(nand, instr->ctx.waitrdy.timeout_ms);685}686 687static const struct nand_op_parser atmel_hsmc_op_parser = NAND_OP_PARSER(688 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_cmd_addr,689 NAND_OP_PARSER_PAT_CMD_ELEM(true),690 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),691 NAND_OP_PARSER_PAT_CMD_ELEM(true)),692 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,693 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 0)),694 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,695 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 0)),696 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_waitrdy,697 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),698);699 700static int atmel_hsmc_nand_exec_op(struct atmel_nand *nand,701 const struct nand_operation *op,702 bool check_only)703{704 int ret;705 706 if (check_only)707 return nand_op_parser_exec_op(&nand->base,708 &atmel_hsmc_op_parser, op, true);709 710 atmel_hsmc_nand_select_target(nand, op->cs);711 ret = nand_op_parser_exec_op(&nand->base, &atmel_hsmc_op_parser, op,712 false);713 714 return ret;715}716 717static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,718 bool oob_required)719{720 struct mtd_info *mtd = nand_to_mtd(chip);721 struct atmel_hsmc_nand_controller *nc;722 int ret = -EIO;723 724 nc = to_hsmc_nand_controller(chip->controller);725 726 if (nc->base.dmac)727 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,728 nc->sram.dma, mtd->writesize,729 DMA_TO_DEVICE);730 731 /* Falling back to CPU copy. */732 if (ret)733 memcpy_toio(nc->sram.virt, buf, mtd->writesize);734 735 if (oob_required)736 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,737 mtd->oobsize);738}739 740static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,741 bool oob_required)742{743 struct mtd_info *mtd = nand_to_mtd(chip);744 struct atmel_hsmc_nand_controller *nc;745 int ret = -EIO;746 747 nc = to_hsmc_nand_controller(chip->controller);748 749 if (nc->base.dmac)750 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,751 mtd->writesize, DMA_FROM_DEVICE);752 753 /* Falling back to CPU copy. */754 if (ret)755 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);756 757 if (oob_required)758 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,759 mtd->oobsize);760}761 762static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)763{764 struct mtd_info *mtd = nand_to_mtd(chip);765 struct atmel_hsmc_nand_controller *nc;766 767 nc = to_hsmc_nand_controller(chip->controller);768 769 if (column >= 0) {770 nc->op.addrs[nc->op.naddrs++] = column;771 772 /*773 * 2 address cycles for the column offset on large page NANDs.774 */775 if (mtd->writesize > 512)776 nc->op.addrs[nc->op.naddrs++] = column >> 8;777 }778 779 if (page >= 0) {780 nc->op.addrs[nc->op.naddrs++] = page;781 nc->op.addrs[nc->op.naddrs++] = page >> 8;782 783 if (chip->options & NAND_ROW_ADDR_3)784 nc->op.addrs[nc->op.naddrs++] = page >> 16;785 }786}787 788static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)789{790 struct atmel_nand *nand = to_atmel_nand(chip);791 struct atmel_nand_controller *nc;792 int ret;793 794 nc = to_nand_controller(chip->controller);795 796 if (raw)797 return 0;798 799 ret = atmel_pmecc_enable(nand->pmecc, op);800 if (ret)801 dev_err(nc->dev,802 "Failed to enable ECC engine (err = %d)\n", ret);803 804 return ret;805}806 807static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)808{809 struct atmel_nand *nand = to_atmel_nand(chip);810 811 if (!raw)812 atmel_pmecc_disable(nand->pmecc);813}814 815static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)816{817 struct atmel_nand *nand = to_atmel_nand(chip);818 struct mtd_info *mtd = nand_to_mtd(chip);819 struct atmel_nand_controller *nc;820 struct mtd_oob_region oobregion;821 void *eccbuf;822 int ret, i;823 824 nc = to_nand_controller(chip->controller);825 826 if (raw)827 return 0;828 829 ret = atmel_pmecc_wait_rdy(nand->pmecc);830 if (ret) {831 dev_err(nc->dev,832 "Failed to transfer NAND page data (err = %d)\n",833 ret);834 return ret;835 }836 837 mtd_ooblayout_ecc(mtd, 0, &oobregion);838 eccbuf = chip->oob_poi + oobregion.offset;839 840 for (i = 0; i < chip->ecc.steps; i++) {841 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,842 eccbuf);843 eccbuf += chip->ecc.bytes;844 }845 846 return 0;847}848 849static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,850 bool raw)851{852 struct atmel_nand *nand = to_atmel_nand(chip);853 struct mtd_info *mtd = nand_to_mtd(chip);854 struct atmel_nand_controller *nc;855 struct mtd_oob_region oobregion;856 int ret, i, max_bitflips = 0;857 void *databuf, *eccbuf;858 859 nc = to_nand_controller(chip->controller);860 861 if (raw)862 return 0;863 864 ret = atmel_pmecc_wait_rdy(nand->pmecc);865 if (ret) {866 dev_err(nc->dev,867 "Failed to read NAND page data (err = %d)\n",868 ret);869 return ret;870 }871 872 mtd_ooblayout_ecc(mtd, 0, &oobregion);873 eccbuf = chip->oob_poi + oobregion.offset;874 databuf = buf;875 876 for (i = 0; i < chip->ecc.steps; i++) {877 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,878 eccbuf);879 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))880 ret = nand_check_erased_ecc_chunk(databuf,881 chip->ecc.size,882 eccbuf,883 chip->ecc.bytes,884 NULL, 0,885 chip->ecc.strength);886 887 if (ret >= 0) {888 mtd->ecc_stats.corrected += ret;889 max_bitflips = max(ret, max_bitflips);890 } else {891 mtd->ecc_stats.failed++;892 }893 894 databuf += chip->ecc.size;895 eccbuf += chip->ecc.bytes;896 }897 898 return max_bitflips;899}900 901static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,902 bool oob_required, int page, bool raw)903{904 struct mtd_info *mtd = nand_to_mtd(chip);905 struct atmel_nand *nand = to_atmel_nand(chip);906 int ret;907 908 nand_prog_page_begin_op(chip, page, 0, NULL, 0);909 910 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);911 if (ret)912 return ret;913 914 nand_write_data_op(chip, buf, mtd->writesize, false);915 916 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);917 if (ret) {918 atmel_pmecc_disable(nand->pmecc);919 return ret;920 }921 922 atmel_nand_pmecc_disable(chip, raw);923 924 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);925 926 return nand_prog_page_end_op(chip);927}928 929static int atmel_nand_pmecc_write_page(struct nand_chip *chip, const u8 *buf,930 int oob_required, int page)931{932 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);933}934 935static int atmel_nand_pmecc_write_page_raw(struct nand_chip *chip,936 const u8 *buf, int oob_required,937 int page)938{939 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);940}941 942static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,943 bool oob_required, int page, bool raw)944{945 struct mtd_info *mtd = nand_to_mtd(chip);946 int ret;947 948 nand_read_page_op(chip, page, 0, NULL, 0);949 950 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);951 if (ret)952 return ret;953 954 ret = nand_read_data_op(chip, buf, mtd->writesize, false, false);955 if (ret)956 goto out_disable;957 958 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, false);959 if (ret)960 goto out_disable;961 962 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);963 964out_disable:965 atmel_nand_pmecc_disable(chip, raw);966 967 return ret;968}969 970static int atmel_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,971 int oob_required, int page)972{973 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);974}975 976static int atmel_nand_pmecc_read_page_raw(struct nand_chip *chip, u8 *buf,977 int oob_required, int page)978{979 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);980}981 982static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,983 const u8 *buf, bool oob_required,984 int page, bool raw)985{986 struct mtd_info *mtd = nand_to_mtd(chip);987 struct atmel_nand *nand = to_atmel_nand(chip);988 struct atmel_hsmc_nand_controller *nc;989 int ret;990 991 atmel_hsmc_nand_select_target(nand, chip->cur_cs);992 nc = to_hsmc_nand_controller(chip->controller);993 994 atmel_nfc_copy_to_sram(chip, buf, false);995 996 nc->op.cmds[0] = NAND_CMD_SEQIN;997 nc->op.ncmds = 1;998 atmel_nfc_set_op_addr(chip, page, 0x0);999 nc->op.cs = nand->activecs->id;1000 nc->op.data = ATMEL_NFC_WRITE_DATA;1001 1002 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);1003 if (ret)1004 return ret;1005 1006 ret = atmel_nfc_exec_op(nc, false);1007 if (ret) {1008 atmel_nand_pmecc_disable(chip, raw);1009 dev_err(nc->base.dev,1010 "Failed to transfer NAND page data (err = %d)\n",1011 ret);1012 return ret;1013 }1014 1015 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);1016 1017 atmel_nand_pmecc_disable(chip, raw);1018 1019 if (ret)1020 return ret;1021 1022 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);1023 1024 return nand_prog_page_end_op(chip);1025}1026 1027static int atmel_hsmc_nand_pmecc_write_page(struct nand_chip *chip,1028 const u8 *buf, int oob_required,1029 int page)1030{1031 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,1032 false);1033}1034 1035static int atmel_hsmc_nand_pmecc_write_page_raw(struct nand_chip *chip,1036 const u8 *buf,1037 int oob_required, int page)1038{1039 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,1040 true);1041}1042 1043static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,1044 bool oob_required, int page,1045 bool raw)1046{1047 struct mtd_info *mtd = nand_to_mtd(chip);1048 struct atmel_nand *nand = to_atmel_nand(chip);1049 struct atmel_hsmc_nand_controller *nc;1050 int ret;1051 1052 atmel_hsmc_nand_select_target(nand, chip->cur_cs);1053 nc = to_hsmc_nand_controller(chip->controller);1054 1055 /*1056 * Optimized read page accessors only work when the NAND R/B pin is1057 * connected to a native SoC R/B pin. If that's not the case, fallback1058 * to the non-optimized one.1059 */1060 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)1061 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,1062 raw);1063 1064 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;1065 1066 if (mtd->writesize > 512)1067 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;1068 1069 atmel_nfc_set_op_addr(chip, page, 0x0);1070 nc->op.cs = nand->activecs->id;1071 nc->op.data = ATMEL_NFC_READ_DATA;1072 1073 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);1074 if (ret)1075 return ret;1076 1077 ret = atmel_nfc_exec_op(nc, false);1078 if (ret) {1079 atmel_nand_pmecc_disable(chip, raw);1080 dev_err(nc->base.dev,1081 "Failed to load NAND page data (err = %d)\n",1082 ret);1083 return ret;1084 }1085 1086 atmel_nfc_copy_from_sram(chip, buf, true);1087 1088 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);1089 1090 atmel_nand_pmecc_disable(chip, raw);1091 1092 return ret;1093}1094 1095static int atmel_hsmc_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,1096 int oob_required, int page)1097{1098 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,1099 false);1100}1101 1102static int atmel_hsmc_nand_pmecc_read_page_raw(struct nand_chip *chip,1103 u8 *buf, int oob_required,1104 int page)1105{1106 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,1107 true);1108}1109 1110static int atmel_nand_pmecc_init(struct nand_chip *chip)1111{1112 const struct nand_ecc_props *requirements =1113 nanddev_get_ecc_requirements(&chip->base);1114 struct mtd_info *mtd = nand_to_mtd(chip);1115 struct nand_device *nanddev = mtd_to_nanddev(mtd);1116 struct atmel_nand *nand = to_atmel_nand(chip);1117 struct atmel_nand_controller *nc;1118 struct atmel_pmecc_user_req req;1119 1120 nc = to_nand_controller(chip->controller);1121 1122 if (!nc->pmecc) {1123 dev_err(nc->dev, "HW ECC not supported\n");1124 return -ENOTSUPP;1125 }1126 1127 if (nc->caps->legacy_of_bindings) {1128 u32 val;1129 1130 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",1131 &val))1132 chip->ecc.strength = val;1133 1134 if (!of_property_read_u32(nc->dev->of_node,1135 "atmel,pmecc-sector-size",1136 &val))1137 chip->ecc.size = val;1138 }1139 1140 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH)1141 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;1142 else if (chip->ecc.strength)1143 req.ecc.strength = chip->ecc.strength;1144 else if (requirements->strength)1145 req.ecc.strength = requirements->strength;1146 else1147 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;1148 1149 if (chip->ecc.size)1150 req.ecc.sectorsize = chip->ecc.size;1151 else if (requirements->step_size)1152 req.ecc.sectorsize = requirements->step_size;1153 else1154 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;1155 1156 req.pagesize = mtd->writesize;1157 req.oobsize = mtd->oobsize;1158 1159 if (mtd->writesize <= 512) {1160 req.ecc.bytes = 4;1161 req.ecc.ooboffset = 0;1162 } else {1163 req.ecc.bytes = mtd->oobsize - 2;1164 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;1165 }1166 1167 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);1168 if (IS_ERR(nand->pmecc))1169 return PTR_ERR(nand->pmecc);1170 1171 chip->ecc.algo = NAND_ECC_ALGO_BCH;1172 chip->ecc.size = req.ecc.sectorsize;1173 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;1174 chip->ecc.strength = req.ecc.strength;1175 1176 chip->options |= NAND_NO_SUBPAGE_WRITE;1177 1178 mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());1179 1180 return 0;1181}1182 1183static int atmel_nand_ecc_init(struct nand_chip *chip)1184{1185 struct atmel_nand_controller *nc;1186 int ret;1187 1188 nc = to_nand_controller(chip->controller);1189 1190 switch (chip->ecc.engine_type) {1191 case NAND_ECC_ENGINE_TYPE_NONE:1192 case NAND_ECC_ENGINE_TYPE_SOFT:1193 /*1194 * Nothing to do, the core will initialize everything for us.1195 */1196 break;1197 1198 case NAND_ECC_ENGINE_TYPE_ON_HOST:1199 ret = atmel_nand_pmecc_init(chip);1200 if (ret)1201 return ret;1202 1203 chip->ecc.read_page = atmel_nand_pmecc_read_page;1204 chip->ecc.write_page = atmel_nand_pmecc_write_page;1205 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;1206 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;1207 break;1208 1209 default:1210 /* Other modes are not supported. */1211 dev_err(nc->dev, "Unsupported ECC mode: %d\n",1212 chip->ecc.engine_type);1213 return -ENOTSUPP;1214 }1215 1216 return 0;1217}1218 1219static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)1220{1221 int ret;1222 1223 ret = atmel_nand_ecc_init(chip);1224 if (ret)1225 return ret;1226 1227 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)1228 return 0;1229 1230 /* Adjust the ECC operations for the HSMC IP. */1231 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;1232 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;1233 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;1234 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;1235 1236 return 0;1237}1238 1239static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,1240 const struct nand_interface_config *conf,1241 struct atmel_smc_cs_conf *smcconf)1242{1243 u32 ncycles, totalcycles, timeps, mckperiodps;1244 struct atmel_nand_controller *nc;1245 int ret;1246 1247 nc = to_nand_controller(nand->base.controller);1248 1249 /* DDR interface not supported. */1250 if (!nand_interface_is_sdr(conf))1251 return -ENOTSUPP;1252 1253 /*1254 * tRC < 30ns implies EDO mode. This controller does not support this1255 * mode.1256 */1257 if (conf->timings.sdr.tRC_min < 30000)1258 return -ENOTSUPP;1259 1260 atmel_smc_cs_conf_init(smcconf);1261 1262 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);1263 mckperiodps *= 1000;1264 1265 /*1266 * Set write pulse timing. This one is easy to extract:1267 *1268 * NWE_PULSE = tWP1269 */1270 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);1271 totalcycles = ncycles;1272 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,1273 ncycles);1274 if (ret)1275 return ret;1276 1277 /*1278 * The write setup timing depends on the operation done on the NAND.1279 * All operations goes through the same data bus, but the operation1280 * type depends on the address we are writing to (ALE/CLE address1281 * lines).1282 * Since we have no way to differentiate the different operations at1283 * the SMC level, we must consider the worst case (the biggest setup1284 * time among all operation types):1285 *1286 * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE1287 */1288 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,1289 conf->timings.sdr.tALS_min);1290 timeps = max(timeps, conf->timings.sdr.tDS_min);1291 ncycles = DIV_ROUND_UP(timeps, mckperiodps);1292 ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;1293 totalcycles += ncycles;1294 ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,1295 ncycles);1296 if (ret)1297 return ret;1298 1299 /*1300 * As for the write setup timing, the write hold timing depends on the1301 * operation done on the NAND:1302 *1303 * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)1304 */1305 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,1306 conf->timings.sdr.tALH_min);1307 timeps = max3(timeps, conf->timings.sdr.tDH_min,1308 conf->timings.sdr.tWH_min);1309 ncycles = DIV_ROUND_UP(timeps, mckperiodps);1310 totalcycles += ncycles;1311 1312 /*1313 * The write cycle timing is directly matching tWC, but is also1314 * dependent on the other timings on the setup and hold timings we1315 * calculated earlier, which gives:1316 *1317 * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)1318 */1319 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);1320 ncycles = max(totalcycles, ncycles);1321 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,1322 ncycles);1323 if (ret)1324 return ret;1325 1326 /*1327 * We don't want the CS line to be toggled between each byte/word1328 * transfer to the NAND. The only way to guarantee that is to have the1329 * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:1330 *1331 * NCS_WR_PULSE = NWE_CYCLE1332 */1333 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,1334 ncycles);1335 if (ret)1336 return ret;1337 1338 /*1339 * As for the write setup timing, the read hold timing depends on the1340 * operation done on the NAND:1341 *1342 * NRD_HOLD = max(tREH, tRHOH)1343 */1344 timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);1345 ncycles = DIV_ROUND_UP(timeps, mckperiodps);1346 totalcycles = ncycles;1347 1348 /*1349 * TDF = tRHZ - NRD_HOLD1350 */1351 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);1352 ncycles -= totalcycles;1353 1354 /*1355 * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and1356 * we might end up with a config that does not fit in the TDF field.1357 * Just take the max value in this case and hope that the NAND is more1358 * tolerant than advertised.1359 */1360 if (ncycles > ATMEL_SMC_MODE_TDF_MAX)1361 ncycles = ATMEL_SMC_MODE_TDF_MAX;1362 else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)1363 ncycles = ATMEL_SMC_MODE_TDF_MIN;1364 1365 smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |1366 ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;1367 1368 /*1369 * Read pulse timing directly matches tRP:1370 *1371 * NRD_PULSE = tRP1372 */1373 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);1374 totalcycles += ncycles;1375 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,1376 ncycles);1377 if (ret)1378 return ret;1379 1380 /*1381 * The read cycle timing is directly matching tRC, but is also1382 * dependent on the setup and hold timings we calculated earlier,1383 * which gives:1384 *1385 * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)1386 *1387 * NRD_SETUP is always 0.1388 */1389 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);1390 ncycles = max(totalcycles, ncycles);1391 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,1392 ncycles);1393 if (ret)1394 return ret;1395 1396 /*1397 * We don't want the CS line to be toggled between each byte/word1398 * transfer from the NAND. The only way to guarantee that is to have1399 * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:1400 *1401 * NCS_RD_PULSE = NRD_CYCLE1402 */1403 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,1404 ncycles);1405 if (ret)1406 return ret;1407 1408 /* Txxx timings are directly matching tXXX ones. */1409 ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);1410 ret = atmel_smc_cs_conf_set_timing(smcconf,1411 ATMEL_HSMC_TIMINGS_TCLR_SHIFT,1412 ncycles);1413 if (ret)1414 return ret;1415 1416 ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);1417 ret = atmel_smc_cs_conf_set_timing(smcconf,1418 ATMEL_HSMC_TIMINGS_TADL_SHIFT,1419 ncycles);1420 /*1421 * Version 4 of the ONFI spec mandates that tADL be at least 4001422 * nanoseconds, but, depending on the master clock rate, 400 ns may not1423 * fit in the tADL field of the SMC reg. We need to relax the check and1424 * accept the -ERANGE return code.1425 *1426 * Note that previous versions of the ONFI spec had a lower tADL_min1427 * (100 or 200 ns). It's not clear why this timing constraint got1428 * increased but it seems most NANDs are fine with values lower than1429 * 400ns, so we should be safe.1430 */1431 if (ret && ret != -ERANGE)1432 return ret;1433 1434 ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);1435 ret = atmel_smc_cs_conf_set_timing(smcconf,1436 ATMEL_HSMC_TIMINGS_TAR_SHIFT,1437 ncycles);1438 if (ret)1439 return ret;1440 1441 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);1442 ret = atmel_smc_cs_conf_set_timing(smcconf,1443 ATMEL_HSMC_TIMINGS_TRR_SHIFT,1444 ncycles);1445 if (ret)1446 return ret;1447 1448 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);1449 ret = atmel_smc_cs_conf_set_timing(smcconf,1450 ATMEL_HSMC_TIMINGS_TWB_SHIFT,1451 ncycles);1452 if (ret)1453 return ret;1454 1455 /* Attach the CS line to the NFC logic. */1456 smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;1457 1458 /* Set the appropriate data bus width. */1459 if (nand->base.options & NAND_BUSWIDTH_16)1460 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;1461 1462 /* Operate in NRD/NWE READ/WRITEMODE. */1463 smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |1464 ATMEL_SMC_MODE_WRITEMODE_NWE;1465 1466 return 0;1467}1468 1469static int atmel_smc_nand_setup_interface(struct atmel_nand *nand,1470 int csline,1471 const struct nand_interface_config *conf)1472{1473 struct atmel_nand_controller *nc;1474 struct atmel_smc_cs_conf smcconf;1475 struct atmel_nand_cs *cs;1476 int ret;1477 1478 nc = to_nand_controller(nand->base.controller);1479 1480 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);1481 if (ret)1482 return ret;1483 1484 if (csline == NAND_DATA_IFACE_CHECK_ONLY)1485 return 0;1486 1487 cs = &nand->cs[csline];1488 cs->smcconf = smcconf;1489 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);1490 1491 return 0;1492}1493 1494static int atmel_hsmc_nand_setup_interface(struct atmel_nand *nand,1495 int csline,1496 const struct nand_interface_config *conf)1497{1498 struct atmel_hsmc_nand_controller *nc;1499 struct atmel_smc_cs_conf smcconf;1500 struct atmel_nand_cs *cs;1501 int ret;1502 1503 nc = to_hsmc_nand_controller(nand->base.controller);1504 1505 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);1506 if (ret)1507 return ret;1508 1509 if (csline == NAND_DATA_IFACE_CHECK_ONLY)1510 return 0;1511 1512 cs = &nand->cs[csline];1513 cs->smcconf = smcconf;1514 1515 if (cs->rb.type == ATMEL_NAND_NATIVE_RB)1516 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);1517 1518 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,1519 &cs->smcconf);1520 1521 return 0;1522}1523 1524static int atmel_nand_setup_interface(struct nand_chip *chip, int csline,1525 const struct nand_interface_config *conf)1526{1527 struct atmel_nand *nand = to_atmel_nand(chip);1528 const struct nand_sdr_timings *sdr;1529 struct atmel_nand_controller *nc;1530 1531 sdr = nand_get_sdr_timings(conf);1532 if (IS_ERR(sdr))1533 return PTR_ERR(sdr);1534 1535 nc = to_nand_controller(nand->base.controller);1536 1537 if (csline >= nand->numcs ||1538 (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))1539 return -EINVAL;1540 1541 return nc->caps->ops->setup_interface(nand, csline, conf);1542}1543 1544static int atmel_nand_exec_op(struct nand_chip *chip,1545 const struct nand_operation *op,1546 bool check_only)1547{1548 struct atmel_nand *nand = to_atmel_nand(chip);1549 struct atmel_nand_controller *nc;1550 1551 nc = to_nand_controller(nand->base.controller);1552 1553 return nc->caps->ops->exec_op(nand, op, check_only);1554}1555 1556static void atmel_nand_init(struct atmel_nand_controller *nc,1557 struct atmel_nand *nand)1558{1559 struct nand_chip *chip = &nand->base;1560 struct mtd_info *mtd = nand_to_mtd(chip);1561 1562 mtd->dev.parent = nc->dev;1563 nand->base.controller = &nc->base;1564 1565 if (!nc->mck || !nc->caps->ops->setup_interface)1566 chip->options |= NAND_KEEP_TIMINGS;1567 1568 /*1569 * Use a bounce buffer when the buffer passed by the MTD user is not1570 * suitable for DMA.1571 */1572 if (nc->dmac)1573 chip->options |= NAND_USES_DMA;1574 1575 /* Default to HW ECC if pmecc is available. */1576 if (nc->pmecc)1577 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;1578}1579 1580static void atmel_smc_nand_init(struct atmel_nand_controller *nc,1581 struct atmel_nand *nand)1582{1583 struct nand_chip *chip = &nand->base;1584 struct atmel_smc_nand_controller *smc_nc;1585 int i;1586 1587 atmel_nand_init(nc, nand);1588 1589 smc_nc = to_smc_nand_controller(chip->controller);1590 if (!smc_nc->ebi_csa_regmap)1591 return;1592 1593 /* Attach the CS to the NAND Flash logic. */1594 for (i = 0; i < nand->numcs; i++)1595 regmap_update_bits(smc_nc->ebi_csa_regmap,1596 smc_nc->ebi_csa->offs,1597 BIT(nand->cs[i].id), BIT(nand->cs[i].id));1598 1599 if (smc_nc->ebi_csa->nfd0_on_d16)1600 regmap_update_bits(smc_nc->ebi_csa_regmap,1601 smc_nc->ebi_csa->offs,1602 smc_nc->ebi_csa->nfd0_on_d16,1603 smc_nc->ebi_csa->nfd0_on_d16);1604}1605 1606static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)1607{1608 struct nand_chip *chip = &nand->base;1609 struct mtd_info *mtd = nand_to_mtd(chip);1610 int ret;1611 1612 ret = mtd_device_unregister(mtd);1613 if (ret)1614 return ret;1615 1616 nand_cleanup(chip);1617 list_del(&nand->node);1618 1619 return 0;1620}1621 1622static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,1623 struct device_node *np,1624 int reg_cells)1625{1626 struct atmel_nand *nand;1627 struct gpio_desc *gpio;1628 int numcs, ret, i;1629 1630 numcs = of_property_count_elems_of_size(np, "reg",1631 reg_cells * sizeof(u32));1632 if (numcs < 1) {1633 dev_err(nc->dev, "Missing or invalid reg property\n");1634 return ERR_PTR(-EINVAL);1635 }1636 1637 nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL);1638 if (!nand)1639 return ERR_PTR(-ENOMEM);1640 1641 nand->numcs = numcs;1642 1643 gpio = devm_fwnode_gpiod_get(nc->dev, of_fwnode_handle(np),1644 "det", GPIOD_IN, "nand-det");1645 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {1646 dev_err(nc->dev,1647 "Failed to get detect gpio (err = %ld)\n",1648 PTR_ERR(gpio));1649 return ERR_CAST(gpio);1650 }1651 1652 if (!IS_ERR(gpio))1653 nand->cdgpio = gpio;1654 1655 for (i = 0; i < numcs; i++) {1656 struct resource res;1657 u32 val;1658 1659 ret = of_address_to_resource(np, 0, &res);1660 if (ret) {1661 dev_err(nc->dev, "Invalid reg property (err = %d)\n",1662 ret);1663 return ERR_PTR(ret);1664 }1665 1666 ret = of_property_read_u32_index(np, "reg", i * reg_cells,1667 &val);1668 if (ret) {1669 dev_err(nc->dev, "Invalid reg property (err = %d)\n",1670 ret);1671 return ERR_PTR(ret);1672 }1673 1674 nand->cs[i].id = val;1675 1676 nand->cs[i].io.dma = res.start;1677 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);1678 if (IS_ERR(nand->cs[i].io.virt))1679 return ERR_CAST(nand->cs[i].io.virt);1680 1681 if (!of_property_read_u32(np, "atmel,rb", &val)) {1682 if (val > ATMEL_NFC_MAX_RB_ID)1683 return ERR_PTR(-EINVAL);1684 1685 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;1686 nand->cs[i].rb.id = val;1687 } else {1688 gpio = devm_fwnode_gpiod_get_index(nc->dev,1689 of_fwnode_handle(np),1690 "rb", i, GPIOD_IN,1691 "nand-rb");1692 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {1693 dev_err(nc->dev,1694 "Failed to get R/B gpio (err = %ld)\n",1695 PTR_ERR(gpio));1696 return ERR_CAST(gpio);1697 }1698 1699 if (!IS_ERR(gpio)) {1700 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;1701 nand->cs[i].rb.gpio = gpio;1702 }1703 }1704 1705 gpio = devm_fwnode_gpiod_get_index(nc->dev,1706 of_fwnode_handle(np),1707 "cs", i, GPIOD_OUT_HIGH,1708 "nand-cs");1709 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {1710 dev_err(nc->dev,1711 "Failed to get CS gpio (err = %ld)\n",1712 PTR_ERR(gpio));1713 return ERR_CAST(gpio);1714 }1715 1716 if (!IS_ERR(gpio))1717 nand->cs[i].csgpio = gpio;1718 }1719 1720 nand_set_flash_node(&nand->base, np);1721 1722 return nand;1723}1724 1725static int1726atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,1727 struct atmel_nand *nand)1728{1729 struct nand_chip *chip = &nand->base;1730 struct mtd_info *mtd = nand_to_mtd(chip);1731 int ret;1732 1733 /* No card inserted, skip this NAND. */1734 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {1735 dev_info(nc->dev, "No SmartMedia card inserted.\n");1736 return 0;1737 }1738 1739 nc->caps->ops->nand_init(nc, nand);1740 1741 ret = nand_scan(chip, nand->numcs);1742 if (ret) {1743 dev_err(nc->dev, "NAND scan failed: %d\n", ret);1744 return ret;1745 }1746 1747 ret = mtd_device_register(mtd, NULL, 0);1748 if (ret) {1749 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);1750 nand_cleanup(chip);1751 return ret;1752 }1753 1754 list_add_tail(&nand->node, &nc->chips);1755 1756 return 0;1757}1758 1759static int1760atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)1761{1762 struct atmel_nand *nand, *tmp;1763 int ret;1764 1765 list_for_each_entry_safe(nand, tmp, &nc->chips, node) {1766 ret = atmel_nand_controller_remove_nand(nand);1767 if (ret)1768 return ret;1769 }1770 1771 return 0;1772}1773 1774static int1775atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)1776{1777 struct device *dev = nc->dev;1778 struct platform_device *pdev = to_platform_device(dev);1779 struct atmel_nand *nand;1780 struct gpio_desc *gpio;1781 struct resource *res;1782 1783 /*1784 * Legacy bindings only allow connecting a single NAND with a unique CS1785 * line to the controller.1786 */1787 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),1788 GFP_KERNEL);1789 if (!nand)1790 return -ENOMEM;1791 1792 nand->numcs = 1;1793 1794 nand->cs[0].io.virt = devm_platform_get_and_ioremap_resource(pdev, 0, &res);1795 if (IS_ERR(nand->cs[0].io.virt))1796 return PTR_ERR(nand->cs[0].io.virt);1797 1798 nand->cs[0].io.dma = res->start;1799 1800 /*1801 * The old driver was hardcoding the CS id to 3 for all sama51802 * controllers. Since this id is only meaningful for the sama51803 * controller we can safely assign this id to 3 no matter the1804 * controller.1805 * If one wants to connect a NAND to a different CS line, he will1806 * have to use the new bindings.1807 */1808 nand->cs[0].id = 3;1809 1810 /* R/B GPIO. */1811 gpio = devm_gpiod_get_index_optional(dev, NULL, 0, GPIOD_IN);1812 if (IS_ERR(gpio)) {1813 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",1814 PTR_ERR(gpio));1815 return PTR_ERR(gpio);1816 }1817 1818 if (gpio) {1819 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;1820 nand->cs[0].rb.gpio = gpio;1821 }1822 1823 /* CS GPIO. */1824 gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);1825 if (IS_ERR(gpio)) {1826 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",1827 PTR_ERR(gpio));1828 return PTR_ERR(gpio);1829 }1830 1831 nand->cs[0].csgpio = gpio;1832 1833 /* Card detect GPIO. */1834 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);1835 if (IS_ERR(gpio)) {1836 dev_err(dev,1837 "Failed to get detect gpio (err = %ld)\n",1838 PTR_ERR(gpio));1839 return PTR_ERR(gpio);1840 }1841 1842 nand->cdgpio = gpio;1843 1844 nand_set_flash_node(&nand->base, nc->dev->of_node);1845 1846 return atmel_nand_controller_add_nand(nc, nand);1847}1848 1849static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)1850{1851 struct device_node *np, *nand_np;1852 struct device *dev = nc->dev;1853 int ret, reg_cells;1854 u32 val;1855 1856 /* We do not retrieve the SMC syscon when parsing old DTs. */1857 if (nc->caps->legacy_of_bindings)1858 return atmel_nand_controller_legacy_add_nands(nc);1859 1860 np = dev->of_node;1861 1862 ret = of_property_read_u32(np, "#address-cells", &val);1863 if (ret) {1864 dev_err(dev, "missing #address-cells property\n");1865 return ret;1866 }1867 1868 reg_cells = val;1869 1870 ret = of_property_read_u32(np, "#size-cells", &val);1871 if (ret) {1872 dev_err(dev, "missing #size-cells property\n");1873 return ret;1874 }1875 1876 reg_cells += val;1877 1878 for_each_child_of_node(np, nand_np) {1879 struct atmel_nand *nand;1880 1881 nand = atmel_nand_create(nc, nand_np, reg_cells);1882 if (IS_ERR(nand)) {1883 ret = PTR_ERR(nand);1884 goto err;1885 }1886 1887 ret = atmel_nand_controller_add_nand(nc, nand);1888 if (ret)1889 goto err;1890 }1891 1892 return 0;1893 1894err:1895 atmel_nand_controller_remove_nands(nc);1896 1897 return ret;1898}1899 1900static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)1901{1902 if (nc->dmac)1903 dma_release_channel(nc->dmac);1904 1905 clk_put(nc->mck);1906}1907 1908static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {1909 .offs = AT91SAM9260_MATRIX_EBICSA,1910};1911 1912static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {1913 .offs = AT91SAM9261_MATRIX_EBICSA,1914};1915 1916static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {1917 .offs = AT91SAM9263_MATRIX_EBI0CSA,1918};1919 1920static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {1921 .offs = AT91SAM9RL_MATRIX_EBICSA,1922};1923 1924static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {1925 .offs = AT91SAM9G45_MATRIX_EBICSA,1926};1927 1928static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {1929 .offs = AT91SAM9N12_MATRIX_EBICSA,1930};1931 1932static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {1933 .offs = AT91SAM9X5_MATRIX_EBICSA,1934};1935 1936static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {1937 .offs = AT91_SFR_CCFG_EBICSA,1938 .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,1939};1940 1941static const struct of_device_id __maybe_unused atmel_ebi_csa_regmap_of_ids[] = {1942 {1943 .compatible = "atmel,at91sam9260-matrix",1944 .data = &at91sam9260_ebi_csa,1945 },1946 {1947 .compatible = "atmel,at91sam9261-matrix",1948 .data = &at91sam9261_ebi_csa,1949 },1950 {1951 .compatible = "atmel,at91sam9263-matrix",1952 .data = &at91sam9263_ebi_csa,1953 },1954 {1955 .compatible = "atmel,at91sam9rl-matrix",1956 .data = &at91sam9rl_ebi_csa,1957 },1958 {1959 .compatible = "atmel,at91sam9g45-matrix",1960 .data = &at91sam9g45_ebi_csa,1961 },1962 {1963 .compatible = "atmel,at91sam9n12-matrix",1964 .data = &at91sam9n12_ebi_csa,1965 },1966 {1967 .compatible = "atmel,at91sam9x5-matrix",1968 .data = &at91sam9x5_ebi_csa,1969 },1970 {1971 .compatible = "microchip,sam9x60-sfr",1972 .data = &sam9x60_ebi_csa,1973 },1974 { /* sentinel */ },1975};1976 1977static int atmel_nand_attach_chip(struct nand_chip *chip)1978{1979 struct atmel_nand_controller *nc = to_nand_controller(chip->controller);1980 struct atmel_nand *nand = to_atmel_nand(chip);1981 struct mtd_info *mtd = nand_to_mtd(chip);1982 int ret;1983 1984 ret = nc->caps->ops->ecc_init(chip);1985 if (ret)1986 return ret;1987 1988 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {1989 /*1990 * We keep the MTD name unchanged to avoid breaking platforms1991 * where the MTD cmdline parser is used and the bootloader1992 * has not been updated to use the new naming scheme.1993 */1994 mtd->name = "atmel_nand";1995 } else if (!mtd->name) {1996 /*1997 * If the new bindings are used and the bootloader has not been1998 * updated to pass a new mtdparts parameter on the cmdline, you1999 * should define the following property in your nand node:2000 *2001 * label = "atmel_nand";2002 *2003 * This way, mtd->name will be set by the core when2004 * nand_set_flash_node() is called.2005 */2006 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,2007 "%s:nand.%d", dev_name(nc->dev),2008 nand->cs[0].id);2009 if (!mtd->name) {2010 dev_err(nc->dev, "Failed to allocate mtd->name\n");2011 return -ENOMEM;2012 }2013 }2014 2015 return 0;2016}2017 2018static const struct nand_controller_ops atmel_nand_controller_ops = {2019 .attach_chip = atmel_nand_attach_chip,2020 .setup_interface = atmel_nand_setup_interface,2021 .exec_op = atmel_nand_exec_op,2022};2023 2024static int atmel_nand_controller_init(struct atmel_nand_controller *nc,2025 struct platform_device *pdev,2026 const struct atmel_nand_controller_caps *caps)2027{2028 struct device *dev = &pdev->dev;2029 struct device_node *np = dev->of_node;2030 int ret;2031 2032 nand_controller_init(&nc->base);2033 nc->base.ops = &atmel_nand_controller_ops;2034 INIT_LIST_HEAD(&nc->chips);2035 nc->dev = dev;2036 nc->caps = caps;2037 2038 platform_set_drvdata(pdev, nc);2039 2040 nc->pmecc = devm_atmel_pmecc_get(dev);2041 if (IS_ERR(nc->pmecc))2042 return dev_err_probe(dev, PTR_ERR(nc->pmecc),2043 "Could not get PMECC object\n");2044 2045 if (nc->caps->has_dma && !atmel_nand_avoid_dma) {2046 dma_cap_mask_t mask;2047 2048 dma_cap_zero(mask);2049 dma_cap_set(DMA_MEMCPY, mask);2050 2051 nc->dmac = dma_request_channel(mask, NULL, NULL);2052 if (nc->dmac)2053 dev_info(nc->dev, "using %s for DMA transfers\n",2054 dma_chan_name(nc->dmac));2055 else2056 dev_err(nc->dev, "Failed to request DMA channel\n");2057 }2058 2059 /* We do not retrieve the SMC syscon when parsing old DTs. */2060 if (nc->caps->legacy_of_bindings)2061 return 0;2062 2063 nc->mck = of_clk_get(dev->parent->of_node, 0);2064 if (IS_ERR(nc->mck)) {2065 dev_err(dev, "Failed to retrieve MCK clk\n");2066 ret = PTR_ERR(nc->mck);2067 goto out_release_dma;2068 }2069 2070 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);2071 if (!np) {2072 dev_err(dev, "Missing or invalid atmel,smc property\n");2073 ret = -EINVAL;2074 goto out_release_dma;2075 }2076 2077 nc->smc = syscon_node_to_regmap(np);2078 of_node_put(np);2079 if (IS_ERR(nc->smc)) {2080 ret = PTR_ERR(nc->smc);2081 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);2082 goto out_release_dma;2083 }2084 2085 return 0;2086 2087out_release_dma:2088 if (nc->dmac)2089 dma_release_channel(nc->dmac);2090 2091 return ret;2092}2093 2094static int2095atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)2096{2097 struct device *dev = nc->base.dev;2098 const struct of_device_id *match;2099 struct device_node *np;2100 int ret;2101 2102 /* We do not retrieve the EBICSA regmap when parsing old DTs. */2103 if (nc->base.caps->legacy_of_bindings)2104 return 0;2105 2106 np = of_parse_phandle(dev->parent->of_node,2107 nc->base.caps->ebi_csa_regmap_name, 0);2108 if (!np)2109 return 0;2110 2111 match = of_match_node(atmel_ebi_csa_regmap_of_ids, np);2112 if (!match) {2113 of_node_put(np);2114 return 0;2115 }2116 2117 nc->ebi_csa_regmap = syscon_node_to_regmap(np);2118 of_node_put(np);2119 if (IS_ERR(nc->ebi_csa_regmap)) {2120 ret = PTR_ERR(nc->ebi_csa_regmap);2121 dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);2122 return ret;2123 }2124 2125 nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;2126 2127 /*2128 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI12129 * add 4 to ->ebi_csa->offs.2130 */2131 if (of_device_is_compatible(dev->parent->of_node,2132 "atmel,at91sam9263-ebi1"))2133 nc->ebi_csa->offs += 4;2134 2135 return 0;2136}2137 2138static int2139atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)2140{2141 struct regmap_config regmap_conf = {2142 .reg_bits = 32,2143 .val_bits = 32,2144 .reg_stride = 4,2145 };2146 2147 struct device *dev = nc->base.dev;2148 struct device_node *nand_np, *nfc_np;2149 void __iomem *iomem;2150 struct resource res;2151 int ret;2152 2153 nand_np = dev->of_node;2154 nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");2155 if (!nfc_np) {2156 dev_err(dev, "Could not find device node for sama5d3-nfc\n");2157 return -ENODEV;2158 }2159 2160 nc->clk = of_clk_get(nfc_np, 0);2161 if (IS_ERR(nc->clk)) {2162 ret = PTR_ERR(nc->clk);2163 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",2164 ret);2165 goto out;2166 }2167 2168 ret = clk_prepare_enable(nc->clk);2169 if (ret) {2170 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",2171 ret);2172 goto out;2173 }2174 2175 nc->irq = of_irq_get(nand_np, 0);2176 if (nc->irq <= 0) {2177 ret = nc->irq ?: -ENXIO;2178 if (ret != -EPROBE_DEFER)2179 dev_err(dev, "Failed to get IRQ number (err = %d)\n",2180 ret);2181 goto out;2182 }2183 2184 ret = of_address_to_resource(nfc_np, 0, &res);2185 if (ret) {2186 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",2187 ret);2188 goto out;2189 }2190 2191 iomem = devm_ioremap_resource(dev, &res);2192 if (IS_ERR(iomem)) {2193 ret = PTR_ERR(iomem);2194 goto out;2195 }2196 2197 regmap_conf.name = "nfc-io";2198 regmap_conf.max_register = resource_size(&res) - 4;2199 nc->io = devm_regmap_init_mmio(dev, iomem, ®map_conf);2200 if (IS_ERR(nc->io)) {2201 ret = PTR_ERR(nc->io);2202 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",2203 ret);2204 goto out;2205 }2206 2207 ret = of_address_to_resource(nfc_np, 1, &res);2208 if (ret) {2209 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",2210 ret);2211 goto out;2212 }2213 2214 iomem = devm_ioremap_resource(dev, &res);2215 if (IS_ERR(iomem)) {2216 ret = PTR_ERR(iomem);2217 goto out;2218 }2219 2220 regmap_conf.name = "smc";2221 regmap_conf.max_register = resource_size(&res) - 4;2222 nc->base.smc = devm_regmap_init_mmio(dev, iomem, ®map_conf);2223 if (IS_ERR(nc->base.smc)) {2224 ret = PTR_ERR(nc->base.smc);2225 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",2226 ret);2227 goto out;2228 }2229 2230 ret = of_address_to_resource(nfc_np, 2, &res);2231 if (ret) {2232 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",2233 ret);2234 goto out;2235 }2236 2237 nc->sram.virt = devm_ioremap_resource(dev, &res);2238 if (IS_ERR(nc->sram.virt)) {2239 ret = PTR_ERR(nc->sram.virt);2240 goto out;2241 }2242 2243 nc->sram.dma = res.start;2244 2245out:2246 of_node_put(nfc_np);2247 2248 return ret;2249}2250 2251static int2252atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)2253{2254 struct device *dev = nc->base.dev;2255 struct device_node *np;2256 int ret;2257 2258 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);2259 if (!np) {2260 dev_err(dev, "Missing or invalid atmel,smc property\n");2261 return -EINVAL;2262 }2263 2264 nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);2265 2266 nc->irq = of_irq_get(np, 0);2267 of_node_put(np);2268 if (nc->irq <= 0) {2269 ret = nc->irq ?: -ENXIO;2270 if (ret != -EPROBE_DEFER)2271 dev_err(dev, "Failed to get IRQ number (err = %d)\n",2272 ret);2273 return ret;2274 }2275 2276 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);2277 if (!np) {2278 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");2279 return -EINVAL;2280 }2281 2282 nc->io = syscon_node_to_regmap(np);2283 of_node_put(np);2284 if (IS_ERR(nc->io)) {2285 ret = PTR_ERR(nc->io);2286 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);2287 return ret;2288 }2289 2290 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,2291 "atmel,nfc-sram", 0);2292 if (!nc->sram.pool) {2293 dev_err(nc->base.dev, "Missing SRAM\n");2294 return -ENOMEM;2295 }2296 2297 nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool,2298 ATMEL_NFC_SRAM_SIZE,2299 &nc->sram.dma);2300 if (!nc->sram.virt) {2301 dev_err(nc->base.dev,2302 "Could not allocate memory from the NFC SRAM pool\n");2303 return -ENOMEM;2304 }2305 2306 return 0;2307}2308 2309static int2310atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)2311{2312 struct atmel_hsmc_nand_controller *hsmc_nc;2313 int ret;2314 2315 ret = atmel_nand_controller_remove_nands(nc);2316 if (ret)2317 return ret;2318 2319 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);2320 regmap_write(hsmc_nc->base.smc, ATMEL_HSMC_NFC_CTRL,2321 ATMEL_HSMC_NFC_CTRL_DIS);2322 2323 if (hsmc_nc->sram.pool)2324 gen_pool_free(hsmc_nc->sram.pool,2325 (unsigned long)hsmc_nc->sram.virt,2326 ATMEL_NFC_SRAM_SIZE);2327 2328 if (hsmc_nc->clk) {2329 clk_disable_unprepare(hsmc_nc->clk);2330 clk_put(hsmc_nc->clk);2331 }2332 2333 atmel_nand_controller_cleanup(nc);2334 2335 return 0;2336}2337 2338static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,2339 const struct atmel_nand_controller_caps *caps)2340{2341 struct device *dev = &pdev->dev;2342 struct atmel_hsmc_nand_controller *nc;2343 int ret;2344 2345 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);2346 if (!nc)2347 return -ENOMEM;2348 2349 ret = atmel_nand_controller_init(&nc->base, pdev, caps);2350 if (ret)2351 return ret;2352 2353 if (caps->legacy_of_bindings)2354 ret = atmel_hsmc_nand_controller_legacy_init(nc);2355 else2356 ret = atmel_hsmc_nand_controller_init(nc);2357 2358 if (ret)2359 return ret;2360 2361 /* Make sure all irqs are masked before registering our IRQ handler. */2362 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);2363 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,2364 IRQF_SHARED, "nfc", nc);2365 if (ret) {2366 dev_err(dev,2367 "Could not get register NFC interrupt handler (err = %d)\n",2368 ret);2369 goto err;2370 }2371 2372 /* Initial NFC configuration. */2373 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,2374 ATMEL_HSMC_NFC_CFG_DTO_MAX);2375 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,2376 ATMEL_HSMC_NFC_CTRL_EN);2377 2378 ret = atmel_nand_controller_add_nands(&nc->base);2379 if (ret)2380 goto err;2381 2382 return 0;2383 2384err:2385 atmel_hsmc_nand_controller_remove(&nc->base);2386 2387 return ret;2388}2389 2390static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {2391 .probe = atmel_hsmc_nand_controller_probe,2392 .remove = atmel_hsmc_nand_controller_remove,2393 .ecc_init = atmel_hsmc_nand_ecc_init,2394 .nand_init = atmel_nand_init,2395 .setup_interface = atmel_hsmc_nand_setup_interface,2396 .exec_op = atmel_hsmc_nand_exec_op,2397};2398 2399static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {2400 .has_dma = true,2401 .ale_offs = BIT(21),2402 .cle_offs = BIT(22),2403 .ops = &atmel_hsmc_nc_ops,2404};2405 2406/* Only used to parse old bindings. */2407static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {2408 .has_dma = true,2409 .ale_offs = BIT(21),2410 .cle_offs = BIT(22),2411 .ops = &atmel_hsmc_nc_ops,2412 .legacy_of_bindings = true,2413};2414 2415static int atmel_smc_nand_controller_probe(struct platform_device *pdev,2416 const struct atmel_nand_controller_caps *caps)2417{2418 struct device *dev = &pdev->dev;2419 struct atmel_smc_nand_controller *nc;2420 int ret;2421 2422 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);2423 if (!nc)2424 return -ENOMEM;2425 2426 ret = atmel_nand_controller_init(&nc->base, pdev, caps);2427 if (ret)2428 return ret;2429 2430 ret = atmel_smc_nand_controller_init(nc);2431 if (ret)2432 return ret;2433 2434 return atmel_nand_controller_add_nands(&nc->base);2435}2436 2437static int2438atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)2439{2440 int ret;2441 2442 ret = atmel_nand_controller_remove_nands(nc);2443 if (ret)2444 return ret;2445 2446 atmel_nand_controller_cleanup(nc);2447 2448 return 0;2449}2450 2451/*2452 * The SMC reg layout of at91rm9200 is completely different which prevents us2453 * from re-using atmel_smc_nand_setup_interface() for the2454 * ->setup_interface() hook.2455 * At this point, there's no support for the at91rm9200 SMC IP, so we leave2456 * ->setup_interface() unassigned.2457 */2458static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {2459 .probe = atmel_smc_nand_controller_probe,2460 .remove = atmel_smc_nand_controller_remove,2461 .ecc_init = atmel_nand_ecc_init,2462 .nand_init = atmel_smc_nand_init,2463 .exec_op = atmel_smc_nand_exec_op,2464};2465 2466static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {2467 .ale_offs = BIT(21),2468 .cle_offs = BIT(22),2469 .ebi_csa_regmap_name = "atmel,matrix",2470 .ops = &at91rm9200_nc_ops,2471};2472 2473static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {2474 .probe = atmel_smc_nand_controller_probe,2475 .remove = atmel_smc_nand_controller_remove,2476 .ecc_init = atmel_nand_ecc_init,2477 .nand_init = atmel_smc_nand_init,2478 .setup_interface = atmel_smc_nand_setup_interface,2479 .exec_op = atmel_smc_nand_exec_op,2480};2481 2482static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {2483 .ale_offs = BIT(21),2484 .cle_offs = BIT(22),2485 .ebi_csa_regmap_name = "atmel,matrix",2486 .ops = &atmel_smc_nc_ops,2487};2488 2489static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {2490 .ale_offs = BIT(22),2491 .cle_offs = BIT(21),2492 .ebi_csa_regmap_name = "atmel,matrix",2493 .ops = &atmel_smc_nc_ops,2494};2495 2496static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {2497 .has_dma = true,2498 .ale_offs = BIT(21),2499 .cle_offs = BIT(22),2500 .ebi_csa_regmap_name = "atmel,matrix",2501 .ops = &atmel_smc_nc_ops,2502};2503 2504static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {2505 .has_dma = true,2506 .ale_offs = BIT(21),2507 .cle_offs = BIT(22),2508 .ebi_csa_regmap_name = "microchip,sfr",2509 .ops = &atmel_smc_nc_ops,2510};2511 2512/* Only used to parse old bindings. */2513static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {2514 .ale_offs = BIT(21),2515 .cle_offs = BIT(22),2516 .ops = &atmel_smc_nc_ops,2517 .legacy_of_bindings = true,2518};2519 2520static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {2521 .ale_offs = BIT(22),2522 .cle_offs = BIT(21),2523 .ops = &atmel_smc_nc_ops,2524 .legacy_of_bindings = true,2525};2526 2527static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {2528 .has_dma = true,2529 .ale_offs = BIT(21),2530 .cle_offs = BIT(22),2531 .ops = &atmel_smc_nc_ops,2532 .legacy_of_bindings = true,2533};2534 2535static const struct of_device_id atmel_nand_controller_of_ids[] = {2536 {2537 .compatible = "atmel,at91rm9200-nand-controller",2538 .data = &atmel_rm9200_nc_caps,2539 },2540 {2541 .compatible = "atmel,at91sam9260-nand-controller",2542 .data = &atmel_sam9260_nc_caps,2543 },2544 {2545 .compatible = "atmel,at91sam9261-nand-controller",2546 .data = &atmel_sam9261_nc_caps,2547 },2548 {2549 .compatible = "atmel,at91sam9g45-nand-controller",2550 .data = &atmel_sam9g45_nc_caps,2551 },2552 {2553 .compatible = "atmel,sama5d3-nand-controller",2554 .data = &atmel_sama5_nc_caps,2555 },2556 {2557 .compatible = "microchip,sam9x60-nand-controller",2558 .data = µchip_sam9x60_nc_caps,2559 },2560 /* Support for old/deprecated bindings: */2561 {2562 .compatible = "atmel,at91rm9200-nand",2563 .data = &atmel_rm9200_nand_caps,2564 },2565 {2566 .compatible = "atmel,sama5d4-nand",2567 .data = &atmel_rm9200_nand_caps,2568 },2569 {2570 .compatible = "atmel,sama5d2-nand",2571 .data = &atmel_rm9200_nand_caps,2572 },2573 { /* sentinel */ },2574};2575MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);2576 2577static int atmel_nand_controller_probe(struct platform_device *pdev)2578{2579 const struct atmel_nand_controller_caps *caps;2580 2581 if (pdev->id_entry)2582 caps = (void *)pdev->id_entry->driver_data;2583 else2584 caps = of_device_get_match_data(&pdev->dev);2585 2586 if (!caps) {2587 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");2588 return -EINVAL;2589 }2590 2591 if (caps->legacy_of_bindings) {2592 struct device_node *nfc_node;2593 u32 ale_offs = 21;2594 2595 /*2596 * If we are parsing legacy DT props and the DT contains a2597 * valid NFC node, forward the request to the sama5 logic.2598 */2599 nfc_node = of_get_compatible_child(pdev->dev.of_node,2600 "atmel,sama5d3-nfc");2601 if (nfc_node) {2602 caps = &atmel_sama5_nand_caps;2603 of_node_put(nfc_node);2604 }2605 2606 /*2607 * Even if the compatible says we are dealing with an2608 * at91rm9200 controller, the atmel,nand-has-dma specify that2609 * this controller supports DMA, which means we are in fact2610 * dealing with an at91sam9g45+ controller.2611 */2612 if (!caps->has_dma &&2613 of_property_read_bool(pdev->dev.of_node,2614 "atmel,nand-has-dma"))2615 caps = &atmel_sam9g45_nand_caps;2616 2617 /*2618 * All SoCs except the at91sam9261 are assigning ALE to A21 and2619 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're2620 * actually dealing with an at91sam9261 controller.2621 */2622 of_property_read_u32(pdev->dev.of_node,2623 "atmel,nand-addr-offset", &ale_offs);2624 if (ale_offs != 21)2625 caps = &atmel_sam9261_nand_caps;2626 }2627 2628 return caps->ops->probe(pdev, caps);2629}2630 2631static void atmel_nand_controller_remove(struct platform_device *pdev)2632{2633 struct atmel_nand_controller *nc = platform_get_drvdata(pdev);2634 2635 WARN_ON(nc->caps->ops->remove(nc));2636}2637 2638static __maybe_unused int atmel_nand_controller_resume(struct device *dev)2639{2640 struct atmel_nand_controller *nc = dev_get_drvdata(dev);2641 struct atmel_nand *nand;2642 2643 if (nc->pmecc)2644 atmel_pmecc_reset(nc->pmecc);2645 2646 list_for_each_entry(nand, &nc->chips, node) {2647 int i;2648 2649 for (i = 0; i < nand->numcs; i++)2650 nand_reset(&nand->base, i);2651 }2652 2653 return 0;2654}2655 2656static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,2657 atmel_nand_controller_resume);2658 2659static struct platform_driver atmel_nand_controller_driver = {2660 .driver = {2661 .name = "atmel-nand-controller",2662 .of_match_table = atmel_nand_controller_of_ids,2663 .pm = &atmel_nand_controller_pm_ops,2664 },2665 .probe = atmel_nand_controller_probe,2666 .remove_new = atmel_nand_controller_remove,2667};2668module_platform_driver(atmel_nand_controller_driver);2669 2670MODULE_LICENSE("GPL");2671MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");2672MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");2673MODULE_ALIAS("platform:atmel-nand-controller");2674