brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright © 2010-2015 Broadcom Corporation4 */5 6#include <linux/clk.h>7#include <linux/module.h>8#include <linux/init.h>9#include <linux/delay.h>10#include <linux/device.h>11#include <linux/platform_device.h>12#include <linux/platform_data/brcmnand.h>13#include <linux/err.h>14#include <linux/completion.h>15#include <linux/interrupt.h>16#include <linux/spinlock.h>17#include <linux/dma-mapping.h>18#include <linux/ioport.h>19#include <linux/bug.h>20#include <linux/kernel.h>21#include <linux/bitops.h>22#include <linux/mm.h>23#include <linux/mtd/mtd.h>24#include <linux/mtd/rawnand.h>25#include <linux/mtd/partitions.h>26#include <linux/of.h>27#include <linux/of_platform.h>28#include <linux/slab.h>29#include <linux/static_key.h>30#include <linux/list.h>31#include <linux/log2.h>32 33#include "brcmnand.h"34 35/*36 * This flag controls if WP stays on between erase/write commands to mitigate37 * flash corruption due to power glitches. Values:38 * 0: NAND_WP is not used or not available39 * 1: NAND_WP is set by default, cleared for erase/write operations40 * 2: NAND_WP is always cleared41 */42static int wp_on = 1;43module_param(wp_on, int, 0444);44 45/***********************************************************************46 * Definitions47 ***********************************************************************/48 49#define DRV_NAME			"brcmnand"50 51#define CMD_NULL			0x0052#define CMD_PAGE_READ			0x0153#define CMD_SPARE_AREA_READ		0x0254#define CMD_STATUS_READ			0x0355#define CMD_PROGRAM_PAGE		0x0456#define CMD_PROGRAM_SPARE_AREA		0x0557#define CMD_COPY_BACK			0x0658#define CMD_DEVICE_ID_READ		0x0759#define CMD_BLOCK_ERASE			0x0860#define CMD_FLASH_RESET			0x0961#define CMD_BLOCKS_LOCK			0x0a62#define CMD_BLOCKS_LOCK_DOWN		0x0b63#define CMD_BLOCKS_UNLOCK		0x0c64#define CMD_READ_BLOCKS_LOCK_STATUS	0x0d65#define CMD_PARAMETER_READ		0x0e66#define CMD_PARAMETER_CHANGE_COL	0x0f67#define CMD_LOW_LEVEL_OP		0x1068 69struct brcm_nand_dma_desc {70	u32 next_desc;71	u32 next_desc_ext;72	u32 cmd_irq;73	u32 dram_addr;74	u32 dram_addr_ext;75	u32 tfr_len;76	u32 total_len;77	u32 flash_addr;78	u32 flash_addr_ext;79	u32 cs;80	u32 pad2[5];81	u32 status_valid;82} __packed;83 84/* Bitfields for brcm_nand_dma_desc::status_valid */85#define FLASH_DMA_ECC_ERROR	(1 << 8)86#define FLASH_DMA_CORR_ERROR	(1 << 9)87 88/* Bitfields for DMA_MODE */89#define FLASH_DMA_MODE_STOP_ON_ERROR	BIT(1) /* stop in Uncorr ECC error */90#define FLASH_DMA_MODE_MODE		BIT(0) /* link list */91#define FLASH_DMA_MODE_MASK		(FLASH_DMA_MODE_STOP_ON_ERROR |	\92						FLASH_DMA_MODE_MODE)93 94/* 512B flash cache in the NAND controller HW */95#define FC_SHIFT		9U96#define FC_BYTES		512U97#define FC_WORDS		(FC_BYTES >> 2)98 99#define BRCMNAND_MIN_PAGESIZE	512100#define BRCMNAND_MIN_BLOCKSIZE	(8 * 1024)101#define BRCMNAND_MIN_DEVSIZE	(4ULL * 1024 * 1024)102 103#define NAND_CTRL_RDY			(INTFC_CTLR_READY | INTFC_FLASH_READY)104#define NAND_POLL_STATUS_TIMEOUT_MS	100105 106#define EDU_CMD_WRITE          0x00107#define EDU_CMD_READ           0x01108#define EDU_STATUS_ACTIVE      BIT(0)109#define EDU_ERR_STATUS_ERRACK  BIT(0)110#define EDU_DONE_MASK		GENMASK(1, 0)111 112#define EDU_CONFIG_MODE_NAND   BIT(0)113#define EDU_CONFIG_SWAP_BYTE   BIT(1)114#ifdef CONFIG_CPU_BIG_ENDIAN115#define EDU_CONFIG_SWAP_CFG     EDU_CONFIG_SWAP_BYTE116#else117#define EDU_CONFIG_SWAP_CFG     0118#endif119 120/* edu registers */121enum edu_reg {122	EDU_CONFIG = 0,123	EDU_DRAM_ADDR,124	EDU_EXT_ADDR,125	EDU_LENGTH,126	EDU_CMD,127	EDU_STOP,128	EDU_STATUS,129	EDU_DONE,130	EDU_ERR_STATUS,131};132 133static const u16  edu_regs[] = {134	[EDU_CONFIG] = 0x00,135	[EDU_DRAM_ADDR] = 0x04,136	[EDU_EXT_ADDR] = 0x08,137	[EDU_LENGTH] = 0x0c,138	[EDU_CMD] = 0x10,139	[EDU_STOP] = 0x14,140	[EDU_STATUS] = 0x18,141	[EDU_DONE] = 0x1c,142	[EDU_ERR_STATUS] = 0x20,143};144 145/* flash_dma registers */146enum flash_dma_reg {147	FLASH_DMA_REVISION = 0,148	FLASH_DMA_FIRST_DESC,149	FLASH_DMA_FIRST_DESC_EXT,150	FLASH_DMA_CTRL,151	FLASH_DMA_MODE,152	FLASH_DMA_STATUS,153	FLASH_DMA_INTERRUPT_DESC,154	FLASH_DMA_INTERRUPT_DESC_EXT,155	FLASH_DMA_ERROR_STATUS,156	FLASH_DMA_CURRENT_DESC,157	FLASH_DMA_CURRENT_DESC_EXT,158};159 160/* flash_dma registers v0*/161static const u16 flash_dma_regs_v0[] = {162	[FLASH_DMA_REVISION]		= 0x00,163	[FLASH_DMA_FIRST_DESC]		= 0x04,164	[FLASH_DMA_CTRL]		= 0x08,165	[FLASH_DMA_MODE]		= 0x0c,166	[FLASH_DMA_STATUS]		= 0x10,167	[FLASH_DMA_INTERRUPT_DESC]	= 0x14,168	[FLASH_DMA_ERROR_STATUS]	= 0x18,169	[FLASH_DMA_CURRENT_DESC]	= 0x1c,170};171 172/* flash_dma registers v1*/173static const u16 flash_dma_regs_v1[] = {174	[FLASH_DMA_REVISION]		= 0x00,175	[FLASH_DMA_FIRST_DESC]		= 0x04,176	[FLASH_DMA_FIRST_DESC_EXT]	= 0x08,177	[FLASH_DMA_CTRL]		= 0x0c,178	[FLASH_DMA_MODE]		= 0x10,179	[FLASH_DMA_STATUS]		= 0x14,180	[FLASH_DMA_INTERRUPT_DESC]	= 0x18,181	[FLASH_DMA_INTERRUPT_DESC_EXT]	= 0x1c,182	[FLASH_DMA_ERROR_STATUS]	= 0x20,183	[FLASH_DMA_CURRENT_DESC]	= 0x24,184	[FLASH_DMA_CURRENT_DESC_EXT]	= 0x28,185};186 187/* flash_dma registers v4 */188static const u16 flash_dma_regs_v4[] = {189	[FLASH_DMA_REVISION]		= 0x00,190	[FLASH_DMA_FIRST_DESC]		= 0x08,191	[FLASH_DMA_FIRST_DESC_EXT]	= 0x0c,192	[FLASH_DMA_CTRL]		= 0x10,193	[FLASH_DMA_MODE]		= 0x14,194	[FLASH_DMA_STATUS]		= 0x18,195	[FLASH_DMA_INTERRUPT_DESC]	= 0x20,196	[FLASH_DMA_INTERRUPT_DESC_EXT]	= 0x24,197	[FLASH_DMA_ERROR_STATUS]	= 0x28,198	[FLASH_DMA_CURRENT_DESC]	= 0x30,199	[FLASH_DMA_CURRENT_DESC_EXT]	= 0x34,200};201 202/* Controller feature flags */203enum {204	BRCMNAND_HAS_1K_SECTORS			= BIT(0),205	BRCMNAND_HAS_PREFETCH			= BIT(1),206	BRCMNAND_HAS_CACHE_MODE			= BIT(2),207	BRCMNAND_HAS_WP				= BIT(3),208};209 210struct brcmnand_host;211 212static DEFINE_STATIC_KEY_FALSE(brcmnand_soc_has_ops_key);213 214struct brcmnand_controller {215	struct device		*dev;216	struct nand_controller	controller;217	void __iomem		*nand_base;218	void __iomem		*nand_fc; /* flash cache */219	void __iomem		*flash_dma_base;220	int			irq;221	unsigned int		dma_irq;222	int			nand_version;223 224	/* Some SoCs provide custom interrupt status register(s) */225	struct brcmnand_soc	*soc;226 227	/* Some SoCs have a gateable clock for the controller */228	struct clk		*clk;229 230	int			cmd_pending;231	bool			dma_pending;232	bool                    edu_pending;233	struct completion	done;234	struct completion	dma_done;235	struct completion       edu_done;236 237	/* List of NAND hosts (one for each chip-select) */238	struct list_head host_list;239 240	/* EDU info, per-transaction */241	const u16               *edu_offsets;242	void __iomem            *edu_base;243	int			edu_irq;244	int                     edu_count;245	u64                     edu_dram_addr;246	u32                     edu_ext_addr;247	u32                     edu_cmd;248	u32                     edu_config;249	int			sas; /* spare area size, per flash cache */250	int			sector_size_1k;251	u8			*oob;252 253	/* flash_dma reg */254	const u16		*flash_dma_offsets;255	struct brcm_nand_dma_desc *dma_desc;256	dma_addr_t		dma_pa;257 258	int (*dma_trans)(struct brcmnand_host *host, u64 addr, u32 *buf,259			 u8 *oob, u32 len, u8 dma_cmd);260 261	/* in-memory cache of the FLASH_CACHE, used only for some commands */262	u8			flash_cache[FC_BYTES];263 264	/* Controller revision details */265	const u16		*reg_offsets;266	unsigned int		reg_spacing; /* between CS1, CS2, ... regs */267	const u8		*cs_offsets; /* within each chip-select */268	const u8		*cs0_offsets; /* within CS0, if different */269	unsigned int		max_block_size;270	const unsigned int	*block_sizes;271	unsigned int		max_page_size;272	const unsigned int	*page_sizes;273	unsigned int		page_size_shift;274	unsigned int		max_oob;275	u32			ecc_level_shift;276	u32			features;277 278	/* for low-power standby/resume only */279	u32			nand_cs_nand_select;280	u32			nand_cs_nand_xor;281	u32			corr_stat_threshold;282	u32			flash_dma_mode;283	u32                     flash_edu_mode;284	bool			pio_poll_mode;285};286 287struct brcmnand_cfg {288	u64			device_size;289	unsigned int		block_size;290	unsigned int		page_size;291	unsigned int		spare_area_size;292	unsigned int		device_width;293	unsigned int		col_adr_bytes;294	unsigned int		blk_adr_bytes;295	unsigned int		ful_adr_bytes;296	unsigned int		sector_size_1k;297	unsigned int		ecc_level;298	/* use for low-power standby/resume only */299	u32			acc_control;300	u32			config;301	u32			config_ext;302	u32			timing_1;303	u32			timing_2;304};305 306struct brcmnand_host {307	struct list_head	node;308 309	struct nand_chip	chip;310	struct platform_device	*pdev;311	int			cs;312 313	unsigned int		last_cmd;314	unsigned int		last_byte;315	u64			last_addr;316	struct brcmnand_cfg	hwcfg;317	struct brcmnand_controller *ctrl;318};319 320enum brcmnand_reg {321	BRCMNAND_CMD_START = 0,322	BRCMNAND_CMD_EXT_ADDRESS,323	BRCMNAND_CMD_ADDRESS,324	BRCMNAND_INTFC_STATUS,325	BRCMNAND_CS_SELECT,326	BRCMNAND_CS_XOR,327	BRCMNAND_LL_OP,328	BRCMNAND_CS0_BASE,329	BRCMNAND_CS1_BASE,		/* CS1 regs, if non-contiguous */330	BRCMNAND_CORR_THRESHOLD,331	BRCMNAND_CORR_THRESHOLD_EXT,332	BRCMNAND_UNCORR_COUNT,333	BRCMNAND_CORR_COUNT,334	BRCMNAND_CORR_EXT_ADDR,335	BRCMNAND_CORR_ADDR,336	BRCMNAND_UNCORR_EXT_ADDR,337	BRCMNAND_UNCORR_ADDR,338	BRCMNAND_SEMAPHORE,339	BRCMNAND_ID,340	BRCMNAND_ID_EXT,341	BRCMNAND_LL_RDATA,342	BRCMNAND_OOB_READ_BASE,343	BRCMNAND_OOB_READ_10_BASE,	/* offset 0x10, if non-contiguous */344	BRCMNAND_OOB_WRITE_BASE,345	BRCMNAND_OOB_WRITE_10_BASE,	/* offset 0x10, if non-contiguous */346	BRCMNAND_FC_BASE,347};348 349/* BRCMNAND v2.1-v2.2 */350static const u16 brcmnand_regs_v21[] = {351	[BRCMNAND_CMD_START]		=  0x04,352	[BRCMNAND_CMD_EXT_ADDRESS]	=  0x08,353	[BRCMNAND_CMD_ADDRESS]		=  0x0c,354	[BRCMNAND_INTFC_STATUS]		=  0x5c,355	[BRCMNAND_CS_SELECT]		=  0x14,356	[BRCMNAND_CS_XOR]		=  0x18,357	[BRCMNAND_LL_OP]		=     0,358	[BRCMNAND_CS0_BASE]		=  0x40,359	[BRCMNAND_CS1_BASE]		=     0,360	[BRCMNAND_CORR_THRESHOLD]	=     0,361	[BRCMNAND_CORR_THRESHOLD_EXT]	=     0,362	[BRCMNAND_UNCORR_COUNT]		=     0,363	[BRCMNAND_CORR_COUNT]		=     0,364	[BRCMNAND_CORR_EXT_ADDR]	=  0x60,365	[BRCMNAND_CORR_ADDR]		=  0x64,366	[BRCMNAND_UNCORR_EXT_ADDR]	=  0x68,367	[BRCMNAND_UNCORR_ADDR]		=  0x6c,368	[BRCMNAND_SEMAPHORE]		=  0x50,369	[BRCMNAND_ID]			=  0x54,370	[BRCMNAND_ID_EXT]		=     0,371	[BRCMNAND_LL_RDATA]		=     0,372	[BRCMNAND_OOB_READ_BASE]	=  0x20,373	[BRCMNAND_OOB_READ_10_BASE]	=     0,374	[BRCMNAND_OOB_WRITE_BASE]	=  0x30,375	[BRCMNAND_OOB_WRITE_10_BASE]	=     0,376	[BRCMNAND_FC_BASE]		= 0x200,377};378 379/* BRCMNAND v3.3-v4.0 */380static const u16 brcmnand_regs_v33[] = {381	[BRCMNAND_CMD_START]		=  0x04,382	[BRCMNAND_CMD_EXT_ADDRESS]	=  0x08,383	[BRCMNAND_CMD_ADDRESS]		=  0x0c,384	[BRCMNAND_INTFC_STATUS]		=  0x6c,385	[BRCMNAND_CS_SELECT]		=  0x14,386	[BRCMNAND_CS_XOR]		=  0x18,387	[BRCMNAND_LL_OP]		= 0x178,388	[BRCMNAND_CS0_BASE]		=  0x40,389	[BRCMNAND_CS1_BASE]		=  0xd0,390	[BRCMNAND_CORR_THRESHOLD]	=  0x84,391	[BRCMNAND_CORR_THRESHOLD_EXT]	=     0,392	[BRCMNAND_UNCORR_COUNT]		=     0,393	[BRCMNAND_CORR_COUNT]		=     0,394	[BRCMNAND_CORR_EXT_ADDR]	=  0x70,395	[BRCMNAND_CORR_ADDR]		=  0x74,396	[BRCMNAND_UNCORR_EXT_ADDR]	=  0x78,397	[BRCMNAND_UNCORR_ADDR]		=  0x7c,398	[BRCMNAND_SEMAPHORE]		=  0x58,399	[BRCMNAND_ID]			=  0x60,400	[BRCMNAND_ID_EXT]		=  0x64,401	[BRCMNAND_LL_RDATA]		= 0x17c,402	[BRCMNAND_OOB_READ_BASE]	=  0x20,403	[BRCMNAND_OOB_READ_10_BASE]	= 0x130,404	[BRCMNAND_OOB_WRITE_BASE]	=  0x30,405	[BRCMNAND_OOB_WRITE_10_BASE]	=     0,406	[BRCMNAND_FC_BASE]		= 0x200,407};408 409/* BRCMNAND v5.0 */410static const u16 brcmnand_regs_v50[] = {411	[BRCMNAND_CMD_START]		=  0x04,412	[BRCMNAND_CMD_EXT_ADDRESS]	=  0x08,413	[BRCMNAND_CMD_ADDRESS]		=  0x0c,414	[BRCMNAND_INTFC_STATUS]		=  0x6c,415	[BRCMNAND_CS_SELECT]		=  0x14,416	[BRCMNAND_CS_XOR]		=  0x18,417	[BRCMNAND_LL_OP]		= 0x178,418	[BRCMNAND_CS0_BASE]		=  0x40,419	[BRCMNAND_CS1_BASE]		=  0xd0,420	[BRCMNAND_CORR_THRESHOLD]	=  0x84,421	[BRCMNAND_CORR_THRESHOLD_EXT]	=     0,422	[BRCMNAND_UNCORR_COUNT]		=     0,423	[BRCMNAND_CORR_COUNT]		=     0,424	[BRCMNAND_CORR_EXT_ADDR]	=  0x70,425	[BRCMNAND_CORR_ADDR]		=  0x74,426	[BRCMNAND_UNCORR_EXT_ADDR]	=  0x78,427	[BRCMNAND_UNCORR_ADDR]		=  0x7c,428	[BRCMNAND_SEMAPHORE]		=  0x58,429	[BRCMNAND_ID]			=  0x60,430	[BRCMNAND_ID_EXT]		=  0x64,431	[BRCMNAND_LL_RDATA]		= 0x17c,432	[BRCMNAND_OOB_READ_BASE]	=  0x20,433	[BRCMNAND_OOB_READ_10_BASE]	= 0x130,434	[BRCMNAND_OOB_WRITE_BASE]	=  0x30,435	[BRCMNAND_OOB_WRITE_10_BASE]	= 0x140,436	[BRCMNAND_FC_BASE]		= 0x200,437};438 439/* BRCMNAND v6.0 - v7.1 */440static const u16 brcmnand_regs_v60[] = {441	[BRCMNAND_CMD_START]		=  0x04,442	[BRCMNAND_CMD_EXT_ADDRESS]	=  0x08,443	[BRCMNAND_CMD_ADDRESS]		=  0x0c,444	[BRCMNAND_INTFC_STATUS]		=  0x14,445	[BRCMNAND_CS_SELECT]		=  0x18,446	[BRCMNAND_CS_XOR]		=  0x1c,447	[BRCMNAND_LL_OP]		=  0x20,448	[BRCMNAND_CS0_BASE]		=  0x50,449	[BRCMNAND_CS1_BASE]		=     0,450	[BRCMNAND_CORR_THRESHOLD]	=  0xc0,451	[BRCMNAND_CORR_THRESHOLD_EXT]	=  0xc4,452	[BRCMNAND_UNCORR_COUNT]		=  0xfc,453	[BRCMNAND_CORR_COUNT]		= 0x100,454	[BRCMNAND_CORR_EXT_ADDR]	= 0x10c,455	[BRCMNAND_CORR_ADDR]		= 0x110,456	[BRCMNAND_UNCORR_EXT_ADDR]	= 0x114,457	[BRCMNAND_UNCORR_ADDR]		= 0x118,458	[BRCMNAND_SEMAPHORE]		= 0x150,459	[BRCMNAND_ID]			= 0x194,460	[BRCMNAND_ID_EXT]		= 0x198,461	[BRCMNAND_LL_RDATA]		= 0x19c,462	[BRCMNAND_OOB_READ_BASE]	= 0x200,463	[BRCMNAND_OOB_READ_10_BASE]	=     0,464	[BRCMNAND_OOB_WRITE_BASE]	= 0x280,465	[BRCMNAND_OOB_WRITE_10_BASE]	=     0,466	[BRCMNAND_FC_BASE]		= 0x400,467};468 469/* BRCMNAND v7.1 */470static const u16 brcmnand_regs_v71[] = {471	[BRCMNAND_CMD_START]		=  0x04,472	[BRCMNAND_CMD_EXT_ADDRESS]	=  0x08,473	[BRCMNAND_CMD_ADDRESS]		=  0x0c,474	[BRCMNAND_INTFC_STATUS]		=  0x14,475	[BRCMNAND_CS_SELECT]		=  0x18,476	[BRCMNAND_CS_XOR]		=  0x1c,477	[BRCMNAND_LL_OP]		=  0x20,478	[BRCMNAND_CS0_BASE]		=  0x50,479	[BRCMNAND_CS1_BASE]		=     0,480	[BRCMNAND_CORR_THRESHOLD]	=  0xdc,481	[BRCMNAND_CORR_THRESHOLD_EXT]	=  0xe0,482	[BRCMNAND_UNCORR_COUNT]		=  0xfc,483	[BRCMNAND_CORR_COUNT]		= 0x100,484	[BRCMNAND_CORR_EXT_ADDR]	= 0x10c,485	[BRCMNAND_CORR_ADDR]		= 0x110,486	[BRCMNAND_UNCORR_EXT_ADDR]	= 0x114,487	[BRCMNAND_UNCORR_ADDR]		= 0x118,488	[BRCMNAND_SEMAPHORE]		= 0x150,489	[BRCMNAND_ID]			= 0x194,490	[BRCMNAND_ID_EXT]		= 0x198,491	[BRCMNAND_LL_RDATA]		= 0x19c,492	[BRCMNAND_OOB_READ_BASE]	= 0x200,493	[BRCMNAND_OOB_READ_10_BASE]	=     0,494	[BRCMNAND_OOB_WRITE_BASE]	= 0x280,495	[BRCMNAND_OOB_WRITE_10_BASE]	=     0,496	[BRCMNAND_FC_BASE]		= 0x400,497};498 499/* BRCMNAND v7.2 */500static const u16 brcmnand_regs_v72[] = {501	[BRCMNAND_CMD_START]		=  0x04,502	[BRCMNAND_CMD_EXT_ADDRESS]	=  0x08,503	[BRCMNAND_CMD_ADDRESS]		=  0x0c,504	[BRCMNAND_INTFC_STATUS]		=  0x14,505	[BRCMNAND_CS_SELECT]		=  0x18,506	[BRCMNAND_CS_XOR]		=  0x1c,507	[BRCMNAND_LL_OP]		=  0x20,508	[BRCMNAND_CS0_BASE]		=  0x50,509	[BRCMNAND_CS1_BASE]		=     0,510	[BRCMNAND_CORR_THRESHOLD]	=  0xdc,511	[BRCMNAND_CORR_THRESHOLD_EXT]	=  0xe0,512	[BRCMNAND_UNCORR_COUNT]		=  0xfc,513	[BRCMNAND_CORR_COUNT]		= 0x100,514	[BRCMNAND_CORR_EXT_ADDR]	= 0x10c,515	[BRCMNAND_CORR_ADDR]		= 0x110,516	[BRCMNAND_UNCORR_EXT_ADDR]	= 0x114,517	[BRCMNAND_UNCORR_ADDR]		= 0x118,518	[BRCMNAND_SEMAPHORE]		= 0x150,519	[BRCMNAND_ID]			= 0x194,520	[BRCMNAND_ID_EXT]		= 0x198,521	[BRCMNAND_LL_RDATA]		= 0x19c,522	[BRCMNAND_OOB_READ_BASE]	= 0x200,523	[BRCMNAND_OOB_READ_10_BASE]	=     0,524	[BRCMNAND_OOB_WRITE_BASE]	= 0x400,525	[BRCMNAND_OOB_WRITE_10_BASE]	=     0,526	[BRCMNAND_FC_BASE]		= 0x600,527};528 529enum brcmnand_cs_reg {530	BRCMNAND_CS_CFG_EXT = 0,531	BRCMNAND_CS_CFG,532	BRCMNAND_CS_ACC_CONTROL,533	BRCMNAND_CS_TIMING1,534	BRCMNAND_CS_TIMING2,535};536 537/* Per chip-select offsets for v7.1 */538static const u8 brcmnand_cs_offsets_v71[] = {539	[BRCMNAND_CS_ACC_CONTROL]	= 0x00,540	[BRCMNAND_CS_CFG_EXT]		= 0x04,541	[BRCMNAND_CS_CFG]		= 0x08,542	[BRCMNAND_CS_TIMING1]		= 0x0c,543	[BRCMNAND_CS_TIMING2]		= 0x10,544};545 546/* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */547static const u8 brcmnand_cs_offsets[] = {548	[BRCMNAND_CS_ACC_CONTROL]	= 0x00,549	[BRCMNAND_CS_CFG_EXT]		= 0x04,550	[BRCMNAND_CS_CFG]		= 0x04,551	[BRCMNAND_CS_TIMING1]		= 0x08,552	[BRCMNAND_CS_TIMING2]		= 0x0c,553};554 555/* Per chip-select offset for <= v5.0 on CS0 only */556static const u8 brcmnand_cs_offsets_cs0[] = {557	[BRCMNAND_CS_ACC_CONTROL]	= 0x00,558	[BRCMNAND_CS_CFG_EXT]		= 0x08,559	[BRCMNAND_CS_CFG]		= 0x08,560	[BRCMNAND_CS_TIMING1]		= 0x10,561	[BRCMNAND_CS_TIMING2]		= 0x14,562};563 564/*565 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had566 * one config register, but once the bitfields overflowed, newer controllers567 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.568 */569enum {570	CFG_BLK_ADR_BYTES_SHIFT		= 8,571	CFG_COL_ADR_BYTES_SHIFT		= 12,572	CFG_FUL_ADR_BYTES_SHIFT		= 16,573	CFG_BUS_WIDTH_SHIFT		= 23,574	CFG_BUS_WIDTH			= BIT(CFG_BUS_WIDTH_SHIFT),575	CFG_DEVICE_SIZE_SHIFT		= 24,576 577	/* Only for v2.1 */578	CFG_PAGE_SIZE_SHIFT_v2_1	= 30,579 580	/* Only for pre-v7.1 (with no CFG_EXT register) */581	CFG_PAGE_SIZE_SHIFT		= 20,582	CFG_BLK_SIZE_SHIFT		= 28,583 584	/* Only for v7.1+ (with CFG_EXT register) */585	CFG_EXT_PAGE_SIZE_SHIFT		= 0,586	CFG_EXT_BLK_SIZE_SHIFT		= 4,587};588 589/* BRCMNAND_INTFC_STATUS */590enum {591	INTFC_FLASH_STATUS		= GENMASK(7, 0),592 593	INTFC_ERASED			= BIT(27),594	INTFC_OOB_VALID			= BIT(28),595	INTFC_CACHE_VALID		= BIT(29),596	INTFC_FLASH_READY		= BIT(30),597	INTFC_CTLR_READY		= BIT(31),598};599 600/***********************************************************************601 * NAND ACC CONTROL bitfield602 *603 * Some bits have remained constant throughout hardware revision, while604 * others have shifted around.605 ***********************************************************************/606 607/* Constant for all versions (where supported) */608enum {609	/* See BRCMNAND_HAS_CACHE_MODE */610	ACC_CONTROL_CACHE_MODE				= BIT(22),611 612	/* See BRCMNAND_HAS_PREFETCH */613	ACC_CONTROL_PREFETCH				= BIT(23),614 615	ACC_CONTROL_PAGE_HIT				= BIT(24),616	ACC_CONTROL_WR_PREEMPT				= BIT(25),617	ACC_CONTROL_PARTIAL_PAGE			= BIT(26),618	ACC_CONTROL_RD_ERASED				= BIT(27),619	ACC_CONTROL_FAST_PGM_RDIN			= BIT(28),620	ACC_CONTROL_WR_ECC				= BIT(30),621	ACC_CONTROL_RD_ECC				= BIT(31),622};623 624#define	ACC_CONTROL_ECC_SHIFT			16625/* Only for v7.2 */626#define	ACC_CONTROL_ECC_EXT_SHIFT		13627 628static int brcmnand_status(struct brcmnand_host *host);629 630static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl)631{632#if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA)633	return static_branch_unlikely(&brcmnand_soc_has_ops_key);634#else635	return false;636#endif637}638 639static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)640{641	if (brcmnand_non_mmio_ops(ctrl))642		return brcmnand_soc_read(ctrl->soc, offs);643	return brcmnand_readl(ctrl->nand_base + offs);644}645 646static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,647				 u32 val)648{649	if (brcmnand_non_mmio_ops(ctrl))650		brcmnand_soc_write(ctrl->soc, val, offs);651	else652		brcmnand_writel(val, ctrl->nand_base + offs);653}654 655static int brcmnand_revision_init(struct brcmnand_controller *ctrl)656{657	static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };658	static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };659	static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };660	static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };661	static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };662	static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };663	static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };664 665	ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;666 667	/* Only support v2.1+ */668	if (ctrl->nand_version < 0x0201) {669		dev_err(ctrl->dev, "version %#x not supported\n",670			ctrl->nand_version);671		return -ENODEV;672	}673 674	/* Register offsets */675	if (ctrl->nand_version >= 0x0702)676		ctrl->reg_offsets = brcmnand_regs_v72;677	else if (ctrl->nand_version == 0x0701)678		ctrl->reg_offsets = brcmnand_regs_v71;679	else if (ctrl->nand_version >= 0x0600)680		ctrl->reg_offsets = brcmnand_regs_v60;681	else if (ctrl->nand_version >= 0x0500)682		ctrl->reg_offsets = brcmnand_regs_v50;683	else if (ctrl->nand_version >= 0x0303)684		ctrl->reg_offsets = brcmnand_regs_v33;685	else if (ctrl->nand_version >= 0x0201)686		ctrl->reg_offsets = brcmnand_regs_v21;687 688	/* Chip-select stride */689	if (ctrl->nand_version >= 0x0701)690		ctrl->reg_spacing = 0x14;691	else692		ctrl->reg_spacing = 0x10;693 694	/* Per chip-select registers */695	if (ctrl->nand_version >= 0x0701) {696		ctrl->cs_offsets = brcmnand_cs_offsets_v71;697	} else {698		ctrl->cs_offsets = brcmnand_cs_offsets;699 700		/* v3.3-5.0 have a different CS0 offset layout */701		if (ctrl->nand_version >= 0x0303 &&702		    ctrl->nand_version <= 0x0500)703			ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;704	}705 706	/* Page / block sizes */707	if (ctrl->nand_version >= 0x0701) {708		/* >= v7.1 use nice power-of-2 values! */709		ctrl->max_page_size = 16 * 1024;710		ctrl->max_block_size = 2 * 1024 * 1024;711	} else {712		if (ctrl->nand_version >= 0x0304)713			ctrl->page_sizes = page_sizes_v3_4;714		else if (ctrl->nand_version >= 0x0202)715			ctrl->page_sizes = page_sizes_v2_2;716		else717			ctrl->page_sizes = page_sizes_v2_1;718 719		if (ctrl->nand_version >= 0x0202)720			ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT;721		else722			ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1;723 724		if (ctrl->nand_version >= 0x0600)725			ctrl->block_sizes = block_sizes_v6;726		else if (ctrl->nand_version >= 0x0400)727			ctrl->block_sizes = block_sizes_v4;728		else if (ctrl->nand_version >= 0x0202)729			ctrl->block_sizes = block_sizes_v2_2;730		else731			ctrl->block_sizes = block_sizes_v2_1;732 733		if (ctrl->nand_version < 0x0400) {734			if (ctrl->nand_version < 0x0202)735				ctrl->max_page_size = 2048;736			else737				ctrl->max_page_size = 4096;738			ctrl->max_block_size = 512 * 1024;739		}740	}741 742	/* Maximum spare area sector size (per 512B) */743	if (ctrl->nand_version == 0x0702)744		ctrl->max_oob = 128;745	else if (ctrl->nand_version >= 0x0600)746		ctrl->max_oob = 64;747	else if (ctrl->nand_version >= 0x0500)748		ctrl->max_oob = 32;749	else750		ctrl->max_oob = 16;751 752	/* v6.0 and newer (except v6.1) have prefetch support */753	if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)754		ctrl->features |= BRCMNAND_HAS_PREFETCH;755 756	/*757	 * v6.x has cache mode, but it's implemented differently. Ignore it for758	 * now.759	 */760	if (ctrl->nand_version >= 0x0700)761		ctrl->features |= BRCMNAND_HAS_CACHE_MODE;762 763	if (ctrl->nand_version >= 0x0500)764		ctrl->features |= BRCMNAND_HAS_1K_SECTORS;765 766	if (ctrl->nand_version >= 0x0700)767		ctrl->features |= BRCMNAND_HAS_WP;768	else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))769		ctrl->features |= BRCMNAND_HAS_WP;770 771	/* v7.2 has different ecc level shift in the acc register */772	if (ctrl->nand_version == 0x0702)773		ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT;774	else775		ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT;776 777	return 0;778}779 780static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl)781{782	/* flash_dma register offsets */783	if (ctrl->nand_version >= 0x0703)784		ctrl->flash_dma_offsets = flash_dma_regs_v4;785	else if (ctrl->nand_version == 0x0602)786		ctrl->flash_dma_offsets = flash_dma_regs_v0;787	else788		ctrl->flash_dma_offsets = flash_dma_regs_v1;789}790 791static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,792		enum brcmnand_reg reg)793{794	u16 offs = ctrl->reg_offsets[reg];795 796	if (offs)797		return nand_readreg(ctrl, offs);798	else799		return 0;800}801 802static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,803				      enum brcmnand_reg reg, u32 val)804{805	u16 offs = ctrl->reg_offsets[reg];806 807	if (offs)808		nand_writereg(ctrl, offs, val);809}810 811static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,812				    enum brcmnand_reg reg, u32 mask, unsigned813				    int shift, u32 val)814{815	u32 tmp = brcmnand_read_reg(ctrl, reg);816 817	tmp &= ~mask;818	tmp |= val << shift;819	brcmnand_write_reg(ctrl, reg, tmp);820}821 822static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)823{824	if (brcmnand_non_mmio_ops(ctrl))825		return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR);826	return __raw_readl(ctrl->nand_fc + word * 4);827}828 829static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,830				     int word, u32 val)831{832	if (brcmnand_non_mmio_ops(ctrl))833		brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR);834	else835		__raw_writel(val, ctrl->nand_fc + word * 4);836}837 838static inline void edu_writel(struct brcmnand_controller *ctrl,839			      enum edu_reg reg, u32 val)840{841	u16 offs = ctrl->edu_offsets[reg];842 843	brcmnand_writel(val, ctrl->edu_base + offs);844}845 846static inline u32 edu_readl(struct brcmnand_controller *ctrl,847			    enum edu_reg reg)848{849	u16 offs = ctrl->edu_offsets[reg];850 851	return brcmnand_readl(ctrl->edu_base + offs);852}853 854static inline void brcmnand_read_data_bus(struct brcmnand_controller *ctrl,855					  void __iomem *flash_cache, u32 *buffer, int fc_words)856{857	struct brcmnand_soc *soc = ctrl->soc;858	int i;859 860	if (soc && soc->read_data_bus) {861		soc->read_data_bus(soc, flash_cache, buffer, fc_words);862	} else {863		for (i = 0; i < fc_words; i++)864			buffer[i] = brcmnand_read_fc(ctrl, i);865	}866}867 868static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl)869{870 871	/* Clear error addresses */872	brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);873	brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);874	brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);875	brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);876}877 878static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl)879{880	u64 err_addr;881 882	err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR);883	err_addr |= ((u64)(brcmnand_read_reg(ctrl,884					     BRCMNAND_UNCORR_EXT_ADDR)885					     & 0xffff) << 32);886 887	return err_addr;888}889 890static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl)891{892	u64 err_addr;893 894	err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR);895	err_addr |= ((u64)(brcmnand_read_reg(ctrl,896					     BRCMNAND_CORR_EXT_ADDR)897					     & 0xffff) << 32);898 899	return err_addr;900}901 902static void brcmnand_set_cmd_addr(struct mtd_info *mtd, u64 addr)903{904	struct nand_chip *chip =  mtd_to_nand(mtd);905	struct brcmnand_host *host = nand_get_controller_data(chip);906	struct brcmnand_controller *ctrl = host->ctrl;907 908	brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,909			   (host->cs << 16) | ((addr >> 32) & 0xffff));910	(void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);911	brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,912			   lower_32_bits(addr));913	(void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);914}915 916static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,917				     enum brcmnand_cs_reg reg)918{919	u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];920	u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];921	u8 cs_offs;922 923	if (cs == 0 && ctrl->cs0_offsets)924		cs_offs = ctrl->cs0_offsets[reg];925	else926		cs_offs = ctrl->cs_offsets[reg];927 928	if (cs && offs_cs1)929		return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;930 931	return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;932}933 934static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)935{936	if (ctrl->nand_version < 0x0600)937		return 1;938	return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);939}940 941static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)942{943	struct brcmnand_controller *ctrl = host->ctrl;944	unsigned int shift = 0, bits;945	enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;946	int cs = host->cs;947 948	if (!ctrl->reg_offsets[reg])949		return;950 951	if (ctrl->nand_version == 0x0702)952		bits = 7;953	else if (ctrl->nand_version >= 0x0600)954		bits = 6;955	else if (ctrl->nand_version >= 0x0500)956		bits = 5;957	else958		bits = 4;959 960	if (ctrl->nand_version >= 0x0702) {961		if (cs >= 4)962			reg = BRCMNAND_CORR_THRESHOLD_EXT;963		shift = (cs % 4) * bits;964	} else if (ctrl->nand_version >= 0x0600) {965		if (cs >= 5)966			reg = BRCMNAND_CORR_THRESHOLD_EXT;967		shift = (cs % 5) * bits;968	}969	brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);970}971 972static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)973{974	/* Kludge for the BCMA-based NAND controller which does not actually975	 * shift the command976	 */977	if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl))978		return 0;979 980	if (ctrl->nand_version < 0x0602)981		return 24;982	return 0;983}984 985static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)986{987	if (ctrl->nand_version == 0x0702)988		return GENMASK(7, 0);989	else if (ctrl->nand_version >= 0x0600)990		return GENMASK(6, 0);991	else if (ctrl->nand_version >= 0x0303)992		return GENMASK(5, 0);993	else994		return GENMASK(4, 0);995}996 997static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)998{999	u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;1000 1001	mask <<= ACC_CONTROL_ECC_SHIFT;1002 1003	/* v7.2 includes additional ECC levels */1004	if (ctrl->nand_version == 0x0702)1005		mask |= 0x7 << ACC_CONTROL_ECC_EXT_SHIFT;1006 1007	return mask;1008}1009 1010static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)1011{1012	struct brcmnand_controller *ctrl = host->ctrl;1013	u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);1014	u32 acc_control = nand_readreg(ctrl, offs);1015	u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;1016 1017	if (en) {1018		acc_control |= ecc_flags; /* enable RD/WR ECC */1019		acc_control &= ~brcmnand_ecc_level_mask(ctrl);1020		acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift;1021	} else {1022		acc_control &= ~ecc_flags; /* disable RD/WR ECC */1023		acc_control &= ~brcmnand_ecc_level_mask(ctrl);1024	}1025 1026	nand_writereg(ctrl, offs, acc_control);1027}1028 1029static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)1030{1031	if (ctrl->nand_version >= 0x0702)1032		return 9;1033	else if (ctrl->nand_version >= 0x0600)1034		return 7;1035	else if (ctrl->nand_version >= 0x0500)1036		return 6;1037	else1038		return -1;1039}1040 1041static bool brcmnand_get_sector_size_1k(struct brcmnand_host *host)1042{1043	struct brcmnand_controller *ctrl = host->ctrl;1044	int sector_size_bit = brcmnand_sector_1k_shift(ctrl);1045	u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,1046						  BRCMNAND_CS_ACC_CONTROL);1047	u32 acc_control;1048 1049	if (sector_size_bit < 0)1050		return false;1051 1052	acc_control = nand_readreg(ctrl, acc_control_offs);1053 1054	return ((acc_control & BIT(sector_size_bit)) != 0);1055}1056 1057static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)1058{1059	struct brcmnand_controller *ctrl = host->ctrl;1060	int shift = brcmnand_sector_1k_shift(ctrl);1061	u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,1062						  BRCMNAND_CS_ACC_CONTROL);1063	u32 tmp;1064 1065	if (shift < 0)1066		return;1067 1068	tmp = nand_readreg(ctrl, acc_control_offs);1069	tmp &= ~(1 << shift);1070	tmp |= (!!val) << shift;1071	nand_writereg(ctrl, acc_control_offs, tmp);1072}1073 1074static int brcmnand_get_spare_size(struct brcmnand_host *host)1075{1076	struct brcmnand_controller *ctrl = host->ctrl;1077	u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,1078						  BRCMNAND_CS_ACC_CONTROL);1079	u32 acc = nand_readreg(ctrl, acc_control_offs);1080 1081	return (acc & brcmnand_spare_area_mask(ctrl));1082}1083 1084static void brcmnand_get_ecc_settings(struct brcmnand_host *host, struct nand_chip *chip)1085{1086	struct brcmnand_controller *ctrl = host->ctrl;1087	u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,1088						  BRCMNAND_CS_ACC_CONTROL);1089	bool sector_size_1k = brcmnand_get_sector_size_1k(host);1090	int spare_area_size, ecc_level;1091	u32 acc;1092 1093	spare_area_size = brcmnand_get_spare_size(host);1094	acc = nand_readreg(ctrl, acc_control_offs);1095	ecc_level = (acc & brcmnand_ecc_level_mask(ctrl)) >> ctrl->ecc_level_shift;1096	if (sector_size_1k)1097		chip->ecc.strength = ecc_level * 2;1098	else if (spare_area_size == 16 && ecc_level == 15)1099		chip->ecc.strength = 1; /* hamming */1100	else1101		chip->ecc.strength = ecc_level;1102 1103	if (chip->ecc.size == 0) {1104		if (sector_size_1k)1105			chip->ecc.size = 1024;1106		else1107			chip->ecc.size = 512;1108	}1109}1110 1111/***********************************************************************1112 * CS_NAND_SELECT1113 ***********************************************************************/1114 1115enum {1116	CS_SELECT_NAND_WP			= BIT(29),1117	CS_SELECT_AUTO_DEVICE_ID_CFG		= BIT(30),1118};1119 1120static int bcmnand_ctrl_poll_status(struct brcmnand_host *host,1121				    u32 mask, u32 expected_val,1122				    unsigned long timeout_ms)1123{1124	struct brcmnand_controller *ctrl = host->ctrl;1125	unsigned long limit;1126	u32 val;1127 1128	if (!timeout_ms)1129		timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS;1130 1131	limit = jiffies + msecs_to_jiffies(timeout_ms);1132	do {1133		if (mask & INTFC_FLASH_STATUS)1134			brcmnand_status(host);1135 1136		val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);1137		if ((val & mask) == expected_val)1138			return 0;1139 1140		cpu_relax();1141	} while (time_after(limit, jiffies));1142 1143	/*1144	 * do a final check after time out in case the CPU was busy and the driver1145	 * did not get enough time to perform the polling to avoid false alarms1146	 */1147	if (mask & INTFC_FLASH_STATUS)1148		brcmnand_status(host);1149 1150	val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);1151	if ((val & mask) == expected_val)1152		return 0;1153 1154	dev_err(ctrl->dev, "timeout on status poll (expected %x got %x)\n",1155		expected_val, val & mask);1156 1157	return -ETIMEDOUT;1158}1159 1160static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)1161{1162	u32 val = en ? CS_SELECT_NAND_WP : 0;1163 1164	brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);1165}1166 1167/***********************************************************************1168 * Flash DMA1169 ***********************************************************************/1170 1171static inline bool has_flash_dma(struct brcmnand_controller *ctrl)1172{1173	return ctrl->flash_dma_base;1174}1175 1176static inline bool has_edu(struct brcmnand_controller *ctrl)1177{1178	return ctrl->edu_base;1179}1180 1181static inline bool use_dma(struct brcmnand_controller *ctrl)1182{1183	return has_flash_dma(ctrl) || has_edu(ctrl);1184}1185 1186static inline void disable_ctrl_irqs(struct brcmnand_controller *ctrl)1187{1188	if (ctrl->pio_poll_mode)1189		return;1190 1191	if (has_flash_dma(ctrl)) {1192		ctrl->flash_dma_base = NULL;1193		disable_irq(ctrl->dma_irq);1194	}1195 1196	disable_irq(ctrl->irq);1197	ctrl->pio_poll_mode = true;1198}1199 1200static inline bool flash_dma_buf_ok(const void *buf)1201{1202	return buf && !is_vmalloc_addr(buf) &&1203		likely(IS_ALIGNED((uintptr_t)buf, 4));1204}1205 1206static inline void flash_dma_writel(struct brcmnand_controller *ctrl,1207				    enum flash_dma_reg dma_reg, u32 val)1208{1209	u16 offs = ctrl->flash_dma_offsets[dma_reg];1210 1211	brcmnand_writel(val, ctrl->flash_dma_base + offs);1212}1213 1214static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl,1215				  enum flash_dma_reg dma_reg)1216{1217	u16 offs = ctrl->flash_dma_offsets[dma_reg];1218 1219	return brcmnand_readl(ctrl->flash_dma_base + offs);1220}1221 1222/* Low-level operation types: command, address, write, or read */1223enum brcmnand_llop_type {1224	LL_OP_CMD,1225	LL_OP_ADDR,1226	LL_OP_WR,1227	LL_OP_RD,1228};1229 1230/***********************************************************************1231 * Internal support functions1232 ***********************************************************************/1233 1234static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl,1235				  struct brcmnand_cfg *cfg)1236{1237	if (ctrl->nand_version <= 0x0701)1238		return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&1239			cfg->ecc_level == 15;1240	else1241		return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 &&1242			cfg->ecc_level == 15) ||1243			(cfg->spare_area_size == 28 && cfg->ecc_level == 16));1244}1245 1246/*1247 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given1248 * the layout/configuration.1249 * Returns -ERRCODE on failure.1250 */1251static int brcmnand_hamming_ooblayout_ecc(struct mtd_info *mtd, int section,1252					  struct mtd_oob_region *oobregion)1253{1254	struct nand_chip *chip = mtd_to_nand(mtd);1255	struct brcmnand_host *host = nand_get_controller_data(chip);1256	struct brcmnand_cfg *cfg = &host->hwcfg;1257	int sas = cfg->spare_area_size << cfg->sector_size_1k;1258	int sectors = cfg->page_size / (512 << cfg->sector_size_1k);1259 1260	if (section >= sectors)1261		return -ERANGE;1262 1263	oobregion->offset = (section * sas) + 6;1264	oobregion->length = 3;1265 1266	return 0;1267}1268 1269static int brcmnand_hamming_ooblayout_free(struct mtd_info *mtd, int section,1270					   struct mtd_oob_region *oobregion)1271{1272	struct nand_chip *chip = mtd_to_nand(mtd);1273	struct brcmnand_host *host = nand_get_controller_data(chip);1274	struct brcmnand_cfg *cfg = &host->hwcfg;1275	int sas = cfg->spare_area_size << cfg->sector_size_1k;1276	int sectors = cfg->page_size / (512 << cfg->sector_size_1k);1277	u32 next;1278 1279	if (section > sectors)1280		return -ERANGE;1281 1282	next = (section * sas);1283	if (section < sectors)1284		next += 6;1285 1286	if (section) {1287		oobregion->offset = ((section - 1) * sas) + 9;1288	} else {1289		if (cfg->page_size > 512) {1290			/* Large page NAND uses first 2 bytes for BBI */1291			oobregion->offset = 2;1292		} else {1293			/* Small page NAND uses last byte before ECC for BBI */1294			oobregion->offset = 0;1295			next--;1296		}1297	}1298 1299	oobregion->length = next - oobregion->offset;1300 1301	return 0;1302}1303 1304static const struct mtd_ooblayout_ops brcmnand_hamming_ooblayout_ops = {1305	.ecc = brcmnand_hamming_ooblayout_ecc,1306	.free = brcmnand_hamming_ooblayout_free,1307};1308 1309static int brcmnand_bch_ooblayout_ecc(struct mtd_info *mtd, int section,1310				      struct mtd_oob_region *oobregion)1311{1312	struct nand_chip *chip = mtd_to_nand(mtd);1313	struct brcmnand_host *host = nand_get_controller_data(chip);1314	struct brcmnand_cfg *cfg = &host->hwcfg;1315	int sas = cfg->spare_area_size << cfg->sector_size_1k;1316	int sectors = cfg->page_size / (512 << cfg->sector_size_1k);1317 1318	if (section >= sectors)1319		return -ERANGE;1320 1321	oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes;1322	oobregion->length = chip->ecc.bytes;1323 1324	return 0;1325}1326 1327static int brcmnand_bch_ooblayout_free_lp(struct mtd_info *mtd, int section,1328					  struct mtd_oob_region *oobregion)1329{1330	struct nand_chip *chip = mtd_to_nand(mtd);1331	struct brcmnand_host *host = nand_get_controller_data(chip);1332	struct brcmnand_cfg *cfg = &host->hwcfg;1333	int sas = cfg->spare_area_size << cfg->sector_size_1k;1334	int sectors = cfg->page_size / (512 << cfg->sector_size_1k);1335 1336	if (section >= sectors)1337		return -ERANGE;1338 1339	if (sas <= chip->ecc.bytes)1340		return 0;1341 1342	oobregion->offset = section * sas;1343	oobregion->length = sas - chip->ecc.bytes;1344 1345	if (!section) {1346		oobregion->offset++;1347		oobregion->length--;1348	}1349 1350	return 0;1351}1352 1353static int brcmnand_bch_ooblayout_free_sp(struct mtd_info *mtd, int section,1354					  struct mtd_oob_region *oobregion)1355{1356	struct nand_chip *chip = mtd_to_nand(mtd);1357	struct brcmnand_host *host = nand_get_controller_data(chip);1358	struct brcmnand_cfg *cfg = &host->hwcfg;1359	int sas = cfg->spare_area_size << cfg->sector_size_1k;1360 1361	if (section > 1 || sas - chip->ecc.bytes < 6 ||1362	    (section && sas - chip->ecc.bytes == 6))1363		return -ERANGE;1364 1365	if (!section) {1366		oobregion->offset = 0;1367		oobregion->length = 5;1368	} else {1369		oobregion->offset = 6;1370		oobregion->length = sas - chip->ecc.bytes - 6;1371	}1372 1373	return 0;1374}1375 1376static const struct mtd_ooblayout_ops brcmnand_bch_lp_ooblayout_ops = {1377	.ecc = brcmnand_bch_ooblayout_ecc,1378	.free = brcmnand_bch_ooblayout_free_lp,1379};1380 1381static const struct mtd_ooblayout_ops brcmnand_bch_sp_ooblayout_ops = {1382	.ecc = brcmnand_bch_ooblayout_ecc,1383	.free = brcmnand_bch_ooblayout_free_sp,1384};1385 1386static int brcmstb_choose_ecc_layout(struct brcmnand_host *host)1387{1388	struct brcmnand_cfg *p = &host->hwcfg;1389	struct mtd_info *mtd = nand_to_mtd(&host->chip);1390	struct nand_ecc_ctrl *ecc = &host->chip.ecc;1391	unsigned int ecc_level = p->ecc_level;1392	int sas = p->spare_area_size << p->sector_size_1k;1393	int sectors = p->page_size / (512 << p->sector_size_1k);1394 1395	if (p->sector_size_1k)1396		ecc_level <<= 1;1397 1398	if (is_hamming_ecc(host->ctrl, p)) {1399		ecc->bytes = 3 * sectors;1400		mtd_set_ooblayout(mtd, &brcmnand_hamming_ooblayout_ops);1401		return 0;1402	}1403 1404	/*1405	 * CONTROLLER_VERSION:1406	 *   < v5.0: ECC_REQ = ceil(BCH_T * 13/8)1407	 *  >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)1408	 * But we will just be conservative.1409	 */1410	ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8);1411	if (p->page_size == 512)1412		mtd_set_ooblayout(mtd, &brcmnand_bch_sp_ooblayout_ops);1413	else1414		mtd_set_ooblayout(mtd, &brcmnand_bch_lp_ooblayout_ops);1415 1416	if (ecc->bytes >= sas) {1417		dev_err(&host->pdev->dev,1418			"error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",1419			ecc->bytes, sas);1420		return -EINVAL;1421	}1422 1423	return 0;1424}1425 1426static void brcmnand_wp(struct mtd_info *mtd, int wp)1427{1428	struct nand_chip *chip = mtd_to_nand(mtd);1429	struct brcmnand_host *host = nand_get_controller_data(chip);1430	struct brcmnand_controller *ctrl = host->ctrl;1431 1432	if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {1433		static int old_wp = -1;1434		int ret;1435 1436		if (old_wp != wp) {1437			dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");1438			old_wp = wp;1439		}1440 1441		/*1442		 * make sure ctrl/flash ready before and after1443		 * changing state of #WP pin1444		 */1445		ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY |1446					       NAND_STATUS_READY,1447					       NAND_CTRL_RDY |1448					       NAND_STATUS_READY, 0);1449		if (ret)1450			return;1451 1452		brcmnand_set_wp(ctrl, wp);1453		/* force controller operation to update internal copy of NAND chip status */1454		brcmnand_status(host);1455		/* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */1456		ret = bcmnand_ctrl_poll_status(host,1457					       NAND_CTRL_RDY |1458					       NAND_STATUS_READY |1459					       NAND_STATUS_WP,1460					       NAND_CTRL_RDY |1461					       NAND_STATUS_READY |1462					       (wp ? 0 : NAND_STATUS_WP), 0);1463 1464		if (ret)1465			dev_err_ratelimited(&host->pdev->dev,1466					    "nand #WP expected %s\n",1467					    wp ? "on" : "off");1468	}1469}1470 1471/* Helper functions for reading and writing OOB registers */1472static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)1473{1474	u16 offset0, offset10, reg_offs;1475 1476	offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];1477	offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];1478 1479	if (offs >= ctrl->max_oob)1480		return 0x77;1481 1482	if (offs >= 16 && offset10)1483		reg_offs = offset10 + ((offs - 0x10) & ~0x03);1484	else1485		reg_offs = offset0 + (offs & ~0x03);1486 1487	return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));1488}1489 1490static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,1491				 u32 data)1492{1493	u16 offset0, offset10, reg_offs;1494 1495	offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];1496	offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];1497 1498	if (offs >= ctrl->max_oob)1499		return;1500 1501	if (offs >= 16 && offset10)1502		reg_offs = offset10 + ((offs - 0x10) & ~0x03);1503	else1504		reg_offs = offset0 + (offs & ~0x03);1505 1506	nand_writereg(ctrl, reg_offs, data);1507}1508 1509/*1510 * read_oob_from_regs - read data from OOB registers1511 * @ctrl: NAND controller1512 * @i: sub-page sector index1513 * @oob: buffer to read to1514 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)1515 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal1516 */1517static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,1518			      int sas, int sector_1k)1519{1520	int tbytes = sas << sector_1k;1521	int j;1522 1523	/* Adjust OOB values for 1K sector size */1524	if (sector_1k && (i & 0x01))1525		tbytes = max(0, tbytes - (int)ctrl->max_oob);1526	tbytes = min_t(int, tbytes, ctrl->max_oob);1527 1528	for (j = 0; j < tbytes; j++)1529		oob[j] = oob_reg_read(ctrl, j);1530	return tbytes;1531}1532 1533/*1534 * write_oob_to_regs - write data to OOB registers1535 * @i: sub-page sector index1536 * @oob: buffer to write from1537 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)1538 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal1539 */1540static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,1541			     const u8 *oob, int sas, int sector_1k)1542{1543	int tbytes = sas << sector_1k;1544	int j, k = 0;1545	u32 last = 0xffffffff;1546	u8 *plast = (u8 *)&last;1547 1548	/* Adjust OOB values for 1K sector size */1549	if (sector_1k && (i & 0x01))1550		tbytes = max(0, tbytes - (int)ctrl->max_oob);1551	tbytes = min_t(int, tbytes, ctrl->max_oob);1552 1553	/*1554	 * tbytes may not be multiple of words. Make sure we don't read out of1555	 * the boundary and stop at last word.1556	 */1557	for (j = 0; (j + 3) < tbytes; j += 4)1558		oob_reg_write(ctrl, j,1559				(oob[j + 0] << 24) |1560				(oob[j + 1] << 16) |1561				(oob[j + 2] <<  8) |1562				(oob[j + 3] <<  0));1563 1564	/* handle the remaing bytes */1565	while (j < tbytes)1566		plast[k++] = oob[j++];1567 1568	if (tbytes & 0x3)1569		oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last));1570 1571	return tbytes;1572}1573 1574static void brcmnand_edu_init(struct brcmnand_controller *ctrl)1575{1576	/* initialize edu */1577	edu_writel(ctrl, EDU_ERR_STATUS, 0);1578	edu_readl(ctrl, EDU_ERR_STATUS);1579	edu_writel(ctrl, EDU_DONE, 0);1580	edu_writel(ctrl, EDU_DONE, 0);1581	edu_writel(ctrl, EDU_DONE, 0);1582	edu_writel(ctrl, EDU_DONE, 0);1583	edu_readl(ctrl, EDU_DONE);1584}1585 1586/* edu irq */1587static irqreturn_t brcmnand_edu_irq(int irq, void *data)1588{1589	struct brcmnand_controller *ctrl = data;1590 1591	if (ctrl->edu_count) {1592		ctrl->edu_count--;1593		while (!(edu_readl(ctrl, EDU_DONE) & EDU_DONE_MASK))1594			udelay(1);1595		edu_writel(ctrl, EDU_DONE, 0);1596		edu_readl(ctrl, EDU_DONE);1597	}1598 1599	if (ctrl->edu_count) {1600		ctrl->edu_dram_addr += FC_BYTES;1601		ctrl->edu_ext_addr += FC_BYTES;1602 1603		edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr);1604		edu_readl(ctrl, EDU_DRAM_ADDR);1605		edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr);1606		edu_readl(ctrl, EDU_EXT_ADDR);1607 1608		if (ctrl->oob) {1609			if (ctrl->edu_cmd == EDU_CMD_READ) {1610				ctrl->oob += read_oob_from_regs(ctrl,1611							ctrl->edu_count + 1,1612							ctrl->oob, ctrl->sas,1613							ctrl->sector_size_1k);1614			} else {1615				brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,1616						   ctrl->edu_ext_addr);1617				brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);1618				ctrl->oob += write_oob_to_regs(ctrl,1619							       ctrl->edu_count,1620							       ctrl->oob, ctrl->sas,1621							       ctrl->sector_size_1k);1622			}1623		}1624 1625		mb(); /* flush previous writes */1626		edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd);1627		edu_readl(ctrl, EDU_CMD);1628 1629		return IRQ_HANDLED;1630	}1631 1632	complete(&ctrl->edu_done);1633 1634	return IRQ_HANDLED;1635}1636 1637static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)1638{1639	struct brcmnand_controller *ctrl = data;1640 1641	/* Discard all NAND_CTLRDY interrupts during DMA */1642	if (ctrl->dma_pending)1643		return IRQ_HANDLED;1644 1645	/* check if you need to piggy back on the ctrlrdy irq */1646	if (ctrl->edu_pending) {1647		if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0))1648	/* Discard interrupts while using dedicated edu irq */1649			return IRQ_HANDLED;1650 1651	/* no registered edu irq, call handler */1652		return brcmnand_edu_irq(irq, data);1653	}1654 1655	complete(&ctrl->done);1656	return IRQ_HANDLED;1657}1658 1659/* Handle SoC-specific interrupt hardware */1660static irqreturn_t brcmnand_irq(int irq, void *data)1661{1662	struct brcmnand_controller *ctrl = data;1663 1664	if (ctrl->soc->ctlrdy_ack(ctrl->soc))1665		return brcmnand_ctlrdy_irq(irq, data);1666 1667	return IRQ_NONE;1668}1669 1670static irqreturn_t brcmnand_dma_irq(int irq, void *data)1671{1672	struct brcmnand_controller *ctrl = data;1673 1674	complete(&ctrl->dma_done);1675 1676	return IRQ_HANDLED;1677}1678 1679static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)1680{1681	struct brcmnand_controller *ctrl = host->ctrl;1682	int ret;1683	u64 cmd_addr;1684 1685	cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);1686 1687	dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr);1688 1689	/*1690	 * If we came here through _panic_write and there is a pending1691	 * command, try to wait for it. If it times out, rather than1692	 * hitting BUG_ON, just return so we don't crash while crashing.1693	 */1694	if (oops_in_progress) {1695		if (ctrl->cmd_pending &&1696			bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0))1697			return;1698	} else1699		BUG_ON(ctrl->cmd_pending != 0);1700	ctrl->cmd_pending = cmd;1701 1702	ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);1703	WARN_ON(ret);1704 1705	mb(); /* flush previous writes */1706	brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,1707			   cmd << brcmnand_cmd_shift(ctrl));1708}1709 1710static bool brcmstb_nand_wait_for_completion(struct nand_chip *chip)1711{1712	struct brcmnand_host *host = nand_get_controller_data(chip);1713	struct brcmnand_controller *ctrl = host->ctrl;1714	struct mtd_info *mtd = nand_to_mtd(chip);1715	bool err = false;1716	int sts;1717 1718	if (mtd->oops_panic_write || ctrl->irq < 0) {1719		/* switch to interrupt polling and PIO mode */1720		disable_ctrl_irqs(ctrl);1721		sts = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY,1722					       NAND_CTRL_RDY, 0);1723		err = sts < 0;1724	} else {1725		unsigned long timeo = msecs_to_jiffies(1726						NAND_POLL_STATUS_TIMEOUT_MS);1727		/* wait for completion interrupt */1728		sts = wait_for_completion_timeout(&ctrl->done, timeo);1729		err = !sts;1730	}1731 1732	return err;1733}1734 1735static int brcmnand_waitfunc(struct nand_chip *chip)1736{1737	struct brcmnand_host *host = nand_get_controller_data(chip);1738	struct brcmnand_controller *ctrl = host->ctrl;1739	bool err = false;1740 1741	dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);1742	if (ctrl->cmd_pending)1743		err = brcmstb_nand_wait_for_completion(chip);1744 1745	ctrl->cmd_pending = 0;1746	if (err) {1747		u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)1748					>> brcmnand_cmd_shift(ctrl);1749 1750		dev_err_ratelimited(ctrl->dev,1751			"timeout waiting for command %#02x\n", cmd);1752		dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",1753			brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));1754		return -ETIMEDOUT;1755	}1756	return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &1757				 INTFC_FLASH_STATUS;1758}1759 1760static int brcmnand_status(struct brcmnand_host *host)1761{1762	struct nand_chip *chip = &host->chip;1763	struct mtd_info *mtd = nand_to_mtd(chip);1764 1765	brcmnand_set_cmd_addr(mtd, 0);1766	brcmnand_send_cmd(host, CMD_STATUS_READ);1767 1768	return brcmnand_waitfunc(chip);1769}1770 1771static int brcmnand_reset(struct brcmnand_host *host)1772{1773	struct nand_chip *chip = &host->chip;1774 1775	brcmnand_send_cmd(host, CMD_FLASH_RESET);1776 1777	return brcmnand_waitfunc(chip);1778}1779 1780enum {1781	LLOP_RE				= BIT(16),1782	LLOP_WE				= BIT(17),1783	LLOP_ALE			= BIT(18),1784	LLOP_CLE			= BIT(19),1785	LLOP_RETURN_IDLE		= BIT(31),1786 1787	LLOP_DATA_MASK			= GENMASK(15, 0),1788};1789 1790static int brcmnand_low_level_op(struct brcmnand_host *host,1791				 enum brcmnand_llop_type type, u32 data,1792				 bool last_op)1793{1794	struct nand_chip *chip = &host->chip;1795	struct brcmnand_controller *ctrl = host->ctrl;1796	u32 tmp;1797 1798	tmp = data & LLOP_DATA_MASK;1799	switch (type) {1800	case LL_OP_CMD:1801		tmp |= LLOP_WE | LLOP_CLE;1802		break;1803	case LL_OP_ADDR:1804		/* WE | ALE */1805		tmp |= LLOP_WE | LLOP_ALE;1806		break;1807	case LL_OP_WR:1808		/* WE */1809		tmp |= LLOP_WE;1810		break;1811	case LL_OP_RD:1812		/* RE */1813		tmp |= LLOP_RE;1814		break;1815	}1816	if (last_op)1817		/* RETURN_IDLE */1818		tmp |= LLOP_RETURN_IDLE;1819 1820	dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);1821 1822	brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);1823	(void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);1824 1825	brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);1826	return brcmnand_waitfunc(chip);1827}1828 1829/*1830 *  Kick EDU engine1831 */1832static int brcmnand_edu_trans(struct brcmnand_host *host, u64 addr, u32 *buf,1833			      u8 *oob, u32 len, u8 cmd)1834{1835	struct brcmnand_controller *ctrl = host->ctrl;1836	struct brcmnand_cfg *cfg = &host->hwcfg;1837	unsigned long timeo = msecs_to_jiffies(200);1838	int ret = 0;1839	int dir = (cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE);1840	u8 edu_cmd = (cmd == CMD_PAGE_READ ? EDU_CMD_READ : EDU_CMD_WRITE);1841	unsigned int trans = len >> FC_SHIFT;1842	dma_addr_t pa;1843 1844	dev_dbg(ctrl->dev, "EDU %s %p:%p\n", ((edu_cmd == EDU_CMD_READ) ?1845					      "read" : "write"), buf, oob);1846 1847	pa = dma_map_single(ctrl->dev, buf, len, dir);1848	if (dma_mapping_error(ctrl->dev, pa)) {1849		dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n");1850		return -ENOMEM;1851	}1852 1853	ctrl->edu_pending = true;1854	ctrl->edu_dram_addr = pa;1855	ctrl->edu_ext_addr = addr;1856	ctrl->edu_cmd = edu_cmd;1857	ctrl->edu_count = trans;1858	ctrl->sas = cfg->spare_area_size;1859	ctrl->oob = oob;1860 1861	edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr);1862	edu_readl(ctrl,  EDU_DRAM_ADDR);1863	edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr);1864	edu_readl(ctrl, EDU_EXT_ADDR);1865	edu_writel(ctrl, EDU_LENGTH, FC_BYTES);1866	edu_readl(ctrl, EDU_LENGTH);1867 1868	if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_WRITE)) {1869		brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,1870				   ctrl->edu_ext_addr);1871		brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);1872		ctrl->oob += write_oob_to_regs(ctrl,1873					       1,1874					       ctrl->oob, ctrl->sas,1875					       ctrl->sector_size_1k);1876	}1877 1878	/* Start edu engine */1879	mb(); /* flush previous writes */1880	edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd);1881	edu_readl(ctrl, EDU_CMD);1882 1883	if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) {1884		dev_err(ctrl->dev,1885			"timeout waiting for EDU; status %#x, error status %#x\n",1886			edu_readl(ctrl, EDU_STATUS),1887			edu_readl(ctrl, EDU_ERR_STATUS));1888	}1889 1890	dma_unmap_single(ctrl->dev, pa, len, dir);1891 1892	/* read last subpage oob */1893	if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_READ)) {1894		ctrl->oob += read_oob_from_regs(ctrl,1895						1,1896						ctrl->oob, ctrl->sas,1897						ctrl->sector_size_1k);1898	}1899 1900	/* for program page check NAND status */1901	if (((brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &1902	      INTFC_FLASH_STATUS) & NAND_STATUS_FAIL) &&1903	    edu_cmd == EDU_CMD_WRITE) {1904		dev_info(ctrl->dev, "program failed at %llx\n",1905			 (unsigned long long)addr);1906		ret = -EIO;1907	}1908 1909	/* Make sure the EDU status is clean */1910	if (edu_readl(ctrl, EDU_STATUS) & EDU_STATUS_ACTIVE)1911		dev_warn(ctrl->dev, "EDU still active: %#x\n",1912			 edu_readl(ctrl, EDU_STATUS));1913 1914	if (unlikely(edu_readl(ctrl, EDU_ERR_STATUS) & EDU_ERR_STATUS_ERRACK)) {1915		dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n",1916			 (unsigned long long)addr);1917		ret = -EIO;1918	}1919 1920	ctrl->edu_pending = false;1921	brcmnand_edu_init(ctrl);1922	edu_writel(ctrl, EDU_STOP, 0); /* force stop */1923	edu_readl(ctrl, EDU_STOP);1924 1925	if (!ret && edu_cmd == EDU_CMD_READ) {1926		u64 err_addr = 0;1927 1928		/*1929		 * check for ECC errors here, subpage ECC errors are1930		 * retained in ECC error address register1931		 */1932		err_addr = brcmnand_get_uncorrecc_addr(ctrl);1933		if (!err_addr) {1934			err_addr = brcmnand_get_correcc_addr(ctrl);1935			if (err_addr)1936				ret = -EUCLEAN;1937		} else1938			ret = -EBADMSG;1939	}1940 1941	return ret;1942}1943 1944/*1945 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the1946 * following ahead of time:1947 *  - Is this descriptor the beginning or end of a linked list?1948 *  - What is the (DMA) address of the next descriptor in the linked list?1949 */1950static int brcmnand_fill_dma_desc(struct brcmnand_host *host,1951				  struct brcm_nand_dma_desc *desc, u64 addr,1952				  dma_addr_t buf, u32 len, u8 dma_cmd,1953				  bool begin, bool end,1954				  dma_addr_t next_desc)1955{1956	memset(desc, 0, sizeof(*desc));1957	/* Descriptors are written in native byte order (wordwise) */1958	desc->next_desc = lower_32_bits(next_desc);1959	desc->next_desc_ext = upper_32_bits(next_desc);1960	desc->cmd_irq = (dma_cmd << 24) |1961		(end ? (0x03 << 8) : 0) | /* IRQ | STOP */1962		(!!begin) | ((!!end) << 1); /* head, tail */1963#ifdef CONFIG_CPU_BIG_ENDIAN1964	desc->cmd_irq |= 0x01 << 12;1965#endif1966	desc->dram_addr = lower_32_bits(buf);1967	desc->dram_addr_ext = upper_32_bits(buf);1968	desc->tfr_len = len;1969	desc->total_len = len;1970	desc->flash_addr = lower_32_bits(addr);1971	desc->flash_addr_ext = upper_32_bits(addr);1972	desc->cs = host->cs;1973	desc->status_valid = 0x01;1974	return 0;1975}1976 1977/*1978 * Kick the FLASH_DMA engine, with a given DMA descriptor1979 */1980static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)1981{1982	struct brcmnand_controller *ctrl = host->ctrl;1983	unsigned long timeo = msecs_to_jiffies(100);1984 1985	flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));1986	(void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);1987	if (ctrl->nand_version > 0x0602) {1988		flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT,1989				 upper_32_bits(desc));1990		(void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);1991	}1992 1993	/* Start FLASH_DMA engine */1994	ctrl->dma_pending = true;1995	mb(); /* flush previous writes */1996	flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */1997 1998	if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {1999		dev_err(ctrl->dev,2000				"timeout waiting for DMA; status %#x, error status %#x\n",2001				flash_dma_readl(ctrl, FLASH_DMA_STATUS),2002				flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));2003	}2004	ctrl->dma_pending = false;2005	flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */2006}2007 2008static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,2009			      u8 *oob, u32 len, u8 dma_cmd)2010{2011	struct brcmnand_controller *ctrl = host->ctrl;2012	dma_addr_t buf_pa;2013	int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;2014 2015	buf_pa = dma_map_single(ctrl->dev, buf, len, dir);2016	if (dma_mapping_error(ctrl->dev, buf_pa)) {2017		dev_err(ctrl->dev, "unable to map buffer for DMA\n");2018		return -ENOMEM;2019	}2020 2021	brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,2022				   dma_cmd, true, true, 0);2023 2024	brcmnand_dma_run(host, ctrl->dma_pa);2025 2026	dma_unmap_single(ctrl->dev, buf_pa, len, dir);2027 2028	if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)2029		return -EBADMSG;2030	else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)2031		return -EUCLEAN;2032 2033	return 0;2034}2035 2036/*2037 * Assumes proper CS is already set2038 */2039static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,2040				u64 addr, unsigned int trans, u32 *buf,2041				u8 *oob, u64 *err_addr)2042{2043	struct brcmnand_host *host = nand_get_controller_data(chip);2044	struct brcmnand_controller *ctrl = host->ctrl;2045	int i, ret = 0;2046 2047	brcmnand_clear_ecc_addr(ctrl);2048 2049	for (i = 0; i < trans; i++, addr += FC_BYTES) {2050		brcmnand_set_cmd_addr(mtd, addr);2051		/* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */2052		brcmnand_send_cmd(host, CMD_PAGE_READ);2053		brcmnand_waitfunc(chip);2054 2055		if (likely(buf)) {2056			brcmnand_soc_data_bus_prepare(ctrl->soc, false);2057 2058			brcmnand_read_data_bus(ctrl, ctrl->nand_fc, buf, FC_WORDS);2059			buf += FC_WORDS;2060 2061			brcmnand_soc_data_bus_unprepare(ctrl->soc, false);2062		}2063 2064		if (oob)2065			oob += read_oob_from_regs(ctrl, i, oob,2066					mtd->oobsize / trans,2067					host->hwcfg.sector_size_1k);2068 2069		if (ret != -EBADMSG) {2070			*err_addr = brcmnand_get_uncorrecc_addr(ctrl);2071 2072			if (*err_addr)2073				ret = -EBADMSG;2074		}2075 2076		if (!ret) {2077			*err_addr = brcmnand_get_correcc_addr(ctrl);2078 2079			if (*err_addr)2080				ret = -EUCLEAN;2081		}2082	}2083 2084	return ret;2085}2086 2087/*2088 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC2089 * error2090 *2091 * Because the HW ECC signals an ECC error if an erase paged has even a single2092 * bitflip, we must check each ECC error to see if it is actually an erased2093 * page with bitflips, not a truly corrupted page.2094 *2095 * On a real error, return a negative error code (-EBADMSG for ECC error), and2096 * buf will contain raw data.2097 * Otherwise, buf gets filled with 0xffs and return the maximum number of2098 * bitflips-per-ECC-sector to the caller.2099 *2100 */2101static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,2102		  struct nand_chip *chip, void *buf, u64 addr)2103{2104	struct mtd_oob_region ecc;2105	int i;2106	int bitflips = 0;2107	int page = addr >> chip->page_shift;2108	int ret;2109	void *ecc_bytes;2110	void *ecc_chunk;2111 2112	if (!buf)2113		buf = nand_get_data_buf(chip);2114 2115	/* read without ecc for verification */2116	ret = chip->ecc.read_page_raw(chip, buf, true, page);2117	if (ret)2118		return ret;2119 2120	for (i = 0; i < chip->ecc.steps; i++) {2121		ecc_chunk = buf + chip->ecc.size * i;2122 2123		mtd_ooblayout_ecc(mtd, i, &ecc);2124		ecc_bytes = chip->oob_poi + ecc.offset;2125 2126		ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,2127						  ecc_bytes, ecc.length,2128						  NULL, 0,2129						  chip->ecc.strength);2130		if (ret < 0)2131			return ret;2132 2133		bitflips = max(bitflips, ret);2134	}2135 2136	return bitflips;2137}2138 2139static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,2140			 u64 addr, unsigned int trans, u32 *buf, u8 *oob)2141{2142	struct brcmnand_host *host = nand_get_controller_data(chip);2143	struct brcmnand_controller *ctrl = host->ctrl;2144	u64 err_addr = 0;2145	int err;2146	bool retry = true;2147	bool edu_err = false;2148 2149	dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);2150 2151try_dmaread:2152	brcmnand_clear_ecc_addr(ctrl);2153 2154	if (ctrl->dma_trans && (has_edu(ctrl) || !oob) &&2155	    flash_dma_buf_ok(buf)) {2156		err = ctrl->dma_trans(host, addr, buf, oob,2157				      trans * FC_BYTES,2158				      CMD_PAGE_READ);2159 2160		if (err) {2161			if (mtd_is_bitflip_or_eccerr(err))2162				err_addr = addr;2163			else2164				return -EIO;2165		}2166 2167		if (has_edu(ctrl) && err_addr)2168			edu_err = true;2169 2170	} else {2171		if (oob)2172			memset(oob, 0x99, mtd->oobsize);2173 2174		err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,2175					       oob, &err_addr);2176	}2177 2178	if (mtd_is_eccerr(err)) {2179		/*2180		 * On controller version and 7.0, 7.1 , DMA read after a2181		 * prior PIO read that reported uncorrectable error,2182		 * the DMA engine captures this error following DMA read2183		 * cleared only on subsequent DMA read, so just retry once2184		 * to clear a possible false error reported for current DMA2185		 * read2186		 */2187		if ((ctrl->nand_version == 0x0700) ||2188		    (ctrl->nand_version == 0x0701)) {2189			if (retry) {2190				retry = false;2191				goto try_dmaread;2192			}2193		}2194 2195		/*2196		 * Controller version 7.2 has hw encoder to detect erased page2197		 * bitflips, apply sw verification for older controllers only2198		 */2199		if (ctrl->nand_version < 0x0702) {2200			err = brcmstb_nand_verify_erased_page(mtd, chip, buf,2201							      addr);2202			/* erased page bitflips corrected */2203			if (err >= 0)2204				return err;2205		}2206 2207		dev_err(ctrl->dev, "uncorrectable error at 0x%llx\n",2208			(unsigned long long)err_addr);2209		mtd->ecc_stats.failed++;2210		/* NAND layer expects zero on ECC errors */2211		return 0;2212	}2213 2214	if (mtd_is_bitflip(err)) {2215		unsigned int corrected = brcmnand_count_corrected(ctrl);2216 2217		/* in case of EDU correctable error we read again using PIO */2218		if (edu_err)2219			err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,2220						   oob, &err_addr);2221 2222		dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",2223			(unsigned long long)err_addr);2224		mtd->ecc_stats.corrected += corrected;2225		/* Always exceed the software-imposed threshold */2226		return max(mtd->bitflip_threshold, corrected);2227	}2228 2229	return 0;2230}2231 2232static int brcmnand_read_page(struct nand_chip *chip, uint8_t *buf,2233			      int oob_required, int page)2234{2235	struct mtd_info *mtd = nand_to_mtd(chip);2236	struct brcmnand_host *host = nand_get_controller_data(chip);2237	u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;2238	u64 addr = (u64)page << chip->page_shift;2239 2240	host->last_addr = addr;2241 2242	return brcmnand_read(mtd, chip, host->last_addr,2243			mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);2244}2245 2246static int brcmnand_read_page_raw(struct nand_chip *chip, uint8_t *buf,2247				  int oob_required, int page)2248{2249	struct brcmnand_host *host = nand_get_controller_data(chip);2250	struct mtd_info *mtd = nand_to_mtd(chip);2251	u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;2252	int ret;2253	u64 addr = (u64)page << chip->page_shift;2254 2255	host->last_addr = addr;2256 2257	brcmnand_set_ecc_enabled(host, 0);2258	ret = brcmnand_read(mtd, chip, host->last_addr,2259			mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);2260	brcmnand_set_ecc_enabled(host, 1);2261	return ret;2262}2263 2264static int brcmnand_read_oob(struct nand_chip *chip, int page)2265{2266	struct mtd_info *mtd = nand_to_mtd(chip);2267 2268	return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,2269			mtd->writesize >> FC_SHIFT,2270			NULL, (u8 *)chip->oob_poi);2271}2272 2273static int brcmnand_read_oob_raw(struct nand_chip *chip, int page)2274{2275	struct mtd_info *mtd = nand_to_mtd(chip);2276	struct brcmnand_host *host = nand_get_controller_data(chip);2277 2278	brcmnand_set_ecc_enabled(host, 0);2279	brcmnand_read(mtd, chip, (u64)page << chip->page_shift,2280		mtd->writesize >> FC_SHIFT,2281		NULL, (u8 *)chip->oob_poi);2282	brcmnand_set_ecc_enabled(host, 1);2283	return 0;2284}2285 2286static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,2287			  u64 addr, const u32 *buf, u8 *oob)2288{2289	struct brcmnand_host *host = nand_get_controller_data(chip);2290	struct brcmnand_controller *ctrl = host->ctrl;2291	unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;2292	int status, ret = 0;2293 2294	dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);2295 2296	if (unlikely((unsigned long)buf & 0x03)) {2297		dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);2298		buf = (u32 *)((unsigned long)buf & ~0x03);2299	}2300 2301	brcmnand_wp(mtd, 0);2302 2303	for (i = 0; i < ctrl->max_oob; i += 4)2304		oob_reg_write(ctrl, i, 0xffffffff);2305 2306	if (mtd->oops_panic_write)2307		/* switch to interrupt polling and PIO mode */2308		disable_ctrl_irqs(ctrl);2309 2310	if (use_dma(ctrl) && (has_edu(ctrl) || !oob) && flash_dma_buf_ok(buf)) {2311		if (ctrl->dma_trans(host, addr, (u32 *)buf, oob, mtd->writesize,2312				    CMD_PROGRAM_PAGE))2313 2314			ret = -EIO;2315 2316		goto out;2317	}2318 2319	for (i = 0; i < trans; i++, addr += FC_BYTES) {2320		/* full address MUST be set before populating FC */2321		brcmnand_set_cmd_addr(mtd, addr);2322 2323		if (buf) {2324			brcmnand_soc_data_bus_prepare(ctrl->soc, false);2325 2326			for (j = 0; j < FC_WORDS; j++, buf++)2327				brcmnand_write_fc(ctrl, j, *buf);2328 2329			brcmnand_soc_data_bus_unprepare(ctrl->soc, false);2330		} else if (oob) {2331			for (j = 0; j < FC_WORDS; j++)2332				brcmnand_write_fc(ctrl, j, 0xffffffff);2333		}2334 2335		if (oob) {2336			oob += write_oob_to_regs(ctrl, i, oob,2337					mtd->oobsize / trans,2338					host->hwcfg.sector_size_1k);2339		}2340 2341		/* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */2342		brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);2343		status = brcmnand_waitfunc(chip);2344 2345		if (status & NAND_STATUS_FAIL) {2346			dev_info(ctrl->dev, "program failed at %llx\n",2347				(unsigned long long)addr);2348			ret = -EIO;2349			goto out;2350		}2351	}2352out:2353	brcmnand_wp(mtd, 1);2354	return ret;2355}2356 2357static int brcmnand_write_page(struct nand_chip *chip, const uint8_t *buf,2358			       int oob_required, int page)2359{2360	struct mtd_info *mtd = nand_to_mtd(chip);2361	struct brcmnand_host *host = nand_get_controller_data(chip);2362	void *oob = oob_required ? chip->oob_poi : NULL;2363	u64 addr = (u64)page << chip->page_shift;2364 2365	host->last_addr = addr;2366 2367	return brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);2368}2369 2370static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,2371				   int oob_required, int page)2372{2373	struct mtd_info *mtd = nand_to_mtd(chip);2374	struct brcmnand_host *host = nand_get_controller_data(chip);2375	void *oob = oob_required ? chip->oob_poi : NULL;2376	u64 addr = (u64)page << chip->page_shift;2377	int ret = 0;2378 2379	host->last_addr = addr;2380	brcmnand_set_ecc_enabled(host, 0);2381	ret = brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);2382	brcmnand_set_ecc_enabled(host, 1);2383 2384	return ret;2385}2386 2387static int brcmnand_write_oob(struct nand_chip *chip, int page)2388{2389	return brcmnand_write(nand_to_mtd(chip), chip,2390			      (u64)page << chip->page_shift, NULL,2391			      chip->oob_poi);2392}2393 2394static int brcmnand_write_oob_raw(struct nand_chip *chip, int page)2395{2396	struct mtd_info *mtd = nand_to_mtd(chip);2397	struct brcmnand_host *host = nand_get_controller_data(chip);2398	int ret;2399 2400	brcmnand_set_ecc_enabled(host, 0);2401	ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,2402				 (u8 *)chip->oob_poi);2403	brcmnand_set_ecc_enabled(host, 1);2404 2405	return ret;2406}2407 2408static int brcmnand_exec_instr(struct brcmnand_host *host, int i,2409		const struct nand_operation *op)2410{2411	const struct nand_op_instr *instr = &op->instrs[i];2412	struct brcmnand_controller *ctrl = host->ctrl;2413	const u8 *out;2414	bool last_op;2415	int ret = 0;2416	u8 *in;2417 2418	/*2419	 * The controller needs to be aware of the last command in the operation2420	 * (WAITRDY excepted).2421	 */2422	last_op = ((i == (op->ninstrs - 1)) && (instr->type != NAND_OP_WAITRDY_INSTR)) ||2423		  ((i == (op->ninstrs - 2)) && (op->instrs[i + 1].type == NAND_OP_WAITRDY_INSTR));2424 2425	switch (instr->type) {2426	case NAND_OP_CMD_INSTR:2427		brcmnand_low_level_op(host, LL_OP_CMD, instr->ctx.cmd.opcode, last_op);2428		break;2429 2430	case NAND_OP_ADDR_INSTR:2431		for (i = 0; i < instr->ctx.addr.naddrs; i++)2432			brcmnand_low_level_op(host, LL_OP_ADDR, instr->ctx.addr.addrs[i],2433					      last_op && (i == (instr->ctx.addr.naddrs - 1)));2434		break;2435 2436	case NAND_OP_DATA_IN_INSTR:2437		in = instr->ctx.data.buf.in;2438		for (i = 0; i < instr->ctx.data.len; i++) {2439			brcmnand_low_level_op(host, LL_OP_RD, 0,2440					      last_op && (i == (instr->ctx.data.len - 1)));2441			in[i] = brcmnand_read_reg(host->ctrl, BRCMNAND_LL_RDATA);2442		}2443		break;2444 2445	case NAND_OP_DATA_OUT_INSTR:2446		out = instr->ctx.data.buf.out;2447		for (i = 0; i < instr->ctx.data.len; i++)2448			brcmnand_low_level_op(host, LL_OP_WR, out[i],2449					      last_op && (i == (instr->ctx.data.len - 1)));2450		break;2451 2452	case NAND_OP_WAITRDY_INSTR:2453		ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);2454		break;2455 2456	default:2457		dev_err(ctrl->dev, "unsupported instruction type: %d\n",2458			instr->type);2459		ret = -EINVAL;2460		break;2461	}2462 2463	return ret;2464}2465 2466static int brcmnand_op_is_status(const struct nand_operation *op)2467{2468	if (op->ninstrs == 2 &&2469	    op->instrs[0].type == NAND_OP_CMD_INSTR &&2470	    op->instrs[0].ctx.cmd.opcode == NAND_CMD_STATUS &&2471	    op->instrs[1].type == NAND_OP_DATA_IN_INSTR)2472		return 1;2473 2474	return 0;2475}2476 2477static int brcmnand_op_is_reset(const struct nand_operation *op)2478{2479	if (op->ninstrs == 2 &&2480	    op->instrs[0].type == NAND_OP_CMD_INSTR &&2481	    op->instrs[0].ctx.cmd.opcode == NAND_CMD_RESET &&2482	    op->instrs[1].type == NAND_OP_WAITRDY_INSTR)2483		return 1;2484 2485	return 0;2486}2487 2488static int brcmnand_exec_op(struct nand_chip *chip,2489			    const struct nand_operation *op,2490			    bool check_only)2491{2492	struct brcmnand_host *host = nand_get_controller_data(chip);2493	struct mtd_info *mtd = nand_to_mtd(chip);2494	u8 *status;2495	unsigned int i;2496	int ret = 0;2497 2498	if (check_only)2499		return 0;2500 2501	if (brcmnand_op_is_status(op)) {2502		status = op->instrs[1].ctx.data.buf.in;2503		ret = brcmnand_status(host);2504		if (ret < 0)2505			return ret;2506 2507		*status = ret & 0xFF;2508 2509		return 0;2510	} else if (brcmnand_op_is_reset(op)) {2511		ret = brcmnand_reset(host);2512		if (ret < 0)2513			return ret;2514 2515		brcmnand_wp(mtd, 1);2516 2517		return 0;2518	}2519 2520	if (op->deassert_wp)2521		brcmnand_wp(mtd, 0);2522 2523	for (i = 0; i < op->ninstrs; i++) {2524		ret = brcmnand_exec_instr(host, i, op);2525		if (ret)2526			break;2527	}2528 2529	if (op->deassert_wp)2530		brcmnand_wp(mtd, 1);2531 2532	return ret;2533}2534 2535/***********************************************************************2536 * Per-CS setup (1 NAND device)2537 ***********************************************************************/2538 2539static int brcmnand_set_cfg(struct brcmnand_host *host,2540			    struct brcmnand_cfg *cfg)2541{2542	struct brcmnand_controller *ctrl = host->ctrl;2543	struct nand_chip *chip = &host->chip;2544	u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);2545	u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,2546			BRCMNAND_CS_CFG_EXT);2547	u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,2548			BRCMNAND_CS_ACC_CONTROL);2549	u8 block_size = 0, page_size = 0, device_size = 0;2550	u32 tmp;2551 2552	if (ctrl->block_sizes) {2553		int i, found;2554 2555		for (i = 0, found = 0; ctrl->block_sizes[i]; i++)2556			if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {2557				block_size = i;2558				found = 1;2559			}2560		if (!found) {2561			dev_warn(ctrl->dev, "invalid block size %u\n",2562					cfg->block_size);2563			return -EINVAL;2564		}2565	} else {2566		block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);2567	}2568 2569	if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&2570				cfg->block_size > ctrl->max_block_size)) {2571		dev_warn(ctrl->dev, "invalid block size %u\n",2572				cfg->block_size);2573		block_size = 0;2574	}2575 2576	if (ctrl->page_sizes) {2577		int i, found;2578 2579		for (i = 0, found = 0; ctrl->page_sizes[i]; i++)2580			if (ctrl->page_sizes[i] == cfg->page_size) {2581				page_size = i;2582				found = 1;2583			}2584		if (!found) {2585			dev_warn(ctrl->dev, "invalid page size %u\n",2586					cfg->page_size);2587			return -EINVAL;2588		}2589	} else {2590		page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);2591	}2592 2593	if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&2594				cfg->page_size > ctrl->max_page_size)) {2595		dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);2596		return -EINVAL;2597	}2598 2599	if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {2600		dev_warn(ctrl->dev, "invalid device size 0x%llx\n",2601			(unsigned long long)cfg->device_size);2602		return -EINVAL;2603	}2604	device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);2605 2606	tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |2607		(cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |2608		(cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |2609		(!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |2610		(device_size << CFG_DEVICE_SIZE_SHIFT);2611	if (cfg_offs == cfg_ext_offs) {2612		tmp |= (page_size << ctrl->page_size_shift) |2613		       (block_size << CFG_BLK_SIZE_SHIFT);2614		nand_writereg(ctrl, cfg_offs, tmp);2615	} else {2616		nand_writereg(ctrl, cfg_offs, tmp);2617		tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |2618		      (block_size << CFG_EXT_BLK_SIZE_SHIFT);2619		nand_writereg(ctrl, cfg_ext_offs, tmp);2620	}2621 2622	tmp = nand_readreg(ctrl, acc_control_offs);2623	tmp &= ~brcmnand_ecc_level_mask(ctrl);2624	tmp &= ~brcmnand_spare_area_mask(ctrl);2625	if (ctrl->nand_version >= 0x0302) {2626		tmp |= cfg->ecc_level << ctrl->ecc_level_shift;2627		tmp |= cfg->spare_area_size;2628	}2629	nand_writereg(ctrl, acc_control_offs, tmp);2630 2631	brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);2632 2633	/* threshold = ceil(BCH-level * 0.75) */2634	brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));2635 2636	return 0;2637}2638 2639static void brcmnand_print_cfg(struct brcmnand_host *host,2640			       char *buf, struct brcmnand_cfg *cfg)2641{2642	buf += sprintf(buf,2643		"%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",2644		(unsigned long long)cfg->device_size >> 20,2645		cfg->block_size >> 10,2646		cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,2647		cfg->page_size >= 1024 ? "KiB" : "B",2648		cfg->spare_area_size, cfg->device_width);2649 2650	/* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */2651	if (is_hamming_ecc(host->ctrl, cfg))2652		sprintf(buf, ", Hamming ECC");2653	else if (cfg->sector_size_1k)2654		sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);2655	else2656		sprintf(buf, ", BCH-%u", cfg->ecc_level);2657}2658 2659/*2660 * Minimum number of bytes to address a page. Calculated as:2661 *     roundup(log2(size / page-size) / 8)2662 *2663 * NB: the following does not "round up" for non-power-of-2 'size'; but this is2664 *     OK because many other things will break if 'size' is irregular...2665 */2666static inline int get_blk_adr_bytes(u64 size, u32 writesize)2667{2668	return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;2669}2670 2671static int brcmnand_setup_dev(struct brcmnand_host *host)2672{2673	struct mtd_info *mtd = nand_to_mtd(&host->chip);2674	struct nand_chip *chip = &host->chip;2675	const struct nand_ecc_props *requirements =2676		nanddev_get_ecc_requirements(&chip->base);2677	struct nand_memory_organization *memorg =2678		nanddev_get_memorg(&chip->base);2679	struct brcmnand_controller *ctrl = host->ctrl;2680	struct brcmnand_cfg *cfg = &host->hwcfg;2681	struct device_node *np = nand_get_flash_node(chip);2682	u32 offs, tmp, oob_sector;2683	bool use_strap = false;2684	char msg[128];2685	int ret;2686 2687	memset(cfg, 0, sizeof(*cfg));2688	use_strap = of_property_read_bool(np, "brcm,nand-ecc-use-strap");2689 2690	/*2691	 * Either nand-ecc-xxx or brcm,nand-ecc-use-strap can be set. Error out2692	 * if both exist.2693	 */2694	if (chip->ecc.strength && use_strap) {2695		dev_err(ctrl->dev,2696			"ECC strap and DT ECC configuration properties are mutually exclusive\n");2697		return -EINVAL;2698	}2699 2700	if (use_strap)2701		brcmnand_get_ecc_settings(host, chip);2702 2703	ret = of_property_read_u32(np, "brcm,nand-oob-sector-size",2704				   &oob_sector);2705	if (ret) {2706		if (use_strap)2707			cfg->spare_area_size = brcmnand_get_spare_size(host);2708		else2709			/* Use detected size */2710			cfg->spare_area_size = mtd->oobsize /2711						(mtd->writesize >> FC_SHIFT);2712	} else {2713		cfg->spare_area_size = oob_sector;2714	}2715	if (cfg->spare_area_size > ctrl->max_oob)2716		cfg->spare_area_size = ctrl->max_oob;2717	/*2718	 * Set mtd and memorg oobsize to be consistent with controller's2719	 * spare_area_size, as the rest is inaccessible.2720	 */2721	mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);2722	memorg->oobsize = mtd->oobsize;2723 2724	cfg->device_size = mtd->size;2725	cfg->block_size = mtd->erasesize;2726	cfg->page_size = mtd->writesize;2727	cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;2728	cfg->col_adr_bytes = 2;2729	cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);2730 2731	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) {2732		dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n",2733			chip->ecc.engine_type);2734		return -EINVAL;2735	}2736 2737	if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) {2738		if (chip->ecc.strength == 1 && chip->ecc.size == 512)2739			/* Default to Hamming for 1-bit ECC, if unspecified */2740			chip->ecc.algo = NAND_ECC_ALGO_HAMMING;2741		else2742			/* Otherwise, BCH */2743			chip->ecc.algo = NAND_ECC_ALGO_BCH;2744	}2745 2746	if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING &&2747	    (chip->ecc.strength != 1 || chip->ecc.size != 512)) {2748		dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",2749			chip->ecc.strength, chip->ecc.size);2750		return -EINVAL;2751	}2752 2753	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE &&2754	    (!chip->ecc.size || !chip->ecc.strength)) {2755		if (requirements->step_size && requirements->strength) {2756			/* use detected ECC parameters */2757			chip->ecc.size = requirements->step_size;2758			chip->ecc.strength = requirements->strength;2759			dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n",2760				chip->ecc.size, chip->ecc.strength);2761		}2762	}2763 2764	switch (chip->ecc.size) {2765	case 512:2766		if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)2767			cfg->ecc_level = 15;2768		else2769			cfg->ecc_level = chip->ecc.strength;2770		cfg->sector_size_1k = 0;2771		break;2772	case 1024:2773		if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {2774			dev_err(ctrl->dev, "1KB sectors not supported\n");2775			return -EINVAL;2776		}2777		if (chip->ecc.strength & 0x1) {2778			dev_err(ctrl->dev,2779				"odd ECC not supported with 1KB sectors\n");2780			return -EINVAL;2781		}2782 2783		cfg->ecc_level = chip->ecc.strength >> 1;2784		cfg->sector_size_1k = 1;2785		break;2786	default:2787		dev_err(ctrl->dev, "unsupported ECC size: %d\n",2788			chip->ecc.size);2789		return -EINVAL;2790	}2791 2792	cfg->ful_adr_bytes = cfg->blk_adr_bytes;2793	if (mtd->writesize > 512)2794		cfg->ful_adr_bytes += cfg->col_adr_bytes;2795	else2796		cfg->ful_adr_bytes += 1;2797 2798	ret = brcmnand_set_cfg(host, cfg);2799	if (ret)2800		return ret;2801 2802	brcmnand_set_ecc_enabled(host, 1);2803 2804	brcmnand_print_cfg(host, msg, cfg);2805	dev_info(ctrl->dev, "detected %s\n", msg);2806 2807	/* Configure ACC_CONTROL */2808	offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);2809	tmp = nand_readreg(ctrl, offs);2810	tmp &= ~ACC_CONTROL_PARTIAL_PAGE;2811	tmp &= ~ACC_CONTROL_RD_ERASED;2812 2813	/* We need to turn on Read from erased paged protected by ECC */2814	if (ctrl->nand_version >= 0x0702)2815		tmp |= ACC_CONTROL_RD_ERASED;2816	tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;2817	if (ctrl->features & BRCMNAND_HAS_PREFETCH)2818		tmp &= ~ACC_CONTROL_PREFETCH;2819 2820	nand_writereg(ctrl, offs, tmp);2821 2822	return 0;2823}2824 2825static int brcmnand_attach_chip(struct nand_chip *chip)2826{2827	struct mtd_info *mtd = nand_to_mtd(chip);2828	struct brcmnand_host *host = nand_get_controller_data(chip);2829	int ret;2830 2831	chip->options |= NAND_NO_SUBPAGE_WRITE;2832	/*2833	 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA2834	 * to/from, and have nand_base pass us a bounce buffer instead, as2835	 * needed.2836	 */2837	chip->options |= NAND_USES_DMA;2838 2839	if (chip->bbt_options & NAND_BBT_USE_FLASH)2840		chip->bbt_options |= NAND_BBT_NO_OOB;2841 2842	if (brcmnand_setup_dev(host))2843		return -ENXIO;2844 2845	chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;2846 2847	/* only use our internal HW threshold */2848	mtd->bitflip_threshold = 1;2849 2850	ret = brcmstb_choose_ecc_layout(host);2851 2852	/* If OOB is written with ECC enabled it will cause ECC errors */2853	if (is_hamming_ecc(host->ctrl, &host->hwcfg)) {2854		chip->ecc.write_oob = brcmnand_write_oob_raw;2855		chip->ecc.read_oob = brcmnand_read_oob_raw;2856	}2857 2858	return ret;2859}2860 2861static const struct nand_controller_ops brcmnand_controller_ops = {2862	.attach_chip = brcmnand_attach_chip,2863	.exec_op = brcmnand_exec_op,2864};2865 2866static int brcmnand_init_cs(struct brcmnand_host *host,2867			    const char * const *part_probe_types)2868{2869	struct brcmnand_controller *ctrl = host->ctrl;2870	struct device *dev = ctrl->dev;2871	struct mtd_info *mtd;2872	struct nand_chip *chip;2873	int ret;2874	u16 cfg_offs;2875 2876	mtd = nand_to_mtd(&host->chip);2877	chip = &host->chip;2878 2879	nand_set_controller_data(chip, host);2880	mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d",2881				   host->cs);2882	if (!mtd->name)2883		return -ENOMEM;2884 2885	mtd->owner = THIS_MODULE;2886	mtd->dev.parent = dev;2887 2888	chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;2889	chip->ecc.read_page = brcmnand_read_page;2890	chip->ecc.write_page = brcmnand_write_page;2891	chip->ecc.read_page_raw = brcmnand_read_page_raw;2892	chip->ecc.write_page_raw = brcmnand_write_page_raw;2893	chip->ecc.write_oob_raw = brcmnand_write_oob_raw;2894	chip->ecc.read_oob_raw = brcmnand_read_oob_raw;2895	chip->ecc.read_oob = brcmnand_read_oob;2896	chip->ecc.write_oob = brcmnand_write_oob;2897 2898	chip->controller = &ctrl->controller;2899	ctrl->controller.controller_wp = 1;2900 2901	/*2902	 * The bootloader might have configured 16bit mode but2903	 * NAND READID command only works in 8bit mode. We force2904	 * 8bit mode here to ensure that NAND READID commands works.2905	 */2906	cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);2907	nand_writereg(ctrl, cfg_offs,2908		      nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);2909 2910	ret = nand_scan(chip, 1);2911	if (ret)2912		return ret;2913 2914	ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);2915	if (ret)2916		nand_cleanup(chip);2917 2918	return ret;2919}2920 2921static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,2922					    int restore)2923{2924	struct brcmnand_controller *ctrl = host->ctrl;2925	u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);2926	u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,2927			BRCMNAND_CS_CFG_EXT);2928	u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,2929			BRCMNAND_CS_ACC_CONTROL);2930	u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);2931	u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);2932 2933	if (restore) {2934		nand_writereg(ctrl, cfg_offs, host->hwcfg.config);2935		if (cfg_offs != cfg_ext_offs)2936			nand_writereg(ctrl, cfg_ext_offs,2937				      host->hwcfg.config_ext);2938		nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);2939		nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);2940		nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);2941	} else {2942		host->hwcfg.config = nand_readreg(ctrl, cfg_offs);2943		if (cfg_offs != cfg_ext_offs)2944			host->hwcfg.config_ext =2945				nand_readreg(ctrl, cfg_ext_offs);2946		host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);2947		host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);2948		host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);2949	}2950}2951 2952static int brcmnand_suspend(struct device *dev)2953{2954	struct brcmnand_controller *ctrl = dev_get_drvdata(dev);2955	struct brcmnand_host *host;2956 2957	list_for_each_entry(host, &ctrl->host_list, node)2958		brcmnand_save_restore_cs_config(host, 0);2959 2960	ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);2961	ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);2962	ctrl->corr_stat_threshold =2963		brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);2964 2965	if (has_flash_dma(ctrl))2966		ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);2967	else if (has_edu(ctrl))2968		ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG);2969 2970	return 0;2971}2972 2973static int brcmnand_resume(struct device *dev)2974{2975	struct brcmnand_controller *ctrl = dev_get_drvdata(dev);2976	struct brcmnand_host *host;2977 2978	if (has_flash_dma(ctrl)) {2979		flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);2980		flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);2981	}2982 2983	if (has_edu(ctrl)) {2984		ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG);2985		edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config);2986		edu_readl(ctrl, EDU_CONFIG);2987		brcmnand_edu_init(ctrl);2988	}2989 2990	brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);2991	brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);2992	brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,2993			ctrl->corr_stat_threshold);2994	if (ctrl->soc) {2995		/* Clear/re-enable interrupt */2996		ctrl->soc->ctlrdy_ack(ctrl->soc);2997		ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);2998	}2999 3000	list_for_each_entry(host, &ctrl->host_list, node) {3001		struct nand_chip *chip = &host->chip;3002 3003		brcmnand_save_restore_cs_config(host, 1);3004 3005		/* Reset the chip, required by some chips after power-up */3006		nand_reset_op(chip);3007	}3008 3009	return 0;3010}3011 3012const struct dev_pm_ops brcmnand_pm_ops = {3013	.suspend		= brcmnand_suspend,3014	.resume			= brcmnand_resume,3015};3016EXPORT_SYMBOL_GPL(brcmnand_pm_ops);3017 3018static const struct of_device_id __maybe_unused brcmnand_of_match[] = {3019	{ .compatible = "brcm,brcmnand-v2.1" },3020	{ .compatible = "brcm,brcmnand-v2.2" },3021	{ .compatible = "brcm,brcmnand-v4.0" },3022	{ .compatible = "brcm,brcmnand-v5.0" },3023	{ .compatible = "brcm,brcmnand-v6.0" },3024	{ .compatible = "brcm,brcmnand-v6.1" },3025	{ .compatible = "brcm,brcmnand-v6.2" },3026	{ .compatible = "brcm,brcmnand-v7.0" },3027	{ .compatible = "brcm,brcmnand-v7.1" },3028	{ .compatible = "brcm,brcmnand-v7.2" },3029	{ .compatible = "brcm,brcmnand-v7.3" },3030	{},3031};3032MODULE_DEVICE_TABLE(of, brcmnand_of_match);3033 3034/***********************************************************************3035 * Platform driver setup (per controller)3036 ***********************************************************************/3037static int brcmnand_edu_setup(struct platform_device *pdev)3038{3039	struct device *dev = &pdev->dev;3040	struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);3041	struct resource *res;3042	int ret;3043 3044	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu");3045	if (res) {3046		ctrl->edu_base = devm_ioremap_resource(dev, res);3047		if (IS_ERR(ctrl->edu_base))3048			return PTR_ERR(ctrl->edu_base);3049 3050		ctrl->edu_offsets = edu_regs;3051 3052		edu_writel(ctrl, EDU_CONFIG, EDU_CONFIG_MODE_NAND |3053			   EDU_CONFIG_SWAP_CFG);3054		edu_readl(ctrl, EDU_CONFIG);3055 3056		/* initialize edu */3057		brcmnand_edu_init(ctrl);3058 3059		ctrl->edu_irq = platform_get_irq_optional(pdev, 1);3060		if (ctrl->edu_irq < 0) {3061			dev_warn(dev,3062				 "FLASH EDU enabled, using ctlrdy irq\n");3063		} else {3064			ret = devm_request_irq(dev, ctrl->edu_irq,3065					       brcmnand_edu_irq, 0,3066					       "brcmnand-edu", ctrl);3067			if (ret < 0) {3068				dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n",3069					ctrl->edu_irq, ret);3070				return ret;3071			}3072 3073			dev_info(dev, "FLASH EDU enabled using irq %u\n",3074				 ctrl->edu_irq);3075		}3076	}3077 3078	return 0;3079}3080 3081int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)3082{3083	struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev);3084	struct device *dev = &pdev->dev;3085	struct device_node *dn = dev->of_node, *child;3086	struct brcmnand_controller *ctrl;3087	struct brcmnand_host *host;3088	struct resource *res;3089	int ret;3090 3091	if (dn && !of_match_node(brcmnand_of_match, dn))3092		return -ENODEV;3093 3094	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);3095	if (!ctrl)3096		return -ENOMEM;3097 3098	dev_set_drvdata(dev, ctrl);3099	ctrl->dev = dev;3100	ctrl->soc = soc;3101 3102	/* Enable the static key if the soc provides I/O operations indicating3103	 * that a non-memory mapped IO access path must be used3104	 */3105	if (brcmnand_soc_has_ops(ctrl->soc))3106		static_branch_enable(&brcmnand_soc_has_ops_key);3107 3108	init_completion(&ctrl->done);3109	init_completion(&ctrl->dma_done);3110	init_completion(&ctrl->edu_done);3111	nand_controller_init(&ctrl->controller);3112	ctrl->controller.ops = &brcmnand_controller_ops;3113	INIT_LIST_HEAD(&ctrl->host_list);3114 3115	/* NAND register range */3116	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);3117	ctrl->nand_base = devm_ioremap_resource(dev, res);3118	if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc))3119		return PTR_ERR(ctrl->nand_base);3120 3121	/* Enable clock before using NAND registers */3122	ctrl->clk = devm_clk_get(dev, "nand");3123	if (!IS_ERR(ctrl->clk)) {3124		ret = clk_prepare_enable(ctrl->clk);3125		if (ret)3126			return ret;3127	} else {3128		ret = PTR_ERR(ctrl->clk);3129		if (ret == -EPROBE_DEFER)3130			return ret;3131 3132		ctrl->clk = NULL;3133	}3134 3135	/* Initialize NAND revision */3136	ret = brcmnand_revision_init(ctrl);3137	if (ret)3138		goto err;3139 3140	/*3141	 * Most chips have this cache at a fixed offset within 'nand' block.3142	 * Some must specify this region separately.3143	 */3144	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");3145	if (res) {3146		ctrl->nand_fc = devm_ioremap_resource(dev, res);3147		if (IS_ERR(ctrl->nand_fc)) {3148			ret = PTR_ERR(ctrl->nand_fc);3149			goto err;3150		}3151	} else {3152		ctrl->nand_fc = ctrl->nand_base +3153				ctrl->reg_offsets[BRCMNAND_FC_BASE];3154	}3155 3156	/* FLASH_DMA */3157	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");3158	if (res) {3159		ctrl->flash_dma_base = devm_ioremap_resource(dev, res);3160		if (IS_ERR(ctrl->flash_dma_base)) {3161			ret = PTR_ERR(ctrl->flash_dma_base);3162			goto err;3163		}3164 3165		/* initialize the dma version */3166		brcmnand_flash_dma_revision_init(ctrl);3167 3168		ret = -EIO;3169		if (ctrl->nand_version >= 0x0700)3170			ret = dma_set_mask_and_coherent(&pdev->dev,3171							DMA_BIT_MASK(40));3172		if (ret)3173			ret = dma_set_mask_and_coherent(&pdev->dev,3174							DMA_BIT_MASK(32));3175		if (ret)3176			goto err;3177 3178		/* linked-list and stop on error */3179		flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK);3180		flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);3181 3182		/* Allocate descriptor(s) */3183		ctrl->dma_desc = dmam_alloc_coherent(dev,3184						     sizeof(*ctrl->dma_desc),3185						     &ctrl->dma_pa, GFP_KERNEL);3186		if (!ctrl->dma_desc) {3187			ret = -ENOMEM;3188			goto err;3189		}3190 3191		ctrl->dma_irq = platform_get_irq(pdev, 1);3192		if ((int)ctrl->dma_irq < 0) {3193			dev_err(dev, "missing FLASH_DMA IRQ\n");3194			ret = -ENODEV;3195			goto err;3196		}3197 3198		ret = devm_request_irq(dev, ctrl->dma_irq,3199				brcmnand_dma_irq, 0, DRV_NAME,3200				ctrl);3201		if (ret < 0) {3202			dev_err(dev, "can't allocate IRQ %d: error %d\n",3203					ctrl->dma_irq, ret);3204			goto err;3205		}3206 3207		dev_info(dev, "enabling FLASH_DMA\n");3208		/* set flash dma transfer function to call */3209		ctrl->dma_trans = brcmnand_dma_trans;3210	} else	{3211		ret = brcmnand_edu_setup(pdev);3212		if (ret < 0)3213			goto err;3214 3215		if (has_edu(ctrl))3216			/* set edu transfer function to call */3217			ctrl->dma_trans = brcmnand_edu_trans;3218	}3219 3220	/* Disable automatic device ID config, direct addressing */3221	brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,3222			 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);3223	/* Disable XOR addressing */3224	brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);3225 3226	/* Check if the board connects the WP pin */3227	if (of_property_read_bool(dn, "brcm,wp-not-connected"))3228		wp_on = 0;3229 3230	if (ctrl->features & BRCMNAND_HAS_WP) {3231		/* Permanently disable write protection */3232		if (wp_on == 2)3233			brcmnand_set_wp(ctrl, false);3234	} else {3235		wp_on = 0;3236	}3237 3238	/* IRQ */3239	ctrl->irq = platform_get_irq_optional(pdev, 0);3240	if (ctrl->irq > 0) {3241		/*3242		 * Some SoCs integrate this controller (e.g., its interrupt bits) in3243		 * interesting ways3244		 */3245		if (soc) {3246			ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,3247					       DRV_NAME, ctrl);3248 3249			/* Enable interrupt */3250			ctrl->soc->ctlrdy_ack(ctrl->soc);3251			ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);3252		} else {3253			/* Use standard interrupt infrastructure */3254			ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,3255					       DRV_NAME, ctrl);3256		}3257		if (ret < 0) {3258			dev_err(dev, "can't allocate IRQ %d: error %d\n",3259				ctrl->irq, ret);3260			goto err;3261		}3262	}3263 3264	for_each_available_child_of_node(dn, child) {3265		if (of_device_is_compatible(child, "brcm,nandcs")) {3266 3267			host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);3268			if (!host) {3269				of_node_put(child);3270				ret = -ENOMEM;3271				goto err;3272			}3273			host->pdev = pdev;3274			host->ctrl = ctrl;3275 3276			ret = of_property_read_u32(child, "reg", &host->cs);3277			if (ret) {3278				dev_err(dev, "can't get chip-select\n");3279				devm_kfree(dev, host);3280				continue;3281			}3282 3283			nand_set_flash_node(&host->chip, child);3284 3285			ret = brcmnand_init_cs(host, NULL);3286			if (ret) {3287				if (ret == -EPROBE_DEFER) {3288					of_node_put(child);3289					goto err;3290				}3291				devm_kfree(dev, host);3292				continue; /* Try all chip-selects */3293			}3294 3295			list_add_tail(&host->node, &ctrl->host_list);3296		}3297	}3298 3299	if (!list_empty(&ctrl->host_list))3300		return 0;3301 3302	if (!pd) {3303		ret = -ENODEV;3304		goto err;3305	}3306 3307	/* If we got there we must have been probing via platform data */3308	host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);3309	if (!host) {3310		ret = -ENOMEM;3311		goto err;3312	}3313	host->pdev = pdev;3314	host->ctrl = ctrl;3315	host->cs = pd->chip_select;3316	host->chip.ecc.size = pd->ecc_stepsize;3317	host->chip.ecc.strength = pd->ecc_strength;3318 3319	ret = brcmnand_init_cs(host, pd->part_probe_types);3320	if (ret)3321		goto err;3322 3323	list_add_tail(&host->node, &ctrl->host_list);3324 3325	/* No chip-selects could initialize properly */3326	if (list_empty(&ctrl->host_list)) {3327		ret = -ENODEV;3328		goto err;3329	}3330 3331	return 0;3332 3333err:3334	clk_disable_unprepare(ctrl->clk);3335	return ret;3336 3337}3338EXPORT_SYMBOL_GPL(brcmnand_probe);3339 3340void brcmnand_remove(struct platform_device *pdev)3341{3342	struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);3343	struct brcmnand_host *host;3344	struct nand_chip *chip;3345	int ret;3346 3347	list_for_each_entry(host, &ctrl->host_list, node) {3348		chip = &host->chip;3349		ret = mtd_device_unregister(nand_to_mtd(chip));3350		WARN_ON(ret);3351		nand_cleanup(chip);3352	}3353 3354	clk_disable_unprepare(ctrl->clk);3355 3356	dev_set_drvdata(&pdev->dev, NULL);3357}3358EXPORT_SYMBOL_GPL(brcmnand_remove);3359 3360MODULE_LICENSE("GPL v2");3361MODULE_AUTHOR("Kevin Cernekee");3362MODULE_AUTHOR("Brian Norris");3363MODULE_DESCRIPTION("NAND driver for Broadcom chips");3364MODULE_ALIAS("platform:brcmnand");3365