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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Freescale GPMI NAND Flash Driver4 *5 * Copyright 2008-2011 Freescale Semiconductor, Inc.6 * Copyright 2008 Embedded Alley Solutions, Inc.7 */8#ifndef __GPMI_NAND_GPMI_REGS_H9#define __GPMI_NAND_GPMI_REGS_H10 11#define HW_GPMI_CTRL0 0x0000000012#define HW_GPMI_CTRL0_SET 0x0000000413#define HW_GPMI_CTRL0_CLR 0x0000000814#define HW_GPMI_CTRL0_TOG 0x0000000c15 16#define BP_GPMI_CTRL0_COMMAND_MODE 2417#define BM_GPMI_CTRL0_COMMAND_MODE (3 << BP_GPMI_CTRL0_COMMAND_MODE)18#define BF_GPMI_CTRL0_COMMAND_MODE(v) \19 (((v) << BP_GPMI_CTRL0_COMMAND_MODE) & BM_GPMI_CTRL0_COMMAND_MODE)20#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x021#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x122#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x223#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x324 25#define BM_GPMI_CTRL0_WORD_LENGTH (1 << 23)26#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x027#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x128 29/*30 * Difference in LOCK_CS between imx23 and imx28 :31 * This bit may impact the _POWER_ consumption. So some chips32 * do not set it.33 */34#define MX23_BP_GPMI_CTRL0_LOCK_CS 2235#define MX28_BP_GPMI_CTRL0_LOCK_CS 2736#define LOCK_CS_ENABLE 0x137#define BF_GPMI_CTRL0_LOCK_CS(v, x) 0x038 39/* Difference in CS between imx23 and imx28 */40#define BP_GPMI_CTRL0_CS 2041#define MX23_BM_GPMI_CTRL0_CS (3 << BP_GPMI_CTRL0_CS)42#define MX28_BM_GPMI_CTRL0_CS (7 << BP_GPMI_CTRL0_CS)43#define BF_GPMI_CTRL0_CS(v, x) (((v) << BP_GPMI_CTRL0_CS) & \44 (GPMI_IS_MX23((x)) \45 ? MX23_BM_GPMI_CTRL0_CS \46 : MX28_BM_GPMI_CTRL0_CS))47 48#define BP_GPMI_CTRL0_ADDRESS 1749#define BM_GPMI_CTRL0_ADDRESS (3 << BP_GPMI_CTRL0_ADDRESS)50#define BF_GPMI_CTRL0_ADDRESS(v) \51 (((v) << BP_GPMI_CTRL0_ADDRESS) & BM_GPMI_CTRL0_ADDRESS)52#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x053#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x154#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x255 56#define BM_GPMI_CTRL0_ADDRESS_INCREMENT (1 << 16)57#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x058#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x159 60#define BP_GPMI_CTRL0_XFER_COUNT 061#define BM_GPMI_CTRL0_XFER_COUNT (0xffff << BP_GPMI_CTRL0_XFER_COUNT)62#define BF_GPMI_CTRL0_XFER_COUNT(v) \63 (((v) << BP_GPMI_CTRL0_XFER_COUNT) & BM_GPMI_CTRL0_XFER_COUNT)64 65#define HW_GPMI_COMPARE 0x0000001066 67#define HW_GPMI_ECCCTRL 0x0000002068#define HW_GPMI_ECCCTRL_SET 0x0000002469#define HW_GPMI_ECCCTRL_CLR 0x0000002870#define HW_GPMI_ECCCTRL_TOG 0x0000002c71 72#define BP_GPMI_ECCCTRL_ECC_CMD 1373#define BM_GPMI_ECCCTRL_ECC_CMD (3 << BP_GPMI_ECCCTRL_ECC_CMD)74#define BF_GPMI_ECCCTRL_ECC_CMD(v) \75 (((v) << BP_GPMI_ECCCTRL_ECC_CMD) & BM_GPMI_ECCCTRL_ECC_CMD)76#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x077#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x178 79#define BM_GPMI_ECCCTRL_ENABLE_ECC (1 << 12)80#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x181#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x082 83#define BP_GPMI_ECCCTRL_BUFFER_MASK 084#define BM_GPMI_ECCCTRL_BUFFER_MASK (0x1ff << BP_GPMI_ECCCTRL_BUFFER_MASK)85#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \86 (((v) << BP_GPMI_ECCCTRL_BUFFER_MASK) & BM_GPMI_ECCCTRL_BUFFER_MASK)87#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x10088#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF89 90#define HW_GPMI_ECCCOUNT 0x0000003091#define HW_GPMI_PAYLOAD 0x0000004092#define HW_GPMI_AUXILIARY 0x0000005093#define HW_GPMI_CTRL1 0x0000006094#define HW_GPMI_CTRL1_SET 0x0000006495#define HW_GPMI_CTRL1_CLR 0x0000006896#define HW_GPMI_CTRL1_TOG 0x0000006c97 98#define BP_GPMI_CTRL1_DECOUPLE_CS 2499#define BM_GPMI_CTRL1_DECOUPLE_CS (1 << BP_GPMI_CTRL1_DECOUPLE_CS)100 101#define BP_GPMI_CTRL1_WRN_DLY_SEL 22102#define BM_GPMI_CTRL1_WRN_DLY_SEL (0x3 << BP_GPMI_CTRL1_WRN_DLY_SEL)103#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \104 (((v) << BP_GPMI_CTRL1_WRN_DLY_SEL) & BM_GPMI_CTRL1_WRN_DLY_SEL)105#define BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS 0x0106#define BV_GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS 0x1107#define BV_GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS 0x2108#define BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY 0x3109 110#define BM_GPMI_CTRL1_GANGED_RDYBUSY (1 << 19)111#define BM_GPMI_CTRL1_BCH_MODE (1 << 18)112 113#define BP_GPMI_CTRL1_DLL_ENABLE 17114#define BM_GPMI_CTRL1_DLL_ENABLE (1 << BP_GPMI_CTRL1_DLL_ENABLE)115 116#define BP_GPMI_CTRL1_HALF_PERIOD 16117#define BM_GPMI_CTRL1_HALF_PERIOD (1 << BP_GPMI_CTRL1_HALF_PERIOD)118 119#define BP_GPMI_CTRL1_RDN_DELAY 12120#define BM_GPMI_CTRL1_RDN_DELAY (0xf << BP_GPMI_CTRL1_RDN_DELAY)121#define BF_GPMI_CTRL1_RDN_DELAY(v) \122 (((v) << BP_GPMI_CTRL1_RDN_DELAY) & BM_GPMI_CTRL1_RDN_DELAY)123 124#define BM_GPMI_CTRL1_DEV_RESET (1 << 3)125#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0126#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1127 128#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2)129#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0130#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1131 132#define BM_GPMI_CTRL1_CAMERA_MODE (1 << 1)133#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0134#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1135 136#define BM_GPMI_CTRL1_GPMI_MODE (1 << 0)137 138#define BM_GPMI_CTRL1_CLEAR_MASK (BM_GPMI_CTRL1_WRN_DLY_SEL | \139 BM_GPMI_CTRL1_DLL_ENABLE | \140 BM_GPMI_CTRL1_RDN_DELAY | \141 BM_GPMI_CTRL1_HALF_PERIOD)142 143#define HW_GPMI_TIMING0 0x00000070144 145#define BP_GPMI_TIMING0_ADDRESS_SETUP 16146#define BM_GPMI_TIMING0_ADDRESS_SETUP (0xff << BP_GPMI_TIMING0_ADDRESS_SETUP)147#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \148 (((v) << BP_GPMI_TIMING0_ADDRESS_SETUP) & BM_GPMI_TIMING0_ADDRESS_SETUP)149 150#define BP_GPMI_TIMING0_DATA_HOLD 8151#define BM_GPMI_TIMING0_DATA_HOLD (0xff << BP_GPMI_TIMING0_DATA_HOLD)152#define BF_GPMI_TIMING0_DATA_HOLD(v) \153 (((v) << BP_GPMI_TIMING0_DATA_HOLD) & BM_GPMI_TIMING0_DATA_HOLD)154 155#define BP_GPMI_TIMING0_DATA_SETUP 0156#define BM_GPMI_TIMING0_DATA_SETUP (0xff << BP_GPMI_TIMING0_DATA_SETUP)157#define BF_GPMI_TIMING0_DATA_SETUP(v) \158 (((v) << BP_GPMI_TIMING0_DATA_SETUP) & BM_GPMI_TIMING0_DATA_SETUP)159 160#define HW_GPMI_TIMING1 0x00000080161#define BP_GPMI_TIMING1_BUSY_TIMEOUT 16162#define BM_GPMI_TIMING1_BUSY_TIMEOUT (0xffff << BP_GPMI_TIMING1_BUSY_TIMEOUT)163#define BF_GPMI_TIMING1_BUSY_TIMEOUT(v) \164 (((v) << BP_GPMI_TIMING1_BUSY_TIMEOUT) & BM_GPMI_TIMING1_BUSY_TIMEOUT)165 166#define HW_GPMI_TIMING2 0x00000090167#define HW_GPMI_DATA 0x000000a0168 169/* MX28 uses this to detect READY. */170#define HW_GPMI_STAT 0x000000b0171#define MX28_BP_GPMI_STAT_READY_BUSY 24172#define MX28_BM_GPMI_STAT_READY_BUSY (0xff << MX28_BP_GPMI_STAT_READY_BUSY)173#define MX28_BF_GPMI_STAT_READY_BUSY(v) \174 (((v) << MX28_BP_GPMI_STAT_READY_BUSY) & MX28_BM_GPMI_STAT_READY_BUSY)175 176/* MX23 uses this to detect READY. */177#define HW_GPMI_DEBUG 0x000000c0178#define MX23_BP_GPMI_DEBUG_READY0 28179#define MX23_BM_GPMI_DEBUG_READY0 (1 << MX23_BP_GPMI_DEBUG_READY0)180#endif181