6727 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Overview:4 * This is the generic MTD driver for NAND flash devices. It should be5 * capable of working with almost all NAND chips currently available.6 *7 * Additional technical information is available on8 * http://www.linux-mtd.infradead.org/doc/nand.html9 *10 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)12 *13 * Credits:14 * David Woodhouse for adding multichip support15 *16 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the17 * rework for 2K page size chips18 *19 * TODO:20 * Enable cached programming for 2k page size chips21 * Check, if mtd->ecctype should be set to MTD_ECC_HW22 * if we have HW ECC support.23 * BBT table is not serialized, has to be fixed24 */25 26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt27 28#include <linux/module.h>29#include <linux/delay.h>30#include <linux/errno.h>31#include <linux/err.h>32#include <linux/sched.h>33#include <linux/slab.h>34#include <linux/mm.h>35#include <linux/types.h>36#include <linux/mtd/mtd.h>37#include <linux/mtd/nand.h>38#include <linux/mtd/nand-ecc-sw-hamming.h>39#include <linux/mtd/nand-ecc-sw-bch.h>40#include <linux/interrupt.h>41#include <linux/bitops.h>42#include <linux/io.h>43#include <linux/mtd/partitions.h>44#include <linux/of.h>45#include <linux/gpio/consumer.h>46 47#include "internals.h"48 49static int nand_pairing_dist3_get_info(struct mtd_info *mtd, int page,50 struct mtd_pairing_info *info)51{52 int lastpage = (mtd->erasesize / mtd->writesize) - 1;53 int dist = 3;54 55 if (page == lastpage)56 dist = 2;57 58 if (!page || (page & 1)) {59 info->group = 0;60 info->pair = (page + 1) / 2;61 } else {62 info->group = 1;63 info->pair = (page + 1 - dist) / 2;64 }65 66 return 0;67}68 69static int nand_pairing_dist3_get_wunit(struct mtd_info *mtd,70 const struct mtd_pairing_info *info)71{72 int lastpair = ((mtd->erasesize / mtd->writesize) - 1) / 2;73 int page = info->pair * 2;74 int dist = 3;75 76 if (!info->group && !info->pair)77 return 0;78 79 if (info->pair == lastpair && info->group)80 dist = 2;81 82 if (!info->group)83 page--;84 else if (info->pair)85 page += dist - 1;86 87 if (page >= mtd->erasesize / mtd->writesize)88 return -EINVAL;89 90 return page;91}92 93const struct mtd_pairing_scheme dist3_pairing_scheme = {94 .ngroups = 2,95 .get_info = nand_pairing_dist3_get_info,96 .get_wunit = nand_pairing_dist3_get_wunit,97};98 99static int check_offs_len(struct nand_chip *chip, loff_t ofs, uint64_t len)100{101 int ret = 0;102 103 /* Start address must align on block boundary */104 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {105 pr_debug("%s: unaligned address\n", __func__);106 ret = -EINVAL;107 }108 109 /* Length must align on block boundary */110 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {111 pr_debug("%s: length not block aligned\n", __func__);112 ret = -EINVAL;113 }114 115 return ret;116}117 118/**119 * nand_extract_bits - Copy unaligned bits from one buffer to another one120 * @dst: destination buffer121 * @dst_off: bit offset at which the writing starts122 * @src: source buffer123 * @src_off: bit offset at which the reading starts124 * @nbits: number of bits to copy from @src to @dst125 *126 * Copy bits from one memory region to another (overlap authorized).127 */128void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,129 unsigned int src_off, unsigned int nbits)130{131 unsigned int tmp, n;132 133 dst += dst_off / 8;134 dst_off %= 8;135 src += src_off / 8;136 src_off %= 8;137 138 while (nbits) {139 n = min3(8 - dst_off, 8 - src_off, nbits);140 141 tmp = (*src >> src_off) & GENMASK(n - 1, 0);142 *dst &= ~GENMASK(n - 1 + dst_off, dst_off);143 *dst |= tmp << dst_off;144 145 dst_off += n;146 if (dst_off >= 8) {147 dst++;148 dst_off -= 8;149 }150 151 src_off += n;152 if (src_off >= 8) {153 src++;154 src_off -= 8;155 }156 157 nbits -= n;158 }159}160EXPORT_SYMBOL_GPL(nand_extract_bits);161 162/**163 * nand_select_target() - Select a NAND target (A.K.A. die)164 * @chip: NAND chip object165 * @cs: the CS line to select. Note that this CS id is always from the chip166 * PoV, not the controller one167 *168 * Select a NAND target so that further operations executed on @chip go to the169 * selected NAND target.170 */171void nand_select_target(struct nand_chip *chip, unsigned int cs)172{173 /*174 * cs should always lie between 0 and nanddev_ntargets(), when that's175 * not the case it's a bug and the caller should be fixed.176 */177 if (WARN_ON(cs > nanddev_ntargets(&chip->base)))178 return;179 180 chip->cur_cs = cs;181 182 if (chip->legacy.select_chip)183 chip->legacy.select_chip(chip, cs);184}185EXPORT_SYMBOL_GPL(nand_select_target);186 187/**188 * nand_deselect_target() - Deselect the currently selected target189 * @chip: NAND chip object190 *191 * Deselect the currently selected NAND target. The result of operations192 * executed on @chip after the target has been deselected is undefined.193 */194void nand_deselect_target(struct nand_chip *chip)195{196 if (chip->legacy.select_chip)197 chip->legacy.select_chip(chip, -1);198 199 chip->cur_cs = -1;200}201EXPORT_SYMBOL_GPL(nand_deselect_target);202 203/**204 * nand_release_device - [GENERIC] release chip205 * @chip: NAND chip object206 *207 * Release chip lock and wake up anyone waiting on the device.208 */209static void nand_release_device(struct nand_chip *chip)210{211 /* Release the controller and the chip */212 mutex_unlock(&chip->controller->lock);213 mutex_unlock(&chip->lock);214}215 216/**217 * nand_bbm_get_next_page - Get the next page for bad block markers218 * @chip: NAND chip object219 * @page: First page to start checking for bad block marker usage220 *221 * Returns an integer that corresponds to the page offset within a block, for222 * a page that is used to store bad block markers. If no more pages are223 * available, -EINVAL is returned.224 */225int nand_bbm_get_next_page(struct nand_chip *chip, int page)226{227 struct mtd_info *mtd = nand_to_mtd(chip);228 int last_page = ((mtd->erasesize - mtd->writesize) >>229 chip->page_shift) & chip->pagemask;230 unsigned int bbm_flags = NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE231 | NAND_BBM_LASTPAGE;232 233 if (page == 0 && !(chip->options & bbm_flags))234 return 0;235 if (page == 0 && chip->options & NAND_BBM_FIRSTPAGE)236 return 0;237 if (page <= 1 && chip->options & NAND_BBM_SECONDPAGE)238 return 1;239 if (page <= last_page && chip->options & NAND_BBM_LASTPAGE)240 return last_page;241 242 return -EINVAL;243}244 245/**246 * nand_block_bad - [DEFAULT] Read bad block marker from the chip247 * @chip: NAND chip object248 * @ofs: offset from device start249 *250 * Check, if the block is bad.251 */252static int nand_block_bad(struct nand_chip *chip, loff_t ofs)253{254 int first_page, page_offset;255 int res;256 u8 bad;257 258 first_page = (int)(ofs >> chip->page_shift) & chip->pagemask;259 page_offset = nand_bbm_get_next_page(chip, 0);260 261 while (page_offset >= 0) {262 res = chip->ecc.read_oob(chip, first_page + page_offset);263 if (res < 0)264 return res;265 266 bad = chip->oob_poi[chip->badblockpos];267 268 if (likely(chip->badblockbits == 8))269 res = bad != 0xFF;270 else271 res = hweight8(bad) < chip->badblockbits;272 if (res)273 return res;274 275 page_offset = nand_bbm_get_next_page(chip, page_offset + 1);276 }277 278 return 0;279}280 281/**282 * nand_region_is_secured() - Check if the region is secured283 * @chip: NAND chip object284 * @offset: Offset of the region to check285 * @size: Size of the region to check286 *287 * Checks if the region is secured by comparing the offset and size with the288 * list of secure regions obtained from DT. Returns true if the region is289 * secured else false.290 */291static bool nand_region_is_secured(struct nand_chip *chip, loff_t offset, u64 size)292{293 int i;294 295 /* Skip touching the secure regions if present */296 for (i = 0; i < chip->nr_secure_regions; i++) {297 const struct nand_secure_region *region = &chip->secure_regions[i];298 299 if (offset + size <= region->offset ||300 offset >= region->offset + region->size)301 continue;302 303 pr_debug("%s: Region 0x%llx - 0x%llx is secured!",304 __func__, offset, offset + size);305 306 return true;307 }308 309 return false;310}311 312static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs)313{314 struct mtd_info *mtd = nand_to_mtd(chip);315 316 if (chip->options & NAND_NO_BBM_QUIRK)317 return 0;318 319 /* Check if the region is secured */320 if (nand_region_is_secured(chip, ofs, mtd->erasesize))321 return -EIO;322 323 if (mtd_check_expert_analysis_mode())324 return 0;325 326 if (chip->legacy.block_bad)327 return chip->legacy.block_bad(chip, ofs);328 329 return nand_block_bad(chip, ofs);330}331 332/**333 * nand_get_device - [GENERIC] Get chip for selected access334 * @chip: NAND chip structure335 *336 * Lock the device and its controller for exclusive access337 */338static void nand_get_device(struct nand_chip *chip)339{340 /* Wait until the device is resumed. */341 while (1) {342 mutex_lock(&chip->lock);343 if (!chip->suspended) {344 mutex_lock(&chip->controller->lock);345 return;346 }347 mutex_unlock(&chip->lock);348 349 wait_event(chip->resume_wq, !chip->suspended);350 }351}352 353/**354 * nand_check_wp - [GENERIC] check if the chip is write protected355 * @chip: NAND chip object356 *357 * Check, if the device is write protected. The function expects, that the358 * device is already selected.359 */360static int nand_check_wp(struct nand_chip *chip)361{362 u8 status;363 int ret;364 365 /* Broken xD cards report WP despite being writable */366 if (chip->options & NAND_BROKEN_XD)367 return 0;368 369 /* controller responsible for NAND write protect */370 if (chip->controller->controller_wp)371 return 0;372 373 /* Check the WP bit */374 ret = nand_status_op(chip, &status);375 if (ret)376 return ret;377 378 return status & NAND_STATUS_WP ? 0 : 1;379}380 381/**382 * nand_fill_oob - [INTERN] Transfer client buffer to oob383 * @chip: NAND chip object384 * @oob: oob data buffer385 * @len: oob data write length386 * @ops: oob ops structure387 */388static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,389 struct mtd_oob_ops *ops)390{391 struct mtd_info *mtd = nand_to_mtd(chip);392 int ret;393 394 /*395 * Initialise to all 0xFF, to avoid the possibility of left over OOB396 * data from a previous OOB read.397 */398 memset(chip->oob_poi, 0xff, mtd->oobsize);399 400 switch (ops->mode) {401 402 case MTD_OPS_PLACE_OOB:403 case MTD_OPS_RAW:404 memcpy(chip->oob_poi + ops->ooboffs, oob, len);405 return oob + len;406 407 case MTD_OPS_AUTO_OOB:408 ret = mtd_ooblayout_set_databytes(mtd, oob, chip->oob_poi,409 ops->ooboffs, len);410 BUG_ON(ret);411 return oob + len;412 413 default:414 BUG();415 }416 return NULL;417}418 419/**420 * nand_do_write_oob - [MTD Interface] NAND write out-of-band421 * @chip: NAND chip object422 * @to: offset to write to423 * @ops: oob operation description structure424 *425 * NAND write out-of-band.426 */427static int nand_do_write_oob(struct nand_chip *chip, loff_t to,428 struct mtd_oob_ops *ops)429{430 struct mtd_info *mtd = nand_to_mtd(chip);431 int chipnr, page, status, len, ret;432 433 pr_debug("%s: to = 0x%08x, len = %i\n",434 __func__, (unsigned int)to, (int)ops->ooblen);435 436 len = mtd_oobavail(mtd, ops);437 438 /* Do not allow write past end of page */439 if ((ops->ooboffs + ops->ooblen) > len) {440 pr_debug("%s: attempt to write past end of page\n",441 __func__);442 return -EINVAL;443 }444 445 /* Check if the region is secured */446 if (nand_region_is_secured(chip, to, ops->ooblen))447 return -EIO;448 449 chipnr = (int)(to >> chip->chip_shift);450 451 /*452 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one453 * of my DiskOnChip 2000 test units) will clear the whole data page too454 * if we don't do this. I have no clue why, but I seem to have 'fixed'455 * it in the doc2000 driver in August 1999. dwmw2.456 */457 ret = nand_reset(chip, chipnr);458 if (ret)459 return ret;460 461 nand_select_target(chip, chipnr);462 463 /* Shift to get page */464 page = (int)(to >> chip->page_shift);465 466 /* Check, if it is write protected */467 if (nand_check_wp(chip)) {468 nand_deselect_target(chip);469 return -EROFS;470 }471 472 /* Invalidate the page cache, if we write to the cached page */473 if (page == chip->pagecache.page)474 chip->pagecache.page = -1;475 476 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);477 478 if (ops->mode == MTD_OPS_RAW)479 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask);480 else481 status = chip->ecc.write_oob(chip, page & chip->pagemask);482 483 nand_deselect_target(chip);484 485 if (status)486 return status;487 488 ops->oobretlen = ops->ooblen;489 490 return 0;491}492 493/**494 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker495 * @chip: NAND chip object496 * @ofs: offset from device start497 *498 * This is the default implementation, which can be overridden by a hardware499 * specific driver. It provides the details for writing a bad block marker to a500 * block.501 */502static int nand_default_block_markbad(struct nand_chip *chip, loff_t ofs)503{504 struct mtd_info *mtd = nand_to_mtd(chip);505 struct mtd_oob_ops ops;506 uint8_t buf[2] = { 0, 0 };507 int ret = 0, res, page_offset;508 509 memset(&ops, 0, sizeof(ops));510 ops.oobbuf = buf;511 ops.ooboffs = chip->badblockpos;512 if (chip->options & NAND_BUSWIDTH_16) {513 ops.ooboffs &= ~0x01;514 ops.len = ops.ooblen = 2;515 } else {516 ops.len = ops.ooblen = 1;517 }518 ops.mode = MTD_OPS_PLACE_OOB;519 520 page_offset = nand_bbm_get_next_page(chip, 0);521 522 while (page_offset >= 0) {523 res = nand_do_write_oob(chip,524 ofs + (page_offset * mtd->writesize),525 &ops);526 527 if (!ret)528 ret = res;529 530 page_offset = nand_bbm_get_next_page(chip, page_offset + 1);531 }532 533 return ret;534}535 536/**537 * nand_markbad_bbm - mark a block by updating the BBM538 * @chip: NAND chip object539 * @ofs: offset of the block to mark bad540 */541int nand_markbad_bbm(struct nand_chip *chip, loff_t ofs)542{543 if (chip->legacy.block_markbad)544 return chip->legacy.block_markbad(chip, ofs);545 546 return nand_default_block_markbad(chip, ofs);547}548 549/**550 * nand_block_markbad_lowlevel - mark a block bad551 * @chip: NAND chip object552 * @ofs: offset from device start553 *554 * This function performs the generic NAND bad block marking steps (i.e., bad555 * block table(s) and/or marker(s)). We only allow the hardware driver to556 * specify how to write bad block markers to OOB (chip->legacy.block_markbad).557 *558 * We try operations in the following order:559 *560 * (1) erase the affected block, to allow OOB marker to be written cleanly561 * (2) write bad block marker to OOB area of affected block (unless flag562 * NAND_BBT_NO_OOB_BBM is present)563 * (3) update the BBT564 *565 * Note that we retain the first error encountered in (2) or (3), finish the566 * procedures, and dump the error in the end.567*/568static int nand_block_markbad_lowlevel(struct nand_chip *chip, loff_t ofs)569{570 struct mtd_info *mtd = nand_to_mtd(chip);571 int res, ret = 0;572 573 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {574 struct erase_info einfo;575 576 /* Attempt erase before marking OOB */577 memset(&einfo, 0, sizeof(einfo));578 einfo.addr = ofs;579 einfo.len = 1ULL << chip->phys_erase_shift;580 nand_erase_nand(chip, &einfo, 0);581 582 /* Write bad block marker to OOB */583 nand_get_device(chip);584 585 ret = nand_markbad_bbm(chip, ofs);586 nand_release_device(chip);587 }588 589 /* Mark block bad in BBT */590 if (chip->bbt) {591 res = nand_markbad_bbt(chip, ofs);592 if (!ret)593 ret = res;594 }595 596 if (!ret)597 mtd->ecc_stats.badblocks++;598 599 return ret;600}601 602/**603 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.604 * @mtd: MTD device structure605 * @ofs: offset from device start606 *607 * Check if the block is marked as reserved.608 */609static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)610{611 struct nand_chip *chip = mtd_to_nand(mtd);612 613 if (!chip->bbt)614 return 0;615 /* Return info from the table */616 return nand_isreserved_bbt(chip, ofs);617}618 619/**620 * nand_block_checkbad - [GENERIC] Check if a block is marked bad621 * @chip: NAND chip object622 * @ofs: offset from device start623 * @allowbbt: 1, if its allowed to access the bbt area624 *625 * Check, if the block is bad. Either by reading the bad block table or626 * calling of the scan function.627 */628static int nand_block_checkbad(struct nand_chip *chip, loff_t ofs, int allowbbt)629{630 /* Return info from the table */631 if (chip->bbt)632 return nand_isbad_bbt(chip, ofs, allowbbt);633 634 return nand_isbad_bbm(chip, ofs);635}636 637/**638 * nand_soft_waitrdy - Poll STATUS reg until RDY bit is set to 1639 * @chip: NAND chip structure640 * @timeout_ms: Timeout in ms641 *642 * Poll the STATUS register using ->exec_op() until the RDY bit becomes 1.643 * If that does not happen whitin the specified timeout, -ETIMEDOUT is644 * returned.645 *646 * This helper is intended to be used when the controller does not have access647 * to the NAND R/B pin.648 *649 * Be aware that calling this helper from an ->exec_op() implementation means650 * ->exec_op() must be re-entrant.651 *652 * Return 0 if the NAND chip is ready, a negative error otherwise.653 */654int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms)655{656 const struct nand_interface_config *conf;657 u8 status = 0;658 int ret;659 660 if (!nand_has_exec_op(chip))661 return -ENOTSUPP;662 663 /* Wait tWB before polling the STATUS reg. */664 conf = nand_get_interface_config(chip);665 ndelay(NAND_COMMON_TIMING_NS(conf, tWB_max));666 667 ret = nand_status_op(chip, NULL);668 if (ret)669 return ret;670 671 /*672 * +1 below is necessary because if we are now in the last fraction673 * of jiffy and msecs_to_jiffies is 1 then we will wait only that674 * small jiffy fraction - possibly leading to false timeout675 */676 timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1;677 do {678 ret = nand_read_data_op(chip, &status, sizeof(status), true,679 false);680 if (ret)681 break;682 683 if (status & NAND_STATUS_READY)684 break;685 686 /*687 * Typical lowest execution time for a tR on most NANDs is 10us,688 * use this as polling delay before doing something smarter (ie.689 * deriving a delay from the timeout value, timeout_ms/ratio).690 */691 udelay(10);692 } while (time_before(jiffies, timeout_ms));693 694 /*695 * We have to exit READ_STATUS mode in order to read real data on the696 * bus in case the WAITRDY instruction is preceding a DATA_IN697 * instruction.698 */699 nand_exit_status_op(chip);700 701 if (ret)702 return ret;703 704 return status & NAND_STATUS_READY ? 0 : -ETIMEDOUT;705};706EXPORT_SYMBOL_GPL(nand_soft_waitrdy);707 708/**709 * nand_gpio_waitrdy - Poll R/B GPIO pin until ready710 * @chip: NAND chip structure711 * @gpiod: GPIO descriptor of R/B pin712 * @timeout_ms: Timeout in ms713 *714 * Poll the R/B GPIO pin until it becomes ready. If that does not happen715 * whitin the specified timeout, -ETIMEDOUT is returned.716 *717 * This helper is intended to be used when the controller has access to the718 * NAND R/B pin over GPIO.719 *720 * Return 0 if the R/B pin indicates chip is ready, a negative error otherwise.721 */722int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,723 unsigned long timeout_ms)724{725 726 /*727 * Wait until R/B pin indicates chip is ready or timeout occurs.728 * +1 below is necessary because if we are now in the last fraction729 * of jiffy and msecs_to_jiffies is 1 then we will wait only that730 * small jiffy fraction - possibly leading to false timeout.731 */732 timeout_ms = jiffies + msecs_to_jiffies(timeout_ms) + 1;733 do {734 if (gpiod_get_value_cansleep(gpiod))735 return 0;736 737 cond_resched();738 } while (time_before(jiffies, timeout_ms));739 740 return gpiod_get_value_cansleep(gpiod) ? 0 : -ETIMEDOUT;741};742EXPORT_SYMBOL_GPL(nand_gpio_waitrdy);743 744/**745 * panic_nand_wait - [GENERIC] wait until the command is done746 * @chip: NAND chip structure747 * @timeo: timeout748 *749 * Wait for command done. This is a helper function for nand_wait used when750 * we are in interrupt context. May happen when in panic and trying to write751 * an oops through mtdoops.752 */753void panic_nand_wait(struct nand_chip *chip, unsigned long timeo)754{755 int i;756 for (i = 0; i < timeo; i++) {757 if (chip->legacy.dev_ready) {758 if (chip->legacy.dev_ready(chip))759 break;760 } else {761 int ret;762 u8 status;763 764 ret = nand_read_data_op(chip, &status, sizeof(status),765 true, false);766 if (ret)767 return;768 769 if (status & NAND_STATUS_READY)770 break;771 }772 mdelay(1);773 }774}775 776static bool nand_supports_get_features(struct nand_chip *chip, int addr)777{778 return (chip->parameters.supports_set_get_features &&779 test_bit(addr, chip->parameters.get_feature_list));780}781 782static bool nand_supports_set_features(struct nand_chip *chip, int addr)783{784 return (chip->parameters.supports_set_get_features &&785 test_bit(addr, chip->parameters.set_feature_list));786}787 788/**789 * nand_reset_interface - Reset data interface and timings790 * @chip: The NAND chip791 * @chipnr: Internal die id792 *793 * Reset the Data interface and timings to ONFI mode 0.794 *795 * Returns 0 for success or negative error code otherwise.796 */797static int nand_reset_interface(struct nand_chip *chip, int chipnr)798{799 const struct nand_controller_ops *ops = chip->controller->ops;800 int ret;801 802 if (!nand_controller_can_setup_interface(chip))803 return 0;804 805 /*806 * The ONFI specification says:807 * "808 * To transition from NV-DDR or NV-DDR2 to the SDR data809 * interface, the host shall use the Reset (FFh) command810 * using SDR timing mode 0. A device in any timing mode is811 * required to recognize Reset (FFh) command issued in SDR812 * timing mode 0.813 * "814 *815 * Configure the data interface in SDR mode and set the816 * timings to timing mode 0.817 */818 819 chip->current_interface_config = nand_get_reset_interface_config();820 ret = ops->setup_interface(chip, chipnr,821 chip->current_interface_config);822 if (ret)823 pr_err("Failed to configure data interface to SDR timing mode 0\n");824 825 return ret;826}827 828/**829 * nand_setup_interface - Setup the best data interface and timings830 * @chip: The NAND chip831 * @chipnr: Internal die id832 *833 * Configure what has been reported to be the best data interface and NAND834 * timings supported by the chip and the driver.835 *836 * Returns 0 for success or negative error code otherwise.837 */838static int nand_setup_interface(struct nand_chip *chip, int chipnr)839{840 const struct nand_controller_ops *ops = chip->controller->ops;841 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { }, request;842 int ret;843 844 if (!nand_controller_can_setup_interface(chip))845 return 0;846 847 /*848 * A nand_reset_interface() put both the NAND chip and the NAND849 * controller in timings mode 0. If the default mode for this chip is850 * also 0, no need to proceed to the change again. Plus, at probe time,851 * nand_setup_interface() uses ->set/get_features() which would852 * fail anyway as the parameter page is not available yet.853 */854 if (!chip->best_interface_config)855 return 0;856 857 request = chip->best_interface_config->timings.mode;858 if (nand_interface_is_sdr(chip->best_interface_config))859 request |= ONFI_DATA_INTERFACE_SDR;860 else861 request |= ONFI_DATA_INTERFACE_NVDDR;862 tmode_param[0] = request;863 864 /* Change the mode on the chip side (if supported by the NAND chip) */865 if (nand_supports_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE)) {866 nand_select_target(chip, chipnr);867 ret = nand_set_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,868 tmode_param);869 nand_deselect_target(chip);870 if (ret)871 return ret;872 }873 874 /* Change the mode on the controller side */875 ret = ops->setup_interface(chip, chipnr, chip->best_interface_config);876 if (ret)877 return ret;878 879 /* Check the mode has been accepted by the chip, if supported */880 if (!nand_supports_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE))881 goto update_interface_config;882 883 memset(tmode_param, 0, ONFI_SUBFEATURE_PARAM_LEN);884 nand_select_target(chip, chipnr);885 ret = nand_get_features(chip, ONFI_FEATURE_ADDR_TIMING_MODE,886 tmode_param);887 nand_deselect_target(chip);888 if (ret)889 goto err_reset_chip;890 891 if (request != tmode_param[0]) {892 pr_warn("%s timing mode %d not acknowledged by the NAND chip\n",893 nand_interface_is_nvddr(chip->best_interface_config) ? "NV-DDR" : "SDR",894 chip->best_interface_config->timings.mode);895 pr_debug("NAND chip would work in %s timing mode %d\n",896 tmode_param[0] & ONFI_DATA_INTERFACE_NVDDR ? "NV-DDR" : "SDR",897 (unsigned int)ONFI_TIMING_MODE_PARAM(tmode_param[0]));898 goto err_reset_chip;899 }900 901update_interface_config:902 chip->current_interface_config = chip->best_interface_config;903 904 return 0;905 906err_reset_chip:907 /*908 * Fallback to mode 0 if the chip explicitly did not ack the chosen909 * timing mode.910 */911 nand_reset_interface(chip, chipnr);912 nand_select_target(chip, chipnr);913 nand_reset_op(chip);914 nand_deselect_target(chip);915 916 return ret;917}918 919/**920 * nand_choose_best_sdr_timings - Pick up the best SDR timings that both the921 * NAND controller and the NAND chip support922 * @chip: the NAND chip923 * @iface: the interface configuration (can eventually be updated)924 * @spec_timings: specific timings, when not fitting the ONFI specification925 *926 * If specific timings are provided, use them. Otherwise, retrieve supported927 * timing modes from ONFI information.928 */929int nand_choose_best_sdr_timings(struct nand_chip *chip,930 struct nand_interface_config *iface,931 struct nand_sdr_timings *spec_timings)932{933 const struct nand_controller_ops *ops = chip->controller->ops;934 int best_mode = 0, mode, ret = -EOPNOTSUPP;935 936 iface->type = NAND_SDR_IFACE;937 938 if (spec_timings) {939 iface->timings.sdr = *spec_timings;940 iface->timings.mode = onfi_find_closest_sdr_mode(spec_timings);941 942 /* Verify the controller supports the requested interface */943 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,944 iface);945 if (!ret) {946 chip->best_interface_config = iface;947 return ret;948 }949 950 /* Fallback to slower modes */951 best_mode = iface->timings.mode;952 } else if (chip->parameters.onfi) {953 best_mode = fls(chip->parameters.onfi->sdr_timing_modes) - 1;954 }955 956 for (mode = best_mode; mode >= 0; mode--) {957 onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, mode);958 959 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,960 iface);961 if (!ret) {962 chip->best_interface_config = iface;963 break;964 }965 }966 967 return ret;968}969 970/**971 * nand_choose_best_nvddr_timings - Pick up the best NVDDR timings that both the972 * NAND controller and the NAND chip support973 * @chip: the NAND chip974 * @iface: the interface configuration (can eventually be updated)975 * @spec_timings: specific timings, when not fitting the ONFI specification976 *977 * If specific timings are provided, use them. Otherwise, retrieve supported978 * timing modes from ONFI information.979 */980int nand_choose_best_nvddr_timings(struct nand_chip *chip,981 struct nand_interface_config *iface,982 struct nand_nvddr_timings *spec_timings)983{984 const struct nand_controller_ops *ops = chip->controller->ops;985 int best_mode = 0, mode, ret = -EOPNOTSUPP;986 987 iface->type = NAND_NVDDR_IFACE;988 989 if (spec_timings) {990 iface->timings.nvddr = *spec_timings;991 iface->timings.mode = onfi_find_closest_nvddr_mode(spec_timings);992 993 /* Verify the controller supports the requested interface */994 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,995 iface);996 if (!ret) {997 chip->best_interface_config = iface;998 return ret;999 }1000 1001 /* Fallback to slower modes */1002 best_mode = iface->timings.mode;1003 } else if (chip->parameters.onfi) {1004 best_mode = fls(chip->parameters.onfi->nvddr_timing_modes) - 1;1005 }1006 1007 for (mode = best_mode; mode >= 0; mode--) {1008 onfi_fill_interface_config(chip, iface, NAND_NVDDR_IFACE, mode);1009 1010 ret = ops->setup_interface(chip, NAND_DATA_IFACE_CHECK_ONLY,1011 iface);1012 if (!ret) {1013 chip->best_interface_config = iface;1014 break;1015 }1016 }1017 1018 return ret;1019}1020 1021/**1022 * nand_choose_best_timings - Pick up the best NVDDR or SDR timings that both1023 * NAND controller and the NAND chip support1024 * @chip: the NAND chip1025 * @iface: the interface configuration (can eventually be updated)1026 *1027 * If specific timings are provided, use them. Otherwise, retrieve supported1028 * timing modes from ONFI information.1029 */1030static int nand_choose_best_timings(struct nand_chip *chip,1031 struct nand_interface_config *iface)1032{1033 int ret;1034 1035 /* Try the fastest timings: NV-DDR */1036 ret = nand_choose_best_nvddr_timings(chip, iface, NULL);1037 if (!ret)1038 return 0;1039 1040 /* Fallback to SDR timings otherwise */1041 return nand_choose_best_sdr_timings(chip, iface, NULL);1042}1043 1044/**1045 * nand_choose_interface_config - find the best data interface and timings1046 * @chip: The NAND chip1047 *1048 * Find the best data interface and NAND timings supported by the chip1049 * and the driver. Eventually let the NAND manufacturer driver propose his own1050 * set of timings.1051 *1052 * After this function nand_chip->interface_config is initialized with the best1053 * timing mode available.1054 *1055 * Returns 0 for success or negative error code otherwise.1056 */1057static int nand_choose_interface_config(struct nand_chip *chip)1058{1059 struct nand_interface_config *iface;1060 int ret;1061 1062 if (!nand_controller_can_setup_interface(chip))1063 return 0;1064 1065 iface = kzalloc(sizeof(*iface), GFP_KERNEL);1066 if (!iface)1067 return -ENOMEM;1068 1069 if (chip->ops.choose_interface_config)1070 ret = chip->ops.choose_interface_config(chip, iface);1071 else1072 ret = nand_choose_best_timings(chip, iface);1073 1074 if (ret)1075 kfree(iface);1076 1077 return ret;1078}1079 1080/**1081 * nand_fill_column_cycles - fill the column cycles of an address1082 * @chip: The NAND chip1083 * @addrs: Array of address cycles to fill1084 * @offset_in_page: The offset in the page1085 *1086 * Fills the first or the first two bytes of the @addrs field depending1087 * on the NAND bus width and the page size.1088 *1089 * Returns the number of cycles needed to encode the column, or a negative1090 * error code in case one of the arguments is invalid.1091 */1092static int nand_fill_column_cycles(struct nand_chip *chip, u8 *addrs,1093 unsigned int offset_in_page)1094{1095 struct mtd_info *mtd = nand_to_mtd(chip);1096 bool ident_stage = !mtd->writesize;1097 1098 /* Bypass all checks during NAND identification */1099 if (likely(!ident_stage)) {1100 /* Make sure the offset is less than the actual page size. */1101 if (offset_in_page > mtd->writesize + mtd->oobsize)1102 return -EINVAL;1103 1104 /*1105 * On small page NANDs, there's a dedicated command to access the OOB1106 * area, and the column address is relative to the start of the OOB1107 * area, not the start of the page. Asjust the address accordingly.1108 */1109 if (mtd->writesize <= 512 && offset_in_page >= mtd->writesize)1110 offset_in_page -= mtd->writesize;1111 1112 /*1113 * The offset in page is expressed in bytes, if the NAND bus is 16-bit1114 * wide, then it must be divided by 2.1115 */1116 if (chip->options & NAND_BUSWIDTH_16) {1117 if (WARN_ON(offset_in_page % 2))1118 return -EINVAL;1119 1120 offset_in_page /= 2;1121 }1122 }1123 1124 addrs[0] = offset_in_page;1125 1126 /*1127 * Small page NANDs use 1 cycle for the columns, while large page NANDs1128 * need 21129 */1130 if (!ident_stage && mtd->writesize <= 512)1131 return 1;1132 1133 addrs[1] = offset_in_page >> 8;1134 1135 return 2;1136}1137 1138static int nand_sp_exec_read_page_op(struct nand_chip *chip, unsigned int page,1139 unsigned int offset_in_page, void *buf,1140 unsigned int len)1141{1142 const struct nand_interface_config *conf =1143 nand_get_interface_config(chip);1144 struct mtd_info *mtd = nand_to_mtd(chip);1145 u8 addrs[4];1146 struct nand_op_instr instrs[] = {1147 NAND_OP_CMD(NAND_CMD_READ0, 0),1148 NAND_OP_ADDR(3, addrs, NAND_COMMON_TIMING_NS(conf, tWB_max)),1149 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),1150 NAND_COMMON_TIMING_NS(conf, tRR_min)),1151 NAND_OP_DATA_IN(len, buf, 0),1152 };1153 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);1154 int ret;1155 1156 /* Drop the DATA_IN instruction if len is set to 0. */1157 if (!len)1158 op.ninstrs--;1159 1160 if (offset_in_page >= mtd->writesize)1161 instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB;1162 else if (offset_in_page >= 256 &&1163 !(chip->options & NAND_BUSWIDTH_16))1164 instrs[0].ctx.cmd.opcode = NAND_CMD_READ1;1165 1166 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);1167 if (ret < 0)1168 return ret;1169 1170 addrs[1] = page;1171 addrs[2] = page >> 8;1172 1173 if (chip->options & NAND_ROW_ADDR_3) {1174 addrs[3] = page >> 16;1175 instrs[1].ctx.addr.naddrs++;1176 }1177 1178 return nand_exec_op(chip, &op);1179}1180 1181static int nand_lp_exec_read_page_op(struct nand_chip *chip, unsigned int page,1182 unsigned int offset_in_page, void *buf,1183 unsigned int len)1184{1185 const struct nand_interface_config *conf =1186 nand_get_interface_config(chip);1187 u8 addrs[5];1188 struct nand_op_instr instrs[] = {1189 NAND_OP_CMD(NAND_CMD_READ0, 0),1190 NAND_OP_ADDR(4, addrs, 0),1191 NAND_OP_CMD(NAND_CMD_READSTART, NAND_COMMON_TIMING_NS(conf, tWB_max)),1192 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),1193 NAND_COMMON_TIMING_NS(conf, tRR_min)),1194 NAND_OP_DATA_IN(len, buf, 0),1195 };1196 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);1197 int ret;1198 1199 /* Drop the DATA_IN instruction if len is set to 0. */1200 if (!len)1201 op.ninstrs--;1202 1203 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);1204 if (ret < 0)1205 return ret;1206 1207 addrs[2] = page;1208 addrs[3] = page >> 8;1209 1210 if (chip->options & NAND_ROW_ADDR_3) {1211 addrs[4] = page >> 16;1212 instrs[1].ctx.addr.naddrs++;1213 }1214 1215 return nand_exec_op(chip, &op);1216}1217 1218static unsigned int rawnand_last_page_of_lun(unsigned int pages_per_lun, unsigned int lun)1219{1220 /* lun is expected to be very small */1221 return (lun * pages_per_lun) + pages_per_lun - 1;1222}1223 1224static void rawnand_cap_cont_reads(struct nand_chip *chip)1225{1226 struct nand_memory_organization *memorg;1227 unsigned int ppl, first_lun, last_lun;1228 1229 memorg = nanddev_get_memorg(&chip->base);1230 ppl = memorg->pages_per_eraseblock * memorg->eraseblocks_per_lun;1231 first_lun = chip->cont_read.first_page / ppl;1232 last_lun = chip->cont_read.last_page / ppl;1233 1234 /* Prevent sequential cache reads across LUN boundaries */1235 if (first_lun != last_lun)1236 chip->cont_read.pause_page = rawnand_last_page_of_lun(ppl, first_lun);1237 else1238 chip->cont_read.pause_page = chip->cont_read.last_page;1239 1240 if (chip->cont_read.first_page == chip->cont_read.pause_page) {1241 chip->cont_read.first_page++;1242 chip->cont_read.pause_page = min(chip->cont_read.last_page,1243 rawnand_last_page_of_lun(ppl, first_lun + 1));1244 }1245 1246 if (chip->cont_read.first_page >= chip->cont_read.last_page)1247 chip->cont_read.ongoing = false;1248}1249 1250static int nand_lp_exec_cont_read_page_op(struct nand_chip *chip, unsigned int page,1251 unsigned int offset_in_page, void *buf,1252 unsigned int len, bool check_only)1253{1254 const struct nand_interface_config *conf =1255 nand_get_interface_config(chip);1256 u8 addrs[5];1257 struct nand_op_instr start_instrs[] = {1258 NAND_OP_CMD(NAND_CMD_READ0, 0),1259 NAND_OP_ADDR(4, addrs, 0),1260 NAND_OP_CMD(NAND_CMD_READSTART, NAND_COMMON_TIMING_NS(conf, tWB_max)),1261 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max), 0),1262 NAND_OP_CMD(NAND_CMD_READCACHESEQ, NAND_COMMON_TIMING_NS(conf, tWB_max)),1263 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),1264 NAND_COMMON_TIMING_NS(conf, tRR_min)),1265 NAND_OP_DATA_IN(len, buf, 0),1266 };1267 struct nand_op_instr cont_instrs[] = {1268 NAND_OP_CMD(page == chip->cont_read.pause_page ?1269 NAND_CMD_READCACHEEND : NAND_CMD_READCACHESEQ,1270 NAND_COMMON_TIMING_NS(conf, tWB_max)),1271 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),1272 NAND_COMMON_TIMING_NS(conf, tRR_min)),1273 NAND_OP_DATA_IN(len, buf, 0),1274 };1275 struct nand_operation start_op = NAND_OPERATION(chip->cur_cs, start_instrs);1276 struct nand_operation cont_op = NAND_OPERATION(chip->cur_cs, cont_instrs);1277 int ret;1278 1279 if (!len) {1280 start_op.ninstrs--;1281 cont_op.ninstrs--;1282 }1283 1284 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);1285 if (ret < 0)1286 return ret;1287 1288 addrs[2] = page;1289 addrs[3] = page >> 8;1290 1291 if (chip->options & NAND_ROW_ADDR_3) {1292 addrs[4] = page >> 16;1293 start_instrs[1].ctx.addr.naddrs++;1294 }1295 1296 /* Check if cache reads are supported */1297 if (check_only) {1298 if (nand_check_op(chip, &start_op) || nand_check_op(chip, &cont_op))1299 return -EOPNOTSUPP;1300 1301 return 0;1302 }1303 1304 if (page == chip->cont_read.first_page)1305 ret = nand_exec_op(chip, &start_op);1306 else1307 ret = nand_exec_op(chip, &cont_op);1308 if (ret)1309 return ret;1310 1311 if (!chip->cont_read.ongoing)1312 return 0;1313 1314 if (page == chip->cont_read.last_page) {1315 chip->cont_read.ongoing = false;1316 } else if (page == chip->cont_read.pause_page) {1317 chip->cont_read.first_page++;1318 rawnand_cap_cont_reads(chip);1319 }1320 1321 return 0;1322}1323 1324static bool rawnand_cont_read_ongoing(struct nand_chip *chip, unsigned int page)1325{1326 return chip->cont_read.ongoing && page >= chip->cont_read.first_page;1327}1328 1329/**1330 * nand_read_page_op - Do a READ PAGE operation1331 * @chip: The NAND chip1332 * @page: page to read1333 * @offset_in_page: offset within the page1334 * @buf: buffer used to store the data1335 * @len: length of the buffer1336 *1337 * This function issues a READ PAGE operation.1338 * This function does not select/unselect the CS line.1339 *1340 * Returns 0 on success, a negative error code otherwise.1341 */1342int nand_read_page_op(struct nand_chip *chip, unsigned int page,1343 unsigned int offset_in_page, void *buf, unsigned int len)1344{1345 struct mtd_info *mtd = nand_to_mtd(chip);1346 1347 if (len && !buf)1348 return -EINVAL;1349 1350 if (offset_in_page + len > mtd->writesize + mtd->oobsize)1351 return -EINVAL;1352 1353 if (nand_has_exec_op(chip)) {1354 if (mtd->writesize > 512) {1355 if (rawnand_cont_read_ongoing(chip, page))1356 return nand_lp_exec_cont_read_page_op(chip, page,1357 offset_in_page,1358 buf, len, false);1359 else1360 return nand_lp_exec_read_page_op(chip, page,1361 offset_in_page, buf,1362 len);1363 }1364 1365 return nand_sp_exec_read_page_op(chip, page, offset_in_page,1366 buf, len);1367 }1368 1369 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, offset_in_page, page);1370 if (len)1371 chip->legacy.read_buf(chip, buf, len);1372 1373 return 0;1374}1375EXPORT_SYMBOL_GPL(nand_read_page_op);1376 1377/**1378 * nand_read_param_page_op - Do a READ PARAMETER PAGE operation1379 * @chip: The NAND chip1380 * @page: parameter page to read1381 * @buf: buffer used to store the data1382 * @len: length of the buffer1383 *1384 * This function issues a READ PARAMETER PAGE operation.1385 * This function does not select/unselect the CS line.1386 *1387 * Returns 0 on success, a negative error code otherwise.1388 */1389int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf,1390 unsigned int len)1391{1392 unsigned int i;1393 u8 *p = buf;1394 1395 if (len && !buf)1396 return -EINVAL;1397 1398 if (nand_has_exec_op(chip)) {1399 const struct nand_interface_config *conf =1400 nand_get_interface_config(chip);1401 struct nand_op_instr instrs[] = {1402 NAND_OP_CMD(NAND_CMD_PARAM, 0),1403 NAND_OP_ADDR(1, &page,1404 NAND_COMMON_TIMING_NS(conf, tWB_max)),1405 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tR_max),1406 NAND_COMMON_TIMING_NS(conf, tRR_min)),1407 NAND_OP_8BIT_DATA_IN(len, buf, 0),1408 };1409 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);1410 1411 /* Drop the DATA_IN instruction if len is set to 0. */1412 if (!len)1413 op.ninstrs--;1414 1415 return nand_exec_op(chip, &op);1416 }1417 1418 chip->legacy.cmdfunc(chip, NAND_CMD_PARAM, page, -1);1419 for (i = 0; i < len; i++)1420 p[i] = chip->legacy.read_byte(chip);1421 1422 return 0;1423}1424 1425/**1426 * nand_change_read_column_op - Do a CHANGE READ COLUMN operation1427 * @chip: The NAND chip1428 * @offset_in_page: offset within the page1429 * @buf: buffer used to store the data1430 * @len: length of the buffer1431 * @force_8bit: force 8-bit bus access1432 *1433 * This function issues a CHANGE READ COLUMN operation.1434 * This function does not select/unselect the CS line.1435 *1436 * Returns 0 on success, a negative error code otherwise.1437 */1438int nand_change_read_column_op(struct nand_chip *chip,1439 unsigned int offset_in_page, void *buf,1440 unsigned int len, bool force_8bit)1441{1442 struct mtd_info *mtd = nand_to_mtd(chip);1443 bool ident_stage = !mtd->writesize;1444 1445 if (len && !buf)1446 return -EINVAL;1447 1448 if (!ident_stage) {1449 if (offset_in_page + len > mtd->writesize + mtd->oobsize)1450 return -EINVAL;1451 1452 /* Small page NANDs do not support column change. */1453 if (mtd->writesize <= 512)1454 return -ENOTSUPP;1455 }1456 1457 if (nand_has_exec_op(chip)) {1458 const struct nand_interface_config *conf =1459 nand_get_interface_config(chip);1460 u8 addrs[2] = {};1461 struct nand_op_instr instrs[] = {1462 NAND_OP_CMD(NAND_CMD_RNDOUT, 0),1463 NAND_OP_ADDR(2, addrs, 0),1464 NAND_OP_CMD(NAND_CMD_RNDOUTSTART,1465 NAND_COMMON_TIMING_NS(conf, tCCS_min)),1466 NAND_OP_DATA_IN(len, buf, 0),1467 };1468 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);1469 int ret;1470 1471 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);1472 if (ret < 0)1473 return ret;1474 1475 /* Drop the DATA_IN instruction if len is set to 0. */1476 if (!len)1477 op.ninstrs--;1478 1479 instrs[3].ctx.data.force_8bit = force_8bit;1480 1481 return nand_exec_op(chip, &op);1482 }1483 1484 chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, offset_in_page, -1);1485 if (len)1486 chip->legacy.read_buf(chip, buf, len);1487 1488 return 0;1489}1490EXPORT_SYMBOL_GPL(nand_change_read_column_op);1491 1492/**1493 * nand_read_oob_op - Do a READ OOB operation1494 * @chip: The NAND chip1495 * @page: page to read1496 * @offset_in_oob: offset within the OOB area1497 * @buf: buffer used to store the data1498 * @len: length of the buffer1499 *1500 * This function issues a READ OOB operation.1501 * This function does not select/unselect the CS line.1502 *1503 * Returns 0 on success, a negative error code otherwise.1504 */1505int nand_read_oob_op(struct nand_chip *chip, unsigned int page,1506 unsigned int offset_in_oob, void *buf, unsigned int len)1507{1508 struct mtd_info *mtd = nand_to_mtd(chip);1509 1510 if (len && !buf)1511 return -EINVAL;1512 1513 if (offset_in_oob + len > mtd->oobsize)1514 return -EINVAL;1515 1516 if (nand_has_exec_op(chip))1517 return nand_read_page_op(chip, page,1518 mtd->writesize + offset_in_oob,1519 buf, len);1520 1521 chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page);1522 if (len)1523 chip->legacy.read_buf(chip, buf, len);1524 1525 return 0;1526}1527EXPORT_SYMBOL_GPL(nand_read_oob_op);1528 1529static int nand_exec_prog_page_op(struct nand_chip *chip, unsigned int page,1530 unsigned int offset_in_page, const void *buf,1531 unsigned int len, bool prog)1532{1533 const struct nand_interface_config *conf =1534 nand_get_interface_config(chip);1535 struct mtd_info *mtd = nand_to_mtd(chip);1536 u8 addrs[5] = {};1537 struct nand_op_instr instrs[] = {1538 /*1539 * The first instruction will be dropped if we're dealing1540 * with a large page NAND and adjusted if we're dealing1541 * with a small page NAND and the page offset is > 255.1542 */1543 NAND_OP_CMD(NAND_CMD_READ0, 0),1544 NAND_OP_CMD(NAND_CMD_SEQIN, 0),1545 NAND_OP_ADDR(0, addrs, NAND_COMMON_TIMING_NS(conf, tADL_min)),1546 NAND_OP_DATA_OUT(len, buf, 0),1547 NAND_OP_CMD(NAND_CMD_PAGEPROG,1548 NAND_COMMON_TIMING_NS(conf, tWB_max)),1549 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tPROG_max), 0),1550 };1551 struct nand_operation op = NAND_DESTRUCTIVE_OPERATION(chip->cur_cs,1552 instrs);1553 int naddrs = nand_fill_column_cycles(chip, addrs, offset_in_page);1554 1555 if (naddrs < 0)1556 return naddrs;1557 1558 addrs[naddrs++] = page;1559 addrs[naddrs++] = page >> 8;1560 if (chip->options & NAND_ROW_ADDR_3)1561 addrs[naddrs++] = page >> 16;1562 1563 instrs[2].ctx.addr.naddrs = naddrs;1564 1565 /* Drop the last two instructions if we're not programming the page. */1566 if (!prog) {1567 op.ninstrs -= 2;1568 /* Also drop the DATA_OUT instruction if empty. */1569 if (!len)1570 op.ninstrs--;1571 }1572 1573 if (mtd->writesize <= 512) {1574 /*1575 * Small pages need some more tweaking: we have to adjust the1576 * first instruction depending on the page offset we're trying1577 * to access.1578 */1579 if (offset_in_page >= mtd->writesize)1580 instrs[0].ctx.cmd.opcode = NAND_CMD_READOOB;1581 else if (offset_in_page >= 256 &&1582 !(chip->options & NAND_BUSWIDTH_16))1583 instrs[0].ctx.cmd.opcode = NAND_CMD_READ1;1584 } else {1585 /*1586 * Drop the first command if we're dealing with a large page1587 * NAND.1588 */1589 op.instrs++;1590 op.ninstrs--;1591 }1592 1593 return nand_exec_op(chip, &op);1594}1595 1596/**1597 * nand_prog_page_begin_op - starts a PROG PAGE operation1598 * @chip: The NAND chip1599 * @page: page to write1600 * @offset_in_page: offset within the page1601 * @buf: buffer containing the data to write to the page1602 * @len: length of the buffer1603 *1604 * This function issues the first half of a PROG PAGE operation.1605 * This function does not select/unselect the CS line.1606 *1607 * Returns 0 on success, a negative error code otherwise.1608 */1609int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,1610 unsigned int offset_in_page, const void *buf,1611 unsigned int len)1612{1613 struct mtd_info *mtd = nand_to_mtd(chip);1614 1615 if (len && !buf)1616 return -EINVAL;1617 1618 if (offset_in_page + len > mtd->writesize + mtd->oobsize)1619 return -EINVAL;1620 1621 if (nand_has_exec_op(chip))1622 return nand_exec_prog_page_op(chip, page, offset_in_page, buf,1623 len, false);1624 1625 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page, page);1626 1627 if (buf)1628 chip->legacy.write_buf(chip, buf, len);1629 1630 return 0;1631}1632EXPORT_SYMBOL_GPL(nand_prog_page_begin_op);1633 1634/**1635 * nand_prog_page_end_op - ends a PROG PAGE operation1636 * @chip: The NAND chip1637 *1638 * This function issues the second half of a PROG PAGE operation.1639 * This function does not select/unselect the CS line.1640 *1641 * Returns 0 on success, a negative error code otherwise.1642 */1643int nand_prog_page_end_op(struct nand_chip *chip)1644{1645 int ret;1646 u8 status;1647 1648 if (nand_has_exec_op(chip)) {1649 const struct nand_interface_config *conf =1650 nand_get_interface_config(chip);1651 struct nand_op_instr instrs[] = {1652 NAND_OP_CMD(NAND_CMD_PAGEPROG,1653 NAND_COMMON_TIMING_NS(conf, tWB_max)),1654 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tPROG_max),1655 0),1656 };1657 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);1658 1659 ret = nand_exec_op(chip, &op);1660 if (ret)1661 return ret;1662 1663 ret = nand_status_op(chip, &status);1664 if (ret)1665 return ret;1666 } else {1667 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);1668 ret = chip->legacy.waitfunc(chip);1669 if (ret < 0)1670 return ret;1671 1672 status = ret;1673 }1674 1675 if (status & NAND_STATUS_FAIL)1676 return -EIO;1677 1678 return 0;1679}1680EXPORT_SYMBOL_GPL(nand_prog_page_end_op);1681 1682/**1683 * nand_prog_page_op - Do a full PROG PAGE operation1684 * @chip: The NAND chip1685 * @page: page to write1686 * @offset_in_page: offset within the page1687 * @buf: buffer containing the data to write to the page1688 * @len: length of the buffer1689 *1690 * This function issues a full PROG PAGE operation.1691 * This function does not select/unselect the CS line.1692 *1693 * Returns 0 on success, a negative error code otherwise.1694 */1695int nand_prog_page_op(struct nand_chip *chip, unsigned int page,1696 unsigned int offset_in_page, const void *buf,1697 unsigned int len)1698{1699 struct mtd_info *mtd = nand_to_mtd(chip);1700 u8 status;1701 int ret;1702 1703 if (!len || !buf)1704 return -EINVAL;1705 1706 if (offset_in_page + len > mtd->writesize + mtd->oobsize)1707 return -EINVAL;1708 1709 if (nand_has_exec_op(chip)) {1710 ret = nand_exec_prog_page_op(chip, page, offset_in_page, buf,1711 len, true);1712 if (ret)1713 return ret;1714 1715 ret = nand_status_op(chip, &status);1716 if (ret)1717 return ret;1718 } else {1719 chip->legacy.cmdfunc(chip, NAND_CMD_SEQIN, offset_in_page,1720 page);1721 chip->legacy.write_buf(chip, buf, len);1722 chip->legacy.cmdfunc(chip, NAND_CMD_PAGEPROG, -1, -1);1723 ret = chip->legacy.waitfunc(chip);1724 if (ret < 0)1725 return ret;1726 1727 status = ret;1728 }1729 1730 if (status & NAND_STATUS_FAIL)1731 return -EIO;1732 1733 return 0;1734}1735EXPORT_SYMBOL_GPL(nand_prog_page_op);1736 1737/**1738 * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation1739 * @chip: The NAND chip1740 * @offset_in_page: offset within the page1741 * @buf: buffer containing the data to send to the NAND1742 * @len: length of the buffer1743 * @force_8bit: force 8-bit bus access1744 *1745 * This function issues a CHANGE WRITE COLUMN operation.1746 * This function does not select/unselect the CS line.1747 *1748 * Returns 0 on success, a negative error code otherwise.1749 */1750int nand_change_write_column_op(struct nand_chip *chip,1751 unsigned int offset_in_page,1752 const void *buf, unsigned int len,1753 bool force_8bit)1754{1755 struct mtd_info *mtd = nand_to_mtd(chip);1756 1757 if (len && !buf)1758 return -EINVAL;1759 1760 if (offset_in_page + len > mtd->writesize + mtd->oobsize)1761 return -EINVAL;1762 1763 /* Small page NANDs do not support column change. */1764 if (mtd->writesize <= 512)1765 return -ENOTSUPP;1766 1767 if (nand_has_exec_op(chip)) {1768 const struct nand_interface_config *conf =1769 nand_get_interface_config(chip);1770 u8 addrs[2];1771 struct nand_op_instr instrs[] = {1772 NAND_OP_CMD(NAND_CMD_RNDIN, 0),1773 NAND_OP_ADDR(2, addrs, NAND_COMMON_TIMING_NS(conf, tCCS_min)),1774 NAND_OP_DATA_OUT(len, buf, 0),1775 };1776 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);1777 int ret;1778 1779 ret = nand_fill_column_cycles(chip, addrs, offset_in_page);1780 if (ret < 0)1781 return ret;1782 1783 instrs[2].ctx.data.force_8bit = force_8bit;1784 1785 /* Drop the DATA_OUT instruction if len is set to 0. */1786 if (!len)1787 op.ninstrs--;1788 1789 return nand_exec_op(chip, &op);1790 }1791 1792 chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1);1793 if (len)1794 chip->legacy.write_buf(chip, buf, len);1795 1796 return 0;1797}1798EXPORT_SYMBOL_GPL(nand_change_write_column_op);1799 1800/**1801 * nand_readid_op - Do a READID operation1802 * @chip: The NAND chip1803 * @addr: address cycle to pass after the READID command1804 * @buf: buffer used to store the ID1805 * @len: length of the buffer1806 *1807 * This function sends a READID command and reads back the ID returned by the1808 * NAND.1809 * This function does not select/unselect the CS line.1810 *1811 * Returns 0 on success, a negative error code otherwise.1812 */1813int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,1814 unsigned int len)1815{1816 unsigned int i;1817 u8 *id = buf, *ddrbuf = NULL;1818 1819 if (len && !buf)1820 return -EINVAL;1821 1822 if (nand_has_exec_op(chip)) {1823 const struct nand_interface_config *conf =1824 nand_get_interface_config(chip);1825 struct nand_op_instr instrs[] = {1826 NAND_OP_CMD(NAND_CMD_READID, 0),1827 NAND_OP_ADDR(1, &addr,1828 NAND_COMMON_TIMING_NS(conf, tADL_min)),1829 NAND_OP_8BIT_DATA_IN(len, buf, 0),1830 };1831 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);1832 int ret;1833 1834 /* READ_ID data bytes are received twice in NV-DDR mode */1835 if (len && nand_interface_is_nvddr(conf)) {1836 ddrbuf = kzalloc(len * 2, GFP_KERNEL);1837 if (!ddrbuf)1838 return -ENOMEM;1839 1840 instrs[2].ctx.data.len *= 2;1841 instrs[2].ctx.data.buf.in = ddrbuf;1842 }1843 1844 /* Drop the DATA_IN instruction if len is set to 0. */1845 if (!len)1846 op.ninstrs--;1847 1848 ret = nand_exec_op(chip, &op);1849 if (!ret && len && nand_interface_is_nvddr(conf)) {1850 for (i = 0; i < len; i++)1851 id[i] = ddrbuf[i * 2];1852 }1853 1854 kfree(ddrbuf);1855 1856 return ret;1857 }1858 1859 chip->legacy.cmdfunc(chip, NAND_CMD_READID, addr, -1);1860 1861 for (i = 0; i < len; i++)1862 id[i] = chip->legacy.read_byte(chip);1863 1864 return 0;1865}1866EXPORT_SYMBOL_GPL(nand_readid_op);1867 1868/**1869 * nand_status_op - Do a STATUS operation1870 * @chip: The NAND chip1871 * @status: out variable to store the NAND status1872 *1873 * This function sends a STATUS command and reads back the status returned by1874 * the NAND.1875 * This function does not select/unselect the CS line.1876 *1877 * Returns 0 on success, a negative error code otherwise.1878 */1879int nand_status_op(struct nand_chip *chip, u8 *status)1880{1881 if (nand_has_exec_op(chip)) {1882 const struct nand_interface_config *conf =1883 nand_get_interface_config(chip);1884 u8 ddrstatus[2];1885 struct nand_op_instr instrs[] = {1886 NAND_OP_CMD(NAND_CMD_STATUS,1887 NAND_COMMON_TIMING_NS(conf, tADL_min)),1888 NAND_OP_8BIT_DATA_IN(1, status, 0),1889 };1890 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);1891 int ret;1892 1893 /* The status data byte will be received twice in NV-DDR mode */1894 if (status && nand_interface_is_nvddr(conf)) {1895 instrs[1].ctx.data.len *= 2;1896 instrs[1].ctx.data.buf.in = ddrstatus;1897 }1898 1899 if (!status)1900 op.ninstrs--;1901 1902 ret = nand_exec_op(chip, &op);1903 if (!ret && status && nand_interface_is_nvddr(conf))1904 *status = ddrstatus[0];1905 1906 return ret;1907 }1908 1909 chip->legacy.cmdfunc(chip, NAND_CMD_STATUS, -1, -1);1910 if (status)1911 *status = chip->legacy.read_byte(chip);1912 1913 return 0;1914}1915EXPORT_SYMBOL_GPL(nand_status_op);1916 1917/**1918 * nand_exit_status_op - Exit a STATUS operation1919 * @chip: The NAND chip1920 *1921 * This function sends a READ0 command to cancel the effect of the STATUS1922 * command to avoid reading only the status until a new read command is sent.1923 *1924 * This function does not select/unselect the CS line.1925 *1926 * Returns 0 on success, a negative error code otherwise.1927 */1928int nand_exit_status_op(struct nand_chip *chip)1929{1930 if (nand_has_exec_op(chip)) {1931 struct nand_op_instr instrs[] = {1932 NAND_OP_CMD(NAND_CMD_READ0, 0),1933 };1934 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);1935 1936 return nand_exec_op(chip, &op);1937 }1938 1939 chip->legacy.cmdfunc(chip, NAND_CMD_READ0, -1, -1);1940 1941 return 0;1942}1943EXPORT_SYMBOL_GPL(nand_exit_status_op);1944 1945/**1946 * nand_erase_op - Do an erase operation1947 * @chip: The NAND chip1948 * @eraseblock: block to erase1949 *1950 * This function sends an ERASE command and waits for the NAND to be ready1951 * before returning.1952 * This function does not select/unselect the CS line.1953 *1954 * Returns 0 on success, a negative error code otherwise.1955 */1956int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock)1957{1958 unsigned int page = eraseblock <<1959 (chip->phys_erase_shift - chip->page_shift);1960 int ret;1961 u8 status;1962 1963 if (nand_has_exec_op(chip)) {1964 const struct nand_interface_config *conf =1965 nand_get_interface_config(chip);1966 u8 addrs[3] = { page, page >> 8, page >> 16 };1967 struct nand_op_instr instrs[] = {1968 NAND_OP_CMD(NAND_CMD_ERASE1, 0),1969 NAND_OP_ADDR(2, addrs, 0),1970 NAND_OP_CMD(NAND_CMD_ERASE2,1971 NAND_COMMON_TIMING_NS(conf, tWB_max)),1972 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tBERS_max),1973 0),1974 };1975 struct nand_operation op = NAND_DESTRUCTIVE_OPERATION(chip->cur_cs,1976 instrs);1977 1978 if (chip->options & NAND_ROW_ADDR_3)1979 instrs[1].ctx.addr.naddrs++;1980 1981 ret = nand_exec_op(chip, &op);1982 if (ret)1983 return ret;1984 1985 ret = nand_status_op(chip, &status);1986 if (ret)1987 return ret;1988 } else {1989 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE1, -1, page);1990 chip->legacy.cmdfunc(chip, NAND_CMD_ERASE2, -1, -1);1991 1992 ret = chip->legacy.waitfunc(chip);1993 if (ret < 0)1994 return ret;1995 1996 status = ret;1997 }1998 1999 if (status & NAND_STATUS_FAIL)2000 return -EIO;2001 2002 return 0;2003}2004EXPORT_SYMBOL_GPL(nand_erase_op);2005 2006/**2007 * nand_set_features_op - Do a SET FEATURES operation2008 * @chip: The NAND chip2009 * @feature: feature id2010 * @data: 4 bytes of data2011 *2012 * This function sends a SET FEATURES command and waits for the NAND to be2013 * ready before returning.2014 * This function does not select/unselect the CS line.2015 *2016 * Returns 0 on success, a negative error code otherwise.2017 */2018static int nand_set_features_op(struct nand_chip *chip, u8 feature,2019 const void *data)2020{2021 const u8 *params = data;2022 int i, ret;2023 2024 if (nand_has_exec_op(chip)) {2025 const struct nand_interface_config *conf =2026 nand_get_interface_config(chip);2027 struct nand_op_instr instrs[] = {2028 NAND_OP_CMD(NAND_CMD_SET_FEATURES, 0),2029 NAND_OP_ADDR(1, &feature, NAND_COMMON_TIMING_NS(conf,2030 tADL_min)),2031 NAND_OP_8BIT_DATA_OUT(ONFI_SUBFEATURE_PARAM_LEN, data,2032 NAND_COMMON_TIMING_NS(conf,2033 tWB_max)),2034 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tFEAT_max),2035 0),2036 };2037 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);2038 2039 return nand_exec_op(chip, &op);2040 }2041 2042 chip->legacy.cmdfunc(chip, NAND_CMD_SET_FEATURES, feature, -1);2043 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)2044 chip->legacy.write_byte(chip, params[i]);2045 2046 ret = chip->legacy.waitfunc(chip);2047 if (ret < 0)2048 return ret;2049 2050 if (ret & NAND_STATUS_FAIL)2051 return -EIO;2052 2053 return 0;2054}2055 2056/**2057 * nand_get_features_op - Do a GET FEATURES operation2058 * @chip: The NAND chip2059 * @feature: feature id2060 * @data: 4 bytes of data2061 *2062 * This function sends a GET FEATURES command and waits for the NAND to be2063 * ready before returning.2064 * This function does not select/unselect the CS line.2065 *2066 * Returns 0 on success, a negative error code otherwise.2067 */2068static int nand_get_features_op(struct nand_chip *chip, u8 feature,2069 void *data)2070{2071 u8 *params = data, ddrbuf[ONFI_SUBFEATURE_PARAM_LEN * 2];2072 int i;2073 2074 if (nand_has_exec_op(chip)) {2075 const struct nand_interface_config *conf =2076 nand_get_interface_config(chip);2077 struct nand_op_instr instrs[] = {2078 NAND_OP_CMD(NAND_CMD_GET_FEATURES, 0),2079 NAND_OP_ADDR(1, &feature,2080 NAND_COMMON_TIMING_NS(conf, tWB_max)),2081 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tFEAT_max),2082 NAND_COMMON_TIMING_NS(conf, tRR_min)),2083 NAND_OP_8BIT_DATA_IN(ONFI_SUBFEATURE_PARAM_LEN,2084 data, 0),2085 };2086 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);2087 int ret;2088 2089 /* GET_FEATURE data bytes are received twice in NV-DDR mode */2090 if (nand_interface_is_nvddr(conf)) {2091 instrs[3].ctx.data.len *= 2;2092 instrs[3].ctx.data.buf.in = ddrbuf;2093 }2094 2095 ret = nand_exec_op(chip, &op);2096 if (nand_interface_is_nvddr(conf)) {2097 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; i++)2098 params[i] = ddrbuf[i * 2];2099 }2100 2101 return ret;2102 }2103 2104 chip->legacy.cmdfunc(chip, NAND_CMD_GET_FEATURES, feature, -1);2105 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)2106 params[i] = chip->legacy.read_byte(chip);2107 2108 return 0;2109}2110 2111static int nand_wait_rdy_op(struct nand_chip *chip, unsigned int timeout_ms,2112 unsigned int delay_ns)2113{2114 if (nand_has_exec_op(chip)) {2115 struct nand_op_instr instrs[] = {2116 NAND_OP_WAIT_RDY(PSEC_TO_MSEC(timeout_ms),2117 PSEC_TO_NSEC(delay_ns)),2118 };2119 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);2120 2121 return nand_exec_op(chip, &op);2122 }2123 2124 /* Apply delay or wait for ready/busy pin */2125 if (!chip->legacy.dev_ready)2126 udelay(chip->legacy.chip_delay);2127 else2128 nand_wait_ready(chip);2129 2130 return 0;2131}2132 2133/**2134 * nand_reset_op - Do a reset operation2135 * @chip: The NAND chip2136 *2137 * This function sends a RESET command and waits for the NAND to be ready2138 * before returning.2139 * This function does not select/unselect the CS line.2140 *2141 * Returns 0 on success, a negative error code otherwise.2142 */2143int nand_reset_op(struct nand_chip *chip)2144{2145 if (nand_has_exec_op(chip)) {2146 const struct nand_interface_config *conf =2147 nand_get_interface_config(chip);2148 struct nand_op_instr instrs[] = {2149 NAND_OP_CMD(NAND_CMD_RESET,2150 NAND_COMMON_TIMING_NS(conf, tWB_max)),2151 NAND_OP_WAIT_RDY(NAND_COMMON_TIMING_MS(conf, tRST_max),2152 0),2153 };2154 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);2155 2156 return nand_exec_op(chip, &op);2157 }2158 2159 chip->legacy.cmdfunc(chip, NAND_CMD_RESET, -1, -1);2160 2161 return 0;2162}2163EXPORT_SYMBOL_GPL(nand_reset_op);2164 2165/**2166 * nand_read_data_op - Read data from the NAND2167 * @chip: The NAND chip2168 * @buf: buffer used to store the data2169 * @len: length of the buffer2170 * @force_8bit: force 8-bit bus access2171 * @check_only: do not actually run the command, only checks if the2172 * controller driver supports it2173 *2174 * This function does a raw data read on the bus. Usually used after launching2175 * another NAND operation like nand_read_page_op().2176 * This function does not select/unselect the CS line.2177 *2178 * Returns 0 on success, a negative error code otherwise.2179 */2180int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,2181 bool force_8bit, bool check_only)2182{2183 if (!len || (!check_only && !buf))2184 return -EINVAL;2185 2186 if (nand_has_exec_op(chip)) {2187 const struct nand_interface_config *conf =2188 nand_get_interface_config(chip);2189 struct nand_op_instr instrs[] = {2190 NAND_OP_DATA_IN(len, buf, 0),2191 };2192 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);2193 u8 *ddrbuf = NULL;2194 int ret, i;2195 2196 instrs[0].ctx.data.force_8bit = force_8bit;2197 2198 /*2199 * Parameter payloads (ID, status, features, etc) do not go2200 * through the same pipeline as regular data, hence the2201 * force_8bit flag must be set and this also indicates that in2202 * case NV-DDR timings are being used the data will be received2203 * twice.2204 */2205 if (force_8bit && nand_interface_is_nvddr(conf)) {2206 ddrbuf = kzalloc(len * 2, GFP_KERNEL);2207 if (!ddrbuf)2208 return -ENOMEM;2209 2210 instrs[0].ctx.data.len *= 2;2211 instrs[0].ctx.data.buf.in = ddrbuf;2212 }2213 2214 if (check_only) {2215 ret = nand_check_op(chip, &op);2216 kfree(ddrbuf);2217 return ret;2218 }2219 2220 ret = nand_exec_op(chip, &op);2221 if (!ret && force_8bit && nand_interface_is_nvddr(conf)) {2222 u8 *dst = buf;2223 2224 for (i = 0; i < len; i++)2225 dst[i] = ddrbuf[i * 2];2226 }2227 2228 kfree(ddrbuf);2229 2230 return ret;2231 }2232 2233 if (check_only)2234 return 0;2235 2236 if (force_8bit) {2237 u8 *p = buf;2238 unsigned int i;2239 2240 for (i = 0; i < len; i++)2241 p[i] = chip->legacy.read_byte(chip);2242 } else {2243 chip->legacy.read_buf(chip, buf, len);2244 }2245 2246 return 0;2247}2248EXPORT_SYMBOL_GPL(nand_read_data_op);2249 2250/**2251 * nand_write_data_op - Write data from the NAND2252 * @chip: The NAND chip2253 * @buf: buffer containing the data to send on the bus2254 * @len: length of the buffer2255 * @force_8bit: force 8-bit bus access2256 *2257 * This function does a raw data write on the bus. Usually used after launching2258 * another NAND operation like nand_write_page_begin_op().2259 * This function does not select/unselect the CS line.2260 *2261 * Returns 0 on success, a negative error code otherwise.2262 */2263int nand_write_data_op(struct nand_chip *chip, const void *buf,2264 unsigned int len, bool force_8bit)2265{2266 if (!len || !buf)2267 return -EINVAL;2268 2269 if (nand_has_exec_op(chip)) {2270 struct nand_op_instr instrs[] = {2271 NAND_OP_DATA_OUT(len, buf, 0),2272 };2273 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);2274 2275 instrs[0].ctx.data.force_8bit = force_8bit;2276 2277 return nand_exec_op(chip, &op);2278 }2279 2280 if (force_8bit) {2281 const u8 *p = buf;2282 unsigned int i;2283 2284 for (i = 0; i < len; i++)2285 chip->legacy.write_byte(chip, p[i]);2286 } else {2287 chip->legacy.write_buf(chip, buf, len);2288 }2289 2290 return 0;2291}2292EXPORT_SYMBOL_GPL(nand_write_data_op);2293 2294/**2295 * struct nand_op_parser_ctx - Context used by the parser2296 * @instrs: array of all the instructions that must be addressed2297 * @ninstrs: length of the @instrs array2298 * @subop: Sub-operation to be passed to the NAND controller2299 *2300 * This structure is used by the core to split NAND operations into2301 * sub-operations that can be handled by the NAND controller.2302 */2303struct nand_op_parser_ctx {2304 const struct nand_op_instr *instrs;2305 unsigned int ninstrs;2306 struct nand_subop subop;2307};2308 2309/**2310 * nand_op_parser_must_split_instr - Checks if an instruction must be split2311 * @pat: the parser pattern element that matches @instr2312 * @instr: pointer to the instruction to check2313 * @start_offset: this is an in/out parameter. If @instr has already been2314 * split, then @start_offset is the offset from which to start2315 * (either an address cycle or an offset in the data buffer).2316 * Conversely, if the function returns true (ie. instr must be2317 * split), this parameter is updated to point to the first2318 * data/address cycle that has not been taken care of.2319 *2320 * Some NAND controllers are limited and cannot send X address cycles with a2321 * unique operation, or cannot read/write more than Y bytes at the same time.2322 * In this case, split the instruction that does not fit in a single2323 * controller-operation into two or more chunks.2324 *2325 * Returns true if the instruction must be split, false otherwise.2326 * The @start_offset parameter is also updated to the offset at which the next2327 * bundle of instruction must start (if an address or a data instruction).2328 */2329static bool2330nand_op_parser_must_split_instr(const struct nand_op_parser_pattern_elem *pat,2331 const struct nand_op_instr *instr,2332 unsigned int *start_offset)2333{2334 switch (pat->type) {2335 case NAND_OP_ADDR_INSTR:2336 if (!pat->ctx.addr.maxcycles)2337 break;2338 2339 if (instr->ctx.addr.naddrs - *start_offset >2340 pat->ctx.addr.maxcycles) {2341 *start_offset += pat->ctx.addr.maxcycles;2342 return true;2343 }2344 break;2345 2346 case NAND_OP_DATA_IN_INSTR:2347 case NAND_OP_DATA_OUT_INSTR:2348 if (!pat->ctx.data.maxlen)2349 break;2350 2351 if (instr->ctx.data.len - *start_offset >2352 pat->ctx.data.maxlen) {2353 *start_offset += pat->ctx.data.maxlen;2354 return true;2355 }2356 break;2357 2358 default:2359 break;2360 }2361 2362 return false;2363}2364 2365/**2366 * nand_op_parser_match_pat - Checks if a pattern matches the instructions2367 * remaining in the parser context2368 * @pat: the pattern to test2369 * @ctx: the parser context structure to match with the pattern @pat2370 *2371 * Check if @pat matches the set or a sub-set of instructions remaining in @ctx.2372 * Returns true if this is the case, false ortherwise. When true is returned,2373 * @ctx->subop is updated with the set of instructions to be passed to the2374 * controller driver.2375 */2376static bool2377nand_op_parser_match_pat(const struct nand_op_parser_pattern *pat,2378 struct nand_op_parser_ctx *ctx)2379{2380 unsigned int instr_offset = ctx->subop.first_instr_start_off;2381 const struct nand_op_instr *end = ctx->instrs + ctx->ninstrs;2382 const struct nand_op_instr *instr = ctx->subop.instrs;2383 unsigned int i, ninstrs;2384 2385 for (i = 0, ninstrs = 0; i < pat->nelems && instr < end; i++) {2386 /*2387 * The pattern instruction does not match the operation2388 * instruction. If the instruction is marked optional in the2389 * pattern definition, we skip the pattern element and continue2390 * to the next one. If the element is mandatory, there's no2391 * match and we can return false directly.2392 */2393 if (instr->type != pat->elems[i].type) {2394 if (!pat->elems[i].optional)2395 return false;2396 2397 continue;2398 }2399 2400 /*2401 * Now check the pattern element constraints. If the pattern is2402 * not able to handle the whole instruction in a single step,2403 * we have to split it.2404 * The last_instr_end_off value comes back updated to point to2405 * the position where we have to split the instruction (the2406 * start of the next subop chunk).2407 */2408 if (nand_op_parser_must_split_instr(&pat->elems[i], instr,2409 &instr_offset)) {2410 ninstrs++;2411 i++;2412 break;2413 }2414 2415 instr++;2416 ninstrs++;2417 instr_offset = 0;2418 }2419 2420 /*2421 * This can happen if all instructions of a pattern are optional.2422 * Still, if there's not at least one instruction handled by this2423 * pattern, this is not a match, and we should try the next one (if2424 * any).2425 */2426 if (!ninstrs)2427 return false;2428 2429 /*2430 * We had a match on the pattern head, but the pattern may be longer2431 * than the instructions we're asked to execute. We need to make sure2432 * there's no mandatory elements in the pattern tail.2433 */2434 for (; i < pat->nelems; i++) {2435 if (!pat->elems[i].optional)2436 return false;2437 }2438 2439 /*2440 * We have a match: update the subop structure accordingly and return2441 * true.2442 */2443 ctx->subop.ninstrs = ninstrs;2444 ctx->subop.last_instr_end_off = instr_offset;2445 2446 return true;2447}2448 2449#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)2450static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx)2451{2452 const struct nand_op_instr *instr;2453 char *prefix = " ";2454 unsigned int i;2455 2456 pr_debug("executing subop (CS%d):\n", ctx->subop.cs);2457 2458 for (i = 0; i < ctx->ninstrs; i++) {2459 instr = &ctx->instrs[i];2460 2461 if (instr == &ctx->subop.instrs[0])2462 prefix = " ->";2463 2464 nand_op_trace(prefix, instr);2465 2466 if (instr == &ctx->subop.instrs[ctx->subop.ninstrs - 1])2467 prefix = " ";2468 }2469}2470#else2471static void nand_op_parser_trace(const struct nand_op_parser_ctx *ctx)2472{2473 /* NOP */2474}2475#endif2476 2477static int nand_op_parser_cmp_ctx(const struct nand_op_parser_ctx *a,2478 const struct nand_op_parser_ctx *b)2479{2480 if (a->subop.ninstrs < b->subop.ninstrs)2481 return -1;2482 else if (a->subop.ninstrs > b->subop.ninstrs)2483 return 1;2484 2485 if (a->subop.last_instr_end_off < b->subop.last_instr_end_off)2486 return -1;2487 else if (a->subop.last_instr_end_off > b->subop.last_instr_end_off)2488 return 1;2489 2490 return 0;2491}2492 2493/**2494 * nand_op_parser_exec_op - exec_op parser2495 * @chip: the NAND chip2496 * @parser: patterns description provided by the controller driver2497 * @op: the NAND operation to address2498 * @check_only: when true, the function only checks if @op can be handled but2499 * does not execute the operation2500 *2501 * Helper function designed to ease integration of NAND controller drivers that2502 * only support a limited set of instruction sequences. The supported sequences2503 * are described in @parser, and the framework takes care of splitting @op into2504 * multiple sub-operations (if required) and pass them back to the ->exec()2505 * callback of the matching pattern if @check_only is set to false.2506 *2507 * NAND controller drivers should call this function from their own ->exec_op()2508 * implementation.2509 *2510 * Returns 0 on success, a negative error code otherwise. A failure can be2511 * caused by an unsupported operation (none of the supported patterns is able2512 * to handle the requested operation), or an error returned by one of the2513 * matching pattern->exec() hook.2514 */2515int nand_op_parser_exec_op(struct nand_chip *chip,2516 const struct nand_op_parser *parser,2517 const struct nand_operation *op, bool check_only)2518{2519 struct nand_op_parser_ctx ctx = {2520 .subop.cs = op->cs,2521 .subop.instrs = op->instrs,2522 .instrs = op->instrs,2523 .ninstrs = op->ninstrs,2524 };2525 unsigned int i;2526 2527 while (ctx.subop.instrs < op->instrs + op->ninstrs) {2528 const struct nand_op_parser_pattern *pattern;2529 struct nand_op_parser_ctx best_ctx;2530 int ret, best_pattern = -1;2531 2532 for (i = 0; i < parser->npatterns; i++) {2533 struct nand_op_parser_ctx test_ctx = ctx;2534 2535 pattern = &parser->patterns[i];2536 if (!nand_op_parser_match_pat(pattern, &test_ctx))2537 continue;2538 2539 if (best_pattern >= 0 &&2540 nand_op_parser_cmp_ctx(&test_ctx, &best_ctx) <= 0)2541 continue;2542 2543 best_pattern = i;2544 best_ctx = test_ctx;2545 }2546 2547 if (best_pattern < 0) {2548 pr_debug("->exec_op() parser: pattern not found!\n");2549 return -ENOTSUPP;2550 }2551 2552 ctx = best_ctx;2553 nand_op_parser_trace(&ctx);2554 2555 if (!check_only) {2556 pattern = &parser->patterns[best_pattern];2557 ret = pattern->exec(chip, &ctx.subop);2558 if (ret)2559 return ret;2560 }2561 2562 /*2563 * Update the context structure by pointing to the start of the2564 * next subop.2565 */2566 ctx.subop.instrs = ctx.subop.instrs + ctx.subop.ninstrs;2567 if (ctx.subop.last_instr_end_off)2568 ctx.subop.instrs -= 1;2569 2570 ctx.subop.first_instr_start_off = ctx.subop.last_instr_end_off;2571 }2572 2573 return 0;2574}2575EXPORT_SYMBOL_GPL(nand_op_parser_exec_op);2576 2577static bool nand_instr_is_data(const struct nand_op_instr *instr)2578{2579 return instr && (instr->type == NAND_OP_DATA_IN_INSTR ||2580 instr->type == NAND_OP_DATA_OUT_INSTR);2581}2582 2583static bool nand_subop_instr_is_valid(const struct nand_subop *subop,2584 unsigned int instr_idx)2585{2586 return subop && instr_idx < subop->ninstrs;2587}2588 2589static unsigned int nand_subop_get_start_off(const struct nand_subop *subop,2590 unsigned int instr_idx)2591{2592 if (instr_idx)2593 return 0;2594 2595 return subop->first_instr_start_off;2596}2597 2598/**2599 * nand_subop_get_addr_start_off - Get the start offset in an address array2600 * @subop: The entire sub-operation2601 * @instr_idx: Index of the instruction inside the sub-operation2602 *2603 * During driver development, one could be tempted to directly use the2604 * ->addr.addrs field of address instructions. This is wrong as address2605 * instructions might be split.2606 *2607 * Given an address instruction, returns the offset of the first cycle to issue.2608 */2609unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,2610 unsigned int instr_idx)2611{2612 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||2613 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR))2614 return 0;2615 2616 return nand_subop_get_start_off(subop, instr_idx);2617}2618EXPORT_SYMBOL_GPL(nand_subop_get_addr_start_off);2619 2620/**2621 * nand_subop_get_num_addr_cyc - Get the remaining address cycles to assert2622 * @subop: The entire sub-operation2623 * @instr_idx: Index of the instruction inside the sub-operation2624 *2625 * During driver development, one could be tempted to directly use the2626 * ->addr->naddrs field of a data instruction. This is wrong as instructions2627 * might be split.2628 *2629 * Given an address instruction, returns the number of address cycle to issue.2630 */2631unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,2632 unsigned int instr_idx)2633{2634 int start_off, end_off;2635 2636 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||2637 subop->instrs[instr_idx].type != NAND_OP_ADDR_INSTR))2638 return 0;2639 2640 start_off = nand_subop_get_addr_start_off(subop, instr_idx);2641 2642 if (instr_idx == subop->ninstrs - 1 &&2643 subop->last_instr_end_off)2644 end_off = subop->last_instr_end_off;2645 else2646 end_off = subop->instrs[instr_idx].ctx.addr.naddrs;2647 2648 return end_off - start_off;2649}2650EXPORT_SYMBOL_GPL(nand_subop_get_num_addr_cyc);2651 2652/**2653 * nand_subop_get_data_start_off - Get the start offset in a data array2654 * @subop: The entire sub-operation2655 * @instr_idx: Index of the instruction inside the sub-operation2656 *2657 * During driver development, one could be tempted to directly use the2658 * ->data->buf.{in,out} field of data instructions. This is wrong as data2659 * instructions might be split.2660 *2661 * Given a data instruction, returns the offset to start from.2662 */2663unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,2664 unsigned int instr_idx)2665{2666 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||2667 !nand_instr_is_data(&subop->instrs[instr_idx])))2668 return 0;2669 2670 return nand_subop_get_start_off(subop, instr_idx);2671}2672EXPORT_SYMBOL_GPL(nand_subop_get_data_start_off);2673 2674/**2675 * nand_subop_get_data_len - Get the number of bytes to retrieve2676 * @subop: The entire sub-operation2677 * @instr_idx: Index of the instruction inside the sub-operation2678 *2679 * During driver development, one could be tempted to directly use the2680 * ->data->len field of a data instruction. This is wrong as data instructions2681 * might be split.2682 *2683 * Returns the length of the chunk of data to send/receive.2684 */2685unsigned int nand_subop_get_data_len(const struct nand_subop *subop,2686 unsigned int instr_idx)2687{2688 int start_off = 0, end_off;2689 2690 if (WARN_ON(!nand_subop_instr_is_valid(subop, instr_idx) ||2691 !nand_instr_is_data(&subop->instrs[instr_idx])))2692 return 0;2693 2694 start_off = nand_subop_get_data_start_off(subop, instr_idx);2695 2696 if (instr_idx == subop->ninstrs - 1 &&2697 subop->last_instr_end_off)2698 end_off = subop->last_instr_end_off;2699 else2700 end_off = subop->instrs[instr_idx].ctx.data.len;2701 2702 return end_off - start_off;2703}2704EXPORT_SYMBOL_GPL(nand_subop_get_data_len);2705 2706/**2707 * nand_reset - Reset and initialize a NAND device2708 * @chip: The NAND chip2709 * @chipnr: Internal die id2710 *2711 * Save the timings data structure, then apply SDR timings mode 0 (see2712 * nand_reset_interface for details), do the reset operation, and apply2713 * back the previous timings.2714 *2715 * Returns 0 on success, a negative error code otherwise.2716 */2717int nand_reset(struct nand_chip *chip, int chipnr)2718{2719 int ret;2720 2721 ret = nand_reset_interface(chip, chipnr);2722 if (ret)2723 return ret;2724 2725 /*2726 * The CS line has to be released before we can apply the new NAND2727 * interface settings, hence this weird nand_select_target()2728 * nand_deselect_target() dance.2729 */2730 nand_select_target(chip, chipnr);2731 ret = nand_reset_op(chip);2732 nand_deselect_target(chip);2733 if (ret)2734 return ret;2735 2736 ret = nand_setup_interface(chip, chipnr);2737 if (ret)2738 return ret;2739 2740 return 0;2741}2742EXPORT_SYMBOL_GPL(nand_reset);2743 2744/**2745 * nand_get_features - wrapper to perform a GET_FEATURE2746 * @chip: NAND chip info structure2747 * @addr: feature address2748 * @subfeature_param: the subfeature parameters, a four bytes array2749 *2750 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the2751 * operation cannot be handled.2752 */2753int nand_get_features(struct nand_chip *chip, int addr,2754 u8 *subfeature_param)2755{2756 if (!nand_supports_get_features(chip, addr))2757 return -ENOTSUPP;2758 2759 if (chip->legacy.get_features)2760 return chip->legacy.get_features(chip, addr, subfeature_param);2761 2762 return nand_get_features_op(chip, addr, subfeature_param);2763}2764 2765/**2766 * nand_set_features - wrapper to perform a SET_FEATURE2767 * @chip: NAND chip info structure2768 * @addr: feature address2769 * @subfeature_param: the subfeature parameters, a four bytes array2770 *2771 * Returns 0 for success, a negative error otherwise. Returns -ENOTSUPP if the2772 * operation cannot be handled.2773 */2774int nand_set_features(struct nand_chip *chip, int addr,2775 u8 *subfeature_param)2776{2777 if (!nand_supports_set_features(chip, addr))2778 return -ENOTSUPP;2779 2780 if (chip->legacy.set_features)2781 return chip->legacy.set_features(chip, addr, subfeature_param);2782 2783 return nand_set_features_op(chip, addr, subfeature_param);2784}2785 2786/**2787 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data2788 * @buf: buffer to test2789 * @len: buffer length2790 * @bitflips_threshold: maximum number of bitflips2791 *2792 * Check if a buffer contains only 0xff, which means the underlying region2793 * has been erased and is ready to be programmed.2794 * The bitflips_threshold specify the maximum number of bitflips before2795 * considering the region is not erased.2796 * Note: The logic of this function has been extracted from the memweight2797 * implementation, except that nand_check_erased_buf function exit before2798 * testing the whole buffer if the number of bitflips exceed the2799 * bitflips_threshold value.2800 *2801 * Returns a positive number of bitflips less than or equal to2802 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the2803 * threshold.2804 */2805static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)2806{2807 const unsigned char *bitmap = buf;2808 int bitflips = 0;2809 int weight;2810 2811 for (; len && ((uintptr_t)bitmap) % sizeof(long);2812 len--, bitmap++) {2813 weight = hweight8(*bitmap);2814 bitflips += BITS_PER_BYTE - weight;2815 if (unlikely(bitflips > bitflips_threshold))2816 return -EBADMSG;2817 }2818 2819 for (; len >= sizeof(long);2820 len -= sizeof(long), bitmap += sizeof(long)) {2821 unsigned long d = *((unsigned long *)bitmap);2822 if (d == ~0UL)2823 continue;2824 weight = hweight_long(d);2825 bitflips += BITS_PER_LONG - weight;2826 if (unlikely(bitflips > bitflips_threshold))2827 return -EBADMSG;2828 }2829 2830 for (; len > 0; len--, bitmap++) {2831 weight = hweight8(*bitmap);2832 bitflips += BITS_PER_BYTE - weight;2833 if (unlikely(bitflips > bitflips_threshold))2834 return -EBADMSG;2835 }2836 2837 return bitflips;2838}2839 2840/**2841 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only2842 * 0xff data2843 * @data: data buffer to test2844 * @datalen: data length2845 * @ecc: ECC buffer2846 * @ecclen: ECC length2847 * @extraoob: extra OOB buffer2848 * @extraooblen: extra OOB length2849 * @bitflips_threshold: maximum number of bitflips2850 *2851 * Check if a data buffer and its associated ECC and OOB data contains only2852 * 0xff pattern, which means the underlying region has been erased and is2853 * ready to be programmed.2854 * The bitflips_threshold specify the maximum number of bitflips before2855 * considering the region as not erased.2856 *2857 * Note:2858 * 1/ ECC algorithms are working on pre-defined block sizes which are usually2859 * different from the NAND page size. When fixing bitflips, ECC engines will2860 * report the number of errors per chunk, and the NAND core infrastructure2861 * expect you to return the maximum number of bitflips for the whole page.2862 * This is why you should always use this function on a single chunk and2863 * not on the whole page. After checking each chunk you should update your2864 * max_bitflips value accordingly.2865 * 2/ When checking for bitflips in erased pages you should not only check2866 * the payload data but also their associated ECC data, because a user might2867 * have programmed almost all bits to 1 but a few. In this case, we2868 * shouldn't consider the chunk as erased, and checking ECC bytes prevent2869 * this case.2870 * 3/ The extraoob argument is optional, and should be used if some of your OOB2871 * data are protected by the ECC engine.2872 * It could also be used if you support subpages and want to attach some2873 * extra OOB data to an ECC chunk.2874 *2875 * Returns a positive number of bitflips less than or equal to2876 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the2877 * threshold. In case of success, the passed buffers are filled with 0xff.2878 */2879int nand_check_erased_ecc_chunk(void *data, int datalen,2880 void *ecc, int ecclen,2881 void *extraoob, int extraooblen,2882 int bitflips_threshold)2883{2884 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;2885 2886 data_bitflips = nand_check_erased_buf(data, datalen,2887 bitflips_threshold);2888 if (data_bitflips < 0)2889 return data_bitflips;2890 2891 bitflips_threshold -= data_bitflips;2892 2893 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);2894 if (ecc_bitflips < 0)2895 return ecc_bitflips;2896 2897 bitflips_threshold -= ecc_bitflips;2898 2899 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,2900 bitflips_threshold);2901 if (extraoob_bitflips < 0)2902 return extraoob_bitflips;2903 2904 if (data_bitflips)2905 memset(data, 0xff, datalen);2906 2907 if (ecc_bitflips)2908 memset(ecc, 0xff, ecclen);2909 2910 if (extraoob_bitflips)2911 memset(extraoob, 0xff, extraooblen);2912 2913 return data_bitflips + ecc_bitflips + extraoob_bitflips;2914}2915EXPORT_SYMBOL(nand_check_erased_ecc_chunk);2916 2917/**2918 * nand_read_page_raw_notsupp - dummy read raw page function2919 * @chip: nand chip info structure2920 * @buf: buffer to store read data2921 * @oob_required: caller requires OOB data read to chip->oob_poi2922 * @page: page number to read2923 *2924 * Returns -ENOTSUPP unconditionally.2925 */2926int nand_read_page_raw_notsupp(struct nand_chip *chip, u8 *buf,2927 int oob_required, int page)2928{2929 return -ENOTSUPP;2930}2931 2932/**2933 * nand_read_page_raw - [INTERN] read raw page data without ecc2934 * @chip: nand chip info structure2935 * @buf: buffer to store read data2936 * @oob_required: caller requires OOB data read to chip->oob_poi2937 * @page: page number to read2938 *2939 * Not for syndrome calculating ECC controllers, which use a special oob layout.2940 */2941int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,2942 int page)2943{2944 struct mtd_info *mtd = nand_to_mtd(chip);2945 int ret;2946 2947 ret = nand_read_page_op(chip, page, 0, buf, mtd->writesize);2948 if (ret)2949 return ret;2950 2951 if (oob_required) {2952 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize,2953 false, false);2954 if (ret)2955 return ret;2956 }2957 2958 return 0;2959}2960EXPORT_SYMBOL(nand_read_page_raw);2961 2962/**2963 * nand_monolithic_read_page_raw - Monolithic page read in raw mode2964 * @chip: NAND chip info structure2965 * @buf: buffer to store read data2966 * @oob_required: caller requires OOB data read to chip->oob_poi2967 * @page: page number to read2968 *2969 * This is a raw page read, ie. without any error detection/correction.2970 * Monolithic means we are requesting all the relevant data (main plus2971 * eventually OOB) to be loaded in the NAND cache and sent over the2972 * bus (from the NAND chip to the NAND controller) in a single2973 * operation. This is an alternative to nand_read_page_raw(), which2974 * first reads the main data, and if the OOB data is requested too,2975 * then reads more data on the bus.2976 */2977int nand_monolithic_read_page_raw(struct nand_chip *chip, u8 *buf,2978 int oob_required, int page)2979{2980 struct mtd_info *mtd = nand_to_mtd(chip);2981 unsigned int size = mtd->writesize;2982 u8 *read_buf = buf;2983 int ret;2984 2985 if (oob_required) {2986 size += mtd->oobsize;2987 2988 if (buf != chip->data_buf)2989 read_buf = nand_get_data_buf(chip);2990 }2991 2992 ret = nand_read_page_op(chip, page, 0, read_buf, size);2993 if (ret)2994 return ret;2995 2996 if (buf != chip->data_buf)2997 memcpy(buf, read_buf, mtd->writesize);2998 2999 return 0;3000}3001EXPORT_SYMBOL(nand_monolithic_read_page_raw);3002 3003/**3004 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc3005 * @chip: nand chip info structure3006 * @buf: buffer to store read data3007 * @oob_required: caller requires OOB data read to chip->oob_poi3008 * @page: page number to read3009 *3010 * We need a special oob layout and handling even when OOB isn't used.3011 */3012static int nand_read_page_raw_syndrome(struct nand_chip *chip, uint8_t *buf,3013 int oob_required, int page)3014{3015 struct mtd_info *mtd = nand_to_mtd(chip);3016 int eccsize = chip->ecc.size;3017 int eccbytes = chip->ecc.bytes;3018 uint8_t *oob = chip->oob_poi;3019 int steps, size, ret;3020 3021 ret = nand_read_page_op(chip, page, 0, NULL, 0);3022 if (ret)3023 return ret;3024 3025 for (steps = chip->ecc.steps; steps > 0; steps--) {3026 ret = nand_read_data_op(chip, buf, eccsize, false, false);3027 if (ret)3028 return ret;3029 3030 buf += eccsize;3031 3032 if (chip->ecc.prepad) {3033 ret = nand_read_data_op(chip, oob, chip->ecc.prepad,3034 false, false);3035 if (ret)3036 return ret;3037 3038 oob += chip->ecc.prepad;3039 }3040 3041 ret = nand_read_data_op(chip, oob, eccbytes, false, false);3042 if (ret)3043 return ret;3044 3045 oob += eccbytes;3046 3047 if (chip->ecc.postpad) {3048 ret = nand_read_data_op(chip, oob, chip->ecc.postpad,3049 false, false);3050 if (ret)3051 return ret;3052 3053 oob += chip->ecc.postpad;3054 }3055 }3056 3057 size = mtd->oobsize - (oob - chip->oob_poi);3058 if (size) {3059 ret = nand_read_data_op(chip, oob, size, false, false);3060 if (ret)3061 return ret;3062 }3063 3064 return 0;3065}3066 3067/**3068 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function3069 * @chip: nand chip info structure3070 * @buf: buffer to store read data3071 * @oob_required: caller requires OOB data read to chip->oob_poi3072 * @page: page number to read3073 */3074static int nand_read_page_swecc(struct nand_chip *chip, uint8_t *buf,3075 int oob_required, int page)3076{3077 struct mtd_info *mtd = nand_to_mtd(chip);3078 int i, eccsize = chip->ecc.size, ret;3079 int eccbytes = chip->ecc.bytes;3080 int eccsteps = chip->ecc.steps;3081 uint8_t *p = buf;3082 uint8_t *ecc_calc = chip->ecc.calc_buf;3083 uint8_t *ecc_code = chip->ecc.code_buf;3084 unsigned int max_bitflips = 0;3085 3086 chip->ecc.read_page_raw(chip, buf, 1, page);3087 3088 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)3089 chip->ecc.calculate(chip, p, &ecc_calc[i]);3090 3091 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,3092 chip->ecc.total);3093 if (ret)3094 return ret;3095 3096 eccsteps = chip->ecc.steps;3097 p = buf;3098 3099 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {3100 int stat;3101 3102 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);3103 if (stat < 0) {3104 mtd->ecc_stats.failed++;3105 } else {3106 mtd->ecc_stats.corrected += stat;3107 max_bitflips = max_t(unsigned int, max_bitflips, stat);3108 }3109 }3110 return max_bitflips;3111}3112 3113/**3114 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function3115 * @chip: nand chip info structure3116 * @data_offs: offset of requested data within the page3117 * @readlen: data length3118 * @bufpoi: buffer to store read data3119 * @page: page number to read3120 */3121static int nand_read_subpage(struct nand_chip *chip, uint32_t data_offs,3122 uint32_t readlen, uint8_t *bufpoi, int page)3123{3124 struct mtd_info *mtd = nand_to_mtd(chip);3125 int start_step, end_step, num_steps, ret;3126 uint8_t *p;3127 int data_col_addr, i, gaps = 0;3128 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;3129 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;3130 int index, section = 0;3131 unsigned int max_bitflips = 0;3132 struct mtd_oob_region oobregion = { };3133 3134 /* Column address within the page aligned to ECC size (256bytes) */3135 start_step = data_offs / chip->ecc.size;3136 end_step = (data_offs + readlen - 1) / chip->ecc.size;3137 num_steps = end_step - start_step + 1;3138 index = start_step * chip->ecc.bytes;3139 3140 /* Data size aligned to ECC ecc.size */3141 datafrag_len = num_steps * chip->ecc.size;3142 eccfrag_len = num_steps * chip->ecc.bytes;3143 3144 data_col_addr = start_step * chip->ecc.size;3145 /* If we read not a page aligned data */3146 p = bufpoi + data_col_addr;3147 ret = nand_read_page_op(chip, page, data_col_addr, p, datafrag_len);3148 if (ret)3149 return ret;3150 3151 /* Calculate ECC */3152 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)3153 chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]);3154 3155 /*3156 * The performance is faster if we position offsets according to3157 * ecc.pos. Let's make sure that there are no gaps in ECC positions.3158 */3159 ret = mtd_ooblayout_find_eccregion(mtd, index, §ion, &oobregion);3160 if (ret)3161 return ret;3162 3163 if (oobregion.length < eccfrag_len)3164 gaps = 1;3165 3166 if (gaps) {3167 ret = nand_change_read_column_op(chip, mtd->writesize,3168 chip->oob_poi, mtd->oobsize,3169 false);3170 if (ret)3171 return ret;3172 } else {3173 /*3174 * Send the command to read the particular ECC bytes take care3175 * about buswidth alignment in read_buf.3176 */3177 aligned_pos = oobregion.offset & ~(busw - 1);3178 aligned_len = eccfrag_len;3179 if (oobregion.offset & (busw - 1))3180 aligned_len++;3181 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) &3182 (busw - 1))3183 aligned_len++;3184 3185 ret = nand_change_read_column_op(chip,3186 mtd->writesize + aligned_pos,3187 &chip->oob_poi[aligned_pos],3188 aligned_len, false);3189 if (ret)3190 return ret;3191 }3192 3193 ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf,3194 chip->oob_poi, index, eccfrag_len);3195 if (ret)3196 return ret;3197 3198 p = bufpoi + data_col_addr;3199 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {3200 int stat;3201 3202 stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i],3203 &chip->ecc.calc_buf[i]);3204 if (stat == -EBADMSG &&3205 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {3206 /* check for empty pages with bitflips */3207 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,3208 &chip->ecc.code_buf[i],3209 chip->ecc.bytes,3210 NULL, 0,3211 chip->ecc.strength);3212 }3213 3214 if (stat < 0) {3215 mtd->ecc_stats.failed++;3216 } else {3217 mtd->ecc_stats.corrected += stat;3218 max_bitflips = max_t(unsigned int, max_bitflips, stat);3219 }3220 }3221 return max_bitflips;3222}3223 3224/**3225 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function3226 * @chip: nand chip info structure3227 * @buf: buffer to store read data3228 * @oob_required: caller requires OOB data read to chip->oob_poi3229 * @page: page number to read3230 *3231 * Not for syndrome calculating ECC controllers which need a special oob layout.3232 */3233static int nand_read_page_hwecc(struct nand_chip *chip, uint8_t *buf,3234 int oob_required, int page)3235{3236 struct mtd_info *mtd = nand_to_mtd(chip);3237 int i, eccsize = chip->ecc.size, ret;3238 int eccbytes = chip->ecc.bytes;3239 int eccsteps = chip->ecc.steps;3240 uint8_t *p = buf;3241 uint8_t *ecc_calc = chip->ecc.calc_buf;3242 uint8_t *ecc_code = chip->ecc.code_buf;3243 unsigned int max_bitflips = 0;3244 3245 ret = nand_read_page_op(chip, page, 0, NULL, 0);3246 if (ret)3247 return ret;3248 3249 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {3250 chip->ecc.hwctl(chip, NAND_ECC_READ);3251 3252 ret = nand_read_data_op(chip, p, eccsize, false, false);3253 if (ret)3254 return ret;3255 3256 chip->ecc.calculate(chip, p, &ecc_calc[i]);3257 }3258 3259 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false,3260 false);3261 if (ret)3262 return ret;3263 3264 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,3265 chip->ecc.total);3266 if (ret)3267 return ret;3268 3269 eccsteps = chip->ecc.steps;3270 p = buf;3271 3272 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {3273 int stat;3274 3275 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]);3276 if (stat == -EBADMSG &&3277 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {3278 /* check for empty pages with bitflips */3279 stat = nand_check_erased_ecc_chunk(p, eccsize,3280 &ecc_code[i], eccbytes,3281 NULL, 0,3282 chip->ecc.strength);3283 }3284 3285 if (stat < 0) {3286 mtd->ecc_stats.failed++;3287 } else {3288 mtd->ecc_stats.corrected += stat;3289 max_bitflips = max_t(unsigned int, max_bitflips, stat);3290 }3291 }3292 return max_bitflips;3293}3294 3295/**3296 * nand_read_page_hwecc_oob_first - Hardware ECC page read with ECC3297 * data read from OOB area3298 * @chip: nand chip info structure3299 * @buf: buffer to store read data3300 * @oob_required: caller requires OOB data read to chip->oob_poi3301 * @page: page number to read3302 *3303 * Hardware ECC for large page chips, which requires the ECC data to be3304 * extracted from the OOB before the actual data is read.3305 */3306int nand_read_page_hwecc_oob_first(struct nand_chip *chip, uint8_t *buf,3307 int oob_required, int page)3308{3309 struct mtd_info *mtd = nand_to_mtd(chip);3310 int i, eccsize = chip->ecc.size, ret;3311 int eccbytes = chip->ecc.bytes;3312 int eccsteps = chip->ecc.steps;3313 uint8_t *p = buf;3314 uint8_t *ecc_code = chip->ecc.code_buf;3315 unsigned int max_bitflips = 0;3316 3317 /* Read the OOB area first */3318 ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);3319 if (ret)3320 return ret;3321 3322 /* Move read cursor to start of page */3323 ret = nand_change_read_column_op(chip, 0, NULL, 0, false);3324 if (ret)3325 return ret;3326 3327 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,3328 chip->ecc.total);3329 if (ret)3330 return ret;3331 3332 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {3333 int stat;3334 3335 chip->ecc.hwctl(chip, NAND_ECC_READ);3336 3337 ret = nand_read_data_op(chip, p, eccsize, false, false);3338 if (ret)3339 return ret;3340 3341 stat = chip->ecc.correct(chip, p, &ecc_code[i], NULL);3342 if (stat == -EBADMSG &&3343 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {3344 /* check for empty pages with bitflips */3345 stat = nand_check_erased_ecc_chunk(p, eccsize,3346 &ecc_code[i],3347 eccbytes, NULL, 0,3348 chip->ecc.strength);3349 }3350 3351 if (stat < 0) {3352 mtd->ecc_stats.failed++;3353 } else {3354 mtd->ecc_stats.corrected += stat;3355 max_bitflips = max_t(unsigned int, max_bitflips, stat);3356 }3357 }3358 return max_bitflips;3359}3360EXPORT_SYMBOL_GPL(nand_read_page_hwecc_oob_first);3361 3362/**3363 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read3364 * @chip: nand chip info structure3365 * @buf: buffer to store read data3366 * @oob_required: caller requires OOB data read to chip->oob_poi3367 * @page: page number to read3368 *3369 * The hw generator calculates the error syndrome automatically. Therefore we3370 * need a special oob layout and handling.3371 */3372static int nand_read_page_syndrome(struct nand_chip *chip, uint8_t *buf,3373 int oob_required, int page)3374{3375 struct mtd_info *mtd = nand_to_mtd(chip);3376 int ret, i, eccsize = chip->ecc.size;3377 int eccbytes = chip->ecc.bytes;3378 int eccsteps = chip->ecc.steps;3379 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;3380 uint8_t *p = buf;3381 uint8_t *oob = chip->oob_poi;3382 unsigned int max_bitflips = 0;3383 3384 ret = nand_read_page_op(chip, page, 0, NULL, 0);3385 if (ret)3386 return ret;3387 3388 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {3389 int stat;3390 3391 chip->ecc.hwctl(chip, NAND_ECC_READ);3392 3393 ret = nand_read_data_op(chip, p, eccsize, false, false);3394 if (ret)3395 return ret;3396 3397 if (chip->ecc.prepad) {3398 ret = nand_read_data_op(chip, oob, chip->ecc.prepad,3399 false, false);3400 if (ret)3401 return ret;3402 3403 oob += chip->ecc.prepad;3404 }3405 3406 chip->ecc.hwctl(chip, NAND_ECC_READSYN);3407 3408 ret = nand_read_data_op(chip, oob, eccbytes, false, false);3409 if (ret)3410 return ret;3411 3412 stat = chip->ecc.correct(chip, p, oob, NULL);3413 3414 oob += eccbytes;3415 3416 if (chip->ecc.postpad) {3417 ret = nand_read_data_op(chip, oob, chip->ecc.postpad,3418 false, false);3419 if (ret)3420 return ret;3421 3422 oob += chip->ecc.postpad;3423 }3424 3425 if (stat == -EBADMSG &&3426 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {3427 /* check for empty pages with bitflips */3428 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,3429 oob - eccpadbytes,3430 eccpadbytes,3431 NULL, 0,3432 chip->ecc.strength);3433 }3434 3435 if (stat < 0) {3436 mtd->ecc_stats.failed++;3437 } else {3438 mtd->ecc_stats.corrected += stat;3439 max_bitflips = max_t(unsigned int, max_bitflips, stat);3440 }3441 }3442 3443 /* Calculate remaining oob bytes */3444 i = mtd->oobsize - (oob - chip->oob_poi);3445 if (i) {3446 ret = nand_read_data_op(chip, oob, i, false, false);3447 if (ret)3448 return ret;3449 }3450 3451 return max_bitflips;3452}3453 3454/**3455 * nand_transfer_oob - [INTERN] Transfer oob to client buffer3456 * @chip: NAND chip object3457 * @oob: oob destination address3458 * @ops: oob ops structure3459 * @len: size of oob to transfer3460 */3461static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,3462 struct mtd_oob_ops *ops, size_t len)3463{3464 struct mtd_info *mtd = nand_to_mtd(chip);3465 int ret;3466 3467 switch (ops->mode) {3468 3469 case MTD_OPS_PLACE_OOB:3470 case MTD_OPS_RAW:3471 memcpy(oob, chip->oob_poi + ops->ooboffs, len);3472 return oob + len;3473 3474 case MTD_OPS_AUTO_OOB:3475 ret = mtd_ooblayout_get_databytes(mtd, oob, chip->oob_poi,3476 ops->ooboffs, len);3477 BUG_ON(ret);3478 return oob + len;3479 3480 default:3481 BUG();3482 }3483 return NULL;3484}3485 3486static void rawnand_enable_cont_reads(struct nand_chip *chip, unsigned int page,3487 u32 readlen, int col)3488{3489 struct mtd_info *mtd = nand_to_mtd(chip);3490 unsigned int first_page, last_page;3491 3492 chip->cont_read.ongoing = false;3493 3494 if (!chip->controller->supported_op.cont_read)3495 return;3496 3497 /*3498 * Don't bother making any calculations if the length is too small.3499 * Side effect: avoids possible integer underflows below.3500 */3501 if (readlen < (2 * mtd->writesize))3502 return;3503 3504 /* Derive the page where continuous read should start (the first full page read) */3505 first_page = page;3506 if (col)3507 first_page++;3508 3509 /* Derive the page where continuous read should stop (the last full page read) */3510 last_page = page + ((col + readlen) / mtd->writesize) - 1;3511 3512 /* Configure and enable continuous read when suitable */3513 if (first_page < last_page) {3514 chip->cont_read.first_page = first_page;3515 chip->cont_read.last_page = last_page;3516 chip->cont_read.ongoing = true;3517 /* May reset the ongoing flag */3518 rawnand_cap_cont_reads(chip);3519 }3520}3521 3522static void rawnand_cont_read_skip_first_page(struct nand_chip *chip, unsigned int page)3523{3524 if (!chip->cont_read.ongoing || page != chip->cont_read.first_page)3525 return;3526 3527 chip->cont_read.first_page++;3528 rawnand_cap_cont_reads(chip);3529}3530 3531/**3532 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode3533 * @chip: NAND chip object3534 * @retry_mode: the retry mode to use3535 *3536 * Some vendors supply a special command to shift the Vt threshold, to be used3537 * when there are too many bitflips in a page (i.e., ECC error). After setting3538 * a new threshold, the host should retry reading the page.3539 */3540static int nand_setup_read_retry(struct nand_chip *chip, int retry_mode)3541{3542 pr_debug("setting READ RETRY mode %d\n", retry_mode);3543 3544 if (retry_mode >= chip->read_retries)3545 return -EINVAL;3546 3547 if (!chip->ops.setup_read_retry)3548 return -EOPNOTSUPP;3549 3550 return chip->ops.setup_read_retry(chip, retry_mode);3551}3552 3553static void nand_wait_readrdy(struct nand_chip *chip)3554{3555 const struct nand_interface_config *conf;3556 3557 if (!(chip->options & NAND_NEED_READRDY))3558 return;3559 3560 conf = nand_get_interface_config(chip);3561 WARN_ON(nand_wait_rdy_op(chip, NAND_COMMON_TIMING_MS(conf, tR_max), 0));3562}3563 3564/**3565 * nand_do_read_ops - [INTERN] Read data with ECC3566 * @chip: NAND chip object3567 * @from: offset to read from3568 * @ops: oob ops structure3569 *3570 * Internal function. Called with chip held.3571 */3572static int nand_do_read_ops(struct nand_chip *chip, loff_t from,3573 struct mtd_oob_ops *ops)3574{3575 int chipnr, page, realpage, col, bytes, aligned, oob_required;3576 struct mtd_info *mtd = nand_to_mtd(chip);3577 int ret = 0;3578 uint32_t readlen = ops->len;3579 uint32_t oobreadlen = ops->ooblen;3580 uint32_t max_oobsize = mtd_oobavail(mtd, ops);3581 3582 uint8_t *bufpoi, *oob, *buf;3583 int use_bounce_buf;3584 unsigned int max_bitflips = 0;3585 int retry_mode = 0;3586 bool ecc_fail = false;3587 3588 /* Check if the region is secured */3589 if (nand_region_is_secured(chip, from, readlen))3590 return -EIO;3591 3592 chipnr = (int)(from >> chip->chip_shift);3593 nand_select_target(chip, chipnr);3594 3595 realpage = (int)(from >> chip->page_shift);3596 page = realpage & chip->pagemask;3597 3598 col = (int)(from & (mtd->writesize - 1));3599 3600 buf = ops->datbuf;3601 oob = ops->oobbuf;3602 oob_required = oob ? 1 : 0;3603 3604 if (likely(ops->mode != MTD_OPS_RAW))3605 rawnand_enable_cont_reads(chip, page, readlen, col);3606 3607 while (1) {3608 struct mtd_ecc_stats ecc_stats = mtd->ecc_stats;3609 3610 bytes = min(mtd->writesize - col, readlen);3611 aligned = (bytes == mtd->writesize);3612 3613 if (!aligned)3614 use_bounce_buf = 1;3615 else if (chip->options & NAND_USES_DMA)3616 use_bounce_buf = !virt_addr_valid(buf) ||3617 !IS_ALIGNED((unsigned long)buf,3618 chip->buf_align);3619 else3620 use_bounce_buf = 0;3621 3622 /* Is the current page in the buffer? */3623 if (realpage != chip->pagecache.page || oob) {3624 bufpoi = use_bounce_buf ? chip->data_buf : buf;3625 3626 if (use_bounce_buf && aligned)3627 pr_debug("%s: using read bounce buffer for buf@%p\n",3628 __func__, buf);3629 3630read_retry:3631 /*3632 * Now read the page into the buffer. Absent an error,3633 * the read methods return max bitflips per ecc step.3634 */3635 if (unlikely(ops->mode == MTD_OPS_RAW))3636 ret = chip->ecc.read_page_raw(chip, bufpoi,3637 oob_required,3638 page);3639 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&3640 !oob)3641 ret = chip->ecc.read_subpage(chip, col, bytes,3642 bufpoi, page);3643 else3644 ret = chip->ecc.read_page(chip, bufpoi,3645 oob_required, page);3646 if (ret < 0) {3647 if (use_bounce_buf)3648 /* Invalidate page cache */3649 chip->pagecache.page = -1;3650 break;3651 }3652 3653 /*3654 * Copy back the data in the initial buffer when reading3655 * partial pages or when a bounce buffer is required.3656 */3657 if (use_bounce_buf) {3658 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&3659 !(mtd->ecc_stats.failed - ecc_stats.failed) &&3660 (ops->mode != MTD_OPS_RAW)) {3661 chip->pagecache.page = realpage;3662 chip->pagecache.bitflips = ret;3663 } else {3664 /* Invalidate page cache */3665 chip->pagecache.page = -1;3666 }3667 memcpy(buf, bufpoi + col, bytes);3668 }3669 3670 if (unlikely(oob)) {3671 int toread = min(oobreadlen, max_oobsize);3672 3673 if (toread) {3674 oob = nand_transfer_oob(chip, oob, ops,3675 toread);3676 oobreadlen -= toread;3677 }3678 }3679 3680 nand_wait_readrdy(chip);3681 3682 if (mtd->ecc_stats.failed - ecc_stats.failed) {3683 if (retry_mode + 1 < chip->read_retries) {3684 retry_mode++;3685 ret = nand_setup_read_retry(chip,3686 retry_mode);3687 if (ret < 0)3688 break;3689 3690 /* Reset ecc_stats; retry */3691 mtd->ecc_stats = ecc_stats;3692 goto read_retry;3693 } else {3694 /* No more retry modes; real failure */3695 ecc_fail = true;3696 }3697 }3698 3699 buf += bytes;3700 max_bitflips = max_t(unsigned int, max_bitflips, ret);3701 } else {3702 memcpy(buf, chip->data_buf + col, bytes);3703 buf += bytes;3704 max_bitflips = max_t(unsigned int, max_bitflips,3705 chip->pagecache.bitflips);3706 3707 rawnand_cont_read_skip_first_page(chip, page);3708 }3709 3710 readlen -= bytes;3711 3712 /* Reset to retry mode 0 */3713 if (retry_mode) {3714 ret = nand_setup_read_retry(chip, 0);3715 if (ret < 0)3716 break;3717 retry_mode = 0;3718 }3719 3720 if (!readlen)3721 break;3722 3723 /* For subsequent reads align to page boundary */3724 col = 0;3725 /* Increment page address */3726 realpage++;3727 3728 page = realpage & chip->pagemask;3729 /* Check, if we cross a chip boundary */3730 if (!page) {3731 chipnr++;3732 nand_deselect_target(chip);3733 nand_select_target(chip, chipnr);3734 }3735 }3736 nand_deselect_target(chip);3737 3738 if (WARN_ON_ONCE(chip->cont_read.ongoing))3739 chip->cont_read.ongoing = false;3740 3741 ops->retlen = ops->len - (size_t) readlen;3742 if (oob)3743 ops->oobretlen = ops->ooblen - oobreadlen;3744 3745 if (ret < 0)3746 return ret;3747 3748 if (ecc_fail)3749 return -EBADMSG;3750 3751 return max_bitflips;3752}3753 3754/**3755 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function3756 * @chip: nand chip info structure3757 * @page: page number to read3758 */3759int nand_read_oob_std(struct nand_chip *chip, int page)3760{3761 struct mtd_info *mtd = nand_to_mtd(chip);3762 3763 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);3764}3765EXPORT_SYMBOL(nand_read_oob_std);3766 3767/**3768 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC3769 * with syndromes3770 * @chip: nand chip info structure3771 * @page: page number to read3772 */3773static int nand_read_oob_syndrome(struct nand_chip *chip, int page)3774{3775 struct mtd_info *mtd = nand_to_mtd(chip);3776 int length = mtd->oobsize;3777 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;3778 int eccsize = chip->ecc.size;3779 uint8_t *bufpoi = chip->oob_poi;3780 int i, toread, sndrnd = 0, pos, ret;3781 3782 ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0);3783 if (ret)3784 return ret;3785 3786 for (i = 0; i < chip->ecc.steps; i++) {3787 if (sndrnd) {3788 int ret;3789 3790 pos = eccsize + i * (eccsize + chunk);3791 if (mtd->writesize > 512)3792 ret = nand_change_read_column_op(chip, pos,3793 NULL, 0,3794 false);3795 else3796 ret = nand_read_page_op(chip, page, pos, NULL,3797 0);3798 3799 if (ret)3800 return ret;3801 } else3802 sndrnd = 1;3803 toread = min_t(int, length, chunk);3804 3805 ret = nand_read_data_op(chip, bufpoi, toread, false, false);3806 if (ret)3807 return ret;3808 3809 bufpoi += toread;3810 length -= toread;3811 }3812 if (length > 0) {3813 ret = nand_read_data_op(chip, bufpoi, length, false, false);3814 if (ret)3815 return ret;3816 }3817 3818 return 0;3819}3820 3821/**3822 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function3823 * @chip: nand chip info structure3824 * @page: page number to write3825 */3826int nand_write_oob_std(struct nand_chip *chip, int page)3827{3828 struct mtd_info *mtd = nand_to_mtd(chip);3829 3830 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,3831 mtd->oobsize);3832}3833EXPORT_SYMBOL(nand_write_oob_std);3834 3835/**3836 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC3837 * with syndrome - only for large page flash3838 * @chip: nand chip info structure3839 * @page: page number to write3840 */3841static int nand_write_oob_syndrome(struct nand_chip *chip, int page)3842{3843 struct mtd_info *mtd = nand_to_mtd(chip);3844 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;3845 int eccsize = chip->ecc.size, length = mtd->oobsize;3846 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps;3847 const uint8_t *bufpoi = chip->oob_poi;3848 3849 /*3850 * data-ecc-data-ecc ... ecc-oob3851 * or3852 * data-pad-ecc-pad-data-pad .... ecc-pad-oob3853 */3854 if (!chip->ecc.prepad && !chip->ecc.postpad) {3855 pos = steps * (eccsize + chunk);3856 steps = 0;3857 } else3858 pos = eccsize;3859 3860 ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0);3861 if (ret)3862 return ret;3863 3864 for (i = 0; i < steps; i++) {3865 if (sndcmd) {3866 if (mtd->writesize <= 512) {3867 uint32_t fill = 0xFFFFFFFF;3868 3869 len = eccsize;3870 while (len > 0) {3871 int num = min_t(int, len, 4);3872 3873 ret = nand_write_data_op(chip, &fill,3874 num, false);3875 if (ret)3876 return ret;3877 3878 len -= num;3879 }3880 } else {3881 pos = eccsize + i * (eccsize + chunk);3882 ret = nand_change_write_column_op(chip, pos,3883 NULL, 0,3884 false);3885 if (ret)3886 return ret;3887 }3888 } else3889 sndcmd = 1;3890 len = min_t(int, length, chunk);3891 3892 ret = nand_write_data_op(chip, bufpoi, len, false);3893 if (ret)3894 return ret;3895 3896 bufpoi += len;3897 length -= len;3898 }3899 if (length > 0) {3900 ret = nand_write_data_op(chip, bufpoi, length, false);3901 if (ret)3902 return ret;3903 }3904 3905 return nand_prog_page_end_op(chip);3906}3907 3908/**3909 * nand_do_read_oob - [INTERN] NAND read out-of-band3910 * @chip: NAND chip object3911 * @from: offset to read from3912 * @ops: oob operations description structure3913 *3914 * NAND read out-of-band data from the spare area.3915 */3916static int nand_do_read_oob(struct nand_chip *chip, loff_t from,3917 struct mtd_oob_ops *ops)3918{3919 struct mtd_info *mtd = nand_to_mtd(chip);3920 unsigned int max_bitflips = 0;3921 int page, realpage, chipnr;3922 struct mtd_ecc_stats stats;3923 int readlen = ops->ooblen;3924 int len;3925 uint8_t *buf = ops->oobbuf;3926 int ret = 0;3927 3928 pr_debug("%s: from = 0x%08Lx, len = %i\n",3929 __func__, (unsigned long long)from, readlen);3930 3931 /* Check if the region is secured */3932 if (nand_region_is_secured(chip, from, readlen))3933 return -EIO;3934 3935 stats = mtd->ecc_stats;3936 3937 len = mtd_oobavail(mtd, ops);3938 3939 chipnr = (int)(from >> chip->chip_shift);3940 nand_select_target(chip, chipnr);3941 3942 /* Shift to get page */3943 realpage = (int)(from >> chip->page_shift);3944 page = realpage & chip->pagemask;3945 3946 while (1) {3947 if (ops->mode == MTD_OPS_RAW)3948 ret = chip->ecc.read_oob_raw(chip, page);3949 else3950 ret = chip->ecc.read_oob(chip, page);3951 3952 if (ret < 0)3953 break;3954 3955 len = min(len, readlen);3956 buf = nand_transfer_oob(chip, buf, ops, len);3957 3958 nand_wait_readrdy(chip);3959 3960 max_bitflips = max_t(unsigned int, max_bitflips, ret);3961 3962 readlen -= len;3963 if (!readlen)3964 break;3965 3966 /* Increment page address */3967 realpage++;3968 3969 page = realpage & chip->pagemask;3970 /* Check, if we cross a chip boundary */3971 if (!page) {3972 chipnr++;3973 nand_deselect_target(chip);3974 nand_select_target(chip, chipnr);3975 }3976 }3977 nand_deselect_target(chip);3978 3979 ops->oobretlen = ops->ooblen - readlen;3980 3981 if (ret < 0)3982 return ret;3983 3984 if (mtd->ecc_stats.failed - stats.failed)3985 return -EBADMSG;3986 3987 return max_bitflips;3988}3989 3990/**3991 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band3992 * @mtd: MTD device structure3993 * @from: offset to read from3994 * @ops: oob operation description structure3995 *3996 * NAND read data and/or out-of-band data.3997 */3998static int nand_read_oob(struct mtd_info *mtd, loff_t from,3999 struct mtd_oob_ops *ops)4000{4001 struct nand_chip *chip = mtd_to_nand(mtd);4002 struct mtd_ecc_stats old_stats;4003 int ret;4004 4005 ops->retlen = 0;4006 4007 if (ops->mode != MTD_OPS_PLACE_OOB &&4008 ops->mode != MTD_OPS_AUTO_OOB &&4009 ops->mode != MTD_OPS_RAW)4010 return -ENOTSUPP;4011 4012 nand_get_device(chip);4013 4014 old_stats = mtd->ecc_stats;4015 4016 if (!ops->datbuf)4017 ret = nand_do_read_oob(chip, from, ops);4018 else4019 ret = nand_do_read_ops(chip, from, ops);4020 4021 if (ops->stats) {4022 ops->stats->uncorrectable_errors +=4023 mtd->ecc_stats.failed - old_stats.failed;4024 ops->stats->corrected_bitflips +=4025 mtd->ecc_stats.corrected - old_stats.corrected;4026 }4027 4028 nand_release_device(chip);4029 return ret;4030}4031 4032/**4033 * nand_write_page_raw_notsupp - dummy raw page write function4034 * @chip: nand chip info structure4035 * @buf: data buffer4036 * @oob_required: must write chip->oob_poi to OOB4037 * @page: page number to write4038 *4039 * Returns -ENOTSUPP unconditionally.4040 */4041int nand_write_page_raw_notsupp(struct nand_chip *chip, const u8 *buf,4042 int oob_required, int page)4043{4044 return -ENOTSUPP;4045}4046 4047/**4048 * nand_write_page_raw - [INTERN] raw page write function4049 * @chip: nand chip info structure4050 * @buf: data buffer4051 * @oob_required: must write chip->oob_poi to OOB4052 * @page: page number to write4053 *4054 * Not for syndrome calculating ECC controllers, which use a special oob layout.4055 */4056int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,4057 int oob_required, int page)4058{4059 struct mtd_info *mtd = nand_to_mtd(chip);4060 int ret;4061 4062 ret = nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);4063 if (ret)4064 return ret;4065 4066 if (oob_required) {4067 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize,4068 false);4069 if (ret)4070 return ret;4071 }4072 4073 return nand_prog_page_end_op(chip);4074}4075EXPORT_SYMBOL(nand_write_page_raw);4076 4077/**4078 * nand_monolithic_write_page_raw - Monolithic page write in raw mode4079 * @chip: NAND chip info structure4080 * @buf: data buffer to write4081 * @oob_required: must write chip->oob_poi to OOB4082 * @page: page number to write4083 *4084 * This is a raw page write, ie. without any error detection/correction.4085 * Monolithic means we are requesting all the relevant data (main plus4086 * eventually OOB) to be sent over the bus and effectively programmed4087 * into the NAND chip arrays in a single operation. This is an4088 * alternative to nand_write_page_raw(), which first sends the main4089 * data, then eventually send the OOB data by latching more data4090 * cycles on the NAND bus, and finally sends the program command to4091 * synchronyze the NAND chip cache.4092 */4093int nand_monolithic_write_page_raw(struct nand_chip *chip, const u8 *buf,4094 int oob_required, int page)4095{4096 struct mtd_info *mtd = nand_to_mtd(chip);4097 unsigned int size = mtd->writesize;4098 u8 *write_buf = (u8 *)buf;4099 4100 if (oob_required) {4101 size += mtd->oobsize;4102 4103 if (buf != chip->data_buf) {4104 write_buf = nand_get_data_buf(chip);4105 memcpy(write_buf, buf, mtd->writesize);4106 }4107 }4108 4109 return nand_prog_page_op(chip, page, 0, write_buf, size);4110}4111EXPORT_SYMBOL(nand_monolithic_write_page_raw);4112 4113/**4114 * nand_write_page_raw_syndrome - [INTERN] raw page write function4115 * @chip: nand chip info structure4116 * @buf: data buffer4117 * @oob_required: must write chip->oob_poi to OOB4118 * @page: page number to write4119 *4120 * We need a special oob layout and handling even when ECC isn't checked.4121 */4122static int nand_write_page_raw_syndrome(struct nand_chip *chip,4123 const uint8_t *buf, int oob_required,4124 int page)4125{4126 struct mtd_info *mtd = nand_to_mtd(chip);4127 int eccsize = chip->ecc.size;4128 int eccbytes = chip->ecc.bytes;4129 uint8_t *oob = chip->oob_poi;4130 int steps, size, ret;4131 4132 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);4133 if (ret)4134 return ret;4135 4136 for (steps = chip->ecc.steps; steps > 0; steps--) {4137 ret = nand_write_data_op(chip, buf, eccsize, false);4138 if (ret)4139 return ret;4140 4141 buf += eccsize;4142 4143 if (chip->ecc.prepad) {4144 ret = nand_write_data_op(chip, oob, chip->ecc.prepad,4145 false);4146 if (ret)4147 return ret;4148 4149 oob += chip->ecc.prepad;4150 }4151 4152 ret = nand_write_data_op(chip, oob, eccbytes, false);4153 if (ret)4154 return ret;4155 4156 oob += eccbytes;4157 4158 if (chip->ecc.postpad) {4159 ret = nand_write_data_op(chip, oob, chip->ecc.postpad,4160 false);4161 if (ret)4162 return ret;4163 4164 oob += chip->ecc.postpad;4165 }4166 }4167 4168 size = mtd->oobsize - (oob - chip->oob_poi);4169 if (size) {4170 ret = nand_write_data_op(chip, oob, size, false);4171 if (ret)4172 return ret;4173 }4174 4175 return nand_prog_page_end_op(chip);4176}4177/**4178 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function4179 * @chip: nand chip info structure4180 * @buf: data buffer4181 * @oob_required: must write chip->oob_poi to OOB4182 * @page: page number to write4183 */4184static int nand_write_page_swecc(struct nand_chip *chip, const uint8_t *buf,4185 int oob_required, int page)4186{4187 struct mtd_info *mtd = nand_to_mtd(chip);4188 int i, eccsize = chip->ecc.size, ret;4189 int eccbytes = chip->ecc.bytes;4190 int eccsteps = chip->ecc.steps;4191 uint8_t *ecc_calc = chip->ecc.calc_buf;4192 const uint8_t *p = buf;4193 4194 /* Software ECC calculation */4195 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)4196 chip->ecc.calculate(chip, p, &ecc_calc[i]);4197 4198 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,4199 chip->ecc.total);4200 if (ret)4201 return ret;4202 4203 return chip->ecc.write_page_raw(chip, buf, 1, page);4204}4205 4206/**4207 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function4208 * @chip: nand chip info structure4209 * @buf: data buffer4210 * @oob_required: must write chip->oob_poi to OOB4211 * @page: page number to write4212 */4213static int nand_write_page_hwecc(struct nand_chip *chip, const uint8_t *buf,4214 int oob_required, int page)4215{4216 struct mtd_info *mtd = nand_to_mtd(chip);4217 int i, eccsize = chip->ecc.size, ret;4218 int eccbytes = chip->ecc.bytes;4219 int eccsteps = chip->ecc.steps;4220 uint8_t *ecc_calc = chip->ecc.calc_buf;4221 const uint8_t *p = buf;4222 4223 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);4224 if (ret)4225 return ret;4226 4227 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {4228 chip->ecc.hwctl(chip, NAND_ECC_WRITE);4229 4230 ret = nand_write_data_op(chip, p, eccsize, false);4231 if (ret)4232 return ret;4233 4234 chip->ecc.calculate(chip, p, &ecc_calc[i]);4235 }4236 4237 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,4238 chip->ecc.total);4239 if (ret)4240 return ret;4241 4242 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);4243 if (ret)4244 return ret;4245 4246 return nand_prog_page_end_op(chip);4247}4248 4249 4250/**4251 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write4252 * @chip: nand chip info structure4253 * @offset: column address of subpage within the page4254 * @data_len: data length4255 * @buf: data buffer4256 * @oob_required: must write chip->oob_poi to OOB4257 * @page: page number to write4258 */4259static int nand_write_subpage_hwecc(struct nand_chip *chip, uint32_t offset,4260 uint32_t data_len, const uint8_t *buf,4261 int oob_required, int page)4262{4263 struct mtd_info *mtd = nand_to_mtd(chip);4264 uint8_t *oob_buf = chip->oob_poi;4265 uint8_t *ecc_calc = chip->ecc.calc_buf;4266 int ecc_size = chip->ecc.size;4267 int ecc_bytes = chip->ecc.bytes;4268 int ecc_steps = chip->ecc.steps;4269 uint32_t start_step = offset / ecc_size;4270 uint32_t end_step = (offset + data_len - 1) / ecc_size;4271 int oob_bytes = mtd->oobsize / ecc_steps;4272 int step, ret;4273 4274 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);4275 if (ret)4276 return ret;4277 4278 for (step = 0; step < ecc_steps; step++) {4279 /* configure controller for WRITE access */4280 chip->ecc.hwctl(chip, NAND_ECC_WRITE);4281 4282 /* write data (untouched subpages already masked by 0xFF) */4283 ret = nand_write_data_op(chip, buf, ecc_size, false);4284 if (ret)4285 return ret;4286 4287 /* mask ECC of un-touched subpages by padding 0xFF */4288 if ((step < start_step) || (step > end_step))4289 memset(ecc_calc, 0xff, ecc_bytes);4290 else4291 chip->ecc.calculate(chip, buf, ecc_calc);4292 4293 /* mask OOB of un-touched subpages by padding 0xFF */4294 /* if oob_required, preserve OOB metadata of written subpage */4295 if (!oob_required || (step < start_step) || (step > end_step))4296 memset(oob_buf, 0xff, oob_bytes);4297 4298 buf += ecc_size;4299 ecc_calc += ecc_bytes;4300 oob_buf += oob_bytes;4301 }4302 4303 /* copy calculated ECC for whole page to chip->buffer->oob */4304 /* this include masked-value(0xFF) for unwritten subpages */4305 ecc_calc = chip->ecc.calc_buf;4306 ret = mtd_ooblayout_set_eccbytes(mtd, ecc_calc, chip->oob_poi, 0,4307 chip->ecc.total);4308 if (ret)4309 return ret;4310 4311 /* write OOB buffer to NAND device */4312 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);4313 if (ret)4314 return ret;4315 4316 return nand_prog_page_end_op(chip);4317}4318 4319 4320/**4321 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write4322 * @chip: nand chip info structure4323 * @buf: data buffer4324 * @oob_required: must write chip->oob_poi to OOB4325 * @page: page number to write4326 *4327 * The hw generator calculates the error syndrome automatically. Therefore we4328 * need a special oob layout and handling.4329 */4330static int nand_write_page_syndrome(struct nand_chip *chip, const uint8_t *buf,4331 int oob_required, int page)4332{4333 struct mtd_info *mtd = nand_to_mtd(chip);4334 int i, eccsize = chip->ecc.size;4335 int eccbytes = chip->ecc.bytes;4336 int eccsteps = chip->ecc.steps;4337 const uint8_t *p = buf;4338 uint8_t *oob = chip->oob_poi;4339 int ret;4340 4341 ret = nand_prog_page_begin_op(chip, page, 0, NULL, 0);4342 if (ret)4343 return ret;4344 4345 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {4346 chip->ecc.hwctl(chip, NAND_ECC_WRITE);4347 4348 ret = nand_write_data_op(chip, p, eccsize, false);4349 if (ret)4350 return ret;4351 4352 if (chip->ecc.prepad) {4353 ret = nand_write_data_op(chip, oob, chip->ecc.prepad,4354 false);4355 if (ret)4356 return ret;4357 4358 oob += chip->ecc.prepad;4359 }4360 4361 chip->ecc.calculate(chip, p, oob);4362 4363 ret = nand_write_data_op(chip, oob, eccbytes, false);4364 if (ret)4365 return ret;4366 4367 oob += eccbytes;4368 4369 if (chip->ecc.postpad) {4370 ret = nand_write_data_op(chip, oob, chip->ecc.postpad,4371 false);4372 if (ret)4373 return ret;4374 4375 oob += chip->ecc.postpad;4376 }4377 }4378 4379 /* Calculate remaining oob bytes */4380 i = mtd->oobsize - (oob - chip->oob_poi);4381 if (i) {4382 ret = nand_write_data_op(chip, oob, i, false);4383 if (ret)4384 return ret;4385 }4386 4387 return nand_prog_page_end_op(chip);4388}4389 4390/**4391 * nand_write_page - write one page4392 * @chip: NAND chip descriptor4393 * @offset: address offset within the page4394 * @data_len: length of actual data to be written4395 * @buf: the data to write4396 * @oob_required: must write chip->oob_poi to OOB4397 * @page: page number to write4398 * @raw: use _raw version of write_page4399 */4400static int nand_write_page(struct nand_chip *chip, uint32_t offset,4401 int data_len, const uint8_t *buf, int oob_required,4402 int page, int raw)4403{4404 struct mtd_info *mtd = nand_to_mtd(chip);4405 int status, subpage;4406 4407 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&4408 chip->ecc.write_subpage)4409 subpage = offset || (data_len < mtd->writesize);4410 else4411 subpage = 0;4412 4413 if (unlikely(raw))4414 status = chip->ecc.write_page_raw(chip, buf, oob_required,4415 page);4416 else if (subpage)4417 status = chip->ecc.write_subpage(chip, offset, data_len, buf,4418 oob_required, page);4419 else4420 status = chip->ecc.write_page(chip, buf, oob_required, page);4421 4422 if (status < 0)4423 return status;4424 4425 return 0;4426}4427 4428#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)4429 4430/**4431 * nand_do_write_ops - [INTERN] NAND write with ECC4432 * @chip: NAND chip object4433 * @to: offset to write to4434 * @ops: oob operations description structure4435 *4436 * NAND write with ECC.4437 */4438static int nand_do_write_ops(struct nand_chip *chip, loff_t to,4439 struct mtd_oob_ops *ops)4440{4441 struct mtd_info *mtd = nand_to_mtd(chip);4442 int chipnr, realpage, page, column;4443 uint32_t writelen = ops->len;4444 4445 uint32_t oobwritelen = ops->ooblen;4446 uint32_t oobmaxlen = mtd_oobavail(mtd, ops);4447 4448 uint8_t *oob = ops->oobbuf;4449 uint8_t *buf = ops->datbuf;4450 int ret;4451 int oob_required = oob ? 1 : 0;4452 4453 ops->retlen = 0;4454 if (!writelen)4455 return 0;4456 4457 /* Reject writes, which are not page aligned */4458 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {4459 pr_notice("%s: attempt to write non page aligned data\n",4460 __func__);4461 return -EINVAL;4462 }4463 4464 /* Check if the region is secured */4465 if (nand_region_is_secured(chip, to, writelen))4466 return -EIO;4467 4468 column = to & (mtd->writesize - 1);4469 4470 chipnr = (int)(to >> chip->chip_shift);4471 nand_select_target(chip, chipnr);4472 4473 /* Check, if it is write protected */4474 if (nand_check_wp(chip)) {4475 ret = -EIO;4476 goto err_out;4477 }4478 4479 realpage = (int)(to >> chip->page_shift);4480 page = realpage & chip->pagemask;4481 4482 /* Invalidate the page cache, when we write to the cached page */4483 if (to <= ((loff_t)chip->pagecache.page << chip->page_shift) &&4484 ((loff_t)chip->pagecache.page << chip->page_shift) < (to + ops->len))4485 chip->pagecache.page = -1;4486 4487 /* Don't allow multipage oob writes with offset */4488 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {4489 ret = -EINVAL;4490 goto err_out;4491 }4492 4493 while (1) {4494 int bytes = mtd->writesize;4495 uint8_t *wbuf = buf;4496 int use_bounce_buf;4497 int part_pagewr = (column || writelen < mtd->writesize);4498 4499 if (part_pagewr)4500 use_bounce_buf = 1;4501 else if (chip->options & NAND_USES_DMA)4502 use_bounce_buf = !virt_addr_valid(buf) ||4503 !IS_ALIGNED((unsigned long)buf,4504 chip->buf_align);4505 else4506 use_bounce_buf = 0;4507 4508 /*4509 * Copy the data from the initial buffer when doing partial page4510 * writes or when a bounce buffer is required.4511 */4512 if (use_bounce_buf) {4513 pr_debug("%s: using write bounce buffer for buf@%p\n",4514 __func__, buf);4515 if (part_pagewr)4516 bytes = min_t(int, bytes - column, writelen);4517 wbuf = nand_get_data_buf(chip);4518 memset(wbuf, 0xff, mtd->writesize);4519 memcpy(&wbuf[column], buf, bytes);4520 }4521 4522 if (unlikely(oob)) {4523 size_t len = min(oobwritelen, oobmaxlen);4524 oob = nand_fill_oob(chip, oob, len, ops);4525 oobwritelen -= len;4526 } else {4527 /* We still need to erase leftover OOB data */4528 memset(chip->oob_poi, 0xff, mtd->oobsize);4529 }4530 4531 ret = nand_write_page(chip, column, bytes, wbuf,4532 oob_required, page,4533 (ops->mode == MTD_OPS_RAW));4534 if (ret)4535 break;4536 4537 writelen -= bytes;4538 if (!writelen)4539 break;4540 4541 column = 0;4542 buf += bytes;4543 realpage++;4544 4545 page = realpage & chip->pagemask;4546 /* Check, if we cross a chip boundary */4547 if (!page) {4548 chipnr++;4549 nand_deselect_target(chip);4550 nand_select_target(chip, chipnr);4551 }4552 }4553 4554 ops->retlen = ops->len - writelen;4555 if (unlikely(oob))4556 ops->oobretlen = ops->ooblen;4557 4558err_out:4559 nand_deselect_target(chip);4560 return ret;4561}4562 4563/**4564 * panic_nand_write - [MTD Interface] NAND write with ECC4565 * @mtd: MTD device structure4566 * @to: offset to write to4567 * @len: number of bytes to write4568 * @retlen: pointer to variable to store the number of written bytes4569 * @buf: the data to write4570 *4571 * NAND write with ECC. Used when performing writes in interrupt context, this4572 * may for example be called by mtdoops when writing an oops while in panic.4573 */4574static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,4575 size_t *retlen, const uint8_t *buf)4576{4577 struct nand_chip *chip = mtd_to_nand(mtd);4578 int chipnr = (int)(to >> chip->chip_shift);4579 struct mtd_oob_ops ops;4580 int ret;4581 4582 nand_select_target(chip, chipnr);4583 4584 /* Wait for the device to get ready */4585 panic_nand_wait(chip, 400);4586 4587 memset(&ops, 0, sizeof(ops));4588 ops.len = len;4589 ops.datbuf = (uint8_t *)buf;4590 ops.mode = MTD_OPS_PLACE_OOB;4591 4592 ret = nand_do_write_ops(chip, to, &ops);4593 4594 *retlen = ops.retlen;4595 return ret;4596}4597 4598/**4599 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band4600 * @mtd: MTD device structure4601 * @to: offset to write to4602 * @ops: oob operation description structure4603 */4604static int nand_write_oob(struct mtd_info *mtd, loff_t to,4605 struct mtd_oob_ops *ops)4606{4607 struct nand_chip *chip = mtd_to_nand(mtd);4608 int ret = 0;4609 4610 ops->retlen = 0;4611 4612 nand_get_device(chip);4613 4614 switch (ops->mode) {4615 case MTD_OPS_PLACE_OOB:4616 case MTD_OPS_AUTO_OOB:4617 case MTD_OPS_RAW:4618 break;4619 4620 default:4621 goto out;4622 }4623 4624 if (!ops->datbuf)4625 ret = nand_do_write_oob(chip, to, ops);4626 else4627 ret = nand_do_write_ops(chip, to, ops);4628 4629out:4630 nand_release_device(chip);4631 return ret;4632}4633 4634/**4635 * nand_erase - [MTD Interface] erase block(s)4636 * @mtd: MTD device structure4637 * @instr: erase instruction4638 *4639 * Erase one ore more blocks.4640 */4641static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)4642{4643 return nand_erase_nand(mtd_to_nand(mtd), instr, 0);4644}4645 4646/**4647 * nand_erase_nand - [INTERN] erase block(s)4648 * @chip: NAND chip object4649 * @instr: erase instruction4650 * @allowbbt: allow erasing the bbt area4651 *4652 * Erase one ore more blocks.4653 */4654int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,4655 int allowbbt)4656{4657 int page, pages_per_block, ret, chipnr;4658 loff_t len;4659 4660 pr_debug("%s: start = 0x%012llx, len = %llu\n",4661 __func__, (unsigned long long)instr->addr,4662 (unsigned long long)instr->len);4663 4664 if (check_offs_len(chip, instr->addr, instr->len))4665 return -EINVAL;4666 4667 /* Check if the region is secured */4668 if (nand_region_is_secured(chip, instr->addr, instr->len))4669 return -EIO;4670 4671 /* Grab the lock and see if the device is available */4672 nand_get_device(chip);4673 4674 /* Shift to get first page */4675 page = (int)(instr->addr >> chip->page_shift);4676 chipnr = (int)(instr->addr >> chip->chip_shift);4677 4678 /* Calculate pages in each block */4679 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);4680 4681 /* Select the NAND device */4682 nand_select_target(chip, chipnr);4683 4684 /* Check, if it is write protected */4685 if (nand_check_wp(chip)) {4686 pr_debug("%s: device is write protected!\n",4687 __func__);4688 ret = -EIO;4689 goto erase_exit;4690 }4691 4692 /* Loop through the pages */4693 len = instr->len;4694 4695 while (len) {4696 loff_t ofs = (loff_t)page << chip->page_shift;4697 4698 /* Check if we have a bad block, we do not erase bad blocks! */4699 if (nand_block_checkbad(chip, ((loff_t) page) <<4700 chip->page_shift, allowbbt)) {4701 pr_warn("%s: attempt to erase a bad block at 0x%08llx\n",4702 __func__, (unsigned long long)ofs);4703 ret = -EIO;4704 goto erase_exit;4705 }4706 4707 /*4708 * Invalidate the page cache, if we erase the block which4709 * contains the current cached page.4710 */4711 if (page <= chip->pagecache.page && chip->pagecache.page <4712 (page + pages_per_block))4713 chip->pagecache.page = -1;4714 4715 ret = nand_erase_op(chip, (page & chip->pagemask) >>4716 (chip->phys_erase_shift - chip->page_shift));4717 if (ret) {4718 pr_debug("%s: failed erase, page 0x%08x\n",4719 __func__, page);4720 instr->fail_addr = ofs;4721 goto erase_exit;4722 }4723 4724 /* Increment page address and decrement length */4725 len -= (1ULL << chip->phys_erase_shift);4726 page += pages_per_block;4727 4728 /* Check, if we cross a chip boundary */4729 if (len && !(page & chip->pagemask)) {4730 chipnr++;4731 nand_deselect_target(chip);4732 nand_select_target(chip, chipnr);4733 }4734 }4735 4736 ret = 0;4737erase_exit:4738 4739 /* Deselect and wake up anyone waiting on the device */4740 nand_deselect_target(chip);4741 nand_release_device(chip);4742 4743 /* Return more or less happy */4744 return ret;4745}4746 4747/**4748 * nand_sync - [MTD Interface] sync4749 * @mtd: MTD device structure4750 *4751 * Sync is actually a wait for chip ready function.4752 */4753static void nand_sync(struct mtd_info *mtd)4754{4755 struct nand_chip *chip = mtd_to_nand(mtd);4756 4757 pr_debug("%s: called\n", __func__);4758 4759 /* Grab the lock and see if the device is available */4760 nand_get_device(chip);4761 /* Release it and go back */4762 nand_release_device(chip);4763}4764 4765/**4766 * nand_block_isbad - [MTD Interface] Check if block at offset is bad4767 * @mtd: MTD device structure4768 * @offs: offset relative to mtd start4769 */4770static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)4771{4772 struct nand_chip *chip = mtd_to_nand(mtd);4773 int chipnr = (int)(offs >> chip->chip_shift);4774 int ret;4775 4776 /* Select the NAND device */4777 nand_get_device(chip);4778 4779 nand_select_target(chip, chipnr);4780 4781 ret = nand_block_checkbad(chip, offs, 0);4782 4783 nand_deselect_target(chip);4784 nand_release_device(chip);4785 4786 return ret;4787}4788 4789/**4790 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad4791 * @mtd: MTD device structure4792 * @ofs: offset relative to mtd start4793 */4794static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)4795{4796 int ret;4797 4798 ret = nand_block_isbad(mtd, ofs);4799 if (ret) {4800 /* If it was bad already, return success and do nothing */4801 if (ret > 0)4802 return 0;4803 return ret;4804 }4805 4806 return nand_block_markbad_lowlevel(mtd_to_nand(mtd), ofs);4807}4808 4809/**4810 * nand_suspend - [MTD Interface] Suspend the NAND flash4811 * @mtd: MTD device structure4812 *4813 * Returns 0 for success or negative error code otherwise.4814 */4815static int nand_suspend(struct mtd_info *mtd)4816{4817 struct nand_chip *chip = mtd_to_nand(mtd);4818 int ret = 0;4819 4820 mutex_lock(&chip->lock);4821 if (chip->ops.suspend)4822 ret = chip->ops.suspend(chip);4823 if (!ret)4824 chip->suspended = 1;4825 mutex_unlock(&chip->lock);4826 4827 return ret;4828}4829 4830/**4831 * nand_resume - [MTD Interface] Resume the NAND flash4832 * @mtd: MTD device structure4833 */4834static void nand_resume(struct mtd_info *mtd)4835{4836 struct nand_chip *chip = mtd_to_nand(mtd);4837 4838 mutex_lock(&chip->lock);4839 if (chip->suspended) {4840 if (chip->ops.resume)4841 chip->ops.resume(chip);4842 chip->suspended = 0;4843 } else {4844 pr_err("%s called for a chip which is not in suspended state\n",4845 __func__);4846 }4847 mutex_unlock(&chip->lock);4848 4849 wake_up_all(&chip->resume_wq);4850}4851 4852/**4853 * nand_shutdown - [MTD Interface] Finish the current NAND operation and4854 * prevent further operations4855 * @mtd: MTD device structure4856 */4857static void nand_shutdown(struct mtd_info *mtd)4858{4859 nand_suspend(mtd);4860}4861 4862/**4863 * nand_lock - [MTD Interface] Lock the NAND flash4864 * @mtd: MTD device structure4865 * @ofs: offset byte address4866 * @len: number of bytes to lock (must be a multiple of block/page size)4867 */4868static int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)4869{4870 struct nand_chip *chip = mtd_to_nand(mtd);4871 4872 if (!chip->ops.lock_area)4873 return -ENOTSUPP;4874 4875 return chip->ops.lock_area(chip, ofs, len);4876}4877 4878/**4879 * nand_unlock - [MTD Interface] Unlock the NAND flash4880 * @mtd: MTD device structure4881 * @ofs: offset byte address4882 * @len: number of bytes to unlock (must be a multiple of block/page size)4883 */4884static int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)4885{4886 struct nand_chip *chip = mtd_to_nand(mtd);4887 4888 if (!chip->ops.unlock_area)4889 return -ENOTSUPP;4890 4891 return chip->ops.unlock_area(chip, ofs, len);4892}4893 4894/* Set default functions */4895static void nand_set_defaults(struct nand_chip *chip)4896{4897 /* If no controller is provided, use the dummy, legacy one. */4898 if (!chip->controller) {4899 chip->controller = &chip->legacy.dummy_controller;4900 nand_controller_init(chip->controller);4901 }4902 4903 nand_legacy_set_defaults(chip);4904 4905 if (!chip->buf_align)4906 chip->buf_align = 1;4907}4908 4909/* Sanitize ONFI strings so we can safely print them */4910void sanitize_string(uint8_t *s, size_t len)4911{4912 ssize_t i;4913 4914 /* Null terminate */4915 s[len - 1] = 0;4916 4917 /* Remove non printable chars */4918 for (i = 0; i < len - 1; i++) {4919 if (s[i] < ' ' || s[i] > 127)4920 s[i] = '?';4921 }4922 4923 /* Remove trailing spaces */4924 strim(s);4925}4926 4927/*4928 * nand_id_has_period - Check if an ID string has a given wraparound period4929 * @id_data: the ID string4930 * @arrlen: the length of the @id_data array4931 * @period: the period of repitition4932 *4933 * Check if an ID string is repeated within a given sequence of bytes at4934 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a4935 * period of 3). This is a helper function for nand_id_len(). Returns non-zero4936 * if the repetition has a period of @period; otherwise, returns zero.4937 */4938static int nand_id_has_period(u8 *id_data, int arrlen, int period)4939{4940 int i, j;4941 for (i = 0; i < period; i++)4942 for (j = i + period; j < arrlen; j += period)4943 if (id_data[i] != id_data[j])4944 return 0;4945 return 1;4946}4947 4948/*4949 * nand_id_len - Get the length of an ID string returned by CMD_READID4950 * @id_data: the ID string4951 * @arrlen: the length of the @id_data array4952 4953 * Returns the length of the ID string, according to known wraparound/trailing4954 * zero patterns. If no pattern exists, returns the length of the array.4955 */4956static int nand_id_len(u8 *id_data, int arrlen)4957{4958 int last_nonzero, period;4959 4960 /* Find last non-zero byte */4961 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)4962 if (id_data[last_nonzero])4963 break;4964 4965 /* All zeros */4966 if (last_nonzero < 0)4967 return 0;4968 4969 /* Calculate wraparound period */4970 for (period = 1; period < arrlen; period++)4971 if (nand_id_has_period(id_data, arrlen, period))4972 break;4973 4974 /* There's a repeated pattern */4975 if (period < arrlen)4976 return period;4977 4978 /* There are trailing zeros */4979 if (last_nonzero < arrlen - 1)4980 return last_nonzero + 1;4981 4982 /* No pattern detected */4983 return arrlen;4984}4985 4986/* Extract the bits of per cell from the 3rd byte of the extended ID */4987static int nand_get_bits_per_cell(u8 cellinfo)4988{4989 int bits;4990 4991 bits = cellinfo & NAND_CI_CELLTYPE_MSK;4992 bits >>= NAND_CI_CELLTYPE_SHIFT;4993 return bits + 1;4994}4995 4996/*4997 * Many new NAND share similar device ID codes, which represent the size of the4998 * chip. The rest of the parameters must be decoded according to generic or4999 * manufacturer-specific "extended ID" decoding patterns.5000 */5001void nand_decode_ext_id(struct nand_chip *chip)5002{5003 struct nand_memory_organization *memorg;5004 struct mtd_info *mtd = nand_to_mtd(chip);5005 int extid;5006 u8 *id_data = chip->id.data;5007 5008 memorg = nanddev_get_memorg(&chip->base);5009 5010 /* The 3rd id byte holds MLC / multichip data */5011 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);5012 /* The 4th id byte is the important one */5013 extid = id_data[3];5014 5015 /* Calc pagesize */5016 memorg->pagesize = 1024 << (extid & 0x03);5017 mtd->writesize = memorg->pagesize;5018 extid >>= 2;5019 /* Calc oobsize */5020 memorg->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);5021 mtd->oobsize = memorg->oobsize;5022 extid >>= 2;5023 /* Calc blocksize. Blocksize is multiples of 64KiB */5024 memorg->pages_per_eraseblock = ((64 * 1024) << (extid & 0x03)) /5025 memorg->pagesize;5026 mtd->erasesize = (64 * 1024) << (extid & 0x03);5027 extid >>= 2;5028 /* Get buswidth information */5029 if (extid & 0x1)5030 chip->options |= NAND_BUSWIDTH_16;5031}5032EXPORT_SYMBOL_GPL(nand_decode_ext_id);5033 5034/*5035 * Old devices have chip data hardcoded in the device ID table. nand_decode_id5036 * decodes a matching ID table entry and assigns the MTD size parameters for5037 * the chip.5038 */5039static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type)5040{5041 struct mtd_info *mtd = nand_to_mtd(chip);5042 struct nand_memory_organization *memorg;5043 5044 memorg = nanddev_get_memorg(&chip->base);5045 5046 memorg->pages_per_eraseblock = type->erasesize / type->pagesize;5047 mtd->erasesize = type->erasesize;5048 memorg->pagesize = type->pagesize;5049 mtd->writesize = memorg->pagesize;5050 memorg->oobsize = memorg->pagesize / 32;5051 mtd->oobsize = memorg->oobsize;5052 5053 /* All legacy ID NAND are small-page, SLC */5054 memorg->bits_per_cell = 1;5055}5056 5057/*5058 * Set the bad block marker/indicator (BBM/BBI) patterns according to some5059 * heuristic patterns using various detected parameters (e.g., manufacturer,5060 * page size, cell-type information).5061 */5062static void nand_decode_bbm_options(struct nand_chip *chip)5063{5064 struct mtd_info *mtd = nand_to_mtd(chip);5065 5066 /* Set the bad block position */5067 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))5068 chip->badblockpos = NAND_BBM_POS_LARGE;5069 else5070 chip->badblockpos = NAND_BBM_POS_SMALL;5071}5072 5073static inline bool is_full_id_nand(struct nand_flash_dev *type)5074{5075 return type->id_len;5076}5077 5078static bool find_full_id_nand(struct nand_chip *chip,5079 struct nand_flash_dev *type)5080{5081 struct nand_device *base = &chip->base;5082 struct nand_ecc_props requirements;5083 struct mtd_info *mtd = nand_to_mtd(chip);5084 struct nand_memory_organization *memorg;5085 u8 *id_data = chip->id.data;5086 5087 memorg = nanddev_get_memorg(&chip->base);5088 5089 if (!strncmp(type->id, id_data, type->id_len)) {5090 memorg->pagesize = type->pagesize;5091 mtd->writesize = memorg->pagesize;5092 memorg->pages_per_eraseblock = type->erasesize /5093 type->pagesize;5094 mtd->erasesize = type->erasesize;5095 memorg->oobsize = type->oobsize;5096 mtd->oobsize = memorg->oobsize;5097 5098 memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);5099 memorg->eraseblocks_per_lun =5100 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,5101 memorg->pagesize *5102 memorg->pages_per_eraseblock);5103 chip->options |= type->options;5104 requirements.strength = NAND_ECC_STRENGTH(type);5105 requirements.step_size = NAND_ECC_STEP(type);5106 nanddev_set_ecc_requirements(base, &requirements);5107 5108 chip->parameters.model = kstrdup(type->name, GFP_KERNEL);5109 if (!chip->parameters.model)5110 return false;5111 5112 return true;5113 }5114 return false;5115}5116 5117/*5118 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC5119 * compliant and does not have a full-id or legacy-id entry in the nand_ids5120 * table.5121 */5122static void nand_manufacturer_detect(struct nand_chip *chip)5123{5124 /*5125 * Try manufacturer detection if available and use5126 * nand_decode_ext_id() otherwise.5127 */5128 if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&5129 chip->manufacturer.desc->ops->detect) {5130 struct nand_memory_organization *memorg;5131 5132 memorg = nanddev_get_memorg(&chip->base);5133 5134 /* The 3rd id byte holds MLC / multichip data */5135 memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);5136 chip->manufacturer.desc->ops->detect(chip);5137 } else {5138 nand_decode_ext_id(chip);5139 }5140}5141 5142/*5143 * Manufacturer initialization. This function is called for all NANDs including5144 * ONFI and JEDEC compliant ones.5145 * Manufacturer drivers should put all their specific initialization code in5146 * their ->init() hook.5147 */5148static int nand_manufacturer_init(struct nand_chip *chip)5149{5150 if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops ||5151 !chip->manufacturer.desc->ops->init)5152 return 0;5153 5154 return chip->manufacturer.desc->ops->init(chip);5155}5156 5157/*5158 * Manufacturer cleanup. This function is called for all NANDs including5159 * ONFI and JEDEC compliant ones.5160 * Manufacturer drivers should put all their specific cleanup code in their5161 * ->cleanup() hook.5162 */5163static void nand_manufacturer_cleanup(struct nand_chip *chip)5164{5165 /* Release manufacturer private data */5166 if (chip->manufacturer.desc && chip->manufacturer.desc->ops &&5167 chip->manufacturer.desc->ops->cleanup)5168 chip->manufacturer.desc->ops->cleanup(chip);5169}5170 5171static const char *5172nand_manufacturer_name(const struct nand_manufacturer_desc *manufacturer_desc)5173{5174 return manufacturer_desc ? manufacturer_desc->name : "Unknown";5175}5176 5177static void rawnand_check_data_only_read_support(struct nand_chip *chip)5178{5179 /* Use an arbitrary size for the check */5180 if (!nand_read_data_op(chip, NULL, SZ_512, true, true))5181 chip->controller->supported_op.data_only_read = 1;5182}5183 5184static void rawnand_early_check_supported_ops(struct nand_chip *chip)5185{5186 /* The supported_op fields should not be set by individual drivers */5187 WARN_ON_ONCE(chip->controller->supported_op.data_only_read);5188 5189 if (!nand_has_exec_op(chip))5190 return;5191 5192 rawnand_check_data_only_read_support(chip);5193}5194 5195static void rawnand_check_cont_read_support(struct nand_chip *chip)5196{5197 struct mtd_info *mtd = nand_to_mtd(chip);5198 5199 if (!chip->parameters.supports_read_cache)5200 return;5201 5202 if (chip->read_retries)5203 return;5204 5205 if (!nand_lp_exec_cont_read_page_op(chip, 0, 0, NULL,5206 mtd->writesize, true))5207 chip->controller->supported_op.cont_read = 1;5208}5209 5210static void rawnand_late_check_supported_ops(struct nand_chip *chip)5211{5212 /* The supported_op fields should not be set by individual drivers */5213 WARN_ON_ONCE(chip->controller->supported_op.cont_read);5214 5215 /*5216 * Too many devices do not support sequential cached reads with on-die5217 * ECC correction enabled, so in this case refuse to perform the5218 * automation.5219 */5220 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE)5221 return;5222 5223 if (!nand_has_exec_op(chip))5224 return;5225 5226 /*5227 * For now, continuous reads can only be used with the core page helpers.5228 * This can be extended later.5229 */5230 if (!(chip->ecc.read_page == nand_read_page_hwecc ||5231 chip->ecc.read_page == nand_read_page_syndrome ||5232 chip->ecc.read_page == nand_read_page_swecc))5233 return;5234 5235 rawnand_check_cont_read_support(chip);5236}5237 5238/*5239 * Get the flash and manufacturer id and lookup if the type is supported.5240 */5241static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)5242{5243 const struct nand_manufacturer_desc *manufacturer_desc;5244 struct mtd_info *mtd = nand_to_mtd(chip);5245 struct nand_memory_organization *memorg;5246 int busw, ret;5247 u8 *id_data = chip->id.data;5248 u8 maf_id, dev_id;5249 u64 targetsize;5250 5251 /*5252 * Let's start by initializing memorg fields that might be left5253 * unassigned by the ID-based detection logic.5254 */5255 memorg = nanddev_get_memorg(&chip->base);5256 memorg->planes_per_lun = 1;5257 memorg->luns_per_target = 1;5258 5259 /*5260 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)5261 * after power-up.5262 */5263 ret = nand_reset(chip, 0);5264 if (ret)5265 return ret;5266 5267 /* Select the device */5268 nand_select_target(chip, 0);5269 5270 rawnand_early_check_supported_ops(chip);5271 5272 /* Send the command for reading device ID */5273 ret = nand_readid_op(chip, 0, id_data, 2);5274 if (ret)5275 return ret;5276 5277 /* Read manufacturer and device IDs */5278 maf_id = id_data[0];5279 dev_id = id_data[1];5280 5281 /*5282 * Try again to make sure, as some systems the bus-hold or other5283 * interface concerns can cause random data which looks like a5284 * possibly credible NAND flash to appear. If the two results do5285 * not match, ignore the device completely.5286 */5287 5288 /* Read entire ID string */5289 ret = nand_readid_op(chip, 0, id_data, sizeof(chip->id.data));5290 if (ret)5291 return ret;5292 5293 if (id_data[0] != maf_id || id_data[1] != dev_id) {5294 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",5295 maf_id, dev_id, id_data[0], id_data[1]);5296 return -ENODEV;5297 }5298 5299 chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data));5300 5301 /* Try to identify manufacturer */5302 manufacturer_desc = nand_get_manufacturer_desc(maf_id);5303 chip->manufacturer.desc = manufacturer_desc;5304 5305 if (!type)5306 type = nand_flash_ids;5307 5308 /*5309 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic5310 * override it.5311 * This is required to make sure initial NAND bus width set by the5312 * NAND controller driver is coherent with the real NAND bus width5313 * (extracted by auto-detection code).5314 */5315 busw = chip->options & NAND_BUSWIDTH_16;5316 5317 /*5318 * The flag is only set (never cleared), reset it to its default value5319 * before starting auto-detection.5320 */5321 chip->options &= ~NAND_BUSWIDTH_16;5322 5323 for (; type->name != NULL; type++) {5324 if (is_full_id_nand(type)) {5325 if (find_full_id_nand(chip, type))5326 goto ident_done;5327 } else if (dev_id == type->dev_id) {5328 break;5329 }5330 }5331 5332 if (!type->name || !type->pagesize) {5333 /* Check if the chip is ONFI compliant */5334 ret = nand_onfi_detect(chip);5335 if (ret < 0)5336 return ret;5337 else if (ret)5338 goto ident_done;5339 5340 /* Check if the chip is JEDEC compliant */5341 ret = nand_jedec_detect(chip);5342 if (ret < 0)5343 return ret;5344 else if (ret)5345 goto ident_done;5346 }5347 5348 if (!type->name)5349 return -ENODEV;5350 5351 chip->parameters.model = kstrdup(type->name, GFP_KERNEL);5352 if (!chip->parameters.model)5353 return -ENOMEM;5354 5355 if (!type->pagesize)5356 nand_manufacturer_detect(chip);5357 else5358 nand_decode_id(chip, type);5359 5360 /* Get chip options */5361 chip->options |= type->options;5362 5363 memorg->eraseblocks_per_lun =5364 DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,5365 memorg->pagesize *5366 memorg->pages_per_eraseblock);5367 5368ident_done:5369 if (!mtd->name)5370 mtd->name = chip->parameters.model;5371 5372 if (chip->options & NAND_BUSWIDTH_AUTO) {5373 WARN_ON(busw & NAND_BUSWIDTH_16);5374 nand_set_defaults(chip);5375 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {5376 /*5377 * Check, if buswidth is correct. Hardware drivers should set5378 * chip correct!5379 */5380 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",5381 maf_id, dev_id);5382 pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc),5383 mtd->name);5384 pr_warn("bus width %d instead of %d bits\n", busw ? 16 : 8,5385 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8);5386 ret = -EINVAL;5387 5388 goto free_detect_allocation;5389 }5390 5391 nand_decode_bbm_options(chip);5392 5393 /* Calculate the address shift from the page size */5394 chip->page_shift = ffs(mtd->writesize) - 1;5395 /* Convert chipsize to number of pages per chip -1 */5396 targetsize = nanddev_target_size(&chip->base);5397 chip->pagemask = (targetsize >> chip->page_shift) - 1;5398 5399 chip->bbt_erase_shift = chip->phys_erase_shift =5400 ffs(mtd->erasesize) - 1;5401 if (targetsize & 0xffffffff)5402 chip->chip_shift = ffs((unsigned)targetsize) - 1;5403 else {5404 chip->chip_shift = ffs((unsigned)(targetsize >> 32));5405 chip->chip_shift += 32 - 1;5406 }5407 5408 if (chip->chip_shift - chip->page_shift > 16)5409 chip->options |= NAND_ROW_ADDR_3;5410 5411 chip->badblockbits = 8;5412 5413 nand_legacy_adjust_cmdfunc(chip);5414 5415 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",5416 maf_id, dev_id);5417 pr_info("%s %s\n", nand_manufacturer_name(manufacturer_desc),5418 chip->parameters.model);5419 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",5420 (int)(targetsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",5421 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);5422 return 0;5423 5424free_detect_allocation:5425 kfree(chip->parameters.model);5426 5427 return ret;5428}5429 5430static enum nand_ecc_engine_type5431of_get_rawnand_ecc_engine_type_legacy(struct device_node *np)5432{5433 enum nand_ecc_legacy_mode {5434 NAND_ECC_INVALID,5435 NAND_ECC_NONE,5436 NAND_ECC_SOFT,5437 NAND_ECC_SOFT_BCH,5438 NAND_ECC_HW,5439 NAND_ECC_HW_SYNDROME,5440 NAND_ECC_ON_DIE,5441 };5442 const char * const nand_ecc_legacy_modes[] = {5443 [NAND_ECC_NONE] = "none",5444 [NAND_ECC_SOFT] = "soft",5445 [NAND_ECC_SOFT_BCH] = "soft_bch",5446 [NAND_ECC_HW] = "hw",5447 [NAND_ECC_HW_SYNDROME] = "hw_syndrome",5448 [NAND_ECC_ON_DIE] = "on-die",5449 };5450 enum nand_ecc_legacy_mode eng_type;5451 const char *pm;5452 int err;5453 5454 err = of_property_read_string(np, "nand-ecc-mode", &pm);5455 if (err)5456 return NAND_ECC_ENGINE_TYPE_INVALID;5457 5458 for (eng_type = NAND_ECC_NONE;5459 eng_type < ARRAY_SIZE(nand_ecc_legacy_modes); eng_type++) {5460 if (!strcasecmp(pm, nand_ecc_legacy_modes[eng_type])) {5461 switch (eng_type) {5462 case NAND_ECC_NONE:5463 return NAND_ECC_ENGINE_TYPE_NONE;5464 case NAND_ECC_SOFT:5465 case NAND_ECC_SOFT_BCH:5466 return NAND_ECC_ENGINE_TYPE_SOFT;5467 case NAND_ECC_HW:5468 case NAND_ECC_HW_SYNDROME:5469 return NAND_ECC_ENGINE_TYPE_ON_HOST;5470 case NAND_ECC_ON_DIE:5471 return NAND_ECC_ENGINE_TYPE_ON_DIE;5472 default:5473 break;5474 }5475 }5476 }5477 5478 return NAND_ECC_ENGINE_TYPE_INVALID;5479}5480 5481static enum nand_ecc_placement5482of_get_rawnand_ecc_placement_legacy(struct device_node *np)5483{5484 const char *pm;5485 int err;5486 5487 err = of_property_read_string(np, "nand-ecc-mode", &pm);5488 if (!err) {5489 if (!strcasecmp(pm, "hw_syndrome"))5490 return NAND_ECC_PLACEMENT_INTERLEAVED;5491 }5492 5493 return NAND_ECC_PLACEMENT_UNKNOWN;5494}5495 5496static enum nand_ecc_algo of_get_rawnand_ecc_algo_legacy(struct device_node *np)5497{5498 const char *pm;5499 int err;5500 5501 err = of_property_read_string(np, "nand-ecc-mode", &pm);5502 if (!err) {5503 if (!strcasecmp(pm, "soft"))5504 return NAND_ECC_ALGO_HAMMING;5505 else if (!strcasecmp(pm, "soft_bch"))5506 return NAND_ECC_ALGO_BCH;5507 }5508 5509 return NAND_ECC_ALGO_UNKNOWN;5510}5511 5512static void of_get_nand_ecc_legacy_user_config(struct nand_chip *chip)5513{5514 struct device_node *dn = nand_get_flash_node(chip);5515 struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf;5516 5517 if (user_conf->engine_type == NAND_ECC_ENGINE_TYPE_INVALID)5518 user_conf->engine_type = of_get_rawnand_ecc_engine_type_legacy(dn);5519 5520 if (user_conf->algo == NAND_ECC_ALGO_UNKNOWN)5521 user_conf->algo = of_get_rawnand_ecc_algo_legacy(dn);5522 5523 if (user_conf->placement == NAND_ECC_PLACEMENT_UNKNOWN)5524 user_conf->placement = of_get_rawnand_ecc_placement_legacy(dn);5525}5526 5527static int of_get_nand_bus_width(struct nand_chip *chip)5528{5529 struct device_node *dn = nand_get_flash_node(chip);5530 u32 val;5531 int ret;5532 5533 ret = of_property_read_u32(dn, "nand-bus-width", &val);5534 if (ret == -EINVAL)5535 /* Buswidth defaults to 8 if the property does not exist .*/5536 return 0;5537 else if (ret)5538 return ret;5539 5540 if (val == 16)5541 chip->options |= NAND_BUSWIDTH_16;5542 else if (val != 8)5543 return -EINVAL;5544 return 0;5545}5546 5547static int of_get_nand_secure_regions(struct nand_chip *chip)5548{5549 struct device_node *dn = nand_get_flash_node(chip);5550 struct property *prop;5551 int nr_elem, i, j;5552 5553 /* Only proceed if the "secure-regions" property is present in DT */5554 prop = of_find_property(dn, "secure-regions", NULL);5555 if (!prop)5556 return 0;5557 5558 nr_elem = of_property_count_elems_of_size(dn, "secure-regions", sizeof(u64));5559 if (nr_elem <= 0)5560 return nr_elem;5561 5562 chip->nr_secure_regions = nr_elem / 2;5563 chip->secure_regions = kcalloc(chip->nr_secure_regions, sizeof(*chip->secure_regions),5564 GFP_KERNEL);5565 if (!chip->secure_regions)5566 return -ENOMEM;5567 5568 for (i = 0, j = 0; i < chip->nr_secure_regions; i++, j += 2) {5569 of_property_read_u64_index(dn, "secure-regions", j,5570 &chip->secure_regions[i].offset);5571 of_property_read_u64_index(dn, "secure-regions", j + 1,5572 &chip->secure_regions[i].size);5573 }5574 5575 return 0;5576}5577 5578/**5579 * rawnand_dt_parse_gpio_cs - Parse the gpio-cs property of a controller5580 * @dev: Device that will be parsed. Also used for managed allocations.5581 * @cs_array: Array of GPIO desc pointers allocated on success5582 * @ncs_array: Number of entries in @cs_array updated on success.5583 * @return 0 on success, an error otherwise.5584 */5585int rawnand_dt_parse_gpio_cs(struct device *dev, struct gpio_desc ***cs_array,5586 unsigned int *ncs_array)5587{5588 struct gpio_desc **descs;5589 int ndescs, i;5590 5591 ndescs = gpiod_count(dev, "cs");5592 if (ndescs < 0) {5593 dev_dbg(dev, "No valid cs-gpios property\n");5594 return 0;5595 }5596 5597 descs = devm_kcalloc(dev, ndescs, sizeof(*descs), GFP_KERNEL);5598 if (!descs)5599 return -ENOMEM;5600 5601 for (i = 0; i < ndescs; i++) {5602 descs[i] = gpiod_get_index_optional(dev, "cs", i,5603 GPIOD_OUT_HIGH);5604 if (IS_ERR(descs[i]))5605 return PTR_ERR(descs[i]);5606 }5607 5608 *ncs_array = ndescs;5609 *cs_array = descs;5610 5611 return 0;5612}5613EXPORT_SYMBOL(rawnand_dt_parse_gpio_cs);5614 5615static int rawnand_dt_init(struct nand_chip *chip)5616{5617 struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip));5618 struct device_node *dn = nand_get_flash_node(chip);5619 int ret;5620 5621 if (!dn)5622 return 0;5623 5624 ret = of_get_nand_bus_width(chip);5625 if (ret)5626 return ret;5627 5628 if (of_property_read_bool(dn, "nand-is-boot-medium"))5629 chip->options |= NAND_IS_BOOT_MEDIUM;5630 5631 if (of_property_read_bool(dn, "nand-on-flash-bbt"))5632 chip->bbt_options |= NAND_BBT_USE_FLASH;5633 5634 of_get_nand_ecc_user_config(nand);5635 of_get_nand_ecc_legacy_user_config(chip);5636 5637 /*5638 * If neither the user nor the NAND controller have requested a specific5639 * ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST.5640 */5641 nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;5642 5643 /*5644 * Use the user requested engine type, unless there is none, in this5645 * case default to the NAND controller choice, otherwise fallback to5646 * the raw NAND default one.5647 */5648 if (nand->ecc.user_conf.engine_type != NAND_ECC_ENGINE_TYPE_INVALID)5649 chip->ecc.engine_type = nand->ecc.user_conf.engine_type;5650 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)5651 chip->ecc.engine_type = nand->ecc.defaults.engine_type;5652 5653 chip->ecc.placement = nand->ecc.user_conf.placement;5654 chip->ecc.algo = nand->ecc.user_conf.algo;5655 chip->ecc.strength = nand->ecc.user_conf.strength;5656 chip->ecc.size = nand->ecc.user_conf.step_size;5657 5658 return 0;5659}5660 5661/**5662 * nand_scan_ident - Scan for the NAND device5663 * @chip: NAND chip object5664 * @maxchips: number of chips to scan for5665 * @table: alternative NAND ID table5666 *5667 * This is the first phase of the normal nand_scan() function. It reads the5668 * flash ID and sets up MTD fields accordingly.5669 *5670 * This helper used to be called directly from controller drivers that needed5671 * to tweak some ECC-related parameters before nand_scan_tail(). This separation5672 * prevented dynamic allocations during this phase which was unconvenient and5673 * as been banned for the benefit of the ->init_ecc()/cleanup_ecc() hooks.5674 */5675static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,5676 struct nand_flash_dev *table)5677{5678 struct mtd_info *mtd = nand_to_mtd(chip);5679 struct nand_memory_organization *memorg;5680 int nand_maf_id, nand_dev_id;5681 unsigned int i;5682 int ret;5683 5684 memorg = nanddev_get_memorg(&chip->base);5685 5686 /* Assume all dies are deselected when we enter nand_scan_ident(). */5687 chip->cur_cs = -1;5688 5689 mutex_init(&chip->lock);5690 init_waitqueue_head(&chip->resume_wq);5691 5692 /* Enforce the right timings for reset/detection */5693 chip->current_interface_config = nand_get_reset_interface_config();5694 5695 ret = rawnand_dt_init(chip);5696 if (ret)5697 return ret;5698 5699 if (!mtd->name && mtd->dev.parent)5700 mtd->name = dev_name(mtd->dev.parent);5701 5702 /* Set the default functions */5703 nand_set_defaults(chip);5704 5705 ret = nand_legacy_check_hooks(chip);5706 if (ret)5707 return ret;5708 5709 memorg->ntargets = maxchips;5710 5711 /* Read the flash type */5712 ret = nand_detect(chip, table);5713 if (ret) {5714 if (!(chip->options & NAND_SCAN_SILENT_NODEV))5715 pr_warn("No NAND device found\n");5716 nand_deselect_target(chip);5717 return ret;5718 }5719 5720 nand_maf_id = chip->id.data[0];5721 nand_dev_id = chip->id.data[1];5722 5723 nand_deselect_target(chip);5724 5725 /* Check for a chip array */5726 for (i = 1; i < maxchips; i++) {5727 u8 id[2];5728 5729 /* See comment in nand_get_flash_type for reset */5730 ret = nand_reset(chip, i);5731 if (ret)5732 break;5733 5734 nand_select_target(chip, i);5735 /* Send the command for reading device ID */5736 ret = nand_readid_op(chip, 0, id, sizeof(id));5737 if (ret)5738 break;5739 /* Read manufacturer and device IDs */5740 if (nand_maf_id != id[0] || nand_dev_id != id[1]) {5741 nand_deselect_target(chip);5742 break;5743 }5744 nand_deselect_target(chip);5745 }5746 if (i > 1)5747 pr_info("%d chips detected\n", i);5748 5749 /* Store the number of chips and calc total size for mtd */5750 memorg->ntargets = i;5751 mtd->size = i * nanddev_target_size(&chip->base);5752 5753 return 0;5754}5755 5756static void nand_scan_ident_cleanup(struct nand_chip *chip)5757{5758 kfree(chip->parameters.model);5759 kfree(chip->parameters.onfi);5760}5761 5762int rawnand_sw_hamming_init(struct nand_chip *chip)5763{5764 struct nand_ecc_sw_hamming_conf *engine_conf;5765 struct nand_device *base = &chip->base;5766 int ret;5767 5768 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;5769 base->ecc.user_conf.algo = NAND_ECC_ALGO_HAMMING;5770 base->ecc.user_conf.strength = chip->ecc.strength;5771 base->ecc.user_conf.step_size = chip->ecc.size;5772 5773 ret = nand_ecc_sw_hamming_init_ctx(base);5774 if (ret)5775 return ret;5776 5777 engine_conf = base->ecc.ctx.priv;5778 5779 if (chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER)5780 engine_conf->sm_order = true;5781 5782 chip->ecc.size = base->ecc.ctx.conf.step_size;5783 chip->ecc.strength = base->ecc.ctx.conf.strength;5784 chip->ecc.total = base->ecc.ctx.total;5785 chip->ecc.steps = nanddev_get_ecc_nsteps(base);5786 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base);5787 5788 return 0;5789}5790EXPORT_SYMBOL(rawnand_sw_hamming_init);5791 5792int rawnand_sw_hamming_calculate(struct nand_chip *chip,5793 const unsigned char *buf,5794 unsigned char *code)5795{5796 struct nand_device *base = &chip->base;5797 5798 return nand_ecc_sw_hamming_calculate(base, buf, code);5799}5800EXPORT_SYMBOL(rawnand_sw_hamming_calculate);5801 5802int rawnand_sw_hamming_correct(struct nand_chip *chip,5803 unsigned char *buf,5804 unsigned char *read_ecc,5805 unsigned char *calc_ecc)5806{5807 struct nand_device *base = &chip->base;5808 5809 return nand_ecc_sw_hamming_correct(base, buf, read_ecc, calc_ecc);5810}5811EXPORT_SYMBOL(rawnand_sw_hamming_correct);5812 5813void rawnand_sw_hamming_cleanup(struct nand_chip *chip)5814{5815 struct nand_device *base = &chip->base;5816 5817 nand_ecc_sw_hamming_cleanup_ctx(base);5818}5819EXPORT_SYMBOL(rawnand_sw_hamming_cleanup);5820 5821int rawnand_sw_bch_init(struct nand_chip *chip)5822{5823 struct nand_device *base = &chip->base;5824 const struct nand_ecc_props *ecc_conf = nanddev_get_ecc_conf(base);5825 int ret;5826 5827 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;5828 base->ecc.user_conf.algo = NAND_ECC_ALGO_BCH;5829 base->ecc.user_conf.step_size = chip->ecc.size;5830 base->ecc.user_conf.strength = chip->ecc.strength;5831 5832 ret = nand_ecc_sw_bch_init_ctx(base);5833 if (ret)5834 return ret;5835 5836 chip->ecc.size = ecc_conf->step_size;5837 chip->ecc.strength = ecc_conf->strength;5838 chip->ecc.total = base->ecc.ctx.total;5839 chip->ecc.steps = nanddev_get_ecc_nsteps(base);5840 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base);5841 5842 return 0;5843}5844EXPORT_SYMBOL(rawnand_sw_bch_init);5845 5846static int rawnand_sw_bch_calculate(struct nand_chip *chip,5847 const unsigned char *buf,5848 unsigned char *code)5849{5850 struct nand_device *base = &chip->base;5851 5852 return nand_ecc_sw_bch_calculate(base, buf, code);5853}5854 5855int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf,5856 unsigned char *read_ecc, unsigned char *calc_ecc)5857{5858 struct nand_device *base = &chip->base;5859 5860 return nand_ecc_sw_bch_correct(base, buf, read_ecc, calc_ecc);5861}5862EXPORT_SYMBOL(rawnand_sw_bch_correct);5863 5864void rawnand_sw_bch_cleanup(struct nand_chip *chip)5865{5866 struct nand_device *base = &chip->base;5867 5868 nand_ecc_sw_bch_cleanup_ctx(base);5869}5870EXPORT_SYMBOL(rawnand_sw_bch_cleanup);5871 5872static int nand_set_ecc_on_host_ops(struct nand_chip *chip)5873{5874 struct nand_ecc_ctrl *ecc = &chip->ecc;5875 5876 switch (ecc->placement) {5877 case NAND_ECC_PLACEMENT_UNKNOWN:5878 case NAND_ECC_PLACEMENT_OOB:5879 /* Use standard hwecc read page function? */5880 if (!ecc->read_page)5881 ecc->read_page = nand_read_page_hwecc;5882 if (!ecc->write_page)5883 ecc->write_page = nand_write_page_hwecc;5884 if (!ecc->read_page_raw)5885 ecc->read_page_raw = nand_read_page_raw;5886 if (!ecc->write_page_raw)5887 ecc->write_page_raw = nand_write_page_raw;5888 if (!ecc->read_oob)5889 ecc->read_oob = nand_read_oob_std;5890 if (!ecc->write_oob)5891 ecc->write_oob = nand_write_oob_std;5892 if (!ecc->read_subpage)5893 ecc->read_subpage = nand_read_subpage;5894 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)5895 ecc->write_subpage = nand_write_subpage_hwecc;5896 fallthrough;5897 5898 case NAND_ECC_PLACEMENT_INTERLEAVED:5899 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&5900 (!ecc->read_page ||5901 ecc->read_page == nand_read_page_hwecc ||5902 !ecc->write_page ||5903 ecc->write_page == nand_write_page_hwecc)) {5904 WARN(1, "No ECC functions supplied; hardware ECC not possible\n");5905 return -EINVAL;5906 }5907 /* Use standard syndrome read/write page function? */5908 if (!ecc->read_page)5909 ecc->read_page = nand_read_page_syndrome;5910 if (!ecc->write_page)5911 ecc->write_page = nand_write_page_syndrome;5912 if (!ecc->read_page_raw)5913 ecc->read_page_raw = nand_read_page_raw_syndrome;5914 if (!ecc->write_page_raw)5915 ecc->write_page_raw = nand_write_page_raw_syndrome;5916 if (!ecc->read_oob)5917 ecc->read_oob = nand_read_oob_syndrome;5918 if (!ecc->write_oob)5919 ecc->write_oob = nand_write_oob_syndrome;5920 break;5921 5922 default:5923 pr_warn("Invalid NAND_ECC_PLACEMENT %d\n",5924 ecc->placement);5925 return -EINVAL;5926 }5927 5928 return 0;5929}5930 5931static int nand_set_ecc_soft_ops(struct nand_chip *chip)5932{5933 struct mtd_info *mtd = nand_to_mtd(chip);5934 struct nand_device *nanddev = mtd_to_nanddev(mtd);5935 struct nand_ecc_ctrl *ecc = &chip->ecc;5936 int ret;5937 5938 if (WARN_ON(ecc->engine_type != NAND_ECC_ENGINE_TYPE_SOFT))5939 return -EINVAL;5940 5941 switch (ecc->algo) {5942 case NAND_ECC_ALGO_HAMMING:5943 ecc->calculate = rawnand_sw_hamming_calculate;5944 ecc->correct = rawnand_sw_hamming_correct;5945 ecc->read_page = nand_read_page_swecc;5946 ecc->read_subpage = nand_read_subpage;5947 ecc->write_page = nand_write_page_swecc;5948 if (!ecc->read_page_raw)5949 ecc->read_page_raw = nand_read_page_raw;5950 if (!ecc->write_page_raw)5951 ecc->write_page_raw = nand_write_page_raw;5952 ecc->read_oob = nand_read_oob_std;5953 ecc->write_oob = nand_write_oob_std;5954 if (!ecc->size)5955 ecc->size = 256;5956 ecc->bytes = 3;5957 ecc->strength = 1;5958 5959 if (IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC))5960 ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;5961 5962 ret = rawnand_sw_hamming_init(chip);5963 if (ret) {5964 WARN(1, "Hamming ECC initialization failed!\n");5965 return ret;5966 }5967 5968 return 0;5969 case NAND_ECC_ALGO_BCH:5970 if (!IS_ENABLED(CONFIG_MTD_NAND_ECC_SW_BCH)) {5971 WARN(1, "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n");5972 return -EINVAL;5973 }5974 ecc->calculate = rawnand_sw_bch_calculate;5975 ecc->correct = rawnand_sw_bch_correct;5976 ecc->read_page = nand_read_page_swecc;5977 ecc->read_subpage = nand_read_subpage;5978 ecc->write_page = nand_write_page_swecc;5979 if (!ecc->read_page_raw)5980 ecc->read_page_raw = nand_read_page_raw;5981 if (!ecc->write_page_raw)5982 ecc->write_page_raw = nand_write_page_raw;5983 ecc->read_oob = nand_read_oob_std;5984 ecc->write_oob = nand_write_oob_std;5985 5986 /*5987 * We can only maximize ECC config when the default layout is5988 * used, otherwise we don't know how many bytes can really be5989 * used.5990 */5991 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH &&5992 mtd->ooblayout != nand_get_large_page_ooblayout())5993 nanddev->ecc.user_conf.flags &= ~NAND_ECC_MAXIMIZE_STRENGTH;5994 5995 ret = rawnand_sw_bch_init(chip);5996 if (ret) {5997 WARN(1, "BCH ECC initialization failed!\n");5998 return ret;5999 }6000 6001 return 0;6002 default:6003 WARN(1, "Unsupported ECC algorithm!\n");6004 return -EINVAL;6005 }6006}6007 6008/**6009 * nand_check_ecc_caps - check the sanity of preset ECC settings6010 * @chip: nand chip info structure6011 * @caps: ECC caps info structure6012 * @oobavail: OOB size that the ECC engine can use6013 *6014 * When ECC step size and strength are already set, check if they are supported6015 * by the controller and the calculated ECC bytes fit within the chip's OOB.6016 * On success, the calculated ECC bytes is set.6017 */6018static int6019nand_check_ecc_caps(struct nand_chip *chip,6020 const struct nand_ecc_caps *caps, int oobavail)6021{6022 struct mtd_info *mtd = nand_to_mtd(chip);6023 const struct nand_ecc_step_info *stepinfo;6024 int preset_step = chip->ecc.size;6025 int preset_strength = chip->ecc.strength;6026 int ecc_bytes, nsteps = mtd->writesize / preset_step;6027 int i, j;6028 6029 for (i = 0; i < caps->nstepinfos; i++) {6030 stepinfo = &caps->stepinfos[i];6031 6032 if (stepinfo->stepsize != preset_step)6033 continue;6034 6035 for (j = 0; j < stepinfo->nstrengths; j++) {6036 if (stepinfo->strengths[j] != preset_strength)6037 continue;6038 6039 ecc_bytes = caps->calc_ecc_bytes(preset_step,6040 preset_strength);6041 if (WARN_ON_ONCE(ecc_bytes < 0))6042 return ecc_bytes;6043 6044 if (ecc_bytes * nsteps > oobavail) {6045 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",6046 preset_step, preset_strength);6047 return -ENOSPC;6048 }6049 6050 chip->ecc.bytes = ecc_bytes;6051 6052 return 0;6053 }6054 }6055 6056 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",6057 preset_step, preset_strength);6058 6059 return -ENOTSUPP;6060}6061 6062/**6063 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes6064 * @chip: nand chip info structure6065 * @caps: ECC engine caps info structure6066 * @oobavail: OOB size that the ECC engine can use6067 *6068 * If a chip's ECC requirement is provided, try to meet it with the least6069 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).6070 * On success, the chosen ECC settings are set.6071 */6072static int6073nand_match_ecc_req(struct nand_chip *chip,6074 const struct nand_ecc_caps *caps, int oobavail)6075{6076 const struct nand_ecc_props *requirements =6077 nanddev_get_ecc_requirements(&chip->base);6078 struct mtd_info *mtd = nand_to_mtd(chip);6079 const struct nand_ecc_step_info *stepinfo;6080 int req_step = requirements->step_size;6081 int req_strength = requirements->strength;6082 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;6083 int best_step = 0, best_strength = 0, best_ecc_bytes = 0;6084 int best_ecc_bytes_total = INT_MAX;6085 int i, j;6086 6087 /* No information provided by the NAND chip */6088 if (!req_step || !req_strength)6089 return -ENOTSUPP;6090 6091 /* number of correctable bits the chip requires in a page */6092 req_corr = mtd->writesize / req_step * req_strength;6093 6094 for (i = 0; i < caps->nstepinfos; i++) {6095 stepinfo = &caps->stepinfos[i];6096 step_size = stepinfo->stepsize;6097 6098 for (j = 0; j < stepinfo->nstrengths; j++) {6099 strength = stepinfo->strengths[j];6100 6101 /*6102 * If both step size and strength are smaller than the6103 * chip's requirement, it is not easy to compare the6104 * resulted reliability.6105 */6106 if (step_size < req_step && strength < req_strength)6107 continue;6108 6109 if (mtd->writesize % step_size)6110 continue;6111 6112 nsteps = mtd->writesize / step_size;6113 6114 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);6115 if (WARN_ON_ONCE(ecc_bytes < 0))6116 continue;6117 ecc_bytes_total = ecc_bytes * nsteps;6118 6119 if (ecc_bytes_total > oobavail ||6120 strength * nsteps < req_corr)6121 continue;6122 6123 /*6124 * We assume the best is to meet the chip's requrement6125 * with the least number of ECC bytes.6126 */6127 if (ecc_bytes_total < best_ecc_bytes_total) {6128 best_ecc_bytes_total = ecc_bytes_total;6129 best_step = step_size;6130 best_strength = strength;6131 best_ecc_bytes = ecc_bytes;6132 }6133 }6134 }6135 6136 if (best_ecc_bytes_total == INT_MAX)6137 return -ENOTSUPP;6138 6139 chip->ecc.size = best_step;6140 chip->ecc.strength = best_strength;6141 chip->ecc.bytes = best_ecc_bytes;6142 6143 return 0;6144}6145 6146/**6147 * nand_maximize_ecc - choose the max ECC strength available6148 * @chip: nand chip info structure6149 * @caps: ECC engine caps info structure6150 * @oobavail: OOB size that the ECC engine can use6151 *6152 * Choose the max ECC strength that is supported on the controller, and can fit6153 * within the chip's OOB. On success, the chosen ECC settings are set.6154 */6155static int6156nand_maximize_ecc(struct nand_chip *chip,6157 const struct nand_ecc_caps *caps, int oobavail)6158{6159 struct mtd_info *mtd = nand_to_mtd(chip);6160 const struct nand_ecc_step_info *stepinfo;6161 int step_size, strength, nsteps, ecc_bytes, corr;6162 int best_corr = 0;6163 int best_step = 0;6164 int best_strength = 0, best_ecc_bytes = 0;6165 int i, j;6166 6167 for (i = 0; i < caps->nstepinfos; i++) {6168 stepinfo = &caps->stepinfos[i];6169 step_size = stepinfo->stepsize;6170 6171 /* If chip->ecc.size is already set, respect it */6172 if (chip->ecc.size && step_size != chip->ecc.size)6173 continue;6174 6175 for (j = 0; j < stepinfo->nstrengths; j++) {6176 strength = stepinfo->strengths[j];6177 6178 if (mtd->writesize % step_size)6179 continue;6180 6181 nsteps = mtd->writesize / step_size;6182 6183 ecc_bytes = caps->calc_ecc_bytes(step_size, strength);6184 if (WARN_ON_ONCE(ecc_bytes < 0))6185 continue;6186 6187 if (ecc_bytes * nsteps > oobavail)6188 continue;6189 6190 corr = strength * nsteps;6191 6192 /*6193 * If the number of correctable bits is the same,6194 * bigger step_size has more reliability.6195 */6196 if (corr > best_corr ||6197 (corr == best_corr && step_size > best_step)) {6198 best_corr = corr;6199 best_step = step_size;6200 best_strength = strength;6201 best_ecc_bytes = ecc_bytes;6202 }6203 }6204 }6205 6206 if (!best_corr)6207 return -ENOTSUPP;6208 6209 chip->ecc.size = best_step;6210 chip->ecc.strength = best_strength;6211 chip->ecc.bytes = best_ecc_bytes;6212 6213 return 0;6214}6215 6216/**6217 * nand_ecc_choose_conf - Set the ECC strength and ECC step size6218 * @chip: nand chip info structure6219 * @caps: ECC engine caps info structure6220 * @oobavail: OOB size that the ECC engine can use6221 *6222 * Choose the ECC configuration according to following logic.6223 *6224 * 1. If both ECC step size and ECC strength are already set (usually by DT)6225 * then check if it is supported by this controller.6226 * 2. If the user provided the nand-ecc-maximize property, then select maximum6227 * ECC strength.6228 * 3. Otherwise, try to match the ECC step size and ECC strength closest6229 * to the chip's requirement. If available OOB size can't fit the chip6230 * requirement then fallback to the maximum ECC step size and ECC strength.6231 *6232 * On success, the chosen ECC settings are set.6233 */6234int nand_ecc_choose_conf(struct nand_chip *chip,6235 const struct nand_ecc_caps *caps, int oobavail)6236{6237 struct mtd_info *mtd = nand_to_mtd(chip);6238 struct nand_device *nanddev = mtd_to_nanddev(mtd);6239 6240 if (WARN_ON(oobavail < 0 || oobavail > mtd->oobsize))6241 return -EINVAL;6242 6243 if (chip->ecc.size && chip->ecc.strength)6244 return nand_check_ecc_caps(chip, caps, oobavail);6245 6246 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH)6247 return nand_maximize_ecc(chip, caps, oobavail);6248 6249 if (!nand_match_ecc_req(chip, caps, oobavail))6250 return 0;6251 6252 return nand_maximize_ecc(chip, caps, oobavail);6253}6254EXPORT_SYMBOL_GPL(nand_ecc_choose_conf);6255 6256static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos)6257{6258 struct nand_chip *chip = container_of(nand, struct nand_chip,6259 base);6260 unsigned int eb = nanddev_pos_to_row(nand, pos);6261 int ret;6262 6263 eb >>= nand->rowconv.eraseblock_addr_shift;6264 6265 nand_select_target(chip, pos->target);6266 ret = nand_erase_op(chip, eb);6267 nand_deselect_target(chip);6268 6269 return ret;6270}6271 6272static int rawnand_markbad(struct nand_device *nand,6273 const struct nand_pos *pos)6274{6275 struct nand_chip *chip = container_of(nand, struct nand_chip,6276 base);6277 6278 return nand_markbad_bbm(chip, nanddev_pos_to_offs(nand, pos));6279}6280 6281static bool rawnand_isbad(struct nand_device *nand, const struct nand_pos *pos)6282{6283 struct nand_chip *chip = container_of(nand, struct nand_chip,6284 base);6285 int ret;6286 6287 nand_select_target(chip, pos->target);6288 ret = nand_isbad_bbm(chip, nanddev_pos_to_offs(nand, pos));6289 nand_deselect_target(chip);6290 6291 return ret;6292}6293 6294static const struct nand_ops rawnand_ops = {6295 .erase = rawnand_erase,6296 .markbad = rawnand_markbad,6297 .isbad = rawnand_isbad,6298};6299 6300/**6301 * nand_scan_tail - Scan for the NAND device6302 * @chip: NAND chip object6303 *6304 * This is the second phase of the normal nand_scan() function. It fills out6305 * all the uninitialized function pointers with the defaults and scans for a6306 * bad block table if appropriate.6307 */6308static int nand_scan_tail(struct nand_chip *chip)6309{6310 struct mtd_info *mtd = nand_to_mtd(chip);6311 struct nand_device *base = &chip->base;6312 struct nand_ecc_ctrl *ecc = &chip->ecc;6313 int ret, i;6314 6315 /* New bad blocks should be marked in OOB, flash-based BBT, or both */6316 if (WARN_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&6317 !(chip->bbt_options & NAND_BBT_USE_FLASH))) {6318 return -EINVAL;6319 }6320 6321 chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);6322 if (!chip->data_buf)6323 return -ENOMEM;6324 6325 /*6326 * FIXME: some NAND manufacturer drivers expect the first die to be6327 * selected when manufacturer->init() is called. They should be fixed6328 * to explictly select the relevant die when interacting with the NAND6329 * chip.6330 */6331 nand_select_target(chip, 0);6332 ret = nand_manufacturer_init(chip);6333 nand_deselect_target(chip);6334 if (ret)6335 goto err_free_buf;6336 6337 /* Set the internal oob buffer location, just after the page data */6338 chip->oob_poi = chip->data_buf + mtd->writesize;6339 6340 /*6341 * If no default placement scheme is given, select an appropriate one.6342 */6343 if (!mtd->ooblayout &&6344 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&6345 ecc->algo == NAND_ECC_ALGO_BCH) &&6346 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&6347 ecc->algo == NAND_ECC_ALGO_HAMMING)) {6348 switch (mtd->oobsize) {6349 case 8:6350 case 16:6351 mtd_set_ooblayout(mtd, nand_get_small_page_ooblayout());6352 break;6353 case 64:6354 case 128:6355 mtd_set_ooblayout(mtd,6356 nand_get_large_page_hamming_ooblayout());6357 break;6358 default:6359 /*6360 * Expose the whole OOB area to users if ECC_NONE6361 * is passed. We could do that for all kind of6362 * ->oobsize, but we must keep the old large/small6363 * page with ECC layout when ->oobsize <= 128 for6364 * compatibility reasons.6365 */6366 if (ecc->engine_type == NAND_ECC_ENGINE_TYPE_NONE) {6367 mtd_set_ooblayout(mtd,6368 nand_get_large_page_ooblayout());6369 break;6370 }6371 6372 WARN(1, "No oob scheme defined for oobsize %d\n",6373 mtd->oobsize);6374 ret = -EINVAL;6375 goto err_nand_manuf_cleanup;6376 }6377 }6378 6379 /*6380 * Check ECC mode, default to software if 3byte/512byte hardware ECC is6381 * selected and we have 256 byte pagesize fallback to software ECC6382 */6383 6384 switch (ecc->engine_type) {6385 case NAND_ECC_ENGINE_TYPE_ON_HOST:6386 ret = nand_set_ecc_on_host_ops(chip);6387 if (ret)6388 goto err_nand_manuf_cleanup;6389 6390 if (mtd->writesize >= ecc->size) {6391 if (!ecc->strength) {6392 WARN(1, "Driver must set ecc.strength when using hardware ECC\n");6393 ret = -EINVAL;6394 goto err_nand_manuf_cleanup;6395 }6396 break;6397 }6398 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",6399 ecc->size, mtd->writesize);6400 ecc->engine_type = NAND_ECC_ENGINE_TYPE_SOFT;6401 ecc->algo = NAND_ECC_ALGO_HAMMING;6402 fallthrough;6403 6404 case NAND_ECC_ENGINE_TYPE_SOFT:6405 ret = nand_set_ecc_soft_ops(chip);6406 if (ret)6407 goto err_nand_manuf_cleanup;6408 break;6409 6410 case NAND_ECC_ENGINE_TYPE_ON_DIE:6411 if (!ecc->read_page || !ecc->write_page) {6412 WARN(1, "No ECC functions supplied; on-die ECC not possible\n");6413 ret = -EINVAL;6414 goto err_nand_manuf_cleanup;6415 }6416 if (!ecc->read_oob)6417 ecc->read_oob = nand_read_oob_std;6418 if (!ecc->write_oob)6419 ecc->write_oob = nand_write_oob_std;6420 break;6421 6422 case NAND_ECC_ENGINE_TYPE_NONE:6423 pr_warn("NAND_ECC_ENGINE_TYPE_NONE selected by board driver. This is not recommended!\n");6424 ecc->read_page = nand_read_page_raw;6425 ecc->write_page = nand_write_page_raw;6426 ecc->read_oob = nand_read_oob_std;6427 ecc->read_page_raw = nand_read_page_raw;6428 ecc->write_page_raw = nand_write_page_raw;6429 ecc->write_oob = nand_write_oob_std;6430 ecc->size = mtd->writesize;6431 ecc->bytes = 0;6432 ecc->strength = 0;6433 break;6434 6435 default:6436 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->engine_type);6437 ret = -EINVAL;6438 goto err_nand_manuf_cleanup;6439 }6440 6441 if (ecc->correct || ecc->calculate) {6442 ecc->calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL);6443 ecc->code_buf = kmalloc(mtd->oobsize, GFP_KERNEL);6444 if (!ecc->calc_buf || !ecc->code_buf) {6445 ret = -ENOMEM;6446 goto err_nand_manuf_cleanup;6447 }6448 }6449 6450 /* For many systems, the standard OOB write also works for raw */6451 if (!ecc->read_oob_raw)6452 ecc->read_oob_raw = ecc->read_oob;6453 if (!ecc->write_oob_raw)6454 ecc->write_oob_raw = ecc->write_oob;6455 6456 /* Propagate ECC info to the generic NAND and MTD layers */6457 mtd->ecc_strength = ecc->strength;6458 if (!base->ecc.ctx.conf.strength)6459 base->ecc.ctx.conf.strength = ecc->strength;6460 mtd->ecc_step_size = ecc->size;6461 if (!base->ecc.ctx.conf.step_size)6462 base->ecc.ctx.conf.step_size = ecc->size;6463 6464 /*6465 * Set the number of read / write steps for one page depending on ECC6466 * mode.6467 */6468 if (!ecc->steps)6469 ecc->steps = mtd->writesize / ecc->size;6470 if (!base->ecc.ctx.nsteps)6471 base->ecc.ctx.nsteps = ecc->steps;6472 if (ecc->steps * ecc->size != mtd->writesize) {6473 WARN(1, "Invalid ECC parameters\n");6474 ret = -EINVAL;6475 goto err_nand_manuf_cleanup;6476 }6477 6478 if (!ecc->total) {6479 ecc->total = ecc->steps * ecc->bytes;6480 chip->base.ecc.ctx.total = ecc->total;6481 }6482 6483 if (ecc->total > mtd->oobsize) {6484 WARN(1, "Total number of ECC bytes exceeded oobsize\n");6485 ret = -EINVAL;6486 goto err_nand_manuf_cleanup;6487 }6488 6489 /*6490 * The number of bytes available for a client to place data into6491 * the out of band area.6492 */6493 ret = mtd_ooblayout_count_freebytes(mtd);6494 if (ret < 0)6495 ret = 0;6496 6497 mtd->oobavail = ret;6498 6499 /* ECC sanity check: warn if it's too weak */6500 if (!nand_ecc_is_strong_enough(&chip->base))6501 pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one required by the NAND chip (%db/%dB)\n",6502 mtd->name, chip->ecc.strength, chip->ecc.size,6503 nanddev_get_ecc_requirements(&chip->base)->strength,6504 nanddev_get_ecc_requirements(&chip->base)->step_size);6505 6506 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */6507 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {6508 switch (ecc->steps) {6509 case 2:6510 mtd->subpage_sft = 1;6511 break;6512 case 4:6513 case 8:6514 case 16:6515 mtd->subpage_sft = 2;6516 break;6517 }6518 }6519 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;6520 6521 /* Invalidate the pagebuffer reference */6522 chip->pagecache.page = -1;6523 6524 /* Large page NAND with SOFT_ECC should support subpage reads */6525 switch (ecc->engine_type) {6526 case NAND_ECC_ENGINE_TYPE_SOFT:6527 if (chip->page_shift > 9)6528 chip->options |= NAND_SUBPAGE_READ;6529 break;6530 6531 default:6532 break;6533 }6534 6535 ret = nanddev_init(&chip->base, &rawnand_ops, mtd->owner);6536 if (ret)6537 goto err_nand_manuf_cleanup;6538 6539 /* Adjust the MTD_CAP_ flags when NAND_ROM is set. */6540 if (chip->options & NAND_ROM)6541 mtd->flags = MTD_CAP_ROM;6542 6543 /* Fill in remaining MTD driver data */6544 mtd->_erase = nand_erase;6545 mtd->_point = NULL;6546 mtd->_unpoint = NULL;6547 mtd->_panic_write = panic_nand_write;6548 mtd->_read_oob = nand_read_oob;6549 mtd->_write_oob = nand_write_oob;6550 mtd->_sync = nand_sync;6551 mtd->_lock = nand_lock;6552 mtd->_unlock = nand_unlock;6553 mtd->_suspend = nand_suspend;6554 mtd->_resume = nand_resume;6555 mtd->_reboot = nand_shutdown;6556 mtd->_block_isreserved = nand_block_isreserved;6557 mtd->_block_isbad = nand_block_isbad;6558 mtd->_block_markbad = nand_block_markbad;6559 mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks;6560 6561 /*6562 * Initialize bitflip_threshold to its default prior scan_bbt() call.6563 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be6564 * properly set.6565 */6566 if (!mtd->bitflip_threshold)6567 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);6568 6569 /* Find the fastest data interface for this chip */6570 ret = nand_choose_interface_config(chip);6571 if (ret)6572 goto err_nanddev_cleanup;6573 6574 /* Enter fastest possible mode on all dies. */6575 for (i = 0; i < nanddev_ntargets(&chip->base); i++) {6576 ret = nand_setup_interface(chip, i);6577 if (ret)6578 goto err_free_interface_config;6579 }6580 6581 rawnand_late_check_supported_ops(chip);6582 6583 /*6584 * Look for secure regions in the NAND chip. These regions are supposed6585 * to be protected by a secure element like Trustzone. So the read/write6586 * accesses to these regions will be blocked in the runtime by this6587 * driver.6588 */6589 ret = of_get_nand_secure_regions(chip);6590 if (ret)6591 goto err_free_interface_config;6592 6593 /* Check, if we should skip the bad block table scan */6594 if (chip->options & NAND_SKIP_BBTSCAN)6595 return 0;6596 6597 /* Build bad block table */6598 ret = nand_create_bbt(chip);6599 if (ret)6600 goto err_free_secure_regions;6601 6602 return 0;6603 6604err_free_secure_regions:6605 kfree(chip->secure_regions);6606 6607err_free_interface_config:6608 kfree(chip->best_interface_config);6609 6610err_nanddev_cleanup:6611 nanddev_cleanup(&chip->base);6612 6613err_nand_manuf_cleanup:6614 nand_manufacturer_cleanup(chip);6615 6616err_free_buf:6617 kfree(chip->data_buf);6618 kfree(ecc->code_buf);6619 kfree(ecc->calc_buf);6620 6621 return ret;6622}6623 6624static int nand_attach(struct nand_chip *chip)6625{6626 if (chip->controller->ops && chip->controller->ops->attach_chip)6627 return chip->controller->ops->attach_chip(chip);6628 6629 return 0;6630}6631 6632static void nand_detach(struct nand_chip *chip)6633{6634 if (chip->controller->ops && chip->controller->ops->detach_chip)6635 chip->controller->ops->detach_chip(chip);6636}6637 6638/**6639 * nand_scan_with_ids - [NAND Interface] Scan for the NAND device6640 * @chip: NAND chip object6641 * @maxchips: number of chips to scan for.6642 * @ids: optional flash IDs table6643 *6644 * This fills out all the uninitialized function pointers with the defaults.6645 * The flash ID is read and the mtd/chip structures are filled with the6646 * appropriate values.6647 */6648int nand_scan_with_ids(struct nand_chip *chip, unsigned int maxchips,6649 struct nand_flash_dev *ids)6650{6651 int ret;6652 6653 if (!maxchips)6654 return -EINVAL;6655 6656 ret = nand_scan_ident(chip, maxchips, ids);6657 if (ret)6658 return ret;6659 6660 ret = nand_attach(chip);6661 if (ret)6662 goto cleanup_ident;6663 6664 ret = nand_scan_tail(chip);6665 if (ret)6666 goto detach_chip;6667 6668 return 0;6669 6670detach_chip:6671 nand_detach(chip);6672cleanup_ident:6673 nand_scan_ident_cleanup(chip);6674 6675 return ret;6676}6677EXPORT_SYMBOL(nand_scan_with_ids);6678 6679/**6680 * nand_cleanup - [NAND Interface] Free resources held by the NAND device6681 * @chip: NAND chip object6682 */6683void nand_cleanup(struct nand_chip *chip)6684{6685 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) {6686 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)6687 rawnand_sw_hamming_cleanup(chip);6688 else if (chip->ecc.algo == NAND_ECC_ALGO_BCH)6689 rawnand_sw_bch_cleanup(chip);6690 }6691 6692 nanddev_cleanup(&chip->base);6693 6694 /* Free secure regions data */6695 kfree(chip->secure_regions);6696 6697 /* Free bad block table memory */6698 kfree(chip->bbt);6699 kfree(chip->data_buf);6700 kfree(chip->ecc.code_buf);6701 kfree(chip->ecc.calc_buf);6702 6703 /* Free bad block descriptor memory */6704 if (chip->badblock_pattern && chip->badblock_pattern->options6705 & NAND_BBT_DYNAMICSTRUCT)6706 kfree(chip->badblock_pattern);6707 6708 /* Free the data interface */6709 kfree(chip->best_interface_config);6710 6711 /* Free manufacturer priv data. */6712 nand_manufacturer_cleanup(chip);6713 6714 /* Free controller specific allocations after chip identification */6715 nand_detach(chip);6716 6717 /* Free identification phase allocations */6718 nand_scan_ident_cleanup(chip);6719}6720 6721EXPORT_SYMBOL_GPL(nand_cleanup);6722 6723MODULE_LICENSE("GPL");6724MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");6725MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");6726MODULE_DESCRIPTION("Generic NAND flash driver code");6727