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1// SPDX-License-Identifier: GPL-2.0-only2/*3 *4 * Copyright © 2012 John Crispin <john@phrozen.org>5 * Copyright © 2016 Hauke Mehrtens <hauke@hauke-m.de>6 */7 8#include <linux/mtd/rawnand.h>9#include <linux/of.h>10#include <linux/platform_device.h>11 12#include <lantiq_soc.h>13 14/* nand registers */15#define EBU_ADDSEL1 0x2416#define EBU_NAND_CON 0xB017#define EBU_NAND_WAIT 0xB418#define NAND_WAIT_RD BIT(0) /* NAND flash status output */19#define NAND_WAIT_WR_C BIT(3) /* NAND Write/Read complete */20#define EBU_NAND_ECC0 0xB821#define EBU_NAND_ECC_AC 0xBC22 23/*24 * nand commands25 * The pins of the NAND chip are selected based on the address bits of the26 * "register" read and write. There are no special registers, but an27 * address range and the lower address bits are used to activate the28 * correct line. For example when the bit (1 << 2) is set in the address29 * the ALE pin will be activated.30 */31#define NAND_CMD_ALE BIT(2) /* address latch enable */32#define NAND_CMD_CLE BIT(3) /* command latch enable */33#define NAND_CMD_CS BIT(4) /* chip select */34#define NAND_CMD_SE BIT(5) /* spare area access latch */35#define NAND_CMD_WP BIT(6) /* write protect */36#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE)37#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE)38#define NAND_WRITE_DATA (NAND_CMD_CS)39#define NAND_READ_DATA (NAND_CMD_CS)40 41/* we need to tel the ebu which addr we mapped the nand to */42#define ADDSEL1_MASK(x) (x << 4)43#define ADDSEL1_REGEN 144 45/* we need to tell the EBU that we have nand attached and set it up properly */46#define BUSCON1_SETUP (1 << 22)47#define BUSCON1_BCGEN_RES (0x3 << 12)48#define BUSCON1_WAITWRC2 (2 << 8)49#define BUSCON1_WAITRDC2 (2 << 6)50#define BUSCON1_HOLDC1 (1 << 4)51#define BUSCON1_RECOVC1 (1 << 2)52#define BUSCON1_CMULT4 153 54#define NAND_CON_CE (1 << 20)55#define NAND_CON_OUT_CS1 (1 << 10)56#define NAND_CON_IN_CS1 (1 << 8)57#define NAND_CON_PRE_P (1 << 7)58#define NAND_CON_WP_P (1 << 6)59#define NAND_CON_SE_P (1 << 5)60#define NAND_CON_CS_P (1 << 4)61#define NAND_CON_CSMUX (1 << 1)62#define NAND_CON_NANDM 163 64struct xway_nand_data {65 struct nand_controller controller;66 struct nand_chip chip;67 unsigned long csflags;68 void __iomem *nandaddr;69};70 71static u8 xway_readb(struct mtd_info *mtd, int op)72{73 struct nand_chip *chip = mtd_to_nand(mtd);74 struct xway_nand_data *data = nand_get_controller_data(chip);75 76 return readb(data->nandaddr + op);77}78 79static void xway_writeb(struct mtd_info *mtd, int op, u8 value)80{81 struct nand_chip *chip = mtd_to_nand(mtd);82 struct xway_nand_data *data = nand_get_controller_data(chip);83 84 writeb(value, data->nandaddr + op);85}86 87static void xway_select_chip(struct nand_chip *chip, int select)88{89 struct xway_nand_data *data = nand_get_controller_data(chip);90 91 switch (select) {92 case -1:93 ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);94 ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);95 spin_unlock_irqrestore(&ebu_lock, data->csflags);96 break;97 case 0:98 spin_lock_irqsave(&ebu_lock, data->csflags);99 ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);100 ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);101 break;102 default:103 BUG();104 }105}106 107static void xway_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl)108{109 struct mtd_info *mtd = nand_to_mtd(chip);110 111 if (cmd == NAND_CMD_NONE)112 return;113 114 if (ctrl & NAND_CLE)115 xway_writeb(mtd, NAND_WRITE_CMD, cmd);116 else if (ctrl & NAND_ALE)117 xway_writeb(mtd, NAND_WRITE_ADDR, cmd);118 119 while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)120 ;121}122 123static int xway_dev_ready(struct nand_chip *chip)124{125 return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;126}127 128static unsigned char xway_read_byte(struct nand_chip *chip)129{130 return xway_readb(nand_to_mtd(chip), NAND_READ_DATA);131}132 133static void xway_read_buf(struct nand_chip *chip, u_char *buf, int len)134{135 int i;136 137 for (i = 0; i < len; i++)138 buf[i] = xway_readb(nand_to_mtd(chip), NAND_WRITE_DATA);139}140 141static void xway_write_buf(struct nand_chip *chip, const u_char *buf, int len)142{143 int i;144 145 for (i = 0; i < len; i++)146 xway_writeb(nand_to_mtd(chip), NAND_WRITE_DATA, buf[i]);147}148 149static int xway_attach_chip(struct nand_chip *chip)150{151 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&152 chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)153 chip->ecc.algo = NAND_ECC_ALGO_HAMMING;154 155 return 0;156}157 158static const struct nand_controller_ops xway_nand_ops = {159 .attach_chip = xway_attach_chip,160};161 162/*163 * Probe for the NAND device.164 */165static int xway_nand_probe(struct platform_device *pdev)166{167 struct xway_nand_data *data;168 struct mtd_info *mtd;169 int err;170 u32 cs;171 u32 cs_flag = 0;172 173 /* Allocate memory for the device structure (and zero it) */174 data = devm_kzalloc(&pdev->dev, sizeof(struct xway_nand_data),175 GFP_KERNEL);176 if (!data)177 return -ENOMEM;178 179 data->nandaddr = devm_platform_ioremap_resource(pdev, 0);180 if (IS_ERR(data->nandaddr))181 return PTR_ERR(data->nandaddr);182 183 nand_set_flash_node(&data->chip, pdev->dev.of_node);184 mtd = nand_to_mtd(&data->chip);185 mtd->dev.parent = &pdev->dev;186 187 data->chip.legacy.cmd_ctrl = xway_cmd_ctrl;188 data->chip.legacy.dev_ready = xway_dev_ready;189 data->chip.legacy.select_chip = xway_select_chip;190 data->chip.legacy.write_buf = xway_write_buf;191 data->chip.legacy.read_buf = xway_read_buf;192 data->chip.legacy.read_byte = xway_read_byte;193 data->chip.legacy.chip_delay = 30;194 195 nand_controller_init(&data->controller);196 data->controller.ops = &xway_nand_ops;197 data->chip.controller = &data->controller;198 199 platform_set_drvdata(pdev, data);200 nand_set_controller_data(&data->chip, data);201 202 /* load our CS from the DT. Either we find a valid 1 or default to 0 */203 err = of_property_read_u32(pdev->dev.of_node, "lantiq,cs", &cs);204 if (!err && cs == 1)205 cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;206 207 /* setup the EBU to run in NAND mode on our base addr */208 ltq_ebu_w32(CPHYSADDR(data->nandaddr)209 | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);210 211 ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2212 | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1213 | BUSCON1_CMULT4, LTQ_EBU_BUSCON1);214 215 ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P216 | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P217 | cs_flag, EBU_NAND_CON);218 219 /*220 * This driver assumes that the default ECC engine should be TYPE_SOFT.221 * Set ->engine_type before registering the NAND devices in order to222 * provide a driver specific default value.223 */224 data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;225 226 /* Scan to find existence of the device */227 err = nand_scan(&data->chip, 1);228 if (err)229 return err;230 231 err = mtd_device_register(mtd, NULL, 0);232 if (err)233 nand_cleanup(&data->chip);234 235 return err;236}237 238/*239 * Remove a NAND device.240 */241static void xway_nand_remove(struct platform_device *pdev)242{243 struct xway_nand_data *data = platform_get_drvdata(pdev);244 struct nand_chip *chip = &data->chip;245 int ret;246 247 ret = mtd_device_unregister(nand_to_mtd(chip));248 WARN_ON(ret);249 nand_cleanup(chip);250}251 252static const struct of_device_id xway_nand_match[] = {253 { .compatible = "lantiq,nand-xway" },254 {},255};256 257static struct platform_driver xway_nand_driver = {258 .probe = xway_nand_probe,259 .remove_new = xway_nand_remove,260 .driver = {261 .name = "lantiq,nand-xway",262 .of_match_table = xway_nand_match,263 },264};265 266builtin_platform_driver(xway_nand_driver);267