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1// SPDX-License-Identifier: GPL-2.02/*3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c5 *6 * Copyright (C) 2005, Intec Automation Inc.7 * Copyright (C) 2014, Freescale Semiconductor, Inc.8 */9 10#include <linux/err.h>11#include <linux/errno.h>12#include <linux/delay.h>13#include <linux/device.h>14#include <linux/math64.h>15#include <linux/module.h>16#include <linux/mtd/mtd.h>17#include <linux/mtd/spi-nor.h>18#include <linux/mutex.h>19#include <linux/of_platform.h>20#include <linux/sched/task_stack.h>21#include <linux/sizes.h>22#include <linux/slab.h>23#include <linux/spi/flash.h>24 25#include "core.h"26 27/* Define max times to check status register before we give up. */28 29/*30 * For everything but full-chip erase; probably could be much smaller, but kept31 * around for safety for now32 */33#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)34 35/*36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up37 * for larger flash38 */39#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)40 41#define SPI_NOR_MAX_ADDR_NBYTES 442 43#define SPI_NOR_SRST_SLEEP_MIN 20044#define SPI_NOR_SRST_SLEEP_MAX 40045 46/**47 * spi_nor_get_cmd_ext() - Get the command opcode extension based on the48 * extension type.49 * @nor: pointer to a 'struct spi_nor'50 * @op: pointer to the 'struct spi_mem_op' whose properties51 * need to be initialized.52 *53 * Right now, only "repeat" and "invert" are supported.54 *55 * Return: The opcode extension.56 */57static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,58 const struct spi_mem_op *op)59{60 switch (nor->cmd_ext_type) {61 case SPI_NOR_EXT_INVERT:62 return ~op->cmd.opcode;63 64 case SPI_NOR_EXT_REPEAT:65 return op->cmd.opcode;66 67 default:68 dev_err(nor->dev, "Unknown command extension type\n");69 return 0;70 }71}72 73/**74 * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.75 * @nor: pointer to a 'struct spi_nor'76 * @op: pointer to the 'struct spi_mem_op' whose properties77 * need to be initialized.78 * @proto: the protocol from which the properties need to be set.79 */80void spi_nor_spimem_setup_op(const struct spi_nor *nor,81 struct spi_mem_op *op,82 const enum spi_nor_protocol proto)83{84 u8 ext;85 86 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto);87 88 if (op->addr.nbytes)89 op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);90 91 if (op->dummy.nbytes)92 op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);93 94 if (op->data.nbytes)95 op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);96 97 if (spi_nor_protocol_is_dtr(proto)) {98 /*99 * SPIMEM supports mixed DTR modes, but right now we can only100 * have all phases either DTR or STR. IOW, SPIMEM can have101 * something like 4S-4D-4D, but SPI NOR can't. So, set all 4102 * phases to either DTR or STR.103 */104 op->cmd.dtr = true;105 op->addr.dtr = true;106 op->dummy.dtr = true;107 op->data.dtr = true;108 109 /* 2 bytes per clock cycle in DTR mode. */110 op->dummy.nbytes *= 2;111 112 ext = spi_nor_get_cmd_ext(nor, op);113 op->cmd.opcode = (op->cmd.opcode << 8) | ext;114 op->cmd.nbytes = 2;115 }116}117 118/**119 * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data120 * transfer121 * @nor: pointer to 'struct spi_nor'122 * @op: pointer to 'struct spi_mem_op' template for transfer123 *124 * If we have to use the bounce buffer, the data field in @op will be updated.125 *126 * Return: true if the bounce buffer is needed, false if not127 */128static bool spi_nor_spimem_bounce(struct spi_nor *nor, struct spi_mem_op *op)129{130 /* op->data.buf.in occupies the same memory as op->data.buf.out */131 if (object_is_on_stack(op->data.buf.in) ||132 !virt_addr_valid(op->data.buf.in)) {133 if (op->data.nbytes > nor->bouncebuf_size)134 op->data.nbytes = nor->bouncebuf_size;135 op->data.buf.in = nor->bouncebuf;136 return true;137 }138 139 return false;140}141 142/**143 * spi_nor_spimem_exec_op() - execute a memory operation144 * @nor: pointer to 'struct spi_nor'145 * @op: pointer to 'struct spi_mem_op' template for transfer146 *147 * Return: 0 on success, -error otherwise.148 */149static int spi_nor_spimem_exec_op(struct spi_nor *nor, struct spi_mem_op *op)150{151 int error;152 153 error = spi_mem_adjust_op_size(nor->spimem, op);154 if (error)155 return error;156 157 return spi_mem_exec_op(nor->spimem, op);158}159 160int spi_nor_controller_ops_read_reg(struct spi_nor *nor, u8 opcode,161 u8 *buf, size_t len)162{163 if (spi_nor_protocol_is_dtr(nor->reg_proto))164 return -EOPNOTSUPP;165 166 return nor->controller_ops->read_reg(nor, opcode, buf, len);167}168 169int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,170 const u8 *buf, size_t len)171{172 if (spi_nor_protocol_is_dtr(nor->reg_proto))173 return -EOPNOTSUPP;174 175 return nor->controller_ops->write_reg(nor, opcode, buf, len);176}177 178static int spi_nor_controller_ops_erase(struct spi_nor *nor, loff_t offs)179{180 if (spi_nor_protocol_is_dtr(nor->reg_proto))181 return -EOPNOTSUPP;182 183 return nor->controller_ops->erase(nor, offs);184}185 186/**187 * spi_nor_spimem_read_data() - read data from flash's memory region via188 * spi-mem189 * @nor: pointer to 'struct spi_nor'190 * @from: offset to read from191 * @len: number of bytes to read192 * @buf: pointer to dst buffer193 *194 * Return: number of bytes read successfully, -errno otherwise195 */196static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,197 size_t len, u8 *buf)198{199 struct spi_mem_op op =200 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),201 SPI_MEM_OP_ADDR(nor->addr_nbytes, from, 0),202 SPI_MEM_OP_DUMMY(nor->read_dummy, 0),203 SPI_MEM_OP_DATA_IN(len, buf, 0));204 bool usebouncebuf;205 ssize_t nbytes;206 int error;207 208 spi_nor_spimem_setup_op(nor, &op, nor->read_proto);209 210 /* convert the dummy cycles to the number of bytes */211 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;212 if (spi_nor_protocol_is_dtr(nor->read_proto))213 op.dummy.nbytes *= 2;214 215 usebouncebuf = spi_nor_spimem_bounce(nor, &op);216 217 if (nor->dirmap.rdesc) {218 nbytes = spi_mem_dirmap_read(nor->dirmap.rdesc, op.addr.val,219 op.data.nbytes, op.data.buf.in);220 } else {221 error = spi_nor_spimem_exec_op(nor, &op);222 if (error)223 return error;224 nbytes = op.data.nbytes;225 }226 227 if (usebouncebuf && nbytes > 0)228 memcpy(buf, op.data.buf.in, nbytes);229 230 return nbytes;231}232 233/**234 * spi_nor_read_data() - read data from flash memory235 * @nor: pointer to 'struct spi_nor'236 * @from: offset to read from237 * @len: number of bytes to read238 * @buf: pointer to dst buffer239 *240 * Return: number of bytes read successfully, -errno otherwise241 */242ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf)243{244 if (nor->spimem)245 return spi_nor_spimem_read_data(nor, from, len, buf);246 247 return nor->controller_ops->read(nor, from, len, buf);248}249 250/**251 * spi_nor_spimem_write_data() - write data to flash memory via252 * spi-mem253 * @nor: pointer to 'struct spi_nor'254 * @to: offset to write to255 * @len: number of bytes to write256 * @buf: pointer to src buffer257 *258 * Return: number of bytes written successfully, -errno otherwise259 */260static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,261 size_t len, const u8 *buf)262{263 struct spi_mem_op op =264 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),265 SPI_MEM_OP_ADDR(nor->addr_nbytes, to, 0),266 SPI_MEM_OP_NO_DUMMY,267 SPI_MEM_OP_DATA_OUT(len, buf, 0));268 ssize_t nbytes;269 int error;270 271 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)272 op.addr.nbytes = 0;273 274 spi_nor_spimem_setup_op(nor, &op, nor->write_proto);275 276 if (spi_nor_spimem_bounce(nor, &op))277 memcpy(nor->bouncebuf, buf, op.data.nbytes);278 279 if (nor->dirmap.wdesc) {280 nbytes = spi_mem_dirmap_write(nor->dirmap.wdesc, op.addr.val,281 op.data.nbytes, op.data.buf.out);282 } else {283 error = spi_nor_spimem_exec_op(nor, &op);284 if (error)285 return error;286 nbytes = op.data.nbytes;287 }288 289 return nbytes;290}291 292/**293 * spi_nor_write_data() - write data to flash memory294 * @nor: pointer to 'struct spi_nor'295 * @to: offset to write to296 * @len: number of bytes to write297 * @buf: pointer to src buffer298 *299 * Return: number of bytes written successfully, -errno otherwise300 */301ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,302 const u8 *buf)303{304 if (nor->spimem)305 return spi_nor_spimem_write_data(nor, to, len, buf);306 307 return nor->controller_ops->write(nor, to, len, buf);308}309 310/**311 * spi_nor_read_any_reg() - read any register from flash memory, nonvolatile or312 * volatile.313 * @nor: pointer to 'struct spi_nor'.314 * @op: SPI memory operation. op->data.buf must be DMA-able.315 * @proto: SPI protocol to use for the register operation.316 *317 * Return: zero on success, -errno otherwise318 */319int spi_nor_read_any_reg(struct spi_nor *nor, struct spi_mem_op *op,320 enum spi_nor_protocol proto)321{322 if (!nor->spimem)323 return -EOPNOTSUPP;324 325 spi_nor_spimem_setup_op(nor, op, proto);326 return spi_nor_spimem_exec_op(nor, op);327}328 329/**330 * spi_nor_write_any_volatile_reg() - write any volatile register to flash331 * memory.332 * @nor: pointer to 'struct spi_nor'333 * @op: SPI memory operation. op->data.buf must be DMA-able.334 * @proto: SPI protocol to use for the register operation.335 *336 * Writing volatile registers are instant according to some manufacturers337 * (Cypress, Micron) and do not need any status polling.338 *339 * Return: zero on success, -errno otherwise340 */341int spi_nor_write_any_volatile_reg(struct spi_nor *nor, struct spi_mem_op *op,342 enum spi_nor_protocol proto)343{344 int ret;345 346 if (!nor->spimem)347 return -EOPNOTSUPP;348 349 ret = spi_nor_write_enable(nor);350 if (ret)351 return ret;352 spi_nor_spimem_setup_op(nor, op, proto);353 return spi_nor_spimem_exec_op(nor, op);354}355 356/**357 * spi_nor_write_enable() - Set write enable latch with Write Enable command.358 * @nor: pointer to 'struct spi_nor'.359 *360 * Return: 0 on success, -errno otherwise.361 */362int spi_nor_write_enable(struct spi_nor *nor)363{364 int ret;365 366 if (nor->spimem) {367 struct spi_mem_op op = SPI_NOR_WREN_OP;368 369 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);370 371 ret = spi_mem_exec_op(nor->spimem, &op);372 } else {373 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WREN,374 NULL, 0);375 }376 377 if (ret)378 dev_dbg(nor->dev, "error %d on Write Enable\n", ret);379 380 return ret;381}382 383/**384 * spi_nor_write_disable() - Send Write Disable instruction to the chip.385 * @nor: pointer to 'struct spi_nor'.386 *387 * Return: 0 on success, -errno otherwise.388 */389int spi_nor_write_disable(struct spi_nor *nor)390{391 int ret;392 393 if (nor->spimem) {394 struct spi_mem_op op = SPI_NOR_WRDI_OP;395 396 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);397 398 ret = spi_mem_exec_op(nor->spimem, &op);399 } else {400 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRDI,401 NULL, 0);402 }403 404 if (ret)405 dev_dbg(nor->dev, "error %d on Write Disable\n", ret);406 407 return ret;408}409 410/**411 * spi_nor_read_id() - Read the JEDEC ID.412 * @nor: pointer to 'struct spi_nor'.413 * @naddr: number of address bytes to send. Can be zero if the operation414 * does not need to send an address.415 * @ndummy: number of dummy bytes to send after an opcode or address. Can416 * be zero if the operation does not require dummy bytes.417 * @id: pointer to a DMA-able buffer where the value of the JEDEC ID418 * will be written.419 * @proto: the SPI protocol for register operation.420 *421 * Return: 0 on success, -errno otherwise.422 */423int spi_nor_read_id(struct spi_nor *nor, u8 naddr, u8 ndummy, u8 *id,424 enum spi_nor_protocol proto)425{426 int ret;427 428 if (nor->spimem) {429 struct spi_mem_op op =430 SPI_NOR_READID_OP(naddr, ndummy, id, SPI_NOR_MAX_ID_LEN);431 432 spi_nor_spimem_setup_op(nor, &op, proto);433 ret = spi_mem_exec_op(nor->spimem, &op);434 } else {435 ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,436 SPI_NOR_MAX_ID_LEN);437 }438 return ret;439}440 441/**442 * spi_nor_read_sr() - Read the Status Register.443 * @nor: pointer to 'struct spi_nor'.444 * @sr: pointer to a DMA-able buffer where the value of the445 * Status Register will be written. Should be at least 2 bytes.446 *447 * Return: 0 on success, -errno otherwise.448 */449int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)450{451 int ret;452 453 if (nor->spimem) {454 struct spi_mem_op op = SPI_NOR_RDSR_OP(sr);455 456 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {457 op.addr.nbytes = nor->params->rdsr_addr_nbytes;458 op.dummy.nbytes = nor->params->rdsr_dummy;459 /*460 * We don't want to read only one byte in DTR mode. So,461 * read 2 and then discard the second byte.462 */463 op.data.nbytes = 2;464 }465 466 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);467 468 ret = spi_mem_exec_op(nor->spimem, &op);469 } else {470 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,471 1);472 }473 474 if (ret)475 dev_dbg(nor->dev, "error %d reading SR\n", ret);476 477 return ret;478}479 480/**481 * spi_nor_read_cr() - Read the Configuration Register using the482 * SPINOR_OP_RDCR (35h) command.483 * @nor: pointer to 'struct spi_nor'484 * @cr: pointer to a DMA-able buffer where the value of the485 * Configuration Register will be written.486 *487 * Return: 0 on success, -errno otherwise.488 */489int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)490{491 int ret;492 493 if (nor->spimem) {494 struct spi_mem_op op = SPI_NOR_RDCR_OP(cr);495 496 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);497 498 ret = spi_mem_exec_op(nor->spimem, &op);499 } else {500 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDCR, cr,501 1);502 }503 504 if (ret)505 dev_dbg(nor->dev, "error %d reading CR\n", ret);506 507 return ret;508}509 510/**511 * spi_nor_set_4byte_addr_mode_en4b_ex4b() - Enter/Exit 4-byte address mode512 * using SPINOR_OP_EN4B/SPINOR_OP_EX4B. Typically used by513 * Winbond and Macronix.514 * @nor: pointer to 'struct spi_nor'.515 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte516 * address mode.517 *518 * Return: 0 on success, -errno otherwise.519 */520int spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor *nor, bool enable)521{522 int ret;523 524 if (nor->spimem) {525 struct spi_mem_op op = SPI_NOR_EN4B_EX4B_OP(enable);526 527 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);528 529 ret = spi_mem_exec_op(nor->spimem, &op);530 } else {531 ret = spi_nor_controller_ops_write_reg(nor,532 enable ? SPINOR_OP_EN4B :533 SPINOR_OP_EX4B,534 NULL, 0);535 }536 537 if (ret)538 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);539 540 return ret;541}542 543/**544 * spi_nor_set_4byte_addr_mode_wren_en4b_ex4b() - Set 4-byte address mode using545 * SPINOR_OP_WREN followed by SPINOR_OP_EN4B or SPINOR_OP_EX4B. Typically used546 * by ST and Micron flashes.547 * @nor: pointer to 'struct spi_nor'.548 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte549 * address mode.550 *551 * Return: 0 on success, -errno otherwise.552 */553int spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor *nor, bool enable)554{555 int ret;556 557 ret = spi_nor_write_enable(nor);558 if (ret)559 return ret;560 561 ret = spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable);562 if (ret)563 return ret;564 565 return spi_nor_write_disable(nor);566}567 568/**569 * spi_nor_set_4byte_addr_mode_brwr() - Set 4-byte address mode using570 * SPINOR_OP_BRWR. Typically used by Spansion flashes.571 * @nor: pointer to 'struct spi_nor'.572 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte573 * address mode.574 *575 * 8-bit volatile bank register used to define A[30:A24] bits. MSB (bit[7]) is576 * used to enable/disable 4-byte address mode. When MSB is set to ‘1’, 4-byte577 * address mode is active and A[30:24] bits are don’t care. Write instruction is578 * SPINOR_OP_BRWR(17h) with 1 byte of data.579 *580 * Return: 0 on success, -errno otherwise.581 */582int spi_nor_set_4byte_addr_mode_brwr(struct spi_nor *nor, bool enable)583{584 int ret;585 586 nor->bouncebuf[0] = enable << 7;587 588 if (nor->spimem) {589 struct spi_mem_op op = SPI_NOR_BRWR_OP(nor->bouncebuf);590 591 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);592 593 ret = spi_mem_exec_op(nor->spimem, &op);594 } else {595 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_BRWR,596 nor->bouncebuf, 1);597 }598 599 if (ret)600 dev_dbg(nor->dev, "error %d setting 4-byte mode\n", ret);601 602 return ret;603}604 605/**606 * spi_nor_sr_ready() - Query the Status Register to see if the flash is ready607 * for new commands.608 * @nor: pointer to 'struct spi_nor'.609 *610 * Return: 1 if ready, 0 if not ready, -errno on errors.611 */612int spi_nor_sr_ready(struct spi_nor *nor)613{614 int ret;615 616 ret = spi_nor_read_sr(nor, nor->bouncebuf);617 if (ret)618 return ret;619 620 return !(nor->bouncebuf[0] & SR_WIP);621}622 623/**624 * spi_nor_use_parallel_locking() - Checks if RWW locking scheme shall be used625 * @nor: pointer to 'struct spi_nor'.626 *627 * Return: true if parallel locking is enabled, false otherwise.628 */629static bool spi_nor_use_parallel_locking(struct spi_nor *nor)630{631 return nor->flags & SNOR_F_RWW;632}633 634/* Locking helpers for status read operations */635static int spi_nor_rww_start_rdst(struct spi_nor *nor)636{637 struct spi_nor_rww *rww = &nor->rww;638 int ret = -EAGAIN;639 640 mutex_lock(&nor->lock);641 642 if (rww->ongoing_io || rww->ongoing_rd)643 goto busy;644 645 rww->ongoing_io = true;646 rww->ongoing_rd = true;647 ret = 0;648 649busy:650 mutex_unlock(&nor->lock);651 return ret;652}653 654static void spi_nor_rww_end_rdst(struct spi_nor *nor)655{656 struct spi_nor_rww *rww = &nor->rww;657 658 mutex_lock(&nor->lock);659 660 rww->ongoing_io = false;661 rww->ongoing_rd = false;662 663 mutex_unlock(&nor->lock);664}665 666static int spi_nor_lock_rdst(struct spi_nor *nor)667{668 if (spi_nor_use_parallel_locking(nor))669 return spi_nor_rww_start_rdst(nor);670 671 return 0;672}673 674static void spi_nor_unlock_rdst(struct spi_nor *nor)675{676 if (spi_nor_use_parallel_locking(nor)) {677 spi_nor_rww_end_rdst(nor);678 wake_up(&nor->rww.wait);679 }680}681 682/**683 * spi_nor_ready() - Query the flash to see if it is ready for new commands.684 * @nor: pointer to 'struct spi_nor'.685 *686 * Return: 1 if ready, 0 if not ready, -errno on errors.687 */688static int spi_nor_ready(struct spi_nor *nor)689{690 int ret;691 692 ret = spi_nor_lock_rdst(nor);693 if (ret)694 return 0;695 696 /* Flashes might override the standard routine. */697 if (nor->params->ready)698 ret = nor->params->ready(nor);699 else700 ret = spi_nor_sr_ready(nor);701 702 spi_nor_unlock_rdst(nor);703 704 return ret;705}706 707/**708 * spi_nor_wait_till_ready_with_timeout() - Service routine to read the709 * Status Register until ready, or timeout occurs.710 * @nor: pointer to "struct spi_nor".711 * @timeout_jiffies: jiffies to wait until timeout.712 *713 * Return: 0 on success, -errno otherwise.714 */715static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,716 unsigned long timeout_jiffies)717{718 unsigned long deadline;719 int timeout = 0, ret;720 721 deadline = jiffies + timeout_jiffies;722 723 while (!timeout) {724 if (time_after_eq(jiffies, deadline))725 timeout = 1;726 727 ret = spi_nor_ready(nor);728 if (ret < 0)729 return ret;730 if (ret)731 return 0;732 733 cond_resched();734 }735 736 dev_dbg(nor->dev, "flash operation timed out\n");737 738 return -ETIMEDOUT;739}740 741/**742 * spi_nor_wait_till_ready() - Wait for a predefined amount of time for the743 * flash to be ready, or timeout occurs.744 * @nor: pointer to "struct spi_nor".745 *746 * Return: 0 on success, -errno otherwise.747 */748int spi_nor_wait_till_ready(struct spi_nor *nor)749{750 return spi_nor_wait_till_ready_with_timeout(nor,751 DEFAULT_READY_WAIT_JIFFIES);752}753 754/**755 * spi_nor_global_block_unlock() - Unlock Global Block Protection.756 * @nor: pointer to 'struct spi_nor'.757 *758 * Return: 0 on success, -errno otherwise.759 */760int spi_nor_global_block_unlock(struct spi_nor *nor)761{762 int ret;763 764 ret = spi_nor_write_enable(nor);765 if (ret)766 return ret;767 768 if (nor->spimem) {769 struct spi_mem_op op = SPI_NOR_GBULK_OP;770 771 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);772 773 ret = spi_mem_exec_op(nor->spimem, &op);774 } else {775 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_GBULK,776 NULL, 0);777 }778 779 if (ret) {780 dev_dbg(nor->dev, "error %d on Global Block Unlock\n", ret);781 return ret;782 }783 784 return spi_nor_wait_till_ready(nor);785}786 787/**788 * spi_nor_write_sr() - Write the Status Register.789 * @nor: pointer to 'struct spi_nor'.790 * @sr: pointer to DMA-able buffer to write to the Status Register.791 * @len: number of bytes to write to the Status Register.792 *793 * Return: 0 on success, -errno otherwise.794 */795int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)796{797 int ret;798 799 ret = spi_nor_write_enable(nor);800 if (ret)801 return ret;802 803 if (nor->spimem) {804 struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len);805 806 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);807 808 ret = spi_mem_exec_op(nor->spimem, &op);809 } else {810 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR, sr,811 len);812 }813 814 if (ret) {815 dev_dbg(nor->dev, "error %d writing SR\n", ret);816 return ret;817 }818 819 return spi_nor_wait_till_ready(nor);820}821 822/**823 * spi_nor_write_sr1_and_check() - Write one byte to the Status Register 1 and824 * ensure that the byte written match the received value.825 * @nor: pointer to a 'struct spi_nor'.826 * @sr1: byte value to be written to the Status Register.827 *828 * Return: 0 on success, -errno otherwise.829 */830static int spi_nor_write_sr1_and_check(struct spi_nor *nor, u8 sr1)831{832 int ret;833 834 nor->bouncebuf[0] = sr1;835 836 ret = spi_nor_write_sr(nor, nor->bouncebuf, 1);837 if (ret)838 return ret;839 840 ret = spi_nor_read_sr(nor, nor->bouncebuf);841 if (ret)842 return ret;843 844 if (nor->bouncebuf[0] != sr1) {845 dev_dbg(nor->dev, "SR1: read back test failed\n");846 return -EIO;847 }848 849 return 0;850}851 852/**853 * spi_nor_write_16bit_sr_and_check() - Write the Status Register 1 and the854 * Status Register 2 in one shot. Ensure that the byte written in the Status855 * Register 1 match the received value, and that the 16-bit Write did not856 * affect what was already in the Status Register 2.857 * @nor: pointer to a 'struct spi_nor'.858 * @sr1: byte value to be written to the Status Register 1.859 *860 * Return: 0 on success, -errno otherwise.861 */862static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)863{864 int ret;865 u8 *sr_cr = nor->bouncebuf;866 u8 cr_written;867 868 /* Make sure we don't overwrite the contents of Status Register 2. */869 if (!(nor->flags & SNOR_F_NO_READ_CR)) {870 ret = spi_nor_read_cr(nor, &sr_cr[1]);871 if (ret)872 return ret;873 } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 &&874 spi_nor_get_protocol_width(nor->write_proto) == 4 &&875 nor->params->quad_enable) {876 /*877 * If the Status Register 2 Read command (35h) is not878 * supported, we should at least be sure we don't879 * change the value of the SR2 Quad Enable bit.880 *881 * When the Quad Enable method is set and the buswidth is 4, we882 * can safely assume that the value of the QE bit is one, as a883 * consequence of the nor->params->quad_enable() call.884 *885 * According to the JESD216 revB standard, BFPT DWORDS[15],886 * bits 22:20, the 16-bit Write Status (01h) command is887 * available just for the cases in which the QE bit is888 * described in SR2 at BIT(1).889 */890 sr_cr[1] = SR2_QUAD_EN_BIT1;891 } else {892 sr_cr[1] = 0;893 }894 895 sr_cr[0] = sr1;896 897 ret = spi_nor_write_sr(nor, sr_cr, 2);898 if (ret)899 return ret;900 901 ret = spi_nor_read_sr(nor, sr_cr);902 if (ret)903 return ret;904 905 if (sr1 != sr_cr[0]) {906 dev_dbg(nor->dev, "SR: Read back test failed\n");907 return -EIO;908 }909 910 if (nor->flags & SNOR_F_NO_READ_CR)911 return 0;912 913 cr_written = sr_cr[1];914 915 ret = spi_nor_read_cr(nor, &sr_cr[1]);916 if (ret)917 return ret;918 919 if (cr_written != sr_cr[1]) {920 dev_dbg(nor->dev, "CR: read back test failed\n");921 return -EIO;922 }923 924 return 0;925}926 927/**928 * spi_nor_write_16bit_cr_and_check() - Write the Status Register 1 and the929 * Configuration Register in one shot. Ensure that the byte written in the930 * Configuration Register match the received value, and that the 16-bit Write931 * did not affect what was already in the Status Register 1.932 * @nor: pointer to a 'struct spi_nor'.933 * @cr: byte value to be written to the Configuration Register.934 *935 * Return: 0 on success, -errno otherwise.936 */937int spi_nor_write_16bit_cr_and_check(struct spi_nor *nor, u8 cr)938{939 int ret;940 u8 *sr_cr = nor->bouncebuf;941 u8 sr_written;942 943 /* Keep the current value of the Status Register 1. */944 ret = spi_nor_read_sr(nor, sr_cr);945 if (ret)946 return ret;947 948 sr_cr[1] = cr;949 950 ret = spi_nor_write_sr(nor, sr_cr, 2);951 if (ret)952 return ret;953 954 sr_written = sr_cr[0];955 956 ret = spi_nor_read_sr(nor, sr_cr);957 if (ret)958 return ret;959 960 if (sr_written != sr_cr[0]) {961 dev_dbg(nor->dev, "SR: Read back test failed\n");962 return -EIO;963 }964 965 if (nor->flags & SNOR_F_NO_READ_CR)966 return 0;967 968 ret = spi_nor_read_cr(nor, &sr_cr[1]);969 if (ret)970 return ret;971 972 if (cr != sr_cr[1]) {973 dev_dbg(nor->dev, "CR: read back test failed\n");974 return -EIO;975 }976 977 return 0;978}979 980/**981 * spi_nor_write_sr_and_check() - Write the Status Register 1 and ensure that982 * the byte written match the received value without affecting other bits in the983 * Status Register 1 and 2.984 * @nor: pointer to a 'struct spi_nor'.985 * @sr1: byte value to be written to the Status Register.986 *987 * Return: 0 on success, -errno otherwise.988 */989int spi_nor_write_sr_and_check(struct spi_nor *nor, u8 sr1)990{991 if (nor->flags & SNOR_F_HAS_16BIT_SR)992 return spi_nor_write_16bit_sr_and_check(nor, sr1);993 994 return spi_nor_write_sr1_and_check(nor, sr1);995}996 997/**998 * spi_nor_write_sr2() - Write the Status Register 2 using the999 * SPINOR_OP_WRSR2 (3eh) command.1000 * @nor: pointer to 'struct spi_nor'.1001 * @sr2: pointer to DMA-able buffer to write to the Status Register 2.1002 *1003 * Return: 0 on success, -errno otherwise.1004 */1005static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)1006{1007 int ret;1008 1009 ret = spi_nor_write_enable(nor);1010 if (ret)1011 return ret;1012 1013 if (nor->spimem) {1014 struct spi_mem_op op = SPI_NOR_WRSR2_OP(sr2);1015 1016 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);1017 1018 ret = spi_mem_exec_op(nor->spimem, &op);1019 } else {1020 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_WRSR2,1021 sr2, 1);1022 }1023 1024 if (ret) {1025 dev_dbg(nor->dev, "error %d writing SR2\n", ret);1026 return ret;1027 }1028 1029 return spi_nor_wait_till_ready(nor);1030}1031 1032/**1033 * spi_nor_read_sr2() - Read the Status Register 2 using the1034 * SPINOR_OP_RDSR2 (3fh) command.1035 * @nor: pointer to 'struct spi_nor'.1036 * @sr2: pointer to DMA-able buffer where the value of the1037 * Status Register 2 will be written.1038 *1039 * Return: 0 on success, -errno otherwise.1040 */1041static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)1042{1043 int ret;1044 1045 if (nor->spimem) {1046 struct spi_mem_op op = SPI_NOR_RDSR2_OP(sr2);1047 1048 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);1049 1050 ret = spi_mem_exec_op(nor->spimem, &op);1051 } else {1052 ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR2, sr2,1053 1);1054 }1055 1056 if (ret)1057 dev_dbg(nor->dev, "error %d reading SR2\n", ret);1058 1059 return ret;1060}1061 1062/**1063 * spi_nor_erase_die() - Erase the entire die.1064 * @nor: pointer to 'struct spi_nor'.1065 * @addr: address of the die.1066 * @die_size: size of the die.1067 *1068 * Return: 0 on success, -errno otherwise.1069 */1070static int spi_nor_erase_die(struct spi_nor *nor, loff_t addr, size_t die_size)1071{1072 bool multi_die = nor->mtd.size != die_size;1073 int ret;1074 1075 dev_dbg(nor->dev, " %lldKiB\n", (long long)(die_size >> 10));1076 1077 if (nor->spimem) {1078 struct spi_mem_op op =1079 SPI_NOR_DIE_ERASE_OP(nor->params->die_erase_opcode,1080 nor->addr_nbytes, addr, multi_die);1081 1082 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);1083 1084 ret = spi_mem_exec_op(nor->spimem, &op);1085 } else {1086 if (multi_die)1087 return -EOPNOTSUPP;1088 1089 ret = spi_nor_controller_ops_write_reg(nor,1090 SPINOR_OP_CHIP_ERASE,1091 NULL, 0);1092 }1093 1094 if (ret)1095 dev_dbg(nor->dev, "error %d erasing chip\n", ret);1096 1097 return ret;1098}1099 1100static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)1101{1102 size_t i;1103 1104 for (i = 0; i < size; i++)1105 if (table[i][0] == opcode)1106 return table[i][1];1107 1108 /* No conversion found, keep input op code. */1109 return opcode;1110}1111 1112u8 spi_nor_convert_3to4_read(u8 opcode)1113{1114 static const u8 spi_nor_3to4_read[][2] = {1115 { SPINOR_OP_READ, SPINOR_OP_READ_4B },1116 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },1117 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },1118 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },1119 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },1120 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },1121 { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },1122 { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },1123 1124 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },1125 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },1126 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B },1127 };1128 1129 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,1130 ARRAY_SIZE(spi_nor_3to4_read));1131}1132 1133static u8 spi_nor_convert_3to4_program(u8 opcode)1134{1135 static const u8 spi_nor_3to4_program[][2] = {1136 { SPINOR_OP_PP, SPINOR_OP_PP_4B },1137 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },1138 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },1139 { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },1140 { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },1141 };1142 1143 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,1144 ARRAY_SIZE(spi_nor_3to4_program));1145}1146 1147static u8 spi_nor_convert_3to4_erase(u8 opcode)1148{1149 static const u8 spi_nor_3to4_erase[][2] = {1150 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },1151 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },1152 { SPINOR_OP_SE, SPINOR_OP_SE_4B },1153 };1154 1155 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,1156 ARRAY_SIZE(spi_nor_3to4_erase));1157}1158 1159static bool spi_nor_has_uniform_erase(const struct spi_nor *nor)1160{1161 return !!nor->params->erase_map.uniform_region.erase_mask;1162}1163 1164static void spi_nor_set_4byte_opcodes(struct spi_nor *nor)1165{1166 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);1167 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);1168 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);1169 1170 if (!spi_nor_has_uniform_erase(nor)) {1171 struct spi_nor_erase_map *map = &nor->params->erase_map;1172 struct spi_nor_erase_type *erase;1173 int i;1174 1175 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {1176 erase = &map->erase_type[i];1177 erase->opcode =1178 spi_nor_convert_3to4_erase(erase->opcode);1179 }1180 }1181}1182 1183static int spi_nor_prep(struct spi_nor *nor)1184{1185 int ret = 0;1186 1187 if (nor->controller_ops && nor->controller_ops->prepare)1188 ret = nor->controller_ops->prepare(nor);1189 1190 return ret;1191}1192 1193static void spi_nor_unprep(struct spi_nor *nor)1194{1195 if (nor->controller_ops && nor->controller_ops->unprepare)1196 nor->controller_ops->unprepare(nor);1197}1198 1199static void spi_nor_offset_to_banks(u64 bank_size, loff_t start, size_t len,1200 u8 *first, u8 *last)1201{1202 /* This is currently safe, the number of banks being very small */1203 *first = DIV_ROUND_DOWN_ULL(start, bank_size);1204 *last = DIV_ROUND_DOWN_ULL(start + len - 1, bank_size);1205}1206 1207/* Generic helpers for internal locking and serialization */1208static bool spi_nor_rww_start_io(struct spi_nor *nor)1209{1210 struct spi_nor_rww *rww = &nor->rww;1211 bool start = false;1212 1213 mutex_lock(&nor->lock);1214 1215 if (rww->ongoing_io)1216 goto busy;1217 1218 rww->ongoing_io = true;1219 start = true;1220 1221busy:1222 mutex_unlock(&nor->lock);1223 return start;1224}1225 1226static void spi_nor_rww_end_io(struct spi_nor *nor)1227{1228 mutex_lock(&nor->lock);1229 nor->rww.ongoing_io = false;1230 mutex_unlock(&nor->lock);1231}1232 1233static int spi_nor_lock_device(struct spi_nor *nor)1234{1235 if (!spi_nor_use_parallel_locking(nor))1236 return 0;1237 1238 return wait_event_killable(nor->rww.wait, spi_nor_rww_start_io(nor));1239}1240 1241static void spi_nor_unlock_device(struct spi_nor *nor)1242{1243 if (spi_nor_use_parallel_locking(nor)) {1244 spi_nor_rww_end_io(nor);1245 wake_up(&nor->rww.wait);1246 }1247}1248 1249/* Generic helpers for internal locking and serialization */1250static bool spi_nor_rww_start_exclusive(struct spi_nor *nor)1251{1252 struct spi_nor_rww *rww = &nor->rww;1253 bool start = false;1254 1255 mutex_lock(&nor->lock);1256 1257 if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe)1258 goto busy;1259 1260 rww->ongoing_io = true;1261 rww->ongoing_rd = true;1262 rww->ongoing_pe = true;1263 start = true;1264 1265busy:1266 mutex_unlock(&nor->lock);1267 return start;1268}1269 1270static void spi_nor_rww_end_exclusive(struct spi_nor *nor)1271{1272 struct spi_nor_rww *rww = &nor->rww;1273 1274 mutex_lock(&nor->lock);1275 rww->ongoing_io = false;1276 rww->ongoing_rd = false;1277 rww->ongoing_pe = false;1278 mutex_unlock(&nor->lock);1279}1280 1281int spi_nor_prep_and_lock(struct spi_nor *nor)1282{1283 int ret;1284 1285 ret = spi_nor_prep(nor);1286 if (ret)1287 return ret;1288 1289 if (!spi_nor_use_parallel_locking(nor))1290 mutex_lock(&nor->lock);1291 else1292 ret = wait_event_killable(nor->rww.wait,1293 spi_nor_rww_start_exclusive(nor));1294 1295 return ret;1296}1297 1298void spi_nor_unlock_and_unprep(struct spi_nor *nor)1299{1300 if (!spi_nor_use_parallel_locking(nor)) {1301 mutex_unlock(&nor->lock);1302 } else {1303 spi_nor_rww_end_exclusive(nor);1304 wake_up(&nor->rww.wait);1305 }1306 1307 spi_nor_unprep(nor);1308}1309 1310/* Internal locking helpers for program and erase operations */1311static bool spi_nor_rww_start_pe(struct spi_nor *nor, loff_t start, size_t len)1312{1313 struct spi_nor_rww *rww = &nor->rww;1314 unsigned int used_banks = 0;1315 bool started = false;1316 u8 first, last;1317 int bank;1318 1319 mutex_lock(&nor->lock);1320 1321 if (rww->ongoing_io || rww->ongoing_rd || rww->ongoing_pe)1322 goto busy;1323 1324 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);1325 for (bank = first; bank <= last; bank++) {1326 if (rww->used_banks & BIT(bank))1327 goto busy;1328 1329 used_banks |= BIT(bank);1330 }1331 1332 rww->used_banks |= used_banks;1333 rww->ongoing_pe = true;1334 started = true;1335 1336busy:1337 mutex_unlock(&nor->lock);1338 return started;1339}1340 1341static void spi_nor_rww_end_pe(struct spi_nor *nor, loff_t start, size_t len)1342{1343 struct spi_nor_rww *rww = &nor->rww;1344 u8 first, last;1345 int bank;1346 1347 mutex_lock(&nor->lock);1348 1349 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);1350 for (bank = first; bank <= last; bank++)1351 rww->used_banks &= ~BIT(bank);1352 1353 rww->ongoing_pe = false;1354 1355 mutex_unlock(&nor->lock);1356}1357 1358static int spi_nor_prep_and_lock_pe(struct spi_nor *nor, loff_t start, size_t len)1359{1360 int ret;1361 1362 ret = spi_nor_prep(nor);1363 if (ret)1364 return ret;1365 1366 if (!spi_nor_use_parallel_locking(nor))1367 mutex_lock(&nor->lock);1368 else1369 ret = wait_event_killable(nor->rww.wait,1370 spi_nor_rww_start_pe(nor, start, len));1371 1372 return ret;1373}1374 1375static void spi_nor_unlock_and_unprep_pe(struct spi_nor *nor, loff_t start, size_t len)1376{1377 if (!spi_nor_use_parallel_locking(nor)) {1378 mutex_unlock(&nor->lock);1379 } else {1380 spi_nor_rww_end_pe(nor, start, len);1381 wake_up(&nor->rww.wait);1382 }1383 1384 spi_nor_unprep(nor);1385}1386 1387/* Internal locking helpers for read operations */1388static bool spi_nor_rww_start_rd(struct spi_nor *nor, loff_t start, size_t len)1389{1390 struct spi_nor_rww *rww = &nor->rww;1391 unsigned int used_banks = 0;1392 bool started = false;1393 u8 first, last;1394 int bank;1395 1396 mutex_lock(&nor->lock);1397 1398 if (rww->ongoing_io || rww->ongoing_rd)1399 goto busy;1400 1401 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);1402 for (bank = first; bank <= last; bank++) {1403 if (rww->used_banks & BIT(bank))1404 goto busy;1405 1406 used_banks |= BIT(bank);1407 }1408 1409 rww->used_banks |= used_banks;1410 rww->ongoing_io = true;1411 rww->ongoing_rd = true;1412 started = true;1413 1414busy:1415 mutex_unlock(&nor->lock);1416 return started;1417}1418 1419static void spi_nor_rww_end_rd(struct spi_nor *nor, loff_t start, size_t len)1420{1421 struct spi_nor_rww *rww = &nor->rww;1422 u8 first, last;1423 int bank;1424 1425 mutex_lock(&nor->lock);1426 1427 spi_nor_offset_to_banks(nor->params->bank_size, start, len, &first, &last);1428 for (bank = first; bank <= last; bank++)1429 nor->rww.used_banks &= ~BIT(bank);1430 1431 rww->ongoing_io = false;1432 rww->ongoing_rd = false;1433 1434 mutex_unlock(&nor->lock);1435}1436 1437static int spi_nor_prep_and_lock_rd(struct spi_nor *nor, loff_t start, size_t len)1438{1439 int ret;1440 1441 ret = spi_nor_prep(nor);1442 if (ret)1443 return ret;1444 1445 if (!spi_nor_use_parallel_locking(nor))1446 mutex_lock(&nor->lock);1447 else1448 ret = wait_event_killable(nor->rww.wait,1449 spi_nor_rww_start_rd(nor, start, len));1450 1451 return ret;1452}1453 1454static void spi_nor_unlock_and_unprep_rd(struct spi_nor *nor, loff_t start, size_t len)1455{1456 if (!spi_nor_use_parallel_locking(nor)) {1457 mutex_unlock(&nor->lock);1458 } else {1459 spi_nor_rww_end_rd(nor, start, len);1460 wake_up(&nor->rww.wait);1461 }1462 1463 spi_nor_unprep(nor);1464}1465 1466/*1467 * Initiate the erasure of a single sector1468 */1469int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)1470{1471 int i;1472 1473 if (nor->spimem) {1474 struct spi_mem_op op =1475 SPI_NOR_SECTOR_ERASE_OP(nor->erase_opcode,1476 nor->addr_nbytes, addr);1477 1478 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);1479 1480 return spi_mem_exec_op(nor->spimem, &op);1481 } else if (nor->controller_ops->erase) {1482 return spi_nor_controller_ops_erase(nor, addr);1483 }1484 1485 /*1486 * Default implementation, if driver doesn't have a specialized HW1487 * control1488 */1489 for (i = nor->addr_nbytes - 1; i >= 0; i--) {1490 nor->bouncebuf[i] = addr & 0xff;1491 addr >>= 8;1492 }1493 1494 return spi_nor_controller_ops_write_reg(nor, nor->erase_opcode,1495 nor->bouncebuf, nor->addr_nbytes);1496}1497 1498/**1499 * spi_nor_div_by_erase_size() - calculate remainder and update new dividend1500 * @erase: pointer to a structure that describes a SPI NOR erase type1501 * @dividend: dividend value1502 * @remainder: pointer to u32 remainder (will be updated)1503 *1504 * Return: the result of the division1505 */1506static u64 spi_nor_div_by_erase_size(const struct spi_nor_erase_type *erase,1507 u64 dividend, u32 *remainder)1508{1509 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */1510 *remainder = (u32)dividend & erase->size_mask;1511 return dividend >> erase->size_shift;1512}1513 1514/**1515 * spi_nor_find_best_erase_type() - find the best erase type for the given1516 * offset in the serial flash memory and the1517 * number of bytes to erase. The region in1518 * which the address fits is expected to be1519 * provided.1520 * @map: the erase map of the SPI NOR1521 * @region: pointer to a structure that describes a SPI NOR erase region1522 * @addr: offset in the serial flash memory1523 * @len: number of bytes to erase1524 *1525 * Return: a pointer to the best fitted erase type, NULL otherwise.1526 */1527static const struct spi_nor_erase_type *1528spi_nor_find_best_erase_type(const struct spi_nor_erase_map *map,1529 const struct spi_nor_erase_region *region,1530 u64 addr, u32 len)1531{1532 const struct spi_nor_erase_type *erase;1533 u32 rem;1534 int i;1535 1536 /*1537 * Erase types are ordered by size, with the smallest erase type at1538 * index 0.1539 */1540 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {1541 /* Does the erase region support the tested erase type? */1542 if (!(region->erase_mask & BIT(i)))1543 continue;1544 1545 erase = &map->erase_type[i];1546 if (!erase->size)1547 continue;1548 1549 /* Alignment is not mandatory for overlaid regions */1550 if (region->overlaid && region->size <= len)1551 return erase;1552 1553 /* Don't erase more than what the user has asked for. */1554 if (erase->size > len)1555 continue;1556 1557 spi_nor_div_by_erase_size(erase, addr, &rem);1558 if (!rem)1559 return erase;1560 }1561 1562 return NULL;1563}1564 1565/**1566 * spi_nor_init_erase_cmd() - initialize an erase command1567 * @region: pointer to a structure that describes a SPI NOR erase region1568 * @erase: pointer to a structure that describes a SPI NOR erase type1569 *1570 * Return: the pointer to the allocated erase command, ERR_PTR(-errno)1571 * otherwise.1572 */1573static struct spi_nor_erase_command *1574spi_nor_init_erase_cmd(const struct spi_nor_erase_region *region,1575 const struct spi_nor_erase_type *erase)1576{1577 struct spi_nor_erase_command *cmd;1578 1579 cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);1580 if (!cmd)1581 return ERR_PTR(-ENOMEM);1582 1583 INIT_LIST_HEAD(&cmd->list);1584 cmd->opcode = erase->opcode;1585 cmd->count = 1;1586 1587 if (region->overlaid)1588 cmd->size = region->size;1589 else1590 cmd->size = erase->size;1591 1592 return cmd;1593}1594 1595/**1596 * spi_nor_destroy_erase_cmd_list() - destroy erase command list1597 * @erase_list: list of erase commands1598 */1599static void spi_nor_destroy_erase_cmd_list(struct list_head *erase_list)1600{1601 struct spi_nor_erase_command *cmd, *next;1602 1603 list_for_each_entry_safe(cmd, next, erase_list, list) {1604 list_del(&cmd->list);1605 kfree(cmd);1606 }1607}1608 1609/**1610 * spi_nor_init_erase_cmd_list() - initialize erase command list1611 * @nor: pointer to a 'struct spi_nor'1612 * @erase_list: list of erase commands to be executed once we validate that the1613 * erase can be performed1614 * @addr: offset in the serial flash memory1615 * @len: number of bytes to erase1616 *1617 * Builds the list of best fitted erase commands and verifies if the erase can1618 * be performed.1619 *1620 * Return: 0 on success, -errno otherwise.1621 */1622static int spi_nor_init_erase_cmd_list(struct spi_nor *nor,1623 struct list_head *erase_list,1624 u64 addr, u32 len)1625{1626 const struct spi_nor_erase_map *map = &nor->params->erase_map;1627 const struct spi_nor_erase_type *erase, *prev_erase = NULL;1628 struct spi_nor_erase_region *region;1629 struct spi_nor_erase_command *cmd = NULL;1630 u64 region_end;1631 unsigned int i;1632 int ret = -EINVAL;1633 1634 for (i = 0; i < map->n_regions && len; i++) {1635 region = &map->regions[i];1636 region_end = region->offset + region->size;1637 1638 while (len && addr >= region->offset && addr < region_end) {1639 erase = spi_nor_find_best_erase_type(map, region, addr,1640 len);1641 if (!erase)1642 goto destroy_erase_cmd_list;1643 1644 if (prev_erase != erase || erase->size != cmd->size ||1645 region->overlaid) {1646 cmd = spi_nor_init_erase_cmd(region, erase);1647 if (IS_ERR(cmd)) {1648 ret = PTR_ERR(cmd);1649 goto destroy_erase_cmd_list;1650 }1651 1652 list_add_tail(&cmd->list, erase_list);1653 } else {1654 cmd->count++;1655 }1656 1657 len -= cmd->size;1658 addr += cmd->size;1659 prev_erase = erase;1660 }1661 }1662 1663 return 0;1664 1665destroy_erase_cmd_list:1666 spi_nor_destroy_erase_cmd_list(erase_list);1667 return ret;1668}1669 1670/**1671 * spi_nor_erase_multi_sectors() - perform a non-uniform erase1672 * @nor: pointer to a 'struct spi_nor'1673 * @addr: offset in the serial flash memory1674 * @len: number of bytes to erase1675 *1676 * Build a list of best fitted erase commands and execute it once we validate1677 * that the erase can be performed.1678 *1679 * Return: 0 on success, -errno otherwise.1680 */1681static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)1682{1683 LIST_HEAD(erase_list);1684 struct spi_nor_erase_command *cmd, *next;1685 int ret;1686 1687 ret = spi_nor_init_erase_cmd_list(nor, &erase_list, addr, len);1688 if (ret)1689 return ret;1690 1691 list_for_each_entry_safe(cmd, next, &erase_list, list) {1692 nor->erase_opcode = cmd->opcode;1693 while (cmd->count) {1694 dev_vdbg(nor->dev, "erase_cmd->size = 0x%08x, erase_cmd->opcode = 0x%02x, erase_cmd->count = %u\n",1695 cmd->size, cmd->opcode, cmd->count);1696 1697 ret = spi_nor_lock_device(nor);1698 if (ret)1699 goto destroy_erase_cmd_list;1700 1701 ret = spi_nor_write_enable(nor);1702 if (ret) {1703 spi_nor_unlock_device(nor);1704 goto destroy_erase_cmd_list;1705 }1706 1707 ret = spi_nor_erase_sector(nor, addr);1708 spi_nor_unlock_device(nor);1709 if (ret)1710 goto destroy_erase_cmd_list;1711 1712 ret = spi_nor_wait_till_ready(nor);1713 if (ret)1714 goto destroy_erase_cmd_list;1715 1716 addr += cmd->size;1717 cmd->count--;1718 }1719 list_del(&cmd->list);1720 kfree(cmd);1721 }1722 1723 return 0;1724 1725destroy_erase_cmd_list:1726 spi_nor_destroy_erase_cmd_list(&erase_list);1727 return ret;1728}1729 1730static int spi_nor_erase_dice(struct spi_nor *nor, loff_t addr,1731 size_t len, size_t die_size)1732{1733 unsigned long timeout;1734 int ret;1735 1736 /*1737 * Scale the timeout linearly with the size of the flash, with1738 * a minimum calibrated to an old 2MB flash. We could try to1739 * pull these from CFI/SFDP, but these values should be good1740 * enough for now.1741 */1742 timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,1743 CHIP_ERASE_2MB_READY_WAIT_JIFFIES *1744 (unsigned long)(nor->mtd.size / SZ_2M));1745 1746 do {1747 ret = spi_nor_lock_device(nor);1748 if (ret)1749 return ret;1750 1751 ret = spi_nor_write_enable(nor);1752 if (ret) {1753 spi_nor_unlock_device(nor);1754 return ret;1755 }1756 1757 ret = spi_nor_erase_die(nor, addr, die_size);1758 1759 spi_nor_unlock_device(nor);1760 if (ret)1761 return ret;1762 1763 ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);1764 if (ret)1765 return ret;1766 1767 addr += die_size;1768 len -= die_size;1769 1770 } while (len);1771 1772 return 0;1773}1774 1775/*1776 * Erase an address range on the nor chip. The address range may extend1777 * one or more erase sectors. Return an error if there is a problem erasing.1778 */1779static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)1780{1781 struct spi_nor *nor = mtd_to_spi_nor(mtd);1782 u8 n_dice = nor->params->n_dice;1783 bool multi_die_erase = false;1784 u32 addr, len, rem;1785 size_t die_size;1786 int ret;1787 1788 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,1789 (long long)instr->len);1790 1791 if (spi_nor_has_uniform_erase(nor)) {1792 div_u64_rem(instr->len, mtd->erasesize, &rem);1793 if (rem)1794 return -EINVAL;1795 }1796 1797 addr = instr->addr;1798 len = instr->len;1799 1800 if (n_dice) {1801 die_size = div_u64(mtd->size, n_dice);1802 if (!(len & (die_size - 1)) && !(addr & (die_size - 1)))1803 multi_die_erase = true;1804 } else {1805 die_size = mtd->size;1806 }1807 1808 ret = spi_nor_prep_and_lock_pe(nor, instr->addr, instr->len);1809 if (ret)1810 return ret;1811 1812 /* chip (die) erase? */1813 if ((len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) ||1814 multi_die_erase) {1815 ret = spi_nor_erase_dice(nor, addr, len, die_size);1816 if (ret)1817 goto erase_err;1818 1819 /* REVISIT in some cases we could speed up erasing large regions1820 * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up1821 * to use "small sector erase", but that's not always optimal.1822 */1823 1824 /* "sector"-at-a-time erase */1825 } else if (spi_nor_has_uniform_erase(nor)) {1826 while (len) {1827 ret = spi_nor_lock_device(nor);1828 if (ret)1829 goto erase_err;1830 1831 ret = spi_nor_write_enable(nor);1832 if (ret) {1833 spi_nor_unlock_device(nor);1834 goto erase_err;1835 }1836 1837 ret = spi_nor_erase_sector(nor, addr);1838 spi_nor_unlock_device(nor);1839 if (ret)1840 goto erase_err;1841 1842 ret = spi_nor_wait_till_ready(nor);1843 if (ret)1844 goto erase_err;1845 1846 addr += mtd->erasesize;1847 len -= mtd->erasesize;1848 }1849 1850 /* erase multiple sectors */1851 } else {1852 ret = spi_nor_erase_multi_sectors(nor, addr, len);1853 if (ret)1854 goto erase_err;1855 }1856 1857 ret = spi_nor_write_disable(nor);1858 1859erase_err:1860 spi_nor_unlock_and_unprep_pe(nor, instr->addr, instr->len);1861 1862 return ret;1863}1864 1865/**1866 * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status1867 * Register 1.1868 * @nor: pointer to a 'struct spi_nor'1869 *1870 * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories.1871 *1872 * Return: 0 on success, -errno otherwise.1873 */1874int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor)1875{1876 int ret;1877 1878 ret = spi_nor_read_sr(nor, nor->bouncebuf);1879 if (ret)1880 return ret;1881 1882 if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6)1883 return 0;1884 1885 nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6;1886 1887 return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]);1888}1889 1890/**1891 * spi_nor_sr2_bit1_quad_enable() - set the Quad Enable BIT(1) in the Status1892 * Register 2.1893 * @nor: pointer to a 'struct spi_nor'.1894 *1895 * Bit 1 of the Status Register 2 is the QE bit for Spansion like QSPI memories.1896 *1897 * Return: 0 on success, -errno otherwise.1898 */1899int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor)1900{1901 int ret;1902 1903 if (nor->flags & SNOR_F_NO_READ_CR)1904 return spi_nor_write_16bit_cr_and_check(nor, SR2_QUAD_EN_BIT1);1905 1906 ret = spi_nor_read_cr(nor, nor->bouncebuf);1907 if (ret)1908 return ret;1909 1910 if (nor->bouncebuf[0] & SR2_QUAD_EN_BIT1)1911 return 0;1912 1913 nor->bouncebuf[0] |= SR2_QUAD_EN_BIT1;1914 1915 return spi_nor_write_16bit_cr_and_check(nor, nor->bouncebuf[0]);1916}1917 1918/**1919 * spi_nor_sr2_bit7_quad_enable() - set QE bit in Status Register 2.1920 * @nor: pointer to a 'struct spi_nor'1921 *1922 * Set the Quad Enable (QE) bit in the Status Register 2.1923 *1924 * This is one of the procedures to set the QE bit described in the SFDP1925 * (JESD216 rev B) specification but no manufacturer using this procedure has1926 * been identified yet, hence the name of the function.1927 *1928 * Return: 0 on success, -errno otherwise.1929 */1930int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)1931{1932 u8 *sr2 = nor->bouncebuf;1933 int ret;1934 u8 sr2_written;1935 1936 /* Check current Quad Enable bit value. */1937 ret = spi_nor_read_sr2(nor, sr2);1938 if (ret)1939 return ret;1940 if (*sr2 & SR2_QUAD_EN_BIT7)1941 return 0;1942 1943 /* Update the Quad Enable bit. */1944 *sr2 |= SR2_QUAD_EN_BIT7;1945 1946 ret = spi_nor_write_sr2(nor, sr2);1947 if (ret)1948 return ret;1949 1950 sr2_written = *sr2;1951 1952 /* Read back and check it. */1953 ret = spi_nor_read_sr2(nor, sr2);1954 if (ret)1955 return ret;1956 1957 if (*sr2 != sr2_written) {1958 dev_dbg(nor->dev, "SR2: Read back test failed\n");1959 return -EIO;1960 }1961 1962 return 0;1963}1964 1965static const struct spi_nor_manufacturer *manufacturers[] = {1966 &spi_nor_atmel,1967 &spi_nor_eon,1968 &spi_nor_esmt,1969 &spi_nor_everspin,1970 &spi_nor_gigadevice,1971 &spi_nor_intel,1972 &spi_nor_issi,1973 &spi_nor_macronix,1974 &spi_nor_micron,1975 &spi_nor_st,1976 &spi_nor_spansion,1977 &spi_nor_sst,1978 &spi_nor_winbond,1979 &spi_nor_xmc,1980};1981 1982static const struct flash_info spi_nor_generic_flash = {1983 .name = "spi-nor-generic",1984};1985 1986static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,1987 const u8 *id)1988{1989 const struct flash_info *part;1990 unsigned int i, j;1991 1992 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {1993 for (j = 0; j < manufacturers[i]->nparts; j++) {1994 part = &manufacturers[i]->parts[j];1995 if (part->id &&1996 !memcmp(part->id->bytes, id, part->id->len)) {1997 nor->manufacturer = manufacturers[i];1998 return part;1999 }2000 }2001 }2002 2003 return NULL;2004}2005 2006static const struct flash_info *spi_nor_detect(struct spi_nor *nor)2007{2008 const struct flash_info *info;2009 u8 *id = nor->bouncebuf;2010 int ret;2011 2012 ret = spi_nor_read_id(nor, 0, 0, id, nor->reg_proto);2013 if (ret) {2014 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", ret);2015 return ERR_PTR(ret);2016 }2017 2018 /* Cache the complete flash ID. */2019 nor->id = devm_kmemdup(nor->dev, id, SPI_NOR_MAX_ID_LEN, GFP_KERNEL);2020 if (!nor->id)2021 return ERR_PTR(-ENOMEM);2022 2023 info = spi_nor_match_id(nor, id);2024 2025 /* Fallback to a generic flash described only by its SFDP data. */2026 if (!info) {2027 ret = spi_nor_check_sfdp_signature(nor);2028 if (!ret)2029 info = &spi_nor_generic_flash;2030 }2031 2032 if (!info) {2033 dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",2034 SPI_NOR_MAX_ID_LEN, id);2035 return ERR_PTR(-ENODEV);2036 }2037 return info;2038}2039 2040static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,2041 size_t *retlen, u_char *buf)2042{2043 struct spi_nor *nor = mtd_to_spi_nor(mtd);2044 loff_t from_lock = from;2045 size_t len_lock = len;2046 ssize_t ret;2047 2048 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);2049 2050 ret = spi_nor_prep_and_lock_rd(nor, from_lock, len_lock);2051 if (ret)2052 return ret;2053 2054 while (len) {2055 loff_t addr = from;2056 2057 ret = spi_nor_read_data(nor, addr, len, buf);2058 if (ret == 0) {2059 /* We shouldn't see 0-length reads */2060 ret = -EIO;2061 goto read_err;2062 }2063 if (ret < 0)2064 goto read_err;2065 2066 WARN_ON(ret > len);2067 *retlen += ret;2068 buf += ret;2069 from += ret;2070 len -= ret;2071 }2072 ret = 0;2073 2074read_err:2075 spi_nor_unlock_and_unprep_rd(nor, from_lock, len_lock);2076 2077 return ret;2078}2079 2080/*2081 * Write an address range to the nor chip. Data must be written in2082 * FLASH_PAGESIZE chunks. The address range may be any size provided2083 * it is within the physical boundaries.2084 */2085static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,2086 size_t *retlen, const u_char *buf)2087{2088 struct spi_nor *nor = mtd_to_spi_nor(mtd);2089 size_t i;2090 ssize_t ret;2091 u32 page_size = nor->params->page_size;2092 2093 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);2094 2095 ret = spi_nor_prep_and_lock_pe(nor, to, len);2096 if (ret)2097 return ret;2098 2099 for (i = 0; i < len; ) {2100 ssize_t written;2101 loff_t addr = to + i;2102 size_t page_offset = addr & (page_size - 1);2103 /* the size of data remaining on the first page */2104 size_t page_remain = min_t(size_t, page_size - page_offset, len - i);2105 2106 ret = spi_nor_lock_device(nor);2107 if (ret)2108 goto write_err;2109 2110 ret = spi_nor_write_enable(nor);2111 if (ret) {2112 spi_nor_unlock_device(nor);2113 goto write_err;2114 }2115 2116 ret = spi_nor_write_data(nor, addr, page_remain, buf + i);2117 spi_nor_unlock_device(nor);2118 if (ret < 0)2119 goto write_err;2120 written = ret;2121 2122 ret = spi_nor_wait_till_ready(nor);2123 if (ret)2124 goto write_err;2125 *retlen += written;2126 i += written;2127 }2128 2129write_err:2130 spi_nor_unlock_and_unprep_pe(nor, to, len);2131 2132 return ret;2133}2134 2135static int spi_nor_check(struct spi_nor *nor)2136{2137 if (!nor->dev ||2138 (!nor->spimem && !nor->controller_ops) ||2139 (!nor->spimem && nor->controller_ops &&2140 (!nor->controller_ops->read ||2141 !nor->controller_ops->write ||2142 !nor->controller_ops->read_reg ||2143 !nor->controller_ops->write_reg))) {2144 pr_err("spi-nor: please fill all the necessary fields!\n");2145 return -EINVAL;2146 }2147 2148 if (nor->spimem && nor->controller_ops) {2149 dev_err(nor->dev, "nor->spimem and nor->controller_ops are mutually exclusive, please set just one of them.\n");2150 return -EINVAL;2151 }2152 2153 return 0;2154}2155 2156void2157spi_nor_set_read_settings(struct spi_nor_read_command *read,2158 u8 num_mode_clocks,2159 u8 num_wait_states,2160 u8 opcode,2161 enum spi_nor_protocol proto)2162{2163 read->num_mode_clocks = num_mode_clocks;2164 read->num_wait_states = num_wait_states;2165 read->opcode = opcode;2166 read->proto = proto;2167}2168 2169void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, u8 opcode,2170 enum spi_nor_protocol proto)2171{2172 pp->opcode = opcode;2173 pp->proto = proto;2174}2175 2176static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size)2177{2178 size_t i;2179 2180 for (i = 0; i < size; i++)2181 if (table[i][0] == (int)hwcaps)2182 return table[i][1];2183 2184 return -EINVAL;2185}2186 2187int spi_nor_hwcaps_read2cmd(u32 hwcaps)2188{2189 static const int hwcaps_read2cmd[][2] = {2190 { SNOR_HWCAPS_READ, SNOR_CMD_READ },2191 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST },2192 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR },2193 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 },2194 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 },2195 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 },2196 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR },2197 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 },2198 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 },2199 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 },2200 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR },2201 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 },2202 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 },2203 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 },2204 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR },2205 { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR },2206 };2207 2208 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,2209 ARRAY_SIZE(hwcaps_read2cmd));2210}2211 2212int spi_nor_hwcaps_pp2cmd(u32 hwcaps)2213{2214 static const int hwcaps_pp2cmd[][2] = {2215 { SNOR_HWCAPS_PP, SNOR_CMD_PP },2216 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 },2217 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 },2218 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 },2219 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 },2220 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 },2221 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 },2222 { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR },2223 };2224 2225 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,2226 ARRAY_SIZE(hwcaps_pp2cmd));2227}2228 2229/**2230 * spi_nor_spimem_check_op - check if the operation is supported2231 * by controller2232 *@nor: pointer to a 'struct spi_nor'2233 *@op: pointer to op template to be checked2234 *2235 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.2236 */2237static int spi_nor_spimem_check_op(struct spi_nor *nor,2238 struct spi_mem_op *op)2239{2240 /*2241 * First test with 4 address bytes. The opcode itself might2242 * be a 3B addressing opcode but we don't care, because2243 * SPI controller implementation should not check the opcode,2244 * but just the sequence.2245 */2246 op->addr.nbytes = 4;2247 if (!spi_mem_supports_op(nor->spimem, op)) {2248 if (nor->params->size > SZ_16M)2249 return -EOPNOTSUPP;2250 2251 /* If flash size <= 16MB, 3 address bytes are sufficient */2252 op->addr.nbytes = 3;2253 if (!spi_mem_supports_op(nor->spimem, op))2254 return -EOPNOTSUPP;2255 }2256 2257 return 0;2258}2259 2260/**2261 * spi_nor_spimem_check_readop - check if the read op is supported2262 * by controller2263 *@nor: pointer to a 'struct spi_nor'2264 *@read: pointer to op template to be checked2265 *2266 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.2267 */2268static int spi_nor_spimem_check_readop(struct spi_nor *nor,2269 const struct spi_nor_read_command *read)2270{2271 struct spi_mem_op op = SPI_NOR_READ_OP(read->opcode);2272 2273 spi_nor_spimem_setup_op(nor, &op, read->proto);2274 2275 /* convert the dummy cycles to the number of bytes */2276 op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) *2277 op.dummy.buswidth / 8;2278 if (spi_nor_protocol_is_dtr(nor->read_proto))2279 op.dummy.nbytes *= 2;2280 2281 return spi_nor_spimem_check_op(nor, &op);2282}2283 2284/**2285 * spi_nor_spimem_check_pp - check if the page program op is supported2286 * by controller2287 *@nor: pointer to a 'struct spi_nor'2288 *@pp: pointer to op template to be checked2289 *2290 * Returns 0 if operation is supported, -EOPNOTSUPP otherwise.2291 */2292static int spi_nor_spimem_check_pp(struct spi_nor *nor,2293 const struct spi_nor_pp_command *pp)2294{2295 struct spi_mem_op op = SPI_NOR_PP_OP(pp->opcode);2296 2297 spi_nor_spimem_setup_op(nor, &op, pp->proto);2298 2299 return spi_nor_spimem_check_op(nor, &op);2300}2301 2302/**2303 * spi_nor_spimem_adjust_hwcaps - Find optimal Read/Write protocol2304 * based on SPI controller capabilities2305 * @nor: pointer to a 'struct spi_nor'2306 * @hwcaps: pointer to resulting capabilities after adjusting2307 * according to controller and flash's capability2308 */2309static void2310spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)2311{2312 struct spi_nor_flash_parameter *params = nor->params;2313 unsigned int cap;2314 2315 /* X-X-X modes are not supported yet, mask them all. */2316 *hwcaps &= ~SNOR_HWCAPS_X_X_X;2317 2318 /*2319 * If the reset line is broken, we do not want to enter a stateful2320 * mode.2321 */2322 if (nor->flags & SNOR_F_BROKEN_RESET)2323 *hwcaps &= ~(SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR);2324 2325 for (cap = 0; cap < sizeof(*hwcaps) * BITS_PER_BYTE; cap++) {2326 int rdidx, ppidx;2327 2328 if (!(*hwcaps & BIT(cap)))2329 continue;2330 2331 rdidx = spi_nor_hwcaps_read2cmd(BIT(cap));2332 if (rdidx >= 0 &&2333 spi_nor_spimem_check_readop(nor, ¶ms->reads[rdidx]))2334 *hwcaps &= ~BIT(cap);2335 2336 ppidx = spi_nor_hwcaps_pp2cmd(BIT(cap));2337 if (ppidx < 0)2338 continue;2339 2340 if (spi_nor_spimem_check_pp(nor,2341 ¶ms->page_programs[ppidx]))2342 *hwcaps &= ~BIT(cap);2343 }2344}2345 2346/**2347 * spi_nor_set_erase_type() - set a SPI NOR erase type2348 * @erase: pointer to a structure that describes a SPI NOR erase type2349 * @size: the size of the sector/block erased by the erase type2350 * @opcode: the SPI command op code to erase the sector/block2351 */2352void spi_nor_set_erase_type(struct spi_nor_erase_type *erase, u32 size,2353 u8 opcode)2354{2355 erase->size = size;2356 erase->opcode = opcode;2357 /* JEDEC JESD216B Standard imposes erase sizes to be power of 2. */2358 erase->size_shift = ffs(erase->size) - 1;2359 erase->size_mask = (1 << erase->size_shift) - 1;2360}2361 2362/**2363 * spi_nor_mask_erase_type() - mask out a SPI NOR erase type2364 * @erase: pointer to a structure that describes a SPI NOR erase type2365 */2366void spi_nor_mask_erase_type(struct spi_nor_erase_type *erase)2367{2368 erase->size = 0;2369}2370 2371/**2372 * spi_nor_init_uniform_erase_map() - Initialize uniform erase map2373 * @map: the erase map of the SPI NOR2374 * @erase_mask: bitmask encoding erase types that can erase the entire2375 * flash memory2376 * @flash_size: the spi nor flash memory size2377 */2378void spi_nor_init_uniform_erase_map(struct spi_nor_erase_map *map,2379 u8 erase_mask, u64 flash_size)2380{2381 map->uniform_region.offset = 0;2382 map->uniform_region.size = flash_size;2383 map->uniform_region.erase_mask = erase_mask;2384 map->regions = &map->uniform_region;2385 map->n_regions = 1;2386}2387 2388int spi_nor_post_bfpt_fixups(struct spi_nor *nor,2389 const struct sfdp_parameter_header *bfpt_header,2390 const struct sfdp_bfpt *bfpt)2391{2392 int ret;2393 2394 if (nor->manufacturer && nor->manufacturer->fixups &&2395 nor->manufacturer->fixups->post_bfpt) {2396 ret = nor->manufacturer->fixups->post_bfpt(nor, bfpt_header,2397 bfpt);2398 if (ret)2399 return ret;2400 }2401 2402 if (nor->info->fixups && nor->info->fixups->post_bfpt)2403 return nor->info->fixups->post_bfpt(nor, bfpt_header, bfpt);2404 2405 return 0;2406}2407 2408static int spi_nor_select_read(struct spi_nor *nor,2409 u32 shared_hwcaps)2410{2411 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1;2412 const struct spi_nor_read_command *read;2413 2414 if (best_match < 0)2415 return -EINVAL;2416 2417 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match));2418 if (cmd < 0)2419 return -EINVAL;2420 2421 read = &nor->params->reads[cmd];2422 nor->read_opcode = read->opcode;2423 nor->read_proto = read->proto;2424 2425 /*2426 * In the SPI NOR framework, we don't need to make the difference2427 * between mode clock cycles and wait state clock cycles.2428 * Indeed, the value of the mode clock cycles is used by a QSPI2429 * flash memory to know whether it should enter or leave its 0-4-42430 * (Continuous Read / XIP) mode.2431 * eXecution In Place is out of the scope of the mtd sub-system.2432 * Hence we choose to merge both mode and wait state clock cycles2433 * into the so called dummy clock cycles.2434 */2435 nor->read_dummy = read->num_mode_clocks + read->num_wait_states;2436 return 0;2437}2438 2439static int spi_nor_select_pp(struct spi_nor *nor,2440 u32 shared_hwcaps)2441{2442 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1;2443 const struct spi_nor_pp_command *pp;2444 2445 if (best_match < 0)2446 return -EINVAL;2447 2448 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match));2449 if (cmd < 0)2450 return -EINVAL;2451 2452 pp = &nor->params->page_programs[cmd];2453 nor->program_opcode = pp->opcode;2454 nor->write_proto = pp->proto;2455 return 0;2456}2457 2458/**2459 * spi_nor_select_uniform_erase() - select optimum uniform erase type2460 * @map: the erase map of the SPI NOR2461 *2462 * Once the optimum uniform sector erase command is found, disable all the2463 * other.2464 *2465 * Return: pointer to erase type on success, NULL otherwise.2466 */2467static const struct spi_nor_erase_type *2468spi_nor_select_uniform_erase(struct spi_nor_erase_map *map)2469{2470 const struct spi_nor_erase_type *tested_erase, *erase = NULL;2471 int i;2472 u8 uniform_erase_type = map->uniform_region.erase_mask;2473 2474 /*2475 * Search for the biggest erase size, except for when compiled2476 * to use 4k erases.2477 */2478 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {2479 if (!(uniform_erase_type & BIT(i)))2480 continue;2481 2482 tested_erase = &map->erase_type[i];2483 2484 /* Skip masked erase types. */2485 if (!tested_erase->size)2486 continue;2487 2488 /*2489 * If the current erase size is the 4k one, stop here,2490 * we have found the right uniform Sector Erase command.2491 */2492 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_USE_4K_SECTORS) &&2493 tested_erase->size == SZ_4K) {2494 erase = tested_erase;2495 break;2496 }2497 2498 /*2499 * Otherwise, the current erase size is still a valid candidate.2500 * Select the biggest valid candidate.2501 */2502 if (!erase && tested_erase->size)2503 erase = tested_erase;2504 /* keep iterating to find the wanted_size */2505 }2506 2507 if (!erase)2508 return NULL;2509 2510 /* Disable all other Sector Erase commands. */2511 map->uniform_region.erase_mask = BIT(erase - map->erase_type);2512 return erase;2513}2514 2515static int spi_nor_select_erase(struct spi_nor *nor)2516{2517 struct spi_nor_erase_map *map = &nor->params->erase_map;2518 const struct spi_nor_erase_type *erase = NULL;2519 struct mtd_info *mtd = &nor->mtd;2520 int i;2521 2522 /*2523 * The previous implementation handling Sector Erase commands assumed2524 * that the SPI flash memory has an uniform layout then used only one2525 * of the supported erase sizes for all Sector Erase commands.2526 * So to be backward compatible, the new implementation also tries to2527 * manage the SPI flash memory as uniform with a single erase sector2528 * size, when possible.2529 */2530 if (spi_nor_has_uniform_erase(nor)) {2531 erase = spi_nor_select_uniform_erase(map);2532 if (!erase)2533 return -EINVAL;2534 nor->erase_opcode = erase->opcode;2535 mtd->erasesize = erase->size;2536 return 0;2537 }2538 2539 /*2540 * For non-uniform SPI flash memory, set mtd->erasesize to the2541 * maximum erase sector size. No need to set nor->erase_opcode.2542 */2543 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {2544 if (map->erase_type[i].size) {2545 erase = &map->erase_type[i];2546 break;2547 }2548 }2549 2550 if (!erase)2551 return -EINVAL;2552 2553 mtd->erasesize = erase->size;2554 return 0;2555}2556 2557static int spi_nor_set_addr_nbytes(struct spi_nor *nor)2558{2559 if (nor->params->addr_nbytes) {2560 nor->addr_nbytes = nor->params->addr_nbytes;2561 } else if (nor->read_proto == SNOR_PROTO_8_8_8_DTR) {2562 /*2563 * In 8D-8D-8D mode, one byte takes half a cycle to transfer. So2564 * in this protocol an odd addr_nbytes cannot be used because2565 * then the address phase would only span a cycle and a half.2566 * Half a cycle would be left over. We would then have to start2567 * the dummy phase in the middle of a cycle and so too the data2568 * phase, and we will end the transaction with half a cycle left2569 * over.2570 *2571 * Force all 8D-8D-8D flashes to use an addr_nbytes of 4 to2572 * avoid this situation.2573 */2574 nor->addr_nbytes = 4;2575 } else if (nor->info->addr_nbytes) {2576 nor->addr_nbytes = nor->info->addr_nbytes;2577 } else {2578 nor->addr_nbytes = 3;2579 }2580 2581 if (nor->addr_nbytes == 3 && nor->params->size > 0x1000000) {2582 /* enable 4-byte addressing if the device exceeds 16MiB */2583 nor->addr_nbytes = 4;2584 }2585 2586 if (nor->addr_nbytes > SPI_NOR_MAX_ADDR_NBYTES) {2587 dev_dbg(nor->dev, "The number of address bytes is too large: %u\n",2588 nor->addr_nbytes);2589 return -EINVAL;2590 }2591 2592 /* Set 4byte opcodes when possible. */2593 if (nor->addr_nbytes == 4 && nor->flags & SNOR_F_4B_OPCODES &&2594 !(nor->flags & SNOR_F_HAS_4BAIT))2595 spi_nor_set_4byte_opcodes(nor);2596 2597 return 0;2598}2599 2600static int spi_nor_setup(struct spi_nor *nor,2601 const struct spi_nor_hwcaps *hwcaps)2602{2603 struct spi_nor_flash_parameter *params = nor->params;2604 u32 ignored_mask, shared_mask;2605 int err;2606 2607 /*2608 * Keep only the hardware capabilities supported by both the SPI2609 * controller and the SPI flash memory.2610 */2611 shared_mask = hwcaps->mask & params->hwcaps.mask;2612 2613 if (nor->spimem) {2614 /*2615 * When called from spi_nor_probe(), all caps are set and we2616 * need to discard some of them based on what the SPI2617 * controller actually supports (using spi_mem_supports_op()).2618 */2619 spi_nor_spimem_adjust_hwcaps(nor, &shared_mask);2620 } else {2621 /*2622 * SPI n-n-n protocols are not supported when the SPI2623 * controller directly implements the spi_nor interface.2624 * Yet another reason to switch to spi-mem.2625 */2626 ignored_mask = SNOR_HWCAPS_X_X_X | SNOR_HWCAPS_X_X_X_DTR;2627 if (shared_mask & ignored_mask) {2628 dev_dbg(nor->dev,2629 "SPI n-n-n protocols are not supported.\n");2630 shared_mask &= ~ignored_mask;2631 }2632 }2633 2634 /* Select the (Fast) Read command. */2635 err = spi_nor_select_read(nor, shared_mask);2636 if (err) {2637 dev_dbg(nor->dev,2638 "can't select read settings supported by both the SPI controller and memory.\n");2639 return err;2640 }2641 2642 /* Select the Page Program command. */2643 err = spi_nor_select_pp(nor, shared_mask);2644 if (err) {2645 dev_dbg(nor->dev,2646 "can't select write settings supported by both the SPI controller and memory.\n");2647 return err;2648 }2649 2650 /* Select the Sector Erase command. */2651 err = spi_nor_select_erase(nor);2652 if (err) {2653 dev_dbg(nor->dev,2654 "can't select erase settings supported by both the SPI controller and memory.\n");2655 return err;2656 }2657 2658 return spi_nor_set_addr_nbytes(nor);2659}2660 2661/**2662 * spi_nor_manufacturer_init_params() - Initialize the flash's parameters and2663 * settings based on MFR register and ->default_init() hook.2664 * @nor: pointer to a 'struct spi_nor'.2665 */2666static void spi_nor_manufacturer_init_params(struct spi_nor *nor)2667{2668 if (nor->manufacturer && nor->manufacturer->fixups &&2669 nor->manufacturer->fixups->default_init)2670 nor->manufacturer->fixups->default_init(nor);2671 2672 if (nor->info->fixups && nor->info->fixups->default_init)2673 nor->info->fixups->default_init(nor);2674}2675 2676/**2677 * spi_nor_no_sfdp_init_params() - Initialize the flash's parameters and2678 * settings based on nor->info->sfdp_flags. This method should be called only by2679 * flashes that do not define SFDP tables. If the flash supports SFDP but the2680 * information is wrong and the settings from this function can not be retrieved2681 * by parsing SFDP, one should instead use the fixup hooks and update the wrong2682 * bits.2683 * @nor: pointer to a 'struct spi_nor'.2684 */2685static void spi_nor_no_sfdp_init_params(struct spi_nor *nor)2686{2687 struct spi_nor_flash_parameter *params = nor->params;2688 struct spi_nor_erase_map *map = ¶ms->erase_map;2689 const struct flash_info *info = nor->info;2690 const u8 no_sfdp_flags = info->no_sfdp_flags;2691 u8 i, erase_mask;2692 2693 if (no_sfdp_flags & SPI_NOR_DUAL_READ) {2694 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;2695 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2],2696 0, 8, SPINOR_OP_READ_1_1_2,2697 SNOR_PROTO_1_1_2);2698 }2699 2700 if (no_sfdp_flags & SPI_NOR_QUAD_READ) {2701 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;2702 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4],2703 0, 8, SPINOR_OP_READ_1_1_4,2704 SNOR_PROTO_1_1_4);2705 }2706 2707 if (no_sfdp_flags & SPI_NOR_OCTAL_READ) {2708 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;2709 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],2710 0, 8, SPINOR_OP_READ_1_1_8,2711 SNOR_PROTO_1_1_8);2712 }2713 2714 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_READ) {2715 params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;2716 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],2717 0, 20, SPINOR_OP_READ_FAST,2718 SNOR_PROTO_8_8_8_DTR);2719 }2720 2721 if (no_sfdp_flags & SPI_NOR_OCTAL_DTR_PP) {2722 params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;2723 /*2724 * Since xSPI Page Program opcode is backward compatible with2725 * Legacy SPI, use Legacy SPI opcode there as well.2726 */2727 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR],2728 SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);2729 }2730 2731 /*2732 * Sector Erase settings. Sort Erase Types in ascending order, with the2733 * smallest erase size starting at BIT(0).2734 */2735 erase_mask = 0;2736 i = 0;2737 if (no_sfdp_flags & SECT_4K) {2738 erase_mask |= BIT(i);2739 spi_nor_set_erase_type(&map->erase_type[i], 4096u,2740 SPINOR_OP_BE_4K);2741 i++;2742 }2743 erase_mask |= BIT(i);2744 spi_nor_set_erase_type(&map->erase_type[i],2745 info->sector_size ?: SPI_NOR_DEFAULT_SECTOR_SIZE,2746 SPINOR_OP_SE);2747 spi_nor_init_uniform_erase_map(map, erase_mask, params->size);2748}2749 2750/**2751 * spi_nor_init_flags() - Initialize NOR flags for settings that are not defined2752 * in the JESD216 SFDP standard, thus can not be retrieved when parsing SFDP.2753 * @nor: pointer to a 'struct spi_nor'2754 */2755static void spi_nor_init_flags(struct spi_nor *nor)2756{2757 struct device_node *np = spi_nor_get_flash_node(nor);2758 const u16 flags = nor->info->flags;2759 2760 if (of_property_read_bool(np, "broken-flash-reset"))2761 nor->flags |= SNOR_F_BROKEN_RESET;2762 2763 if (of_property_read_bool(np, "no-wp"))2764 nor->flags |= SNOR_F_NO_WP;2765 2766 if (flags & SPI_NOR_SWP_IS_VOLATILE)2767 nor->flags |= SNOR_F_SWP_IS_VOLATILE;2768 2769 if (flags & SPI_NOR_HAS_LOCK)2770 nor->flags |= SNOR_F_HAS_LOCK;2771 2772 if (flags & SPI_NOR_HAS_TB) {2773 nor->flags |= SNOR_F_HAS_SR_TB;2774 if (flags & SPI_NOR_TB_SR_BIT6)2775 nor->flags |= SNOR_F_HAS_SR_TB_BIT6;2776 }2777 2778 if (flags & SPI_NOR_4BIT_BP) {2779 nor->flags |= SNOR_F_HAS_4BIT_BP;2780 if (flags & SPI_NOR_BP3_SR_BIT6)2781 nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;2782 }2783 2784 if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 &&2785 !nor->controller_ops)2786 nor->flags |= SNOR_F_RWW;2787}2788 2789/**2790 * spi_nor_init_fixup_flags() - Initialize NOR flags for settings that can not2791 * be discovered by SFDP for this particular flash because the SFDP table that2792 * indicates this support is not defined in the flash. In case the table for2793 * this support is defined but has wrong values, one should instead use a2794 * post_sfdp() hook to set the SNOR_F equivalent flag.2795 * @nor: pointer to a 'struct spi_nor'2796 */2797static void spi_nor_init_fixup_flags(struct spi_nor *nor)2798{2799 const u8 fixup_flags = nor->info->fixup_flags;2800 2801 if (fixup_flags & SPI_NOR_4B_OPCODES)2802 nor->flags |= SNOR_F_4B_OPCODES;2803 2804 if (fixup_flags & SPI_NOR_IO_MODE_EN_VOLATILE)2805 nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;2806}2807 2808/**2809 * spi_nor_late_init_params() - Late initialization of default flash parameters.2810 * @nor: pointer to a 'struct spi_nor'2811 *2812 * Used to initialize flash parameters that are not declared in the JESD2162813 * SFDP standard, or where SFDP tables are not defined at all.2814 * Will replace the spi_nor_manufacturer_init_params() method.2815 */2816static int spi_nor_late_init_params(struct spi_nor *nor)2817{2818 struct spi_nor_flash_parameter *params = nor->params;2819 int ret;2820 2821 if (nor->manufacturer && nor->manufacturer->fixups &&2822 nor->manufacturer->fixups->late_init) {2823 ret = nor->manufacturer->fixups->late_init(nor);2824 if (ret)2825 return ret;2826 }2827 2828 /* Needed by some flashes late_init hooks. */2829 spi_nor_init_flags(nor);2830 2831 if (nor->info->fixups && nor->info->fixups->late_init) {2832 ret = nor->info->fixups->late_init(nor);2833 if (ret)2834 return ret;2835 }2836 2837 if (!nor->params->die_erase_opcode)2838 nor->params->die_erase_opcode = SPINOR_OP_CHIP_ERASE;2839 2840 /* Default method kept for backward compatibility. */2841 if (!params->set_4byte_addr_mode)2842 params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_brwr;2843 2844 spi_nor_init_fixup_flags(nor);2845 2846 /*2847 * NOR protection support. When locking_ops are not provided, we pick2848 * the default ones.2849 */2850 if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops)2851 spi_nor_init_default_locking_ops(nor);2852 2853 if (params->n_banks > 1)2854 params->bank_size = div_u64(params->size, params->n_banks);2855 2856 return 0;2857}2858 2859/**2860 * spi_nor_sfdp_init_params_deprecated() - Deprecated way of initializing flash2861 * parameters and settings based on JESD216 SFDP standard.2862 * @nor: pointer to a 'struct spi_nor'.2863 *2864 * The method has a roll-back mechanism: in case the SFDP parsing fails, the2865 * legacy flash parameters and settings will be restored.2866 */2867static void spi_nor_sfdp_init_params_deprecated(struct spi_nor *nor)2868{2869 struct spi_nor_flash_parameter sfdp_params;2870 2871 memcpy(&sfdp_params, nor->params, sizeof(sfdp_params));2872 2873 if (spi_nor_parse_sfdp(nor)) {2874 memcpy(nor->params, &sfdp_params, sizeof(*nor->params));2875 nor->flags &= ~SNOR_F_4B_OPCODES;2876 }2877}2878 2879/**2880 * spi_nor_init_params_deprecated() - Deprecated way of initializing flash2881 * parameters and settings.2882 * @nor: pointer to a 'struct spi_nor'.2883 *2884 * The method assumes that flash doesn't support SFDP so it initializes flash2885 * parameters in spi_nor_no_sfdp_init_params() which later on can be overwritten2886 * when parsing SFDP, if supported.2887 */2888static void spi_nor_init_params_deprecated(struct spi_nor *nor)2889{2890 spi_nor_no_sfdp_init_params(nor);2891 2892 spi_nor_manufacturer_init_params(nor);2893 2894 if (nor->info->no_sfdp_flags & (SPI_NOR_DUAL_READ |2895 SPI_NOR_QUAD_READ |2896 SPI_NOR_OCTAL_READ |2897 SPI_NOR_OCTAL_DTR_READ))2898 spi_nor_sfdp_init_params_deprecated(nor);2899}2900 2901/**2902 * spi_nor_init_default_params() - Default initialization of flash parameters2903 * and settings. Done for all flashes, regardless is they define SFDP tables2904 * or not.2905 * @nor: pointer to a 'struct spi_nor'.2906 */2907static void spi_nor_init_default_params(struct spi_nor *nor)2908{2909 struct spi_nor_flash_parameter *params = nor->params;2910 const struct flash_info *info = nor->info;2911 struct device_node *np = spi_nor_get_flash_node(nor);2912 2913 params->quad_enable = spi_nor_sr2_bit1_quad_enable;2914 params->otp.org = info->otp;2915 2916 /* Default to 16-bit Write Status (01h) Command */2917 nor->flags |= SNOR_F_HAS_16BIT_SR;2918 2919 /* Set SPI NOR sizes. */2920 params->writesize = 1;2921 params->size = info->size;2922 params->bank_size = params->size;2923 params->page_size = info->page_size ?: SPI_NOR_DEFAULT_PAGE_SIZE;2924 params->n_banks = info->n_banks ?: SPI_NOR_DEFAULT_N_BANKS;2925 2926 /* Default to Fast Read for non-DT and enable it if requested by DT. */2927 if (!np || of_property_read_bool(np, "m25p,fast-read"))2928 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST;2929 2930 /* (Fast) Read settings. */2931 params->hwcaps.mask |= SNOR_HWCAPS_READ;2932 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ],2933 0, 0, SPINOR_OP_READ,2934 SNOR_PROTO_1_1_1);2935 2936 if (params->hwcaps.mask & SNOR_HWCAPS_READ_FAST)2937 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST],2938 0, 8, SPINOR_OP_READ_FAST,2939 SNOR_PROTO_1_1_1);2940 /* Page Program settings. */2941 params->hwcaps.mask |= SNOR_HWCAPS_PP;2942 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],2943 SPINOR_OP_PP, SNOR_PROTO_1_1_1);2944 2945 if (info->flags & SPI_NOR_QUAD_PP) {2946 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;2947 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],2948 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4);2949 }2950}2951 2952/**2953 * spi_nor_init_params() - Initialize the flash's parameters and settings.2954 * @nor: pointer to a 'struct spi_nor'.2955 *2956 * The flash parameters and settings are initialized based on a sequence of2957 * calls that are ordered by priority:2958 *2959 * 1/ Default flash parameters initialization. The initializations are done2960 * based on nor->info data:2961 * spi_nor_info_init_params()2962 *2963 * which can be overwritten by:2964 * 2/ Manufacturer flash parameters initialization. The initializations are2965 * done based on MFR register, or when the decisions can not be done solely2966 * based on MFR, by using specific flash_info tweeks, ->default_init():2967 * spi_nor_manufacturer_init_params()2968 *2969 * which can be overwritten by:2970 * 3/ SFDP flash parameters initialization. JESD216 SFDP is a standard and2971 * should be more accurate that the above.2972 * spi_nor_parse_sfdp() or spi_nor_no_sfdp_init_params()2973 *2974 * Please note that there is a ->post_bfpt() fixup hook that can overwrite2975 * the flash parameters and settings immediately after parsing the Basic2976 * Flash Parameter Table.2977 * spi_nor_post_sfdp_fixups() is called after the SFDP tables are parsed.2978 * It is used to tweak various flash parameters when information provided2979 * by the SFDP tables are wrong.2980 *2981 * which can be overwritten by:2982 * 4/ Late flash parameters initialization, used to initialize flash2983 * parameters that are not declared in the JESD216 SFDP standard, or where SFDP2984 * tables are not defined at all.2985 * spi_nor_late_init_params()2986 *2987 * Return: 0 on success, -errno otherwise.2988 */2989static int spi_nor_init_params(struct spi_nor *nor)2990{2991 int ret;2992 2993 nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL);2994 if (!nor->params)2995 return -ENOMEM;2996 2997 spi_nor_init_default_params(nor);2998 2999 if (spi_nor_needs_sfdp(nor)) {3000 ret = spi_nor_parse_sfdp(nor);3001 if (ret) {3002 dev_err(nor->dev, "BFPT parsing failed. Please consider using SPI_NOR_SKIP_SFDP when declaring the flash\n");3003 return ret;3004 }3005 } else if (nor->info->no_sfdp_flags & SPI_NOR_SKIP_SFDP) {3006 spi_nor_no_sfdp_init_params(nor);3007 } else {3008 spi_nor_init_params_deprecated(nor);3009 }3010 3011 ret = spi_nor_late_init_params(nor);3012 if (ret)3013 return ret;3014 3015 if (WARN_ON(!is_power_of_2(nor->params->page_size)))3016 return -EINVAL;3017 3018 return 0;3019}3020 3021/** spi_nor_set_octal_dtr() - enable or disable Octal DTR I/O.3022 * @nor: pointer to a 'struct spi_nor'3023 * @enable: whether to enable or disable Octal DTR3024 *3025 * Return: 0 on success, -errno otherwise.3026 */3027static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable)3028{3029 int ret;3030 3031 if (!nor->params->set_octal_dtr)3032 return 0;3033 3034 if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&3035 nor->write_proto == SNOR_PROTO_8_8_8_DTR))3036 return 0;3037 3038 if (!(nor->flags & SNOR_F_IO_MODE_EN_VOLATILE))3039 return 0;3040 3041 ret = nor->params->set_octal_dtr(nor, enable);3042 if (ret)3043 return ret;3044 3045 if (enable)3046 nor->reg_proto = SNOR_PROTO_8_8_8_DTR;3047 else3048 nor->reg_proto = SNOR_PROTO_1_1_1;3049 3050 return 0;3051}3052 3053/**3054 * spi_nor_quad_enable() - enable Quad I/O if needed.3055 * @nor: pointer to a 'struct spi_nor'3056 *3057 * Return: 0 on success, -errno otherwise.3058 */3059static int spi_nor_quad_enable(struct spi_nor *nor)3060{3061 if (!nor->params->quad_enable)3062 return 0;3063 3064 if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||3065 spi_nor_get_protocol_width(nor->write_proto) == 4))3066 return 0;3067 3068 return nor->params->quad_enable(nor);3069}3070 3071/**3072 * spi_nor_set_4byte_addr_mode() - Set address mode.3073 * @nor: pointer to a 'struct spi_nor'.3074 * @enable: enable/disable 4 byte address mode.3075 *3076 * Return: 0 on success, -errno otherwise.3077 */3078int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)3079{3080 struct spi_nor_flash_parameter *params = nor->params;3081 int ret;3082 3083 if (enable) {3084 /*3085 * If the RESET# pin isn't hooked up properly, or the system3086 * otherwise doesn't perform a reset command in the boot3087 * sequence, it's impossible to 100% protect against unexpected3088 * reboots (e.g., crashes). Warn the user (or hopefully, system3089 * designer) that this is bad.3090 */3091 WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,3092 "enabling reset hack; may not recover from unexpected reboots\n");3093 }3094 3095 ret = params->set_4byte_addr_mode(nor, enable);3096 if (ret && ret != -EOPNOTSUPP)3097 return ret;3098 3099 if (enable) {3100 params->addr_nbytes = 4;3101 params->addr_mode_nbytes = 4;3102 } else {3103 params->addr_nbytes = 3;3104 params->addr_mode_nbytes = 3;3105 }3106 3107 return 0;3108}3109 3110static int spi_nor_init(struct spi_nor *nor)3111{3112 int err;3113 3114 err = spi_nor_set_octal_dtr(nor, true);3115 if (err) {3116 dev_dbg(nor->dev, "octal mode not supported\n");3117 return err;3118 }3119 3120 err = spi_nor_quad_enable(nor);3121 if (err) {3122 dev_dbg(nor->dev, "quad mode not supported\n");3123 return err;3124 }3125 3126 /*3127 * Some SPI NOR flashes are write protected by default after a power-on3128 * reset cycle, in order to avoid inadvertent writes during power-up.3129 * Backward compatibility imposes to unlock the entire flash memory3130 * array at power-up by default. Depending on the kernel configuration3131 * (1) do nothing, (2) always unlock the entire flash array or (3)3132 * unlock the entire flash array only when the software write3133 * protection bits are volatile. The latter is indicated by3134 * SNOR_F_SWP_IS_VOLATILE.3135 */3136 if (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE) ||3137 (IS_ENABLED(CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE) &&3138 nor->flags & SNOR_F_SWP_IS_VOLATILE))3139 spi_nor_try_unlock_all(nor);3140 3141 if (nor->addr_nbytes == 4 &&3142 nor->read_proto != SNOR_PROTO_8_8_8_DTR &&3143 !(nor->flags & SNOR_F_4B_OPCODES))3144 return spi_nor_set_4byte_addr_mode(nor, true);3145 3146 return 0;3147}3148 3149/**3150 * spi_nor_soft_reset() - Perform a software reset3151 * @nor: pointer to 'struct spi_nor'3152 *3153 * Performs a "Soft Reset and Enter Default Protocol Mode" sequence which resets3154 * the device to its power-on-reset state. This is useful when the software has3155 * made some changes to device (volatile) registers and needs to reset it before3156 * shutting down, for example.3157 *3158 * Not every flash supports this sequence. The same set of opcodes might be used3159 * for some other operation on a flash that does not support this. Support for3160 * this sequence can be discovered via SFDP in the BFPT table.3161 *3162 * Return: 0 on success, -errno otherwise.3163 */3164static void spi_nor_soft_reset(struct spi_nor *nor)3165{3166 struct spi_mem_op op;3167 int ret;3168 3169 op = (struct spi_mem_op)SPINOR_SRSTEN_OP;3170 3171 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);3172 3173 ret = spi_mem_exec_op(nor->spimem, &op);3174 if (ret) {3175 if (ret != -EOPNOTSUPP)3176 dev_warn(nor->dev, "Software reset failed: %d\n", ret);3177 return;3178 }3179 3180 op = (struct spi_mem_op)SPINOR_SRST_OP;3181 3182 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);3183 3184 ret = spi_mem_exec_op(nor->spimem, &op);3185 if (ret) {3186 dev_warn(nor->dev, "Software reset failed: %d\n", ret);3187 return;3188 }3189 3190 /*3191 * Software Reset is not instant, and the delay varies from flash to3192 * flash. Looking at a few flashes, most range somewhere below 1003193 * microseconds. So, sleep for a range of 200-400 us.3194 */3195 usleep_range(SPI_NOR_SRST_SLEEP_MIN, SPI_NOR_SRST_SLEEP_MAX);3196}3197 3198/* mtd suspend handler */3199static int spi_nor_suspend(struct mtd_info *mtd)3200{3201 struct spi_nor *nor = mtd_to_spi_nor(mtd);3202 int ret;3203 3204 /* Disable octal DTR mode if we enabled it. */3205 ret = spi_nor_set_octal_dtr(nor, false);3206 if (ret)3207 dev_err(nor->dev, "suspend() failed\n");3208 3209 return ret;3210}3211 3212/* mtd resume handler */3213static void spi_nor_resume(struct mtd_info *mtd)3214{3215 struct spi_nor *nor = mtd_to_spi_nor(mtd);3216 struct device *dev = nor->dev;3217 int ret;3218 3219 /* re-initialize the nor chip */3220 ret = spi_nor_init(nor);3221 if (ret)3222 dev_err(dev, "resume() failed\n");3223}3224 3225static int spi_nor_get_device(struct mtd_info *mtd)3226{3227 struct mtd_info *master = mtd_get_master(mtd);3228 struct spi_nor *nor = mtd_to_spi_nor(master);3229 struct device *dev;3230 3231 if (nor->spimem)3232 dev = nor->spimem->spi->controller->dev.parent;3233 else3234 dev = nor->dev;3235 3236 if (!try_module_get(dev->driver->owner))3237 return -ENODEV;3238 3239 return 0;3240}3241 3242static void spi_nor_put_device(struct mtd_info *mtd)3243{3244 struct mtd_info *master = mtd_get_master(mtd);3245 struct spi_nor *nor = mtd_to_spi_nor(master);3246 struct device *dev;3247 3248 if (nor->spimem)3249 dev = nor->spimem->spi->controller->dev.parent;3250 else3251 dev = nor->dev;3252 3253 module_put(dev->driver->owner);3254}3255 3256static void spi_nor_restore(struct spi_nor *nor)3257{3258 int ret;3259 3260 /* restore the addressing mode */3261 if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&3262 nor->flags & SNOR_F_BROKEN_RESET) {3263 ret = spi_nor_set_4byte_addr_mode(nor, false);3264 if (ret)3265 /*3266 * Do not stop the execution in the hope that the flash3267 * will default to the 3-byte address mode after the3268 * software reset.3269 */3270 dev_err(nor->dev, "Failed to exit 4-byte address mode, err = %d\n", ret);3271 }3272 3273 if (nor->flags & SNOR_F_SOFT_RESET)3274 spi_nor_soft_reset(nor);3275}3276 3277static const struct flash_info *spi_nor_match_name(struct spi_nor *nor,3278 const char *name)3279{3280 unsigned int i, j;3281 3282 for (i = 0; i < ARRAY_SIZE(manufacturers); i++) {3283 for (j = 0; j < manufacturers[i]->nparts; j++) {3284 if (manufacturers[i]->parts[j].name &&3285 !strcmp(name, manufacturers[i]->parts[j].name)) {3286 nor->manufacturer = manufacturers[i];3287 return &manufacturers[i]->parts[j];3288 }3289 }3290 }3291 3292 return NULL;3293}3294 3295static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,3296 const char *name)3297{3298 const struct flash_info *info = NULL;3299 3300 if (name)3301 info = spi_nor_match_name(nor, name);3302 /*3303 * Auto-detect if chip name wasn't specified or not found, or the chip3304 * has an ID. If the chip supposedly has an ID, we also do an3305 * auto-detection to compare it later.3306 */3307 if (!info || info->id) {3308 const struct flash_info *jinfo;3309 3310 jinfo = spi_nor_detect(nor);3311 if (IS_ERR(jinfo))3312 return jinfo;3313 3314 /*3315 * If caller has specified name of flash model that can normally3316 * be detected using JEDEC, let's verify it.3317 */3318 if (info && jinfo != info)3319 dev_warn(nor->dev, "found %s, expected %s\n",3320 jinfo->name, info->name);3321 3322 /* If info was set before, JEDEC knows better. */3323 info = jinfo;3324 }3325 3326 return info;3327}3328 3329static u323330spi_nor_get_region_erasesize(const struct spi_nor_erase_region *region,3331 const struct spi_nor_erase_type *erase_type)3332{3333 int i;3334 3335 if (region->overlaid)3336 return region->size;3337 3338 for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {3339 if (region->erase_mask & BIT(i))3340 return erase_type[i].size;3341 }3342 3343 return 0;3344}3345 3346static int spi_nor_set_mtd_eraseregions(struct spi_nor *nor)3347{3348 const struct spi_nor_erase_map *map = &nor->params->erase_map;3349 const struct spi_nor_erase_region *region = map->regions;3350 struct mtd_erase_region_info *mtd_region;3351 struct mtd_info *mtd = &nor->mtd;3352 u32 erasesize, i;3353 3354 mtd_region = devm_kcalloc(nor->dev, map->n_regions, sizeof(*mtd_region),3355 GFP_KERNEL);3356 if (!mtd_region)3357 return -ENOMEM;3358 3359 for (i = 0; i < map->n_regions; i++) {3360 erasesize = spi_nor_get_region_erasesize(®ion[i],3361 map->erase_type);3362 if (!erasesize)3363 return -EINVAL;3364 3365 mtd_region[i].erasesize = erasesize;3366 mtd_region[i].numblocks = div_u64(region[i].size, erasesize);3367 mtd_region[i].offset = region[i].offset;3368 }3369 3370 mtd->numeraseregions = map->n_regions;3371 mtd->eraseregions = mtd_region;3372 3373 return 0;3374}3375 3376static int spi_nor_set_mtd_info(struct spi_nor *nor)3377{3378 struct mtd_info *mtd = &nor->mtd;3379 struct device *dev = nor->dev;3380 3381 spi_nor_set_mtd_locking_ops(nor);3382 spi_nor_set_mtd_otp_ops(nor);3383 3384 mtd->dev.parent = dev;3385 if (!mtd->name)3386 mtd->name = dev_name(dev);3387 mtd->type = MTD_NORFLASH;3388 mtd->flags = MTD_CAP_NORFLASH;3389 /* Unset BIT_WRITEABLE to enable JFFS2 write buffer for ECC'd NOR */3390 if (nor->flags & SNOR_F_ECC)3391 mtd->flags &= ~MTD_BIT_WRITEABLE;3392 if (nor->info->flags & SPI_NOR_NO_ERASE)3393 mtd->flags |= MTD_NO_ERASE;3394 else3395 mtd->_erase = spi_nor_erase;3396 mtd->writesize = nor->params->writesize;3397 mtd->writebufsize = nor->params->page_size;3398 mtd->size = nor->params->size;3399 mtd->_read = spi_nor_read;3400 /* Might be already set by some SST flashes. */3401 if (!mtd->_write)3402 mtd->_write = spi_nor_write;3403 mtd->_suspend = spi_nor_suspend;3404 mtd->_resume = spi_nor_resume;3405 mtd->_get_device = spi_nor_get_device;3406 mtd->_put_device = spi_nor_put_device;3407 3408 if (!spi_nor_has_uniform_erase(nor))3409 return spi_nor_set_mtd_eraseregions(nor);3410 3411 return 0;3412}3413 3414static int spi_nor_hw_reset(struct spi_nor *nor)3415{3416 struct gpio_desc *reset;3417 3418 reset = devm_gpiod_get_optional(nor->dev, "reset", GPIOD_OUT_LOW);3419 if (IS_ERR_OR_NULL(reset))3420 return PTR_ERR_OR_ZERO(reset);3421 3422 /*3423 * Experimental delay values by looking at different flash device3424 * vendors datasheets.3425 */3426 usleep_range(1, 5);3427 gpiod_set_value_cansleep(reset, 1);3428 usleep_range(100, 150);3429 gpiod_set_value_cansleep(reset, 0);3430 usleep_range(1000, 1200);3431 3432 return 0;3433}3434 3435int spi_nor_scan(struct spi_nor *nor, const char *name,3436 const struct spi_nor_hwcaps *hwcaps)3437{3438 const struct flash_info *info;3439 struct device *dev = nor->dev;3440 int ret;3441 3442 ret = spi_nor_check(nor);3443 if (ret)3444 return ret;3445 3446 /* Reset SPI protocol for all commands. */3447 nor->reg_proto = SNOR_PROTO_1_1_1;3448 nor->read_proto = SNOR_PROTO_1_1_1;3449 nor->write_proto = SNOR_PROTO_1_1_1;3450 3451 /*3452 * We need the bounce buffer early to read/write registers when going3453 * through the spi-mem layer (buffers have to be DMA-able).3454 * For spi-mem drivers, we'll reallocate a new buffer if3455 * nor->params->page_size turns out to be greater than PAGE_SIZE (which3456 * shouldn't happen before long since NOR pages are usually less3457 * than 1KB) after spi_nor_scan() returns.3458 */3459 nor->bouncebuf_size = PAGE_SIZE;3460 nor->bouncebuf = devm_kmalloc(dev, nor->bouncebuf_size,3461 GFP_KERNEL);3462 if (!nor->bouncebuf)3463 return -ENOMEM;3464 3465 ret = spi_nor_hw_reset(nor);3466 if (ret)3467 return ret;3468 3469 info = spi_nor_get_flash_info(nor, name);3470 if (IS_ERR(info))3471 return PTR_ERR(info);3472 3473 nor->info = info;3474 3475 mutex_init(&nor->lock);3476 3477 /* Init flash parameters based on flash_info struct and SFDP */3478 ret = spi_nor_init_params(nor);3479 if (ret)3480 return ret;3481 3482 if (spi_nor_use_parallel_locking(nor))3483 init_waitqueue_head(&nor->rww.wait);3484 3485 /*3486 * Configure the SPI memory:3487 * - select op codes for (Fast) Read, Page Program and Sector Erase.3488 * - set the number of dummy cycles (mode cycles + wait states).3489 * - set the SPI protocols for register and memory accesses.3490 * - set the number of address bytes.3491 */3492 ret = spi_nor_setup(nor, hwcaps);3493 if (ret)3494 return ret;3495 3496 /* Send all the required SPI flash commands to initialize device */3497 ret = spi_nor_init(nor);3498 if (ret)3499 return ret;3500 3501 /* No mtd_info fields should be used up to this point. */3502 ret = spi_nor_set_mtd_info(nor);3503 if (ret)3504 return ret;3505 3506 dev_dbg(dev, "Manufacturer and device ID: %*phN\n",3507 SPI_NOR_MAX_ID_LEN, nor->id);3508 3509 return 0;3510}3511EXPORT_SYMBOL_GPL(spi_nor_scan);3512 3513static int spi_nor_create_read_dirmap(struct spi_nor *nor)3514{3515 struct spi_mem_dirmap_info info = {3516 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),3517 SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),3518 SPI_MEM_OP_DUMMY(nor->read_dummy, 0),3519 SPI_MEM_OP_DATA_IN(0, NULL, 0)),3520 .offset = 0,3521 .length = nor->params->size,3522 };3523 struct spi_mem_op *op = &info.op_tmpl;3524 3525 spi_nor_spimem_setup_op(nor, op, nor->read_proto);3526 3527 /* convert the dummy cycles to the number of bytes */3528 op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) / 8;3529 if (spi_nor_protocol_is_dtr(nor->read_proto))3530 op->dummy.nbytes *= 2;3531 3532 /*3533 * Since spi_nor_spimem_setup_op() only sets buswidth when the number3534 * of data bytes is non-zero, the data buswidth won't be set here. So,3535 * do it explicitly.3536 */3537 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto);3538 3539 nor->dirmap.rdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,3540 &info);3541 return PTR_ERR_OR_ZERO(nor->dirmap.rdesc);3542}3543 3544static int spi_nor_create_write_dirmap(struct spi_nor *nor)3545{3546 struct spi_mem_dirmap_info info = {3547 .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),3548 SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),3549 SPI_MEM_OP_NO_DUMMY,3550 SPI_MEM_OP_DATA_OUT(0, NULL, 0)),3551 .offset = 0,3552 .length = nor->params->size,3553 };3554 struct spi_mem_op *op = &info.op_tmpl;3555 3556 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)3557 op->addr.nbytes = 0;3558 3559 spi_nor_spimem_setup_op(nor, op, nor->write_proto);3560 3561 /*3562 * Since spi_nor_spimem_setup_op() only sets buswidth when the number3563 * of data bytes is non-zero, the data buswidth won't be set here. So,3564 * do it explicitly.3565 */3566 op->data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto);3567 3568 nor->dirmap.wdesc = devm_spi_mem_dirmap_create(nor->dev, nor->spimem,3569 &info);3570 return PTR_ERR_OR_ZERO(nor->dirmap.wdesc);3571}3572 3573static int spi_nor_probe(struct spi_mem *spimem)3574{3575 struct spi_device *spi = spimem->spi;3576 struct flash_platform_data *data = dev_get_platdata(&spi->dev);3577 struct spi_nor *nor;3578 /*3579 * Enable all caps by default. The core will mask them after3580 * checking what's really supported using spi_mem_supports_op().3581 */3582 const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_ALL };3583 char *flash_name;3584 int ret;3585 3586 nor = devm_kzalloc(&spi->dev, sizeof(*nor), GFP_KERNEL);3587 if (!nor)3588 return -ENOMEM;3589 3590 nor->spimem = spimem;3591 nor->dev = &spi->dev;3592 spi_nor_set_flash_node(nor, spi->dev.of_node);3593 3594 spi_mem_set_drvdata(spimem, nor);3595 3596 if (data && data->name)3597 nor->mtd.name = data->name;3598 3599 if (!nor->mtd.name)3600 nor->mtd.name = spi_mem_get_name(spimem);3601 3602 /*3603 * For some (historical?) reason many platforms provide two different3604 * names in flash_platform_data: "name" and "type". Quite often name is3605 * set to "m25p80" and then "type" provides a real chip name.3606 * If that's the case, respect "type" and ignore a "name".3607 */3608 if (data && data->type)3609 flash_name = data->type;3610 else if (!strcmp(spi->modalias, "spi-nor"))3611 flash_name = NULL; /* auto-detect */3612 else3613 flash_name = spi->modalias;3614 3615 ret = spi_nor_scan(nor, flash_name, &hwcaps);3616 if (ret)3617 return ret;3618 3619 spi_nor_debugfs_register(nor);3620 3621 /*3622 * None of the existing parts have > 512B pages, but let's play safe3623 * and add this logic so that if anyone ever adds support for such3624 * a NOR we don't end up with buffer overflows.3625 */3626 if (nor->params->page_size > PAGE_SIZE) {3627 nor->bouncebuf_size = nor->params->page_size;3628 devm_kfree(nor->dev, nor->bouncebuf);3629 nor->bouncebuf = devm_kmalloc(nor->dev,3630 nor->bouncebuf_size,3631 GFP_KERNEL);3632 if (!nor->bouncebuf)3633 return -ENOMEM;3634 }3635 3636 ret = spi_nor_create_read_dirmap(nor);3637 if (ret)3638 return ret;3639 3640 ret = spi_nor_create_write_dirmap(nor);3641 if (ret)3642 return ret;3643 3644 return mtd_device_register(&nor->mtd, data ? data->parts : NULL,3645 data ? data->nr_parts : 0);3646}3647 3648static int spi_nor_remove(struct spi_mem *spimem)3649{3650 struct spi_nor *nor = spi_mem_get_drvdata(spimem);3651 3652 spi_nor_restore(nor);3653 3654 /* Clean up MTD stuff. */3655 return mtd_device_unregister(&nor->mtd);3656}3657 3658static void spi_nor_shutdown(struct spi_mem *spimem)3659{3660 struct spi_nor *nor = spi_mem_get_drvdata(spimem);3661 3662 spi_nor_restore(nor);3663}3664 3665/*3666 * Do NOT add to this array without reading the following:3667 *3668 * Historically, many flash devices are bound to this driver by their name. But3669 * since most of these flash are compatible to some extent, and their3670 * differences can often be differentiated by the JEDEC read-ID command, we3671 * encourage new users to add support to the spi-nor library, and simply bind3672 * against a generic string here (e.g., "jedec,spi-nor").3673 *3674 * Many flash names are kept here in this list to keep them available3675 * as module aliases for existing platforms.3676 */3677static const struct spi_device_id spi_nor_dev_ids[] = {3678 /*3679 * Allow non-DT platform devices to bind to the "spi-nor" modalias, and3680 * hack around the fact that the SPI core does not provide uevent3681 * matching for .of_match_table3682 */3683 {"spi-nor"},3684 3685 /*3686 * Entries not used in DTs that should be safe to drop after replacing3687 * them with "spi-nor" in platform data.3688 */3689 {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},3690 3691 /*3692 * Entries that were used in DTs without "jedec,spi-nor" fallback and3693 * should be kept for backward compatibility.3694 */3695 {"at25df321a"}, {"at25df641"}, {"at26df081a"},3696 {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},3697 {"mx25l25635e"},{"mx66l51235l"},3698 {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},3699 {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},3700 {"s25fl064k"},3701 {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},3702 {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},3703 {"m25p64"}, {"m25p128"},3704 {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},3705 {"w25q80bl"}, {"w25q128"}, {"w25q256"},3706 3707 /* Flashes that can't be detected using JEDEC */3708 {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},3709 {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},3710 {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},3711 3712 /* Everspin MRAMs (non-JEDEC) */3713 { "mr25h128" }, /* 128 Kib, 40 MHz */3714 { "mr25h256" }, /* 256 Kib, 40 MHz */3715 { "mr25h10" }, /* 1 Mib, 40 MHz */3716 { "mr25h40" }, /* 4 Mib, 40 MHz */3717 3718 { },3719};3720MODULE_DEVICE_TABLE(spi, spi_nor_dev_ids);3721 3722static const struct of_device_id spi_nor_of_table[] = {3723 /*3724 * Generic compatibility for SPI NOR that can be identified by the3725 * JEDEC READ ID opcode (0x9F). Use this, if possible.3726 */3727 { .compatible = "jedec,spi-nor" },3728 { /* sentinel */ },3729};3730MODULE_DEVICE_TABLE(of, spi_nor_of_table);3731 3732/*3733 * REVISIT: many of these chips have deep power-down modes, which3734 * should clearly be entered on suspend() to minimize power use.3735 * And also when they're otherwise idle...3736 */3737static struct spi_mem_driver spi_nor_driver = {3738 .spidrv = {3739 .driver = {3740 .name = "spi-nor",3741 .of_match_table = spi_nor_of_table,3742 .dev_groups = spi_nor_sysfs_groups,3743 },3744 .id_table = spi_nor_dev_ids,3745 },3746 .probe = spi_nor_probe,3747 .remove = spi_nor_remove,3748 .shutdown = spi_nor_shutdown,3749};3750 3751static int __init spi_nor_module_init(void)3752{3753 return spi_mem_driver_register(&spi_nor_driver);3754}3755module_init(spi_nor_module_init);3756 3757static void __exit spi_nor_module_exit(void)3758{3759 spi_mem_driver_unregister(&spi_nor_driver);3760 spi_nor_debugfs_shutdown();3761}3762module_exit(spi_nor_module_exit);3763 3764MODULE_LICENSE("GPL v2");3765MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");3766MODULE_AUTHOR("Mike Lavender");3767MODULE_DESCRIPTION("framework for SPI NOR");3768