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1/* SPDX-License-Identifier: GPL-2.02 * flexcan.c - FLEXCAN CAN controller driver3 *4 * Copyright (c) 2005-2006 Varma Electronics Oy5 * Copyright (c) 2009 Sascha Hauer, Pengutronix6 * Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>7 * Copyright (c) 2014 David Jander, Protonic Holland8 * Copyright (C) 2022 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>9 *10 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>11 *12 */13 14#ifndef _FLEXCAN_H15#define _FLEXCAN_H16 17#include <linux/can/rx-offload.h>18 19/* FLEXCAN hardware feature flags20 *21 * Below is some version info we got:22 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode MB23 * Filter? connected? Passive detection ption in MB Supported?24 * MCF5441X FlexCAN2 ? no yes no no no no 1625 * MX25 FlexCAN2 03.00.00.00 no no no no no no 6426 * MX28 FlexCAN2 03.00.04.00 yes yes no no no no 6427 * MX35 FlexCAN2 03.00.00.00 no no no no no no 6428 * MX53 FlexCAN2 03.00.00.00 yes no no no no no 6429 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes no 6430 * MX8QM FlexCAN3 03.00.23.00 yes yes no no yes yes 6431 * MX8MP FlexCAN3 03.00.17.01 yes yes no yes yes yes 6432 * VF610 FlexCAN3 ? no yes no yes yes? no 6433 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes no 6434 * LX2160A FlexCAN3 03.00.23.00 no yes no yes yes yes 6435 *36 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.37 */38 39/* [TR]WRN_INT not connected */40#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)41 /* Disable RX FIFO Global mask */42#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)43/* Enable EACEN and RRS bit in ctrl2 */44#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3)45/* Disable non-correctable errors interrupt and freeze mode */46#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)47/* Use mailboxes (not FIFO) for RX path */48#define FLEXCAN_QUIRK_USE_RX_MAILBOX BIT(5)49/* No interrupt for error passive */50#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)51/* default to BE register access */52#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)53/* Setup stop mode with GPR to support wakeup */54#define FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR BIT(8)55/* Support CAN-FD mode */56#define FLEXCAN_QUIRK_SUPPORT_FD BIT(9)57/* support memory detection and correction */58#define FLEXCAN_QUIRK_SUPPORT_ECC BIT(10)59/* Setup stop mode with SCU firmware to support wakeup */60#define FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW BIT(11)61/* Setup 3 separate interrupts, main, boff and err */62#define FLEXCAN_QUIRK_NR_IRQ_3 BIT(12)63/* Setup 16 mailboxes */64#define FLEXCAN_QUIRK_NR_MB_16 BIT(13)65/* Device supports RX via mailboxes */66#define FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX BIT(14)67/* Device supports RTR reception via mailboxes */68#define FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR BIT(15)69/* Device supports RX via FIFO */70#define FLEXCAN_QUIRK_SUPPORT_RX_FIFO BIT(16)71/* Setup stop mode with ATF SCMI protocol to support wakeup */72#define FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI BIT(17)73 74struct flexcan_devtype_data {75 u32 quirks; /* quirks needed for different IP cores */76};77 78struct flexcan_stop_mode {79 struct regmap *gpr;80 u8 req_gpr;81 u8 req_bit;82};83 84struct flexcan_priv {85 struct can_priv can;86 struct can_rx_offload offload;87 struct device *dev;88 89 struct flexcan_regs __iomem *regs;90 struct flexcan_mb __iomem *tx_mb;91 struct flexcan_mb __iomem *tx_mb_reserved;92 u8 tx_mb_idx;93 u8 mb_count;94 u8 mb_size;95 u8 clk_src; /* clock source of CAN Protocol Engine */96 u8 scu_idx;97 98 u64 rx_mask;99 u64 tx_mask;100 u32 reg_ctrl_default;101 102 struct clk *clk_ipg;103 struct clk *clk_per;104 struct flexcan_devtype_data devtype_data;105 struct regulator *reg_xceiver;106 struct flexcan_stop_mode stm;107 108 int irq_boff;109 int irq_err;110 111 /* IPC handle when setup stop mode by System Controller firmware(scfw) */112 struct imx_sc_ipc *sc_ipc_handle;113 114 /* Read and Write APIs */115 u32 (*read)(void __iomem *addr);116 void (*write)(u32 val, void __iomem *addr);117};118 119extern const struct ethtool_ops flexcan_ethtool_ops;120 121static inline bool122flexcan_supports_rx_mailbox(const struct flexcan_priv *priv)123{124 const u32 quirks = priv->devtype_data.quirks;125 126 return quirks & FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX;127}128 129static inline bool130flexcan_supports_rx_mailbox_rtr(const struct flexcan_priv *priv)131{132 const u32 quirks = priv->devtype_data.quirks;133 134 return (quirks & (FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |135 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR)) ==136 (FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |137 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR);138}139 140static inline bool141flexcan_supports_rx_fifo(const struct flexcan_priv *priv)142{143 const u32 quirks = priv->devtype_data.quirks;144 145 return quirks & FLEXCAN_QUIRK_SUPPORT_RX_FIFO;146}147 148static inline bool149flexcan_active_rx_rtr(const struct flexcan_priv *priv)150{151 const u32 quirks = priv->devtype_data.quirks;152 153 if (quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) {154 if (quirks & FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR)155 return true;156 } else {157 /* RX-FIFO is always RTR capable */158 return true;159 }160 161 return false;162}163 164 165#endif /* _FLEXCAN_H */166