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1/* SPDX-License-Identifier: GPL-2.0 */2/* CAN bus driver for Bosch M_CAN controller3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/4 */5 6#ifndef _CAN_M_CAN_H_7#define _CAN_M_CAN_H_8 9#include <linux/can/core.h>10#include <linux/can/dev.h>11#include <linux/can/rx-offload.h>12#include <linux/clk.h>13#include <linux/completion.h>14#include <linux/delay.h>15#include <linux/device.h>16#include <linux/dma-mapping.h>17#include <linux/freezer.h>18#include <linux/hrtimer.h>19#include <linux/interrupt.h>20#include <linux/io.h>21#include <linux/iopoll.h>22#include <linux/kernel.h>23#include <linux/module.h>24#include <linux/netdevice.h>25#include <linux/of.h>26#include <linux/phy/phy.h>27#include <linux/pinctrl/consumer.h>28#include <linux/pm_runtime.h>29#include <linux/slab.h>30#include <linux/uaccess.h>31 32/* m_can lec values */33enum m_can_lec_type {34 LEC_NO_ERROR = 0,35 LEC_STUFF_ERROR,36 LEC_FORM_ERROR,37 LEC_ACK_ERROR,38 LEC_BIT1_ERROR,39 LEC_BIT0_ERROR,40 LEC_CRC_ERROR,41 LEC_NO_CHANGE,42};43 44enum m_can_mram_cfg {45 MRAM_SIDF = 0,46 MRAM_XIDF,47 MRAM_RXF0,48 MRAM_RXF1,49 MRAM_RXB,50 MRAM_TXE,51 MRAM_TXB,52 MRAM_CFG_NUM,53};54 55/* address offset and element number for each FIFO/Buffer in the Message RAM */56struct mram_cfg {57 u16 off;58 u8 num;59};60 61struct m_can_classdev;62struct m_can_ops {63 /* Device specific call backs */64 int (*clear_interrupts)(struct m_can_classdev *cdev);65 u32 (*read_reg)(struct m_can_classdev *cdev, int reg);66 int (*write_reg)(struct m_can_classdev *cdev, int reg, int val);67 int (*read_fifo)(struct m_can_classdev *cdev, int addr_offset, void *val, size_t val_count);68 int (*write_fifo)(struct m_can_classdev *cdev, int addr_offset,69 const void *val, size_t val_count);70 int (*init)(struct m_can_classdev *cdev);71};72 73struct m_can_tx_op {74 struct m_can_classdev *cdev;75 struct work_struct work;76 struct sk_buff *skb;77 bool submit;78};79 80struct m_can_classdev {81 struct can_priv can;82 struct can_rx_offload offload;83 struct napi_struct napi;84 struct net_device *net;85 struct device *dev;86 struct clk *hclk;87 struct clk *cclk;88 89 struct workqueue_struct *tx_wq;90 struct phy *transceiver;91 92 ktime_t irq_timer_wait;93 94 const struct m_can_ops *ops;95 96 int version;97 u32 irqstatus;98 99 int pm_clock_support;100 int pm_wake_source;101 int is_peripheral;102 103 // Cached M_CAN_IE register content104 u32 active_interrupts;105 u32 rx_max_coalesced_frames_irq;106 u32 rx_coalesce_usecs_irq;107 u32 tx_max_coalesced_frames;108 u32 tx_max_coalesced_frames_irq;109 u32 tx_coalesce_usecs_irq;110 111 // Store this internally to avoid fetch delays on peripheral chips112 u32 tx_fifo_putidx;113 114 /* Protects shared state between start_xmit and m_can_isr */115 spinlock_t tx_handling_spinlock;116 int tx_fifo_in_flight;117 118 struct m_can_tx_op *tx_ops;119 int tx_fifo_size;120 int next_tx_op;121 122 int nr_txs_without_submit;123 /* bitfield of fifo elements that will be submitted together */124 u32 tx_peripheral_submit;125 126 struct mram_cfg mcfg[MRAM_CFG_NUM];127 128 struct hrtimer hrtimer;129};130 131struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv);132void m_can_class_free_dev(struct net_device *net);133int m_can_class_register(struct m_can_classdev *cdev);134void m_can_class_unregister(struct m_can_classdev *cdev);135int m_can_class_get_clocks(struct m_can_classdev *cdev);136int m_can_init_ram(struct m_can_classdev *priv);137int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size);138 139int m_can_class_suspend(struct device *dev);140int m_can_class_resume(struct device *dev);141#endif /* _CAN_M_H_ */142