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1// SPDX-License-Identifier: GPL-2.02/*3 * PCI Specific M_CAN Glue4 *5 * Copyright (C) 2018-2020 Intel Corporation6 * Author: Felipe Balbi (Intel)7 * Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>8 * Author: Raymond Tan <raymond.tan@intel.com>9 */10 11#include <linux/kernel.h>12#include <linux/module.h>13#include <linux/netdevice.h>14#include <linux/pci.h>15#include <linux/pm_runtime.h>16 17#include "m_can.h"18 19#define M_CAN_PCI_MMIO_BAR 020 21#define M_CAN_CLOCK_FREQ_EHL 20000000022#define CTL_CSR_INT_CTL_OFFSET 0x50823 24struct m_can_pci_priv {25 struct m_can_classdev cdev;26 27 void __iomem *base;28};29 30static inline struct m_can_pci_priv *cdev_to_priv(struct m_can_classdev *cdev)31{32 return container_of(cdev, struct m_can_pci_priv, cdev);33}34 35static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)36{37 struct m_can_pci_priv *priv = cdev_to_priv(cdev);38 39 return readl(priv->base + reg);40}41 42static int iomap_read_fifo(struct m_can_classdev *cdev, int offset, void *val, size_t val_count)43{44 struct m_can_pci_priv *priv = cdev_to_priv(cdev);45 void __iomem *src = priv->base + offset;46 47 while (val_count--) {48 *(unsigned int *)val = ioread32(src);49 val += 4;50 src += 4;51 }52 53 return 0;54}55 56static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)57{58 struct m_can_pci_priv *priv = cdev_to_priv(cdev);59 60 writel(val, priv->base + reg);61 62 return 0;63}64 65static int iomap_write_fifo(struct m_can_classdev *cdev, int offset,66 const void *val, size_t val_count)67{68 struct m_can_pci_priv *priv = cdev_to_priv(cdev);69 void __iomem *dst = priv->base + offset;70 71 while (val_count--) {72 iowrite32(*(unsigned int *)val, dst);73 val += 4;74 dst += 4;75 }76 77 return 0;78}79 80static const struct m_can_ops m_can_pci_ops = {81 .read_reg = iomap_read_reg,82 .write_reg = iomap_write_reg,83 .write_fifo = iomap_write_fifo,84 .read_fifo = iomap_read_fifo,85};86 87static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)88{89 struct device *dev = &pci->dev;90 struct m_can_classdev *mcan_class;91 struct m_can_pci_priv *priv;92 void __iomem *base;93 int ret;94 95 ret = pcim_enable_device(pci);96 if (ret)97 return ret;98 99 pci_set_master(pci);100 101 ret = pcim_iomap_regions(pci, BIT(M_CAN_PCI_MMIO_BAR), pci_name(pci));102 if (ret)103 return ret;104 105 base = pcim_iomap_table(pci)[M_CAN_PCI_MMIO_BAR];106 107 if (!base) {108 dev_err(dev, "failed to map BARs\n");109 return -ENOMEM;110 }111 112 mcan_class = m_can_class_allocate_dev(&pci->dev,113 sizeof(struct m_can_pci_priv));114 if (!mcan_class)115 return -ENOMEM;116 117 priv = cdev_to_priv(mcan_class);118 119 priv->base = base;120 121 ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_ALL_TYPES);122 if (ret < 0)123 goto err_free_dev;124 125 mcan_class->dev = &pci->dev;126 mcan_class->net->irq = pci_irq_vector(pci, 0);127 mcan_class->pm_clock_support = 1;128 mcan_class->pm_wake_source = 0;129 mcan_class->can.clock.freq = id->driver_data;130 mcan_class->ops = &m_can_pci_ops;131 132 pci_set_drvdata(pci, mcan_class);133 134 ret = m_can_class_register(mcan_class);135 if (ret)136 goto err_free_irq;137 138 /* Enable interrupt control at CAN wrapper IP */139 writel(0x1, base + CTL_CSR_INT_CTL_OFFSET);140 141 pm_runtime_set_autosuspend_delay(dev, 1000);142 pm_runtime_use_autosuspend(dev);143 pm_runtime_put_noidle(dev);144 pm_runtime_allow(dev);145 146 return 0;147 148err_free_irq:149 pci_free_irq_vectors(pci);150err_free_dev:151 m_can_class_free_dev(mcan_class->net);152 return ret;153}154 155static void m_can_pci_remove(struct pci_dev *pci)156{157 struct m_can_classdev *mcan_class = pci_get_drvdata(pci);158 struct m_can_pci_priv *priv = cdev_to_priv(mcan_class);159 160 pm_runtime_forbid(&pci->dev);161 pm_runtime_get_noresume(&pci->dev);162 163 /* Disable interrupt control at CAN wrapper IP */164 writel(0x0, priv->base + CTL_CSR_INT_CTL_OFFSET);165 166 m_can_class_unregister(mcan_class);167 m_can_class_free_dev(mcan_class->net);168 pci_free_irq_vectors(pci);169}170 171static __maybe_unused int m_can_pci_suspend(struct device *dev)172{173 return m_can_class_suspend(dev);174}175 176static __maybe_unused int m_can_pci_resume(struct device *dev)177{178 return m_can_class_resume(dev);179}180 181static SIMPLE_DEV_PM_OPS(m_can_pci_pm_ops,182 m_can_pci_suspend, m_can_pci_resume);183 184static const struct pci_device_id m_can_pci_id_table[] = {185 { PCI_VDEVICE(INTEL, 0x4bc1), M_CAN_CLOCK_FREQ_EHL, },186 { PCI_VDEVICE(INTEL, 0x4bc2), M_CAN_CLOCK_FREQ_EHL, },187 { } /* Terminating Entry */188};189MODULE_DEVICE_TABLE(pci, m_can_pci_id_table);190 191static struct pci_driver m_can_pci_driver = {192 .name = "m_can_pci",193 .probe = m_can_pci_probe,194 .remove = m_can_pci_remove,195 .id_table = m_can_pci_id_table,196 .driver = {197 .pm = &m_can_pci_pm_ops,198 },199};200 201module_pci_driver(m_can_pci_driver);202 203MODULE_AUTHOR("Felipe Balbi (Intel)");204MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");205MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");206MODULE_LICENSE("GPL");207MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller on PCI bus");208