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1// SPDX-License-Identifier: GPL-2.0+2/* Renesas R-Car CAN device driver3 *4 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com>5 * Copyright (C) 2013 Renesas Solutions Corp.6 */7 8#include <linux/module.h>9#include <linux/kernel.h>10#include <linux/types.h>11#include <linux/interrupt.h>12#include <linux/errno.h>13#include <linux/ethtool.h>14#include <linux/netdevice.h>15#include <linux/platform_device.h>16#include <linux/can/dev.h>17#include <linux/clk.h>18#include <linux/of.h>19 20#define RCAR_CAN_DRV_NAME "rcar_can"21 22/* Clock Select Register settings */23enum CLKR {24 CLKR_CLKP1 = 0, /* Peripheral clock (clkp1) */25 CLKR_CLKP2 = 1, /* Peripheral clock (clkp2) */26 CLKR_CLKEXT = 3, /* Externally input clock */27};28 29#define RCAR_SUPPORTED_CLOCKS (BIT(CLKR_CLKP1) | BIT(CLKR_CLKP2) | \30 BIT(CLKR_CLKEXT))31 32/* Mailbox configuration:33 * mailbox 60 - 63 - Rx FIFO mailboxes34 * mailbox 56 - 59 - Tx FIFO mailboxes35 * non-FIFO mailboxes are not used36 */37#define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */38#define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */39#define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */40#define RCAR_CAN_FIFO_DEPTH 441 42/* Mailbox registers structure */43struct rcar_can_mbox_regs {44 u32 id; /* IDE and RTR bits, SID and EID */45 u8 stub; /* Not used */46 u8 dlc; /* Data Length Code - bits [0..3] */47 u8 data[8]; /* Data Bytes */48 u8 tsh; /* Time Stamp Higher Byte */49 u8 tsl; /* Time Stamp Lower Byte */50};51 52struct rcar_can_regs {53 struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */54 u32 mkr_2_9[8]; /* Mask Registers 2-9 */55 u32 fidcr[2]; /* FIFO Received ID Compare Register */56 u32 mkivlr1; /* Mask Invalid Register 1 */57 u32 mier1; /* Mailbox Interrupt Enable Register 1 */58 u32 mkr_0_1[2]; /* Mask Registers 0-1 */59 u32 mkivlr0; /* Mask Invalid Register 0*/60 u32 mier0; /* Mailbox Interrupt Enable Register 0 */61 u8 pad_440[0x3c0];62 u8 mctl[64]; /* Message Control Registers */63 u16 ctlr; /* Control Register */64 u16 str; /* Status register */65 u8 bcr[3]; /* Bit Configuration Register */66 u8 clkr; /* Clock Select Register */67 u8 rfcr; /* Receive FIFO Control Register */68 u8 rfpcr; /* Receive FIFO Pointer Control Register */69 u8 tfcr; /* Transmit FIFO Control Register */70 u8 tfpcr; /* Transmit FIFO Pointer Control Register */71 u8 eier; /* Error Interrupt Enable Register */72 u8 eifr; /* Error Interrupt Factor Judge Register */73 u8 recr; /* Receive Error Count Register */74 u8 tecr; /* Transmit Error Count Register */75 u8 ecsr; /* Error Code Store Register */76 u8 cssr; /* Channel Search Support Register */77 u8 mssr; /* Mailbox Search Status Register */78 u8 msmr; /* Mailbox Search Mode Register */79 u16 tsr; /* Time Stamp Register */80 u8 afsr; /* Acceptance Filter Support Register */81 u8 pad_857;82 u8 tcr; /* Test Control Register */83 u8 pad_859[7];84 u8 ier; /* Interrupt Enable Register */85 u8 isr; /* Interrupt Status Register */86 u8 pad_862;87 u8 mbsmr; /* Mailbox Search Mask Register */88};89 90struct rcar_can_priv {91 struct can_priv can; /* Must be the first member! */92 struct net_device *ndev;93 struct napi_struct napi;94 struct rcar_can_regs __iomem *regs;95 struct clk *clk;96 struct clk *can_clk;97 u32 tx_head;98 u32 tx_tail;99 u8 clock_select;100 u8 ier;101};102 103static const struct can_bittiming_const rcar_can_bittiming_const = {104 .name = RCAR_CAN_DRV_NAME,105 .tseg1_min = 4,106 .tseg1_max = 16,107 .tseg2_min = 2,108 .tseg2_max = 8,109 .sjw_max = 4,110 .brp_min = 1,111 .brp_max = 1024,112 .brp_inc = 1,113};114 115/* Control Register bits */116#define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */117#define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */118 /* at bus-off entry */119#define RCAR_CAN_CTLR_SLPM (1 << 10)120#define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */121#define RCAR_CAN_CTLR_CANM_HALT (1 << 9)122#define RCAR_CAN_CTLR_CANM_RESET (1 << 8)123#define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8)124#define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */125#define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */126#define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */127#define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */128 129/* Status Register bits */130#define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */131 132/* FIFO Received ID Compare Registers 0 and 1 bits */133#define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */134#define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */135 136/* Receive FIFO Control Register bits */137#define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */138#define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */139 140/* Transmit FIFO Control Register bits */141#define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */142 /* Number Status Bits */143#define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */144 /* Message Number Status Bits */145#define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */146 147#define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */148 /* for Rx mailboxes 0-31 */149#define RCAR_CAN_N_RX_MKREGS2 8150 151/* Bit Configuration Register settings */152#define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20)153#define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8)154#define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4)155#define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07)156 157/* Mailbox and Mask Registers bits */158#define RCAR_CAN_IDE (1 << 31)159#define RCAR_CAN_RTR (1 << 30)160#define RCAR_CAN_SID_SHIFT 18161 162/* Mailbox Interrupt Enable Register 1 bits */163#define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */164#define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */165 166/* Interrupt Enable Register bits */167#define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */168#define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */169 /* Enable Bit */170#define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */171 /* Enable Bit */172/* Interrupt Status Register bits */173#define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */174#define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */175 /* Status Bit */176#define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */177 /* Status Bit */178 179/* Error Interrupt Enable Register bits */180#define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */181#define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */182 /* Interrupt Enable */183#define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */184#define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */185#define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */186#define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */187#define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */188#define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */189 190/* Error Interrupt Factor Judge Register bits */191#define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */192#define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */193 /* Detect Flag */194#define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */195#define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */196#define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */197#define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */198#define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */199#define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */200 201/* Error Code Store Register bits */202#define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */203#define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */204#define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */205#define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */206#define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */207#define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */208#define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */209#define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */210 211#define RCAR_CAN_NAPI_WEIGHT 4212#define MAX_STR_READS 0x100213 214static void tx_failure_cleanup(struct net_device *ndev)215{216 int i;217 218 for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++)219 can_free_echo_skb(ndev, i, NULL);220}221 222static void rcar_can_error(struct net_device *ndev)223{224 struct rcar_can_priv *priv = netdev_priv(ndev);225 struct can_frame *cf;226 struct sk_buff *skb;227 u8 eifr, txerr = 0, rxerr = 0;228 229 /* Propagate the error condition to the CAN stack */230 skb = alloc_can_err_skb(ndev, &cf);231 232 eifr = readb(&priv->regs->eifr);233 if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) {234 txerr = readb(&priv->regs->tecr);235 rxerr = readb(&priv->regs->recr);236 if (skb)237 cf->can_id |= CAN_ERR_CRTL;238 }239 if (eifr & RCAR_CAN_EIFR_BEIF) {240 int rx_errors = 0, tx_errors = 0;241 u8 ecsr;242 243 netdev_dbg(priv->ndev, "Bus error interrupt:\n");244 if (skb)245 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;246 247 ecsr = readb(&priv->regs->ecsr);248 if (ecsr & RCAR_CAN_ECSR_ADEF) {249 netdev_dbg(priv->ndev, "ACK Delimiter Error\n");250 tx_errors++;251 writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr);252 if (skb)253 cf->data[3] = CAN_ERR_PROT_LOC_ACK_DEL;254 }255 if (ecsr & RCAR_CAN_ECSR_BE0F) {256 netdev_dbg(priv->ndev, "Bit Error (dominant)\n");257 tx_errors++;258 writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr);259 if (skb)260 cf->data[2] |= CAN_ERR_PROT_BIT0;261 }262 if (ecsr & RCAR_CAN_ECSR_BE1F) {263 netdev_dbg(priv->ndev, "Bit Error (recessive)\n");264 tx_errors++;265 writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr);266 if (skb)267 cf->data[2] |= CAN_ERR_PROT_BIT1;268 }269 if (ecsr & RCAR_CAN_ECSR_CEF) {270 netdev_dbg(priv->ndev, "CRC Error\n");271 rx_errors++;272 writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr);273 if (skb)274 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;275 }276 if (ecsr & RCAR_CAN_ECSR_AEF) {277 netdev_dbg(priv->ndev, "ACK Error\n");278 tx_errors++;279 writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr);280 if (skb) {281 cf->can_id |= CAN_ERR_ACK;282 cf->data[3] = CAN_ERR_PROT_LOC_ACK;283 }284 }285 if (ecsr & RCAR_CAN_ECSR_FEF) {286 netdev_dbg(priv->ndev, "Form Error\n");287 rx_errors++;288 writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr);289 if (skb)290 cf->data[2] |= CAN_ERR_PROT_FORM;291 }292 if (ecsr & RCAR_CAN_ECSR_SEF) {293 netdev_dbg(priv->ndev, "Stuff Error\n");294 rx_errors++;295 writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr);296 if (skb)297 cf->data[2] |= CAN_ERR_PROT_STUFF;298 }299 300 priv->can.can_stats.bus_error++;301 ndev->stats.rx_errors += rx_errors;302 ndev->stats.tx_errors += tx_errors;303 writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr);304 }305 if (eifr & RCAR_CAN_EIFR_EWIF) {306 netdev_dbg(priv->ndev, "Error warning interrupt\n");307 priv->can.state = CAN_STATE_ERROR_WARNING;308 priv->can.can_stats.error_warning++;309 /* Clear interrupt condition */310 writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr);311 if (skb)312 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :313 CAN_ERR_CRTL_RX_WARNING;314 }315 if (eifr & RCAR_CAN_EIFR_EPIF) {316 netdev_dbg(priv->ndev, "Error passive interrupt\n");317 priv->can.state = CAN_STATE_ERROR_PASSIVE;318 priv->can.can_stats.error_passive++;319 /* Clear interrupt condition */320 writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr);321 if (skb)322 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :323 CAN_ERR_CRTL_RX_PASSIVE;324 }325 if (eifr & RCAR_CAN_EIFR_BOEIF) {326 netdev_dbg(priv->ndev, "Bus-off entry interrupt\n");327 tx_failure_cleanup(ndev);328 priv->ier = RCAR_CAN_IER_ERSIE;329 writeb(priv->ier, &priv->regs->ier);330 priv->can.state = CAN_STATE_BUS_OFF;331 /* Clear interrupt condition */332 writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr);333 priv->can.can_stats.bus_off++;334 can_bus_off(ndev);335 if (skb)336 cf->can_id |= CAN_ERR_BUSOFF;337 } else if (skb) {338 cf->can_id |= CAN_ERR_CNT;339 cf->data[6] = txerr;340 cf->data[7] = rxerr;341 }342 if (eifr & RCAR_CAN_EIFR_ORIF) {343 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n");344 ndev->stats.rx_over_errors++;345 ndev->stats.rx_errors++;346 writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr);347 if (skb) {348 cf->can_id |= CAN_ERR_CRTL;349 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;350 }351 }352 if (eifr & RCAR_CAN_EIFR_OLIF) {353 netdev_dbg(priv->ndev,354 "Overload Frame Transmission error interrupt\n");355 ndev->stats.rx_over_errors++;356 ndev->stats.rx_errors++;357 writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr);358 if (skb) {359 cf->can_id |= CAN_ERR_PROT;360 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;361 }362 }363 364 if (skb)365 netif_rx(skb);366}367 368static void rcar_can_tx_done(struct net_device *ndev)369{370 struct rcar_can_priv *priv = netdev_priv(ndev);371 struct net_device_stats *stats = &ndev->stats;372 u8 isr;373 374 while (1) {375 u8 unsent = readb(&priv->regs->tfcr);376 377 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >>378 RCAR_CAN_TFCR_TFUST_SHIFT;379 if (priv->tx_head - priv->tx_tail <= unsent)380 break;381 stats->tx_packets++;382 stats->tx_bytes +=383 can_get_echo_skb(ndev,384 priv->tx_tail % RCAR_CAN_FIFO_DEPTH,385 NULL);386 387 priv->tx_tail++;388 netif_wake_queue(ndev);389 }390 /* Clear interrupt */391 isr = readb(&priv->regs->isr);392 writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr);393}394 395static irqreturn_t rcar_can_interrupt(int irq, void *dev_id)396{397 struct net_device *ndev = dev_id;398 struct rcar_can_priv *priv = netdev_priv(ndev);399 u8 isr;400 401 isr = readb(&priv->regs->isr);402 if (!(isr & priv->ier))403 return IRQ_NONE;404 405 if (isr & RCAR_CAN_ISR_ERSF)406 rcar_can_error(ndev);407 408 if (isr & RCAR_CAN_ISR_TXFF)409 rcar_can_tx_done(ndev);410 411 if (isr & RCAR_CAN_ISR_RXFF) {412 if (napi_schedule_prep(&priv->napi)) {413 /* Disable Rx FIFO interrupts */414 priv->ier &= ~RCAR_CAN_IER_RXFIE;415 writeb(priv->ier, &priv->regs->ier);416 __napi_schedule(&priv->napi);417 }418 }419 420 return IRQ_HANDLED;421}422 423static void rcar_can_set_bittiming(struct net_device *dev)424{425 struct rcar_can_priv *priv = netdev_priv(dev);426 struct can_bittiming *bt = &priv->can.bittiming;427 u32 bcr;428 429 bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) |430 RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) |431 RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1);432 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access.433 * All the registers are big-endian but they get byte-swapped on 32-bit434 * read/write (but not on 8-bit, contrary to the manuals)...435 */436 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr);437}438 439static void rcar_can_start(struct net_device *ndev)440{441 struct rcar_can_priv *priv = netdev_priv(ndev);442 u16 ctlr;443 int i;444 445 /* Set controller to known mode:446 * - FIFO mailbox mode447 * - accept all messages448 * - overrun mode449 * CAN is in sleep mode after MCU hardware or software reset.450 */451 ctlr = readw(&priv->regs->ctlr);452 ctlr &= ~RCAR_CAN_CTLR_SLPM;453 writew(ctlr, &priv->regs->ctlr);454 /* Go to reset mode */455 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET;456 writew(ctlr, &priv->regs->ctlr);457 for (i = 0; i < MAX_STR_READS; i++) {458 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)459 break;460 }461 rcar_can_set_bittiming(ndev);462 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */463 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */464 /* at bus-off */465 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */466 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */467 writew(ctlr, &priv->regs->ctlr);468 469 /* Accept all SID and EID */470 writel(0, &priv->regs->mkr_2_9[6]);471 writel(0, &priv->regs->mkr_2_9[7]);472 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */473 writel(0, &priv->regs->mkivlr1);474 /* Accept all frames */475 writel(0, &priv->regs->fidcr[0]);476 writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]);477 /* Enable and configure FIFO mailbox interrupts */478 writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1);479 480 priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE |481 RCAR_CAN_IER_TXFIE;482 writeb(priv->ier, &priv->regs->ier);483 484 /* Accumulate error codes */485 writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr);486 /* Enable error interrupts */487 writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE |488 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ?489 RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE |490 RCAR_CAN_EIER_OLIE, &priv->regs->eier);491 priv->can.state = CAN_STATE_ERROR_ACTIVE;492 493 /* Go to operation mode */494 writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr);495 for (i = 0; i < MAX_STR_READS; i++) {496 if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST))497 break;498 }499 /* Enable Rx and Tx FIFO */500 writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr);501 writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr);502}503 504static int rcar_can_open(struct net_device *ndev)505{506 struct rcar_can_priv *priv = netdev_priv(ndev);507 int err;508 509 err = clk_prepare_enable(priv->clk);510 if (err) {511 netdev_err(ndev,512 "failed to enable peripheral clock, error %d\n",513 err);514 goto out;515 }516 err = clk_prepare_enable(priv->can_clk);517 if (err) {518 netdev_err(ndev, "failed to enable CAN clock, error %d\n",519 err);520 goto out_clock;521 }522 err = open_candev(ndev);523 if (err) {524 netdev_err(ndev, "open_candev() failed, error %d\n", err);525 goto out_can_clock;526 }527 napi_enable(&priv->napi);528 err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev);529 if (err) {530 netdev_err(ndev, "request_irq(%d) failed, error %d\n",531 ndev->irq, err);532 goto out_close;533 }534 rcar_can_start(ndev);535 netif_start_queue(ndev);536 return 0;537out_close:538 napi_disable(&priv->napi);539 close_candev(ndev);540out_can_clock:541 clk_disable_unprepare(priv->can_clk);542out_clock:543 clk_disable_unprepare(priv->clk);544out:545 return err;546}547 548static void rcar_can_stop(struct net_device *ndev)549{550 struct rcar_can_priv *priv = netdev_priv(ndev);551 u16 ctlr;552 int i;553 554 /* Go to (force) reset mode */555 ctlr = readw(&priv->regs->ctlr);556 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET;557 writew(ctlr, &priv->regs->ctlr);558 for (i = 0; i < MAX_STR_READS; i++) {559 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)560 break;561 }562 writel(0, &priv->regs->mier0);563 writel(0, &priv->regs->mier1);564 writeb(0, &priv->regs->ier);565 writeb(0, &priv->regs->eier);566 /* Go to sleep mode */567 ctlr |= RCAR_CAN_CTLR_SLPM;568 writew(ctlr, &priv->regs->ctlr);569 priv->can.state = CAN_STATE_STOPPED;570}571 572static int rcar_can_close(struct net_device *ndev)573{574 struct rcar_can_priv *priv = netdev_priv(ndev);575 576 netif_stop_queue(ndev);577 rcar_can_stop(ndev);578 free_irq(ndev->irq, ndev);579 napi_disable(&priv->napi);580 clk_disable_unprepare(priv->can_clk);581 clk_disable_unprepare(priv->clk);582 close_candev(ndev);583 return 0;584}585 586static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb,587 struct net_device *ndev)588{589 struct rcar_can_priv *priv = netdev_priv(ndev);590 struct can_frame *cf = (struct can_frame *)skb->data;591 u32 data, i;592 593 if (can_dev_dropped_skb(ndev, skb))594 return NETDEV_TX_OK;595 596 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */597 data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE;598 else /* Standard frame format */599 data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT;600 601 if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */602 data |= RCAR_CAN_RTR;603 } else {604 for (i = 0; i < cf->len; i++)605 writeb(cf->data[i],606 &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]);607 }608 609 writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id);610 611 writeb(cf->len, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc);612 613 can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH, 0);614 priv->tx_head++;615 /* Start Tx: write 0xff to the TFPCR register to increment616 * the CPU-side pointer for the transmit FIFO to the next617 * mailbox location618 */619 writeb(0xff, &priv->regs->tfpcr);620 /* Stop the queue if we've filled all FIFO entries */621 if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH)622 netif_stop_queue(ndev);623 624 return NETDEV_TX_OK;625}626 627static const struct net_device_ops rcar_can_netdev_ops = {628 .ndo_open = rcar_can_open,629 .ndo_stop = rcar_can_close,630 .ndo_start_xmit = rcar_can_start_xmit,631 .ndo_change_mtu = can_change_mtu,632};633 634static const struct ethtool_ops rcar_can_ethtool_ops = {635 .get_ts_info = ethtool_op_get_ts_info,636};637 638static void rcar_can_rx_pkt(struct rcar_can_priv *priv)639{640 struct net_device_stats *stats = &priv->ndev->stats;641 struct can_frame *cf;642 struct sk_buff *skb;643 u32 data;644 u8 dlc;645 646 skb = alloc_can_skb(priv->ndev, &cf);647 if (!skb) {648 stats->rx_dropped++;649 return;650 }651 652 data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id);653 if (data & RCAR_CAN_IDE)654 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG;655 else656 cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK;657 658 dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc);659 cf->len = can_cc_dlc2len(dlc);660 if (data & RCAR_CAN_RTR) {661 cf->can_id |= CAN_RTR_FLAG;662 } else {663 for (dlc = 0; dlc < cf->len; dlc++)664 cf->data[dlc] =665 readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]);666 667 stats->rx_bytes += cf->len;668 }669 stats->rx_packets++;670 671 netif_receive_skb(skb);672}673 674static int rcar_can_rx_poll(struct napi_struct *napi, int quota)675{676 struct rcar_can_priv *priv = container_of(napi,677 struct rcar_can_priv, napi);678 int num_pkts;679 680 for (num_pkts = 0; num_pkts < quota; num_pkts++) {681 u8 rfcr, isr;682 683 isr = readb(&priv->regs->isr);684 /* Clear interrupt bit */685 if (isr & RCAR_CAN_ISR_RXFF)686 writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr);687 rfcr = readb(&priv->regs->rfcr);688 if (rfcr & RCAR_CAN_RFCR_RFEST)689 break;690 rcar_can_rx_pkt(priv);691 /* Write 0xff to the RFPCR register to increment692 * the CPU-side pointer for the receive FIFO693 * to the next mailbox location694 */695 writeb(0xff, &priv->regs->rfpcr);696 }697 /* All packets processed */698 if (num_pkts < quota) {699 napi_complete_done(napi, num_pkts);700 priv->ier |= RCAR_CAN_IER_RXFIE;701 writeb(priv->ier, &priv->regs->ier);702 }703 return num_pkts;704}705 706static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode)707{708 switch (mode) {709 case CAN_MODE_START:710 rcar_can_start(ndev);711 netif_wake_queue(ndev);712 return 0;713 default:714 return -EOPNOTSUPP;715 }716}717 718static int rcar_can_get_berr_counter(const struct net_device *dev,719 struct can_berr_counter *bec)720{721 struct rcar_can_priv *priv = netdev_priv(dev);722 int err;723 724 err = clk_prepare_enable(priv->clk);725 if (err)726 return err;727 bec->txerr = readb(&priv->regs->tecr);728 bec->rxerr = readb(&priv->regs->recr);729 clk_disable_unprepare(priv->clk);730 return 0;731}732 733static const char * const clock_names[] = {734 [CLKR_CLKP1] = "clkp1",735 [CLKR_CLKP2] = "clkp2",736 [CLKR_CLKEXT] = "can_clk",737};738 739static int rcar_can_probe(struct platform_device *pdev)740{741 struct rcar_can_priv *priv;742 struct net_device *ndev;743 void __iomem *addr;744 u32 clock_select = CLKR_CLKP1;745 int err = -ENODEV;746 int irq;747 748 of_property_read_u32(pdev->dev.of_node, "renesas,can-clock-select",749 &clock_select);750 751 irq = platform_get_irq(pdev, 0);752 if (irq < 0) {753 err = irq;754 goto fail;755 }756 757 addr = devm_platform_ioremap_resource(pdev, 0);758 if (IS_ERR(addr)) {759 err = PTR_ERR(addr);760 goto fail;761 }762 763 ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH);764 if (!ndev) {765 dev_err(&pdev->dev, "alloc_candev() failed\n");766 err = -ENOMEM;767 goto fail;768 }769 770 priv = netdev_priv(ndev);771 772 priv->clk = devm_clk_get(&pdev->dev, "clkp1");773 if (IS_ERR(priv->clk)) {774 err = PTR_ERR(priv->clk);775 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",776 err);777 goto fail_clk;778 }779 780 if (!(BIT(clock_select) & RCAR_SUPPORTED_CLOCKS)) {781 err = -EINVAL;782 dev_err(&pdev->dev, "invalid CAN clock selected\n");783 goto fail_clk;784 }785 priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]);786 if (IS_ERR(priv->can_clk)) {787 err = PTR_ERR(priv->can_clk);788 dev_err(&pdev->dev, "cannot get CAN clock, error %d\n", err);789 goto fail_clk;790 }791 792 ndev->netdev_ops = &rcar_can_netdev_ops;793 ndev->ethtool_ops = &rcar_can_ethtool_ops;794 ndev->irq = irq;795 ndev->flags |= IFF_ECHO;796 priv->ndev = ndev;797 priv->regs = addr;798 priv->clock_select = clock_select;799 priv->can.clock.freq = clk_get_rate(priv->can_clk);800 priv->can.bittiming_const = &rcar_can_bittiming_const;801 priv->can.do_set_mode = rcar_can_do_set_mode;802 priv->can.do_get_berr_counter = rcar_can_get_berr_counter;803 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;804 platform_set_drvdata(pdev, ndev);805 SET_NETDEV_DEV(ndev, &pdev->dev);806 807 netif_napi_add_weight(ndev, &priv->napi, rcar_can_rx_poll,808 RCAR_CAN_NAPI_WEIGHT);809 err = register_candev(ndev);810 if (err) {811 dev_err(&pdev->dev, "register_candev() failed, error %d\n",812 err);813 goto fail_candev;814 }815 816 dev_info(&pdev->dev, "device registered (IRQ%d)\n", ndev->irq);817 818 return 0;819fail_candev:820 netif_napi_del(&priv->napi);821fail_clk:822 free_candev(ndev);823fail:824 return err;825}826 827static void rcar_can_remove(struct platform_device *pdev)828{829 struct net_device *ndev = platform_get_drvdata(pdev);830 struct rcar_can_priv *priv = netdev_priv(ndev);831 832 unregister_candev(ndev);833 netif_napi_del(&priv->napi);834 free_candev(ndev);835}836 837static int __maybe_unused rcar_can_suspend(struct device *dev)838{839 struct net_device *ndev = dev_get_drvdata(dev);840 struct rcar_can_priv *priv = netdev_priv(ndev);841 u16 ctlr;842 843 if (!netif_running(ndev))844 return 0;845 846 netif_stop_queue(ndev);847 netif_device_detach(ndev);848 849 ctlr = readw(&priv->regs->ctlr);850 ctlr |= RCAR_CAN_CTLR_CANM_HALT;851 writew(ctlr, &priv->regs->ctlr);852 ctlr |= RCAR_CAN_CTLR_SLPM;853 writew(ctlr, &priv->regs->ctlr);854 priv->can.state = CAN_STATE_SLEEPING;855 856 clk_disable(priv->clk);857 return 0;858}859 860static int __maybe_unused rcar_can_resume(struct device *dev)861{862 struct net_device *ndev = dev_get_drvdata(dev);863 struct rcar_can_priv *priv = netdev_priv(ndev);864 u16 ctlr;865 int err;866 867 if (!netif_running(ndev))868 return 0;869 870 err = clk_enable(priv->clk);871 if (err) {872 netdev_err(ndev, "clk_enable() failed, error %d\n", err);873 return err;874 }875 876 ctlr = readw(&priv->regs->ctlr);877 ctlr &= ~RCAR_CAN_CTLR_SLPM;878 writew(ctlr, &priv->regs->ctlr);879 ctlr &= ~RCAR_CAN_CTLR_CANM;880 writew(ctlr, &priv->regs->ctlr);881 priv->can.state = CAN_STATE_ERROR_ACTIVE;882 883 netif_device_attach(ndev);884 netif_start_queue(ndev);885 886 return 0;887}888 889static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume);890 891static const struct of_device_id rcar_can_of_table[] __maybe_unused = {892 { .compatible = "renesas,can-r8a7778" },893 { .compatible = "renesas,can-r8a7779" },894 { .compatible = "renesas,can-r8a7790" },895 { .compatible = "renesas,can-r8a7791" },896 { .compatible = "renesas,rcar-gen1-can" },897 { .compatible = "renesas,rcar-gen2-can" },898 { .compatible = "renesas,rcar-gen3-can" },899 { }900};901MODULE_DEVICE_TABLE(of, rcar_can_of_table);902 903static struct platform_driver rcar_can_driver = {904 .driver = {905 .name = RCAR_CAN_DRV_NAME,906 .of_match_table = of_match_ptr(rcar_can_of_table),907 .pm = &rcar_can_pm_ops,908 },909 .probe = rcar_can_probe,910 .remove = rcar_can_remove,911};912 913module_platform_driver(rcar_can_driver);914 915MODULE_AUTHOR("Cogent Embedded, Inc.");916MODULE_LICENSE("GPL");917MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC");918MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME);919