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1// SPDX-License-Identifier: GPL-2.02//3// mcp251xfd - Microchip MCP251xFD Family CAN controller driver4//5// Copyright (c) 2019, 2020, 2021, 2023 Pengutronix,6// Marc Kleine-Budde <kernel@pengutronix.de>7//8// Based on:9//10// CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface11//12// Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>13//14 15#include <linux/unaligned.h>16#include <linux/bitfield.h>17#include <linux/clk.h>18#include <linux/device.h>19#include <linux/mod_devicetable.h>20#include <linux/module.h>21#include <linux/pm_runtime.h>22#include <linux/property.h>23 24#include "mcp251xfd.h"25 26#define DEVICE_NAME "mcp251xfd"27 28static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = {29 .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG |30 MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX |31 MCP251XFD_QUIRK_ECC,32 .model = MCP251XFD_MODEL_MCP2517FD,33};34 35static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = {36 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |37 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,38 .model = MCP251XFD_MODEL_MCP2518FD,39};40 41static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251863 = {42 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |43 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,44 .model = MCP251XFD_MODEL_MCP251863,45};46 47/* Autodetect model, start with CRC enabled. */48static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = {49 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |50 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,51 .model = MCP251XFD_MODEL_MCP251XFD,52};53 54static const struct can_bittiming_const mcp251xfd_bittiming_const = {55 .name = DEVICE_NAME,56 .tseg1_min = 2,57 .tseg1_max = 256,58 .tseg2_min = 1,59 .tseg2_max = 128,60 .sjw_max = 128,61 .brp_min = 1,62 .brp_max = 256,63 .brp_inc = 1,64};65 66static const struct can_bittiming_const mcp251xfd_data_bittiming_const = {67 .name = DEVICE_NAME,68 .tseg1_min = 1,69 .tseg1_max = 32,70 .tseg2_min = 1,71 .tseg2_max = 16,72 .sjw_max = 16,73 .brp_min = 1,74 .brp_max = 256,75 .brp_inc = 1,76};77 78static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model)79{80 switch (model) {81 case MCP251XFD_MODEL_MCP2517FD:82 return "MCP2517FD";83 case MCP251XFD_MODEL_MCP2518FD:84 return "MCP2518FD";85 case MCP251XFD_MODEL_MCP251863:86 return "MCP251863";87 case MCP251XFD_MODEL_MCP251XFD:88 return "MCP251xFD";89 }90 91 return "<unknown>";92}93 94static inline const char *95mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv)96{97 return __mcp251xfd_get_model_str(priv->devtype_data.model);98}99 100static const char *mcp251xfd_get_mode_str(const u8 mode)101{102 switch (mode) {103 case MCP251XFD_REG_CON_MODE_MIXED:104 return "Mixed (CAN FD/CAN 2.0)";105 case MCP251XFD_REG_CON_MODE_SLEEP:106 return "Sleep";107 case MCP251XFD_REG_CON_MODE_INT_LOOPBACK:108 return "Internal Loopback";109 case MCP251XFD_REG_CON_MODE_LISTENONLY:110 return "Listen Only";111 case MCP251XFD_REG_CON_MODE_CONFIG:112 return "Configuration";113 case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK:114 return "External Loopback";115 case MCP251XFD_REG_CON_MODE_CAN2_0:116 return "CAN 2.0";117 case MCP251XFD_REG_CON_MODE_RESTRICTED:118 return "Restricted Operation";119 }120 121 return "<unknown>";122}123 124static const char *125mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference)126{127 switch (~osc & osc_reference &128 (MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) {129 case MCP251XFD_REG_OSC_PLLRDY:130 return "PLL";131 case MCP251XFD_REG_OSC_OSCRDY:132 return "Oscillator";133 case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY:134 return "Oscillator/PLL";135 }136 137 return "<unknown>";138}139 140static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv)141{142 if (!priv->reg_vdd)143 return 0;144 145 return regulator_enable(priv->reg_vdd);146}147 148static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv)149{150 if (!priv->reg_vdd)151 return 0;152 153 return regulator_disable(priv->reg_vdd);154}155 156static inline int157mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv)158{159 if (!priv->reg_xceiver)160 return 0;161 162 return regulator_enable(priv->reg_xceiver);163}164 165static inline int166mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv)167{168 if (!priv->reg_xceiver)169 return 0;170 171 return regulator_disable(priv->reg_xceiver);172}173 174static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv)175{176 int err;177 178 err = clk_prepare_enable(priv->clk);179 if (err)180 return err;181 182 err = mcp251xfd_vdd_enable(priv);183 if (err)184 clk_disable_unprepare(priv->clk);185 186 /* Wait for oscillator stabilisation time after power up */187 usleep_range(MCP251XFD_OSC_STAB_SLEEP_US,188 2 * MCP251XFD_OSC_STAB_SLEEP_US);189 190 return err;191}192 193static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv)194{195 int err;196 197 err = mcp251xfd_vdd_disable(priv);198 if (err)199 return err;200 201 clk_disable_unprepare(priv->clk);202 203 return 0;204}205 206static inline bool mcp251xfd_reg_invalid(u32 reg)207{208 return reg == 0x0 || reg == 0xffffffff;209}210 211static inline int212mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode)213{214 u32 val;215 int err;216 217 err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val);218 if (err)219 return err;220 221 *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val);222 223 return 0;224}225 226static int227__mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,228 const u8 mode_req, bool nowait)229{230 const struct can_bittiming *bt = &priv->can.bittiming;231 unsigned long timeout_us = MCP251XFD_POLL_TIMEOUT_US;232 u32 con = 0, con_reqop, osc = 0;233 u8 mode;234 int err;235 236 con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req);237 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON,238 MCP251XFD_REG_CON_REQOP_MASK, con_reqop);239 if (err == -EBADMSG) {240 netdev_err(priv->ndev,241 "Failed to set Requested Operation Mode.\n");242 243 return -ENODEV;244 } else if (err) {245 return err;246 }247 248 if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait)249 return 0;250 251 if (bt->bitrate)252 timeout_us = max_t(unsigned long, timeout_us,253 MCP251XFD_FRAME_LEN_MAX_BITS * USEC_PER_SEC /254 bt->bitrate);255 256 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con,257 !mcp251xfd_reg_invalid(con) &&258 FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK,259 con) == mode_req,260 MCP251XFD_POLL_SLEEP_US, timeout_us);261 if (err != -ETIMEDOUT && err != -EBADMSG)262 return err;263 264 /* Ignore return value.265 * Print below error messages, even if this fails.266 */267 regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);268 269 if (mcp251xfd_reg_invalid(con)) {270 netdev_err(priv->ndev,271 "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n",272 con, osc);273 274 return -ENODEV;275 }276 277 mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con);278 netdev_err(priv->ndev,279 "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n",280 mcp251xfd_get_mode_str(mode_req), mode_req,281 mcp251xfd_get_mode_str(mode), mode,282 con, osc);283 284 return -ETIMEDOUT;285}286 287static inline int288mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,289 const u8 mode_req)290{291 return __mcp251xfd_chip_set_mode(priv, mode_req, false);292}293 294static inline int __maybe_unused295mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv,296 const u8 mode_req)297{298 return __mcp251xfd_chip_set_mode(priv, mode_req, true);299}300 301static int302mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv,303 u32 osc_reference, u32 osc_mask)304{305 u32 osc;306 int err;307 308 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc,309 !mcp251xfd_reg_invalid(osc) &&310 (osc & osc_mask) == osc_reference,311 MCP251XFD_OSC_STAB_SLEEP_US,312 MCP251XFD_OSC_STAB_TIMEOUT_US);313 if (err != -ETIMEDOUT)314 return err;315 316 if (mcp251xfd_reg_invalid(osc)) {317 netdev_err(priv->ndev,318 "Failed to read Oscillator Configuration Register (osc=0x%08x).\n",319 osc);320 return -ENODEV;321 }322 323 netdev_err(priv->ndev,324 "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n",325 mcp251xfd_get_osc_str(osc, osc_reference),326 osc, osc_reference, osc_mask);327 328 return -ETIMEDOUT;329}330 331static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv)332{333 u32 osc, osc_reference, osc_mask;334 int err;335 336 /* For normal sleep on MCP2517FD and MCP2518FD, clearing337 * "Oscillator Disable" will wake the chip. For low power mode338 * on MCP2518FD, asserting the chip select will wake the339 * chip. Writing to the Oscillator register will wake it in340 * both cases.341 */342 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,343 MCP251XFD_REG_OSC_CLKODIV_10);344 345 /* We cannot check for the PLL ready bit (either set or346 * unset), as the PLL might be enabled. This can happen if the347 * system reboots, while the mcp251xfd stays powered.348 */349 osc_reference = MCP251XFD_REG_OSC_OSCRDY;350 osc_mask = MCP251XFD_REG_OSC_OSCRDY;351 352 /* If the controller is in Sleep Mode the following write only353 * removes the "Oscillator Disable" bit and powers it up. All354 * other bits are unaffected.355 */356 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);357 if (err)358 return err;359 360 /* Sometimes the PLL is stuck enabled, the controller never361 * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our362 * caller takes care of retry.363 */364 return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);365}366 367static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv)368{369 if (priv->pll_enable) {370 u32 osc;371 int err;372 373 /* Turn off PLL */374 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,375 MCP251XFD_REG_OSC_CLKODIV_10);376 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);377 if (err)378 netdev_err(priv->ndev,379 "Failed to disable PLL.\n");380 381 priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow;382 }383 384 return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP);385}386 387static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv)388{389 const __be16 cmd = mcp251xfd_cmd_reset();390 int err;391 392 /* The Set Mode and SPI Reset command only works if the393 * controller is not in Sleep Mode.394 */395 err = mcp251xfd_chip_wake(priv);396 if (err)397 return err;398 399 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);400 if (err)401 return err;402 403 /* spi_write_then_read() works with non DMA-safe buffers */404 return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0);405}406 407static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv)408{409 u32 osc_reference, osc_mask;410 u8 mode;411 int err;412 413 /* Check for reset defaults of OSC reg.414 * This will take care of stabilization period.415 */416 osc_reference = MCP251XFD_REG_OSC_OSCRDY |417 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,418 MCP251XFD_REG_OSC_CLKODIV_10);419 osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY;420 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);421 if (err)422 return err;423 424 err = mcp251xfd_chip_get_mode(priv, &mode);425 if (err)426 return err;427 428 if (mode != MCP251XFD_REG_CON_MODE_CONFIG) {429 netdev_info(priv->ndev,430 "Controller not in Config Mode after reset, but in %s Mode (%u).\n",431 mcp251xfd_get_mode_str(mode), mode);432 return -ETIMEDOUT;433 }434 435 return 0;436}437 438static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv)439{440 int err, i;441 442 for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) {443 if (i)444 netdev_info(priv->ndev,445 "Retrying to reset controller.\n");446 447 err = mcp251xfd_chip_softreset_do(priv);448 if (err == -ETIMEDOUT)449 continue;450 if (err)451 return err;452 453 err = mcp251xfd_chip_softreset_check(priv);454 if (err == -ETIMEDOUT)455 continue;456 if (err)457 return err;458 459 return 0;460 }461 462 return err;463}464 465static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv)466{467 u32 osc, osc_reference, osc_mask;468 int err;469 470 /* Activate Low Power Mode on Oscillator Disable. This only471 * works on the MCP2518FD. The MCP2517FD will go into normal472 * Sleep Mode instead.473 */474 osc = MCP251XFD_REG_OSC_LPMEN |475 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,476 MCP251XFD_REG_OSC_CLKODIV_10);477 osc_reference = MCP251XFD_REG_OSC_OSCRDY;478 osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY;479 480 if (priv->pll_enable) {481 osc |= MCP251XFD_REG_OSC_PLLEN;482 osc_reference |= MCP251XFD_REG_OSC_PLLRDY;483 }484 485 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);486 if (err)487 return err;488 489 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);490 if (err)491 return err;492 493 priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast;494 495 return 0;496}497 498static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv)499{500 /* Set Time Base Counter Prescaler to 1.501 *502 * This means an overflow of the 32 bit Time Base Counter503 * register at 40 MHz every 107 seconds.504 */505 return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON,506 MCP251XFD_REG_TSCON_TBCEN);507}508 509static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv)510{511 const struct can_bittiming *bt = &priv->can.bittiming;512 const struct can_bittiming *dbt = &priv->can.data_bittiming;513 u32 val = 0;514 s8 tdco;515 int err;516 517 /* CAN Control Register518 *519 * - no transmit bandwidth sharing520 * - config mode521 * - disable transmit queue522 * - store in transmit FIFO event523 * - transition to restricted operation mode on system error524 * - ESI is transmitted recessive when ESI of message is high or525 * CAN controller error passive526 * - restricted retransmission attempts,527 * use TQXCON_TXAT and FIFOCON_TXAT528 * - wake-up filter bits T11FILTER529 * - use CAN bus line filter for wakeup530 * - protocol exception is treated as a form error531 * - Do not compare data bytes532 */533 val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK,534 MCP251XFD_REG_CON_MODE_CONFIG) |535 MCP251XFD_REG_CON_STEF |536 MCP251XFD_REG_CON_ESIGM |537 MCP251XFD_REG_CON_RTXAT |538 FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK,539 MCP251XFD_REG_CON_WFT_T11FILTER) |540 MCP251XFD_REG_CON_WAKFIL |541 MCP251XFD_REG_CON_PXEDIS;542 543 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))544 val |= MCP251XFD_REG_CON_ISOCRCEN;545 546 err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val);547 if (err)548 return err;549 550 /* Nominal Bit Time */551 val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) |552 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK,553 bt->prop_seg + bt->phase_seg1 - 1) |554 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK,555 bt->phase_seg2 - 1) |556 FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1);557 558 err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val);559 if (err)560 return err;561 562 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))563 return 0;564 565 /* Data Bit Time */566 val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) |567 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK,568 dbt->prop_seg + dbt->phase_seg1 - 1) |569 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK,570 dbt->phase_seg2 - 1) |571 FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1);572 573 err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val);574 if (err)575 return err;576 577 /* Transmitter Delay Compensation */578 tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1),579 -64, 63);580 val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK,581 MCP251XFD_REG_TDC_TDCMOD_AUTO) |582 FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco);583 584 return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val);585}586 587static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv)588{589 u32 val;590 591 if (!priv->rx_int)592 return 0;593 594 /* Configure GPIOs:595 * - PIN0: GPIO Input596 * - PIN1: GPIO Input/RX Interrupt597 *598 * PIN1 must be Input, otherwise there is a glitch on the599 * rx-INT line. It happens between setting the PIN as output600 * (in the first byte of the SPI transfer) and configuring the601 * PIN as interrupt (in the last byte of the SPI transfer).602 */603 val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 |604 MCP251XFD_REG_IOCON_TRIS0;605 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);606}607 608static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv)609{610 u32 val;611 612 if (!priv->rx_int)613 return 0;614 615 /* Configure GPIOs:616 * - PIN0: GPIO Input617 * - PIN1: GPIO Input618 */619 val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 |620 MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0;621 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);622}623 624static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv)625{626 struct mcp251xfd_ecc *ecc = &priv->ecc;627 void *ram;628 u32 val = 0;629 int err;630 631 ecc->ecc_stat = 0;632 633 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC)634 val = MCP251XFD_REG_ECCCON_ECCEN;635 636 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,637 MCP251XFD_REG_ECCCON_ECCEN, val);638 if (err)639 return err;640 641 ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL);642 if (!ram)643 return -ENOMEM;644 645 err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram,646 MCP251XFD_RAM_SIZE);647 kfree(ram);648 649 return err;650}651 652static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv)653{654 u8 mode;655 656 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)657 mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK;658 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)659 mode = MCP251XFD_REG_CON_MODE_LISTENONLY;660 else if (priv->can.ctrlmode & CAN_CTRLMODE_FD)661 mode = MCP251XFD_REG_CON_MODE_MIXED;662 else663 mode = MCP251XFD_REG_CON_MODE_CAN2_0;664 665 return mode;666}667 668static int669__mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv,670 bool nowait)671{672 u8 mode;673 674 mode = mcp251xfd_get_normal_mode(priv);675 676 return __mcp251xfd_chip_set_mode(priv, mode, nowait);677}678 679static inline int680mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv)681{682 return __mcp251xfd_chip_set_normal_mode(priv, false);683}684 685static inline int686mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv)687{688 return __mcp251xfd_chip_set_normal_mode(priv, true);689}690 691static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv)692{693 u32 val;694 int err;695 696 val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE;697 err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val);698 if (err)699 return err;700 701 val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;702 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val);703 if (err)704 return err;705 706 val = MCP251XFD_REG_INT_CERRIE |707 MCP251XFD_REG_INT_SERRIE |708 MCP251XFD_REG_INT_RXOVIE |709 MCP251XFD_REG_INT_TXATIE |710 MCP251XFD_REG_INT_SPICRCIE |711 MCP251XFD_REG_INT_ECCIE |712 MCP251XFD_REG_INT_TEFIE |713 MCP251XFD_REG_INT_MODIE |714 MCP251XFD_REG_INT_RXIE;715 716 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)717 val |= MCP251XFD_REG_INT_IVMIE;718 719 return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val);720}721 722static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv)723{724 int err;725 u32 mask;726 727 err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0);728 if (err)729 return err;730 731 mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;732 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,733 mask, 0x0);734 if (err)735 return err;736 737 return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0);738}739 740static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv,741 const enum can_state state)742{743 priv->can.state = state;744 745 mcp251xfd_chip_interrupts_disable(priv);746 mcp251xfd_chip_rx_int_disable(priv);747 mcp251xfd_timestamp_stop(priv);748 mcp251xfd_chip_sleep(priv);749}750 751static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv)752{753 int err;754 755 err = mcp251xfd_chip_softreset(priv);756 if (err)757 goto out_chip_stop;758 759 err = mcp251xfd_chip_clock_init(priv);760 if (err)761 goto out_chip_stop;762 763 err = mcp251xfd_chip_timestamp_init(priv);764 if (err)765 goto out_chip_stop;766 767 mcp251xfd_timestamp_start(priv);768 769 err = mcp251xfd_set_bittiming(priv);770 if (err)771 goto out_chip_stop;772 773 err = mcp251xfd_chip_rx_int_enable(priv);774 if (err)775 goto out_chip_stop;776 777 err = mcp251xfd_chip_ecc_init(priv);778 if (err)779 goto out_chip_stop;780 781 err = mcp251xfd_ring_init(priv);782 if (err)783 goto out_chip_stop;784 785 err = mcp251xfd_chip_fifo_init(priv);786 if (err)787 goto out_chip_stop;788 789 priv->can.state = CAN_STATE_ERROR_ACTIVE;790 791 err = mcp251xfd_chip_set_normal_mode(priv);792 if (err)793 goto out_chip_stop;794 795 return 0;796 797out_chip_stop:798 mcp251xfd_dump(priv);799 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);800 801 return err;802}803 804static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode)805{806 struct mcp251xfd_priv *priv = netdev_priv(ndev);807 int err;808 809 switch (mode) {810 case CAN_MODE_START:811 err = mcp251xfd_chip_start(priv);812 if (err)813 return err;814 815 err = mcp251xfd_chip_interrupts_enable(priv);816 if (err) {817 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);818 return err;819 }820 821 netif_wake_queue(ndev);822 break;823 824 default:825 return -EOPNOTSUPP;826 }827 828 return 0;829}830 831static int __mcp251xfd_get_berr_counter(const struct net_device *ndev,832 struct can_berr_counter *bec)833{834 const struct mcp251xfd_priv *priv = netdev_priv(ndev);835 u32 trec;836 int err;837 838 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);839 if (err)840 return err;841 842 if (trec & MCP251XFD_REG_TREC_TXBO)843 bec->txerr = CAN_BUS_OFF_THRESHOLD;844 else845 bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec);846 bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec);847 848 return 0;849}850 851static int mcp251xfd_get_berr_counter(const struct net_device *ndev,852 struct can_berr_counter *bec)853{854 const struct mcp251xfd_priv *priv = netdev_priv(ndev);855 856 /* Avoid waking up the controller if the interface is down */857 if (!(ndev->flags & IFF_UP))858 return 0;859 860 /* The controller is powered down during Bus Off, use saved861 * bec values.862 */863 if (priv->can.state == CAN_STATE_BUS_OFF) {864 *bec = priv->bec;865 return 0;866 }867 868 return __mcp251xfd_get_berr_counter(ndev, bec);869}870 871static struct sk_buff *872mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv,873 struct can_frame **cf, u32 *ts_raw)874{875 struct sk_buff *skb;876 int err;877 878 err = mcp251xfd_get_timestamp_raw(priv, ts_raw);879 if (err)880 return NULL;881 882 skb = alloc_can_err_skb(priv->ndev, cf);883 if (skb)884 mcp251xfd_skb_set_timestamp_raw(priv, skb, *ts_raw);885 886 return skb;887}888 889static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv)890{891 struct net_device_stats *stats = &priv->ndev->stats;892 struct mcp251xfd_rx_ring *ring;893 struct sk_buff *skb;894 struct can_frame *cf;895 u32 ts_raw, rxovif;896 int err, i;897 898 stats->rx_over_errors++;899 stats->rx_errors++;900 901 err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif);902 if (err)903 return err;904 905 mcp251xfd_for_each_rx_ring(priv, ring, i) {906 if (!(rxovif & BIT(ring->fifo_nr)))907 continue;908 909 /* If SERRIF is active, there was a RX MAB overflow. */910 if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) {911 if (net_ratelimit())912 netdev_dbg(priv->ndev,913 "RX-%d: MAB overflow detected.\n",914 ring->nr);915 } else {916 if (net_ratelimit())917 netdev_dbg(priv->ndev,918 "RX-%d: FIFO overflow.\n",919 ring->nr);920 }921 922 err = regmap_update_bits(priv->map_reg,923 MCP251XFD_REG_FIFOSTA(ring->fifo_nr),924 MCP251XFD_REG_FIFOSTA_RXOVIF,925 0x0);926 if (err)927 return err;928 }929 930 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, &ts_raw);931 if (!skb)932 return 0;933 934 cf->can_id |= CAN_ERR_CRTL;935 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;936 937 err = can_rx_offload_queue_timestamp(&priv->offload, skb, ts_raw);938 if (err)939 stats->rx_fifo_errors++;940 941 return 0;942}943 944static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv)945{946 netdev_info(priv->ndev, "%s\n", __func__);947 948 return 0;949}950 951static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv)952{953 struct net_device_stats *stats = &priv->ndev->stats;954 u32 bdiag1, ts_raw;955 struct sk_buff *skb;956 struct can_frame *cf = NULL;957 int err;958 959 err = mcp251xfd_get_timestamp_raw(priv, &ts_raw);960 if (err)961 return err;962 963 err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1);964 if (err)965 return err;966 967 /* Write 0s to clear error bits, don't write 1s to non active968 * bits, as they will be set.969 */970 err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0);971 if (err)972 return err;973 974 priv->can.can_stats.bus_error++;975 976 skb = alloc_can_err_skb(priv->ndev, &cf);977 if (cf)978 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;979 980 /* Controller misconfiguration */981 if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM))982 netdev_err(priv->ndev,983 "recv'd DLC is larger than PLSIZE of FIFO element.");984 985 /* RX errors */986 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR |987 MCP251XFD_REG_BDIAG1_NCRCERR)) {988 netdev_dbg(priv->ndev, "CRC error\n");989 990 stats->rx_errors++;991 if (cf)992 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;993 }994 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR |995 MCP251XFD_REG_BDIAG1_NSTUFERR)) {996 netdev_dbg(priv->ndev, "Stuff error\n");997 998 stats->rx_errors++;999 if (cf)1000 cf->data[2] |= CAN_ERR_PROT_STUFF;1001 }1002 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR |1003 MCP251XFD_REG_BDIAG1_NFORMERR)) {1004 netdev_dbg(priv->ndev, "Format error\n");1005 1006 stats->rx_errors++;1007 if (cf)1008 cf->data[2] |= CAN_ERR_PROT_FORM;1009 }1010 1011 /* TX errors */1012 if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) {1013 netdev_dbg(priv->ndev, "NACK error\n");1014 1015 stats->tx_errors++;1016 if (cf) {1017 cf->can_id |= CAN_ERR_ACK;1018 cf->data[2] |= CAN_ERR_PROT_TX;1019 }1020 }1021 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR |1022 MCP251XFD_REG_BDIAG1_NBIT1ERR)) {1023 netdev_dbg(priv->ndev, "Bit1 error\n");1024 1025 stats->tx_errors++;1026 if (cf)1027 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1;1028 }1029 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR |1030 MCP251XFD_REG_BDIAG1_NBIT0ERR)) {1031 netdev_dbg(priv->ndev, "Bit0 error\n");1032 1033 stats->tx_errors++;1034 if (cf)1035 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0;1036 }1037 1038 if (!cf)1039 return 0;1040 1041 mcp251xfd_skb_set_timestamp_raw(priv, skb, ts_raw);1042 err = can_rx_offload_queue_timestamp(&priv->offload, skb, ts_raw);1043 if (err)1044 stats->rx_fifo_errors++;1045 1046 return 0;1047}1048 1049static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv)1050{1051 struct net_device_stats *stats = &priv->ndev->stats;1052 struct sk_buff *skb;1053 struct can_frame *cf = NULL;1054 enum can_state new_state, rx_state, tx_state;1055 u32 trec, ts_raw;1056 int err;1057 1058 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);1059 if (err)1060 return err;1061 1062 if (trec & MCP251XFD_REG_TREC_TXBO)1063 tx_state = CAN_STATE_BUS_OFF;1064 else if (trec & MCP251XFD_REG_TREC_TXBP)1065 tx_state = CAN_STATE_ERROR_PASSIVE;1066 else if (trec & MCP251XFD_REG_TREC_TXWARN)1067 tx_state = CAN_STATE_ERROR_WARNING;1068 else1069 tx_state = CAN_STATE_ERROR_ACTIVE;1070 1071 if (trec & MCP251XFD_REG_TREC_RXBP)1072 rx_state = CAN_STATE_ERROR_PASSIVE;1073 else if (trec & MCP251XFD_REG_TREC_RXWARN)1074 rx_state = CAN_STATE_ERROR_WARNING;1075 else1076 rx_state = CAN_STATE_ERROR_ACTIVE;1077 1078 new_state = max(tx_state, rx_state);1079 if (new_state == priv->can.state)1080 return 0;1081 1082 /* The skb allocation might fail, but can_change_state()1083 * handles cf == NULL.1084 */1085 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, &ts_raw);1086 can_change_state(priv->ndev, cf, tx_state, rx_state);1087 1088 if (new_state == CAN_STATE_BUS_OFF) {1089 /* As we're going to switch off the chip now, let's1090 * save the error counters and return them to1091 * userspace, if do_get_berr_counter() is called while1092 * the chip is in Bus Off.1093 */1094 err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec);1095 if (err)1096 return err;1097 1098 mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF);1099 can_bus_off(priv->ndev);1100 }1101 1102 if (!skb)1103 return 0;1104 1105 if (new_state != CAN_STATE_BUS_OFF) {1106 struct can_berr_counter bec;1107 1108 err = mcp251xfd_get_berr_counter(priv->ndev, &bec);1109 if (err)1110 return err;1111 cf->can_id |= CAN_ERR_CNT;1112 cf->data[6] = bec.txerr;1113 cf->data[7] = bec.rxerr;1114 }1115 1116 err = can_rx_offload_queue_timestamp(&priv->offload, skb, ts_raw);1117 if (err)1118 stats->rx_fifo_errors++;1119 1120 return 0;1121}1122 1123static int1124mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode)1125{1126 const u8 mode_reference = mcp251xfd_get_normal_mode(priv);1127 u8 mode;1128 int err;1129 1130 err = mcp251xfd_chip_get_mode(priv, &mode);1131 if (err)1132 return err;1133 1134 if (mode == mode_reference) {1135 netdev_dbg(priv->ndev,1136 "Controller changed into %s Mode (%u).\n",1137 mcp251xfd_get_mode_str(mode), mode);1138 return 0;1139 }1140 1141 /* According to MCP2517FD errata DS80000792C 1., during a TX1142 * MAB underflow, the controller will transition to Restricted1143 * Operation Mode or Listen Only Mode (depending on SERR2LOM).1144 *1145 * However this is not always the case. If SERR2LOM is1146 * configured for Restricted Operation Mode (SERR2LOM not set)1147 * the MCP2517FD will sometimes transition to Listen Only Mode1148 * first. When polling this bit we see that it will transition1149 * to Restricted Operation Mode shortly after.1150 */1151 if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) &&1152 (mode == MCP251XFD_REG_CON_MODE_RESTRICTED ||1153 mode == MCP251XFD_REG_CON_MODE_LISTENONLY))1154 netdev_dbg(priv->ndev,1155 "Controller changed into %s Mode (%u).\n",1156 mcp251xfd_get_mode_str(mode), mode);1157 else1158 netdev_err(priv->ndev,1159 "Controller changed into %s Mode (%u).\n",1160 mcp251xfd_get_mode_str(mode), mode);1161 1162 /* After the application requests Normal mode, the controller1163 * will automatically attempt to retransmit the message that1164 * caused the TX MAB underflow.1165 *1166 * However, if there is an ECC error in the TX-RAM, we first1167 * have to reload the tx-object before requesting Normal1168 * mode. This is done later in mcp251xfd_handle_eccif().1169 */1170 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) {1171 *set_normal_mode = true;1172 return 0;1173 }1174 1175 return mcp251xfd_chip_set_normal_mode_nowait(priv);1176}1177 1178static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv)1179{1180 struct mcp251xfd_ecc *ecc = &priv->ecc;1181 struct net_device_stats *stats = &priv->ndev->stats;1182 bool handled = false;1183 1184 /* TX MAB underflow1185 *1186 * According to MCP2517FD Errata DS80000792C 1. a TX MAB1187 * underflow is indicated by SERRIF and MODIF.1188 *1189 * In addition to the effects mentioned in the Errata, there1190 * are Bus Errors due to the aborted CAN frame, so a IVMIF1191 * will be seen as well.1192 *1193 * Sometimes there is an ECC error in the TX-RAM, which leads1194 * to a TX MAB underflow.1195 *1196 * However, probably due to a race condition, there is no1197 * associated MODIF pending.1198 *1199 * Further, there are situations, where the SERRIF is caused1200 * by an ECC error in the TX-RAM, but not even the ECCIF is1201 * set. This only seems to happen _after_ the first occurrence1202 * of a ECCIF (which is tracked in ecc->cnt).1203 *1204 * Treat all as a known system errors..1205 */1206 if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF &&1207 priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) ||1208 priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||1209 ecc->cnt) {1210 const char *msg;1211 1212 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||1213 ecc->cnt)1214 msg = "TX MAB underflow due to ECC error detected.";1215 else1216 msg = "TX MAB underflow detected.";1217 1218 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN)1219 netdev_dbg(priv->ndev, "%s\n", msg);1220 else1221 netdev_info(priv->ndev, "%s\n", msg);1222 1223 stats->tx_aborted_errors++;1224 stats->tx_errors++;1225 handled = true;1226 }1227 1228 /* RX MAB overflow1229 *1230 * According to MCP2517FD Errata DS80000792C 1. a RX MAB1231 * overflow is indicated by SERRIF.1232 *1233 * In addition to the effects mentioned in the Errata, (most1234 * of the times) a RXOVIF is raised, if the FIFO that is being1235 * received into has the RXOVIE activated (and we have enabled1236 * RXOVIE on all FIFOs).1237 *1238 * Sometimes there is no RXOVIF just a RXIF is pending.1239 *1240 * Treat all as a known system errors..1241 */1242 if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF ||1243 priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) {1244 stats->rx_dropped++;1245 handled = true;1246 }1247 1248 if (!handled)1249 netdev_err(priv->ndev,1250 "Unhandled System Error Interrupt (intf=0x%08x)!\n",1251 priv->regs_status.intf);1252 1253 return 0;1254}1255 1256static int1257mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr)1258{1259 struct mcp251xfd_tx_ring *tx_ring = priv->tx;1260 struct mcp251xfd_ecc *ecc = &priv->ecc;1261 struct mcp251xfd_tx_obj *tx_obj;1262 u8 chip_tx_tail, tx_tail, offset;1263 u16 addr;1264 int err;1265 1266 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat);1267 1268 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail);1269 if (err)1270 return err;1271 1272 tx_tail = mcp251xfd_get_tx_tail(tx_ring);1273 offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1);1274 1275 /* Bail out if one of the following is met:1276 * - tx_tail information is inconsistent1277 * - for mcp2517fd: offset not 01278 * - for mcp2518fd: offset not 0 or 11279 */1280 if (chip_tx_tail != tx_tail ||1281 !(offset == 0 || (offset == 1 && (mcp251xfd_is_2518FD(priv) ||1282 mcp251xfd_is_251863(priv))))) {1283 netdev_err(priv->ndev,1284 "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n",1285 addr, nr, tx_ring->tail, tx_tail, chip_tx_tail,1286 offset);1287 return -EINVAL;1288 }1289 1290 netdev_info(priv->ndev,1291 "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n",1292 ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ?1293 "Single" : "Double",1294 addr, nr, tx_ring->tail, tx_tail, offset);1295 1296 /* reload tx_obj into controller RAM ... */1297 tx_obj = &tx_ring->obj[nr];1298 err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1);1299 if (err)1300 return err;1301 1302 /* ... and trigger retransmit */1303 return mcp251xfd_chip_set_normal_mode(priv);1304}1305 1306static int1307mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode)1308{1309 struct mcp251xfd_ecc *ecc = &priv->ecc;1310 const char *msg;1311 bool in_tx_ram;1312 u32 ecc_stat;1313 u16 addr;1314 u8 nr;1315 int err;1316 1317 err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat);1318 if (err)1319 return err;1320 1321 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT,1322 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat);1323 if (err)1324 return err;1325 1326 /* Check if ECC error occurred in TX-RAM */1327 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat);1328 err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr);1329 if (!err)1330 in_tx_ram = true;1331 else if (err == -ENOENT)1332 in_tx_ram = false;1333 else1334 return err;1335 1336 /* Errata Reference:1337 * mcp2517fd: DS80000789C 3., mcp2518fd: DS80000792E 2.,1338 * mcp251863: DS80000984A 2.1339 *1340 * ECC single error correction does not work in all cases:1341 *1342 * Fix/Work Around:1343 * Enable single error correction and double error detection1344 * interrupts by setting SECIE and DEDIE. Handle SECIF as a1345 * detection interrupt and do not rely on the error1346 * correction. Instead, handle both interrupts as a1347 * notification that the RAM word at ERRADDR was corrupted.1348 */1349 if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF)1350 msg = "Single ECC Error detected at address";1351 else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF)1352 msg = "Double ECC Error detected at address";1353 else1354 return -EINVAL;1355 1356 if (!in_tx_ram) {1357 ecc->ecc_stat = 0;1358 1359 netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr);1360 } else {1361 /* Re-occurring error? */1362 if (ecc->ecc_stat == ecc_stat) {1363 ecc->cnt++;1364 } else {1365 ecc->ecc_stat = ecc_stat;1366 ecc->cnt = 1;1367 }1368 1369 netdev_info(priv->ndev,1370 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n",1371 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : "");1372 1373 if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX)1374 return mcp251xfd_handle_eccif_recover(priv, nr);1375 }1376 1377 if (set_normal_mode)1378 return mcp251xfd_chip_set_normal_mode_nowait(priv);1379 1380 return 0;1381}1382 1383static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv)1384{1385 int err;1386 u32 crc;1387 1388 err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc);1389 if (err)1390 return err;1391 1392 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC,1393 MCP251XFD_REG_CRC_IF_MASK,1394 ~crc);1395 if (err)1396 return err;1397 1398 if (crc & MCP251XFD_REG_CRC_FERRIF)1399 netdev_notice(priv->ndev, "CRC write command format error.\n");1400 else if (crc & MCP251XFD_REG_CRC_CRCERRIF)1401 netdev_notice(priv->ndev,1402 "CRC write error detected. CRC=0x%04lx.\n",1403 FIELD_GET(MCP251XFD_REG_CRC_MASK, crc));1404 1405 return 0;1406}1407 1408static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv)1409{1410 const int val_bytes = regmap_get_val_bytes(priv->map_reg);1411 size_t len;1412 1413 if (priv->rx_ring_num == 1)1414 len = sizeof(priv->regs_status.intf);1415 else1416 len = sizeof(priv->regs_status);1417 1418 return regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT,1419 &priv->regs_status, len / val_bytes);1420}1421 1422#define mcp251xfd_handle(priv, irq, ...) \1423({ \1424 struct mcp251xfd_priv *_priv = (priv); \1425 int err; \1426\1427 err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \1428 if (err) \1429 netdev_err(_priv->ndev, \1430 "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \1431 __stringify(irq), err); \1432 err; \1433})1434 1435static irqreturn_t mcp251xfd_irq(int irq, void *dev_id)1436{1437 struct mcp251xfd_priv *priv = dev_id;1438 irqreturn_t handled = IRQ_NONE;1439 int err;1440 1441 if (priv->rx_int)1442 do {1443 int rx_pending;1444 1445 rx_pending = gpiod_get_value_cansleep(priv->rx_int);1446 if (!rx_pending)1447 break;1448 1449 /* Assume 1st RX-FIFO pending, if other FIFOs1450 * are pending the main IRQ handler will take1451 * care.1452 */1453 priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr);1454 err = mcp251xfd_handle(priv, rxif);1455 if (err)1456 goto out_fail;1457 1458 handled = IRQ_HANDLED;1459 1460 /* We don't know which RX-FIFO is pending, but only1461 * handle the 1st RX-FIFO. Leave loop here if we have1462 * more than 1 RX-FIFO to avoid starvation.1463 */1464 } while (priv->rx_ring_num == 1);1465 1466 do {1467 u32 intf_pending, intf_pending_clearable;1468 bool set_normal_mode = false;1469 1470 err = mcp251xfd_read_regs_status(priv);1471 if (err)1472 goto out_fail;1473 1474 intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK,1475 priv->regs_status.intf) &1476 FIELD_GET(MCP251XFD_REG_INT_IE_MASK,1477 priv->regs_status.intf);1478 1479 if (!(intf_pending)) {1480 can_rx_offload_threaded_irq_finish(&priv->offload);1481 return handled;1482 }1483 1484 /* Some interrupts must be ACKed in the1485 * MCP251XFD_REG_INT register.1486 * - First ACK then handle, to avoid lost-IRQ race1487 * condition on fast re-occurring interrupts.1488 * - Write "0" to clear active IRQs, "1" to all other,1489 * to avoid r/m/w race condition on the1490 * MCP251XFD_REG_INT register.1491 */1492 intf_pending_clearable = intf_pending &1493 MCP251XFD_REG_INT_IF_CLEARABLE_MASK;1494 if (intf_pending_clearable) {1495 err = regmap_update_bits(priv->map_reg,1496 MCP251XFD_REG_INT,1497 MCP251XFD_REG_INT_IF_MASK,1498 ~intf_pending_clearable);1499 if (err)1500 goto out_fail;1501 }1502 1503 if (intf_pending & MCP251XFD_REG_INT_MODIF) {1504 err = mcp251xfd_handle(priv, modif, &set_normal_mode);1505 if (err)1506 goto out_fail;1507 }1508 1509 if (intf_pending & MCP251XFD_REG_INT_RXIF) {1510 err = mcp251xfd_handle(priv, rxif);1511 if (err)1512 goto out_fail;1513 }1514 1515 if (intf_pending & MCP251XFD_REG_INT_TEFIF) {1516 err = mcp251xfd_handle(priv, tefif);1517 if (err)1518 goto out_fail;1519 }1520 1521 if (intf_pending & MCP251XFD_REG_INT_RXOVIF) {1522 err = mcp251xfd_handle(priv, rxovif);1523 if (err)1524 goto out_fail;1525 }1526 1527 if (intf_pending & MCP251XFD_REG_INT_TXATIF) {1528 err = mcp251xfd_handle(priv, txatif);1529 if (err)1530 goto out_fail;1531 }1532 1533 if (intf_pending & MCP251XFD_REG_INT_IVMIF) {1534 err = mcp251xfd_handle(priv, ivmif);1535 if (err)1536 goto out_fail;1537 }1538 1539 if (intf_pending & MCP251XFD_REG_INT_SERRIF) {1540 err = mcp251xfd_handle(priv, serrif);1541 if (err)1542 goto out_fail;1543 }1544 1545 if (intf_pending & MCP251XFD_REG_INT_ECCIF) {1546 err = mcp251xfd_handle(priv, eccif, set_normal_mode);1547 if (err)1548 goto out_fail;1549 }1550 1551 if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) {1552 err = mcp251xfd_handle(priv, spicrcif);1553 if (err)1554 goto out_fail;1555 }1556 1557 /* On the MCP2527FD and MCP2518FD, we don't get a1558 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX1559 * ERROR_ACTIVE.1560 */1561 if (intf_pending & MCP251XFD_REG_INT_CERRIF ||1562 priv->can.state > CAN_STATE_ERROR_ACTIVE) {1563 err = mcp251xfd_handle(priv, cerrif);1564 if (err)1565 goto out_fail;1566 1567 /* In Bus Off we completely shut down the1568 * controller. Every subsequent register read1569 * will read bogus data, and if1570 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC1571 * check will fail, too. So leave IRQ handler1572 * directly.1573 */1574 if (priv->can.state == CAN_STATE_BUS_OFF) {1575 can_rx_offload_threaded_irq_finish(&priv->offload);1576 return IRQ_HANDLED;1577 }1578 }1579 1580 handled = IRQ_HANDLED;1581 } while (1);1582 1583out_fail:1584 can_rx_offload_threaded_irq_finish(&priv->offload);1585 1586 netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n",1587 err, priv->regs_status.intf);1588 mcp251xfd_dump(priv);1589 mcp251xfd_chip_interrupts_disable(priv);1590 mcp251xfd_timestamp_stop(priv);1591 1592 return handled;1593}1594 1595static int mcp251xfd_open(struct net_device *ndev)1596{1597 struct mcp251xfd_priv *priv = netdev_priv(ndev);1598 const struct spi_device *spi = priv->spi;1599 int err;1600 1601 err = open_candev(ndev);1602 if (err)1603 return err;1604 1605 err = pm_runtime_resume_and_get(ndev->dev.parent);1606 if (err)1607 goto out_close_candev;1608 1609 err = mcp251xfd_ring_alloc(priv);1610 if (err)1611 goto out_pm_runtime_put;1612 1613 err = mcp251xfd_transceiver_enable(priv);1614 if (err)1615 goto out_mcp251xfd_ring_free;1616 1617 mcp251xfd_timestamp_init(priv);1618 1619 err = mcp251xfd_chip_start(priv);1620 if (err)1621 goto out_transceiver_disable;1622 1623 clear_bit(MCP251XFD_FLAGS_DOWN, priv->flags);1624 can_rx_offload_enable(&priv->offload);1625 1626 priv->wq = alloc_ordered_workqueue("%s-mcp251xfd_wq",1627 WQ_FREEZABLE | WQ_MEM_RECLAIM,1628 dev_name(&spi->dev));1629 if (!priv->wq) {1630 err = -ENOMEM;1631 goto out_can_rx_offload_disable;1632 }1633 INIT_WORK(&priv->tx_work, mcp251xfd_tx_obj_write_sync);1634 1635 err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq,1636 IRQF_SHARED | IRQF_ONESHOT,1637 dev_name(&spi->dev), priv);1638 if (err)1639 goto out_destroy_workqueue;1640 1641 err = mcp251xfd_chip_interrupts_enable(priv);1642 if (err)1643 goto out_free_irq;1644 1645 netif_start_queue(ndev);1646 1647 return 0;1648 1649out_free_irq:1650 free_irq(spi->irq, priv);1651out_destroy_workqueue:1652 destroy_workqueue(priv->wq);1653out_can_rx_offload_disable:1654 can_rx_offload_disable(&priv->offload);1655 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);1656out_transceiver_disable:1657 mcp251xfd_transceiver_disable(priv);1658out_mcp251xfd_ring_free:1659 mcp251xfd_ring_free(priv);1660out_pm_runtime_put:1661 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);1662 pm_runtime_put(ndev->dev.parent);1663out_close_candev:1664 close_candev(ndev);1665 1666 return err;1667}1668 1669static int mcp251xfd_stop(struct net_device *ndev)1670{1671 struct mcp251xfd_priv *priv = netdev_priv(ndev);1672 1673 netif_stop_queue(ndev);1674 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);1675 hrtimer_cancel(&priv->rx_irq_timer);1676 hrtimer_cancel(&priv->tx_irq_timer);1677 mcp251xfd_chip_interrupts_disable(priv);1678 free_irq(ndev->irq, priv);1679 destroy_workqueue(priv->wq);1680 can_rx_offload_disable(&priv->offload);1681 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);1682 mcp251xfd_transceiver_disable(priv);1683 mcp251xfd_ring_free(priv);1684 close_candev(ndev);1685 1686 pm_runtime_put(ndev->dev.parent);1687 1688 return 0;1689}1690 1691static const struct net_device_ops mcp251xfd_netdev_ops = {1692 .ndo_open = mcp251xfd_open,1693 .ndo_stop = mcp251xfd_stop,1694 .ndo_start_xmit = mcp251xfd_start_xmit,1695 .ndo_eth_ioctl = can_eth_ioctl_hwts,1696 .ndo_change_mtu = can_change_mtu,1697};1698 1699static void1700mcp251xfd_register_quirks(struct mcp251xfd_priv *priv)1701{1702 const struct spi_device *spi = priv->spi;1703 const struct spi_controller *ctlr = spi->controller;1704 1705 if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)1706 priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX;1707}1708 1709static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv)1710{1711 const struct net_device *ndev = priv->ndev;1712 const struct mcp251xfd_devtype_data *devtype_data;1713 u32 osc;1714 int err;1715 1716 /* The OSC_LPMEN is only supported on MCP2518FD and MCP251863,1717 * so use it to autodetect the model.1718 */1719 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC,1720 MCP251XFD_REG_OSC_LPMEN,1721 MCP251XFD_REG_OSC_LPMEN);1722 if (err)1723 return err;1724 1725 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);1726 if (err)1727 return err;1728 1729 if (osc & MCP251XFD_REG_OSC_LPMEN) {1730 /* We cannot distinguish between MCP2518FD and1731 * MCP251863. If firmware specifies MCP251863, keep1732 * it, otherwise set to MCP2518FD.1733 */1734 if (mcp251xfd_is_251863(priv))1735 devtype_data = &mcp251xfd_devtype_data_mcp251863;1736 else1737 devtype_data = &mcp251xfd_devtype_data_mcp2518fd;1738 } else {1739 devtype_data = &mcp251xfd_devtype_data_mcp2517fd;1740 }1741 1742 if (!mcp251xfd_is_251XFD(priv) &&1743 priv->devtype_data.model != devtype_data->model) {1744 netdev_info(ndev,1745 "Detected %s, but firmware specifies a %s. Fixing up.\n",1746 __mcp251xfd_get_model_str(devtype_data->model),1747 mcp251xfd_get_model_str(priv));1748 }1749 priv->devtype_data = *devtype_data;1750 1751 /* We need to preserve the Half Duplex Quirk. */1752 mcp251xfd_register_quirks(priv);1753 1754 /* Re-init regmap with quirks of detected model. */1755 return mcp251xfd_regmap_init(priv);1756}1757 1758static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv)1759{1760 int err, rx_pending;1761 1762 if (!priv->rx_int)1763 return 0;1764 1765 err = mcp251xfd_chip_rx_int_enable(priv);1766 if (err)1767 return err;1768 1769 /* Check if RX_INT is properly working. The RX_INT should not1770 * be active after a softreset.1771 */1772 rx_pending = gpiod_get_value_cansleep(priv->rx_int);1773 1774 err = mcp251xfd_chip_rx_int_disable(priv);1775 if (err)1776 return err;1777 1778 if (!rx_pending)1779 return 0;1780 1781 netdev_info(priv->ndev,1782 "RX_INT active after softreset, disabling RX_INT support.\n");1783 devm_gpiod_put(&priv->spi->dev, priv->rx_int);1784 priv->rx_int = NULL;1785 1786 return 0;1787}1788 1789static int1790mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id,1791 u32 *effective_speed_hz_slow,1792 u32 *effective_speed_hz_fast)1793{1794 struct mcp251xfd_map_buf_nocrc *buf_rx;1795 struct mcp251xfd_map_buf_nocrc *buf_tx;1796 struct spi_transfer xfer[2] = { };1797 int err;1798 1799 buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL);1800 if (!buf_rx)1801 return -ENOMEM;1802 1803 buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL);1804 if (!buf_tx) {1805 err = -ENOMEM;1806 goto out_kfree_buf_rx;1807 }1808 1809 xfer[0].tx_buf = buf_tx;1810 xfer[0].len = sizeof(buf_tx->cmd);1811 xfer[0].speed_hz = priv->spi_max_speed_hz_slow;1812 xfer[1].rx_buf = buf_rx->data;1813 xfer[1].len = sizeof(*dev_id);1814 xfer[1].speed_hz = priv->spi_max_speed_hz_fast;1815 1816 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID);1817 1818 err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer));1819 if (err)1820 goto out_kfree_buf_tx;1821 1822 *dev_id = get_unaligned_le32(buf_rx->data);1823 *effective_speed_hz_slow = xfer[0].effective_speed_hz;1824 *effective_speed_hz_fast = xfer[1].effective_speed_hz;1825 1826out_kfree_buf_tx:1827 kfree(buf_tx);1828out_kfree_buf_rx:1829 kfree(buf_rx);1830 1831 return err;1832}1833 1834#define MCP251XFD_QUIRK_ACTIVE(quirk) \1835 (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-')1836 1837static int1838mcp251xfd_register_done(const struct mcp251xfd_priv *priv)1839{1840 u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast;1841 unsigned long clk_rate;1842 int err;1843 1844 err = mcp251xfd_register_get_dev_id(priv, &dev_id,1845 &effective_speed_hz_slow,1846 &effective_speed_hz_fast);1847 if (err)1848 return err;1849 1850 clk_rate = clk_get_rate(priv->clk);1851 1852 netdev_info(priv->ndev,1853 "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n",1854 mcp251xfd_get_model_str(priv),1855 FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id),1856 FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id),1857 priv->rx_int ? '+' : '-',1858 priv->pll_enable ? '+' : '-',1859 MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN),1860 MCP251XFD_QUIRK_ACTIVE(CRC_REG),1861 MCP251XFD_QUIRK_ACTIVE(CRC_RX),1862 MCP251XFD_QUIRK_ACTIVE(CRC_TX),1863 MCP251XFD_QUIRK_ACTIVE(ECC),1864 MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX),1865 clk_rate / 1000000,1866 clk_rate % 1000000 / 1000 / 10,1867 priv->can.clock.freq / 1000000,1868 priv->can.clock.freq % 1000000 / 1000 / 10,1869 priv->spi_max_speed_hz_orig / 1000000,1870 priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10,1871 priv->spi_max_speed_hz_slow / 1000000,1872 priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10,1873 effective_speed_hz_slow / 1000000,1874 effective_speed_hz_slow % 1000000 / 1000 / 10,1875 priv->spi_max_speed_hz_fast / 1000000,1876 priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10,1877 effective_speed_hz_fast / 1000000,1878 effective_speed_hz_fast % 1000000 / 1000 / 10);1879 1880 return 0;1881}1882 1883static int mcp251xfd_register(struct mcp251xfd_priv *priv)1884{1885 struct net_device *ndev = priv->ndev;1886 int err;1887 1888 err = mcp251xfd_clks_and_vdd_enable(priv);1889 if (err)1890 return err;1891 1892 pm_runtime_get_noresume(ndev->dev.parent);1893 err = pm_runtime_set_active(ndev->dev.parent);1894 if (err)1895 goto out_runtime_put_noidle;1896 pm_runtime_enable(ndev->dev.parent);1897 1898 mcp251xfd_register_quirks(priv);1899 1900 err = mcp251xfd_chip_softreset(priv);1901 if (err == -ENODEV)1902 goto out_runtime_disable;1903 if (err)1904 goto out_chip_sleep;1905 1906 err = mcp251xfd_chip_clock_init(priv);1907 if (err == -ENODEV)1908 goto out_runtime_disable;1909 if (err)1910 goto out_chip_sleep;1911 1912 err = mcp251xfd_register_chip_detect(priv);1913 if (err)1914 goto out_chip_sleep;1915 1916 err = mcp251xfd_register_check_rx_int(priv);1917 if (err)1918 goto out_chip_sleep;1919 1920 mcp251xfd_ethtool_init(priv);1921 1922 err = register_candev(ndev);1923 if (err)1924 goto out_chip_sleep;1925 1926 err = mcp251xfd_register_done(priv);1927 if (err)1928 goto out_unregister_candev;1929 1930 /* Put controller into sleep mode and let pm_runtime_put()1931 * disable the clocks and vdd. If CONFIG_PM is not enabled,1932 * the clocks and vdd will stay powered.1933 */1934 err = mcp251xfd_chip_sleep(priv);1935 if (err)1936 goto out_unregister_candev;1937 1938 pm_runtime_put(ndev->dev.parent);1939 1940 return 0;1941 1942out_unregister_candev:1943 unregister_candev(ndev);1944out_chip_sleep:1945 mcp251xfd_chip_sleep(priv);1946out_runtime_disable:1947 pm_runtime_disable(ndev->dev.parent);1948out_runtime_put_noidle:1949 pm_runtime_put_noidle(ndev->dev.parent);1950 mcp251xfd_clks_and_vdd_disable(priv);1951 1952 return err;1953}1954 1955static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv)1956{1957 struct net_device *ndev = priv->ndev;1958 1959 unregister_candev(ndev);1960 1961 if (pm_runtime_enabled(ndev->dev.parent))1962 pm_runtime_disable(ndev->dev.parent);1963 else1964 mcp251xfd_clks_and_vdd_disable(priv);1965}1966 1967static const struct of_device_id mcp251xfd_of_match[] = {1968 {1969 .compatible = "microchip,mcp2517fd",1970 .data = &mcp251xfd_devtype_data_mcp2517fd,1971 }, {1972 .compatible = "microchip,mcp2518fd",1973 .data = &mcp251xfd_devtype_data_mcp2518fd,1974 }, {1975 .compatible = "microchip,mcp251863",1976 .data = &mcp251xfd_devtype_data_mcp251863,1977 }, {1978 .compatible = "microchip,mcp251xfd",1979 .data = &mcp251xfd_devtype_data_mcp251xfd,1980 }, {1981 /* sentinel */1982 },1983};1984MODULE_DEVICE_TABLE(of, mcp251xfd_of_match);1985 1986static const struct spi_device_id mcp251xfd_id_table[] = {1987 {1988 .name = "mcp2517fd",1989 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd,1990 }, {1991 .name = "mcp2518fd",1992 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd,1993 }, {1994 .name = "mcp251863",1995 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251863,1996 }, {1997 .name = "mcp251xfd",1998 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd,1999 }, {2000 /* sentinel */2001 },2002};2003MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table);2004 2005static int mcp251xfd_probe(struct spi_device *spi)2006{2007 struct net_device *ndev;2008 struct mcp251xfd_priv *priv;2009 struct gpio_desc *rx_int;2010 struct regulator *reg_vdd, *reg_xceiver;2011 struct clk *clk;2012 bool pll_enable = false;2013 u32 freq = 0;2014 int err;2015 2016 if (!spi->irq)2017 return dev_err_probe(&spi->dev, -ENXIO,2018 "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n");2019 2020 rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int",2021 GPIOD_IN);2022 if (IS_ERR(rx_int))2023 return dev_err_probe(&spi->dev, PTR_ERR(rx_int),2024 "Failed to get RX-INT!\n");2025 2026 reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd");2027 if (PTR_ERR(reg_vdd) == -ENODEV)2028 reg_vdd = NULL;2029 else if (IS_ERR(reg_vdd))2030 return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd),2031 "Failed to get VDD regulator!\n");2032 2033 reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver");2034 if (PTR_ERR(reg_xceiver) == -ENODEV)2035 reg_xceiver = NULL;2036 else if (IS_ERR(reg_xceiver))2037 return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver),2038 "Failed to get Transceiver regulator!\n");2039 2040 clk = devm_clk_get_optional(&spi->dev, NULL);2041 if (IS_ERR(clk))2042 return dev_err_probe(&spi->dev, PTR_ERR(clk),2043 "Failed to get Oscillator (clock)!\n");2044 if (clk) {2045 freq = clk_get_rate(clk);2046 } else {2047 err = device_property_read_u32(&spi->dev, "clock-frequency",2048 &freq);2049 if (err)2050 return dev_err_probe(&spi->dev, err,2051 "Failed to get clock-frequency!\n");2052 }2053 2054 /* Sanity check */2055 if (freq < MCP251XFD_SYSCLOCK_HZ_MIN ||2056 freq > MCP251XFD_SYSCLOCK_HZ_MAX) {2057 dev_err(&spi->dev,2058 "Oscillator frequency (%u Hz) is too low or high.\n",2059 freq);2060 return -ERANGE;2061 }2062 2063 if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER)2064 pll_enable = true;2065 2066 ndev = alloc_candev(sizeof(struct mcp251xfd_priv),2067 MCP251XFD_TX_OBJ_NUM_MAX);2068 if (!ndev)2069 return -ENOMEM;2070 2071 SET_NETDEV_DEV(ndev, &spi->dev);2072 2073 ndev->netdev_ops = &mcp251xfd_netdev_ops;2074 ndev->irq = spi->irq;2075 ndev->flags |= IFF_ECHO;2076 2077 priv = netdev_priv(ndev);2078 spi_set_drvdata(spi, priv);2079 priv->can.clock.freq = freq;2080 if (pll_enable)2081 priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER;2082 priv->can.do_set_mode = mcp251xfd_set_mode;2083 priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter;2084 priv->can.bittiming_const = &mcp251xfd_bittiming_const;2085 priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const;2086 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |2087 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING |2088 CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO |2089 CAN_CTRLMODE_CC_LEN8_DLC;2090 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);2091 priv->ndev = ndev;2092 priv->spi = spi;2093 priv->rx_int = rx_int;2094 priv->clk = clk;2095 priv->pll_enable = pll_enable;2096 priv->reg_vdd = reg_vdd;2097 priv->reg_xceiver = reg_xceiver;2098 priv->devtype_data = *(struct mcp251xfd_devtype_data *)spi_get_device_match_data(spi);2099 2100 /* Errata Reference:2101 * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789E 4.,2102 * mcp251863: DS80000984A 4.2103 *2104 * The SPI can write corrupted data to the RAM at fast SPI2105 * speeds:2106 *2107 * Simultaneous activity on the CAN bus while writing data to2108 * RAM via the SPI interface, with high SCK frequency, can2109 * lead to corrupted data being written to RAM.2110 *2111 * Fix/Work Around:2112 * Ensure that FSCK is less than or equal to 0.85 *2113 * (FSYSCLK/2).2114 *2115 * Known good combinations are:2116 *2117 * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk config2118 *2119 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>2120 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>2121 * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default2122 * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default2123 * 2518 40 MHz fsl,imx6dl fsl,imx51-ecspi 15000000 Hz 75.00% 30000000 Hz default2124 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>2125 *2126 */2127 priv->spi_max_speed_hz_orig = spi->max_speed_hz;2128 priv->spi_max_speed_hz_slow = min(spi->max_speed_hz,2129 freq / 2 / 1000 * 850);2130 if (priv->pll_enable)2131 priv->spi_max_speed_hz_fast = min(spi->max_speed_hz,2132 freq *2133 MCP251XFD_OSC_PLL_MULTIPLIER /2134 2 / 1000 * 850);2135 else2136 priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow;2137 spi->max_speed_hz = priv->spi_max_speed_hz_slow;2138 spi->bits_per_word = 8;2139 spi->rt = true;2140 err = spi_setup(spi);2141 if (err)2142 goto out_free_candev;2143 2144 err = mcp251xfd_regmap_init(priv);2145 if (err)2146 goto out_free_candev;2147 2148 err = can_rx_offload_add_manual(ndev, &priv->offload,2149 MCP251XFD_NAPI_WEIGHT);2150 if (err)2151 goto out_free_candev;2152 2153 err = mcp251xfd_register(priv);2154 if (err) {2155 dev_err_probe(&spi->dev, err, "Failed to detect %s.\n",2156 mcp251xfd_get_model_str(priv));2157 goto out_can_rx_offload_del;2158 }2159 2160 return 0;2161 2162out_can_rx_offload_del:2163 can_rx_offload_del(&priv->offload);2164out_free_candev:2165 spi->max_speed_hz = priv->spi_max_speed_hz_orig;2166 2167 free_candev(ndev);2168 2169 return err;2170}2171 2172static void mcp251xfd_remove(struct spi_device *spi)2173{2174 struct mcp251xfd_priv *priv = spi_get_drvdata(spi);2175 struct net_device *ndev = priv->ndev;2176 2177 can_rx_offload_del(&priv->offload);2178 mcp251xfd_unregister(priv);2179 spi->max_speed_hz = priv->spi_max_speed_hz_orig;2180 free_candev(ndev);2181}2182 2183static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device)2184{2185 const struct mcp251xfd_priv *priv = dev_get_drvdata(device);2186 2187 return mcp251xfd_clks_and_vdd_disable(priv);2188}2189 2190static int __maybe_unused mcp251xfd_runtime_resume(struct device *device)2191{2192 const struct mcp251xfd_priv *priv = dev_get_drvdata(device);2193 2194 return mcp251xfd_clks_and_vdd_enable(priv);2195}2196 2197static const struct dev_pm_ops mcp251xfd_pm_ops = {2198 SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend,2199 mcp251xfd_runtime_resume, NULL)2200};2201 2202static struct spi_driver mcp251xfd_driver = {2203 .driver = {2204 .name = DEVICE_NAME,2205 .pm = &mcp251xfd_pm_ops,2206 .of_match_table = mcp251xfd_of_match,2207 },2208 .probe = mcp251xfd_probe,2209 .remove = mcp251xfd_remove,2210 .id_table = mcp251xfd_id_table,2211};2212module_spi_driver(mcp251xfd_driver);2213 2214MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");2215MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver");2216MODULE_LICENSE("GPL v2");2217