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1/*2 * B53 register definitions3 *4 * Copyright (C) 2004 Broadcom Corporation5 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>6 *7 * Permission to use, copy, modify, and/or distribute this software for any8 * purpose with or without fee is hereby granted, provided that the above9 * copyright notice and this permission notice appear in all copies.10 *11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.18 */19 20#ifndef __B53_REGS_H21#define __B53_REGS_H22 23/* Management Port (SMP) Page offsets */24#define B53_CTRL_PAGE 0x00 /* Control */25#define B53_STAT_PAGE 0x01 /* Status */26#define B53_MGMT_PAGE 0x02 /* Management Mode */27#define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */28#define B53_ARLCTRL_PAGE 0x04 /* ARL Control */29#define B53_ARLIO_PAGE 0x05 /* ARL Access */30#define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */31#define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */32 33/* PHY Registers */34#define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */35#define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */36#define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */37 38/* MIB registers */39#define B53_MIB_PAGE(i) (0x20 + (i))40 41/* Quality of Service (QoS) Registers */42#define B53_QOS_PAGE 0x3043 44/* Port VLAN Page */45#define B53_PVLAN_PAGE 0x3146 47/* VLAN Registers */48#define B53_VLAN_PAGE 0x3449 50/* Jumbo Frame Registers */51#define B53_JUMBO_PAGE 0x4052 53/* EEE Control Registers Page */54#define B53_EEE_PAGE 0x9255 56/* CFP Configuration Registers Page */57#define B53_CFP_PAGE 0xa158 59/*************************************************************************60 * Control Page registers61 *************************************************************************/62 63/* Port Control Register (8 bit) */64#define B53_PORT_CTRL(i) (0x00 + (i))65#define PORT_CTRL_RX_DISABLE BIT(0)66#define PORT_CTRL_TX_DISABLE BIT(1)67#define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */68#define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */69#define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */70#define PORT_CTRL_STP_STATE_S 571#define PORT_CTRL_NO_STP (0 << PORT_CTRL_STP_STATE_S)72#define PORT_CTRL_DIS_STATE (1 << PORT_CTRL_STP_STATE_S)73#define PORT_CTRL_BLOCK_STATE (2 << PORT_CTRL_STP_STATE_S)74#define PORT_CTRL_LISTEN_STATE (3 << PORT_CTRL_STP_STATE_S)75#define PORT_CTRL_LEARN_STATE (4 << PORT_CTRL_STP_STATE_S)76#define PORT_CTRL_FWD_STATE (5 << PORT_CTRL_STP_STATE_S)77#define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S)78 79/* SMP Control Register (8 bit) */80#define B53_SMP_CTRL 0x0a81 82/* Switch Mode Control Register (8 bit) */83#define B53_SWITCH_MODE 0x0b84#define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */85#define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */86 87/* IMP Port state override register (8 bit) */88#define B53_PORT_OVERRIDE_CTRL 0x0e89#define PORT_OVERRIDE_LINK BIT(0)90#define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */91#define PORT_OVERRIDE_SPEED_S 292#define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S)93#define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S)94#define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S)95#define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */96#define PORT_OVERRIDE_RX_FLOW BIT(4)97#define PORT_OVERRIDE_TX_FLOW BIT(5)98#define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */99#define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */100 101/* Power-down mode control */102#define B53_PD_MODE_CTRL_25 0x0f103 104/* IP Multicast control (8 bit) */105#define B53_IP_MULTICAST_CTRL 0x21106#define B53_IPMC_FWD_EN BIT(1)107#define B53_UC_FWD_EN BIT(6)108#define B53_MC_FWD_EN BIT(7)109 110/* Switch control (8 bit) */111#define B53_SWITCH_CTRL 0x22112#define B53_MII_DUMB_FWDG_EN BIT(6)113 114/* (16 bit) */115#define B53_UC_FLOOD_MASK 0x32116#define B53_MC_FLOOD_MASK 0x34117#define B53_IPMC_FLOOD_MASK 0x36118#define B53_DIS_LEARNING 0x3c119 120/*121 * Override Ports 0-7 State on devices with xMII interfaces (8 bit)122 *123 * For port 8 still use B53_PORT_OVERRIDE_CTRL124 * Please note that not all ports are available on every hardware, e.g. BCM5301X125 * don't include overriding port 6, BCM63xx also have some limitations.126 */127#define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i))128#define GMII_PO_LINK BIT(0)129#define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */130#define GMII_PO_SPEED_S 2131#define GMII_PO_SPEED_10M (0 << GMII_PO_SPEED_S)132#define GMII_PO_SPEED_100M (1 << GMII_PO_SPEED_S)133#define GMII_PO_SPEED_1000M (2 << GMII_PO_SPEED_S)134#define GMII_PO_RX_FLOW BIT(4)135#define GMII_PO_TX_FLOW BIT(5)136#define GMII_PO_EN BIT(6) /* Use the register contents */137#define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */138 139#define B53_RGMII_CTRL_IMP 0x60140#define RGMII_CTRL_ENABLE_GMII BIT(7)141#define RGMII_CTRL_MII_OVERRIDE BIT(6)142#define RGMII_CTRL_TIMING_SEL BIT(2)143#define RGMII_CTRL_DLL_RXC BIT(1)144#define RGMII_CTRL_DLL_TXC BIT(0)145 146#define B53_RGMII_CTRL_P(i) (B53_RGMII_CTRL_IMP + (i))147 148/* Software reset register (8 bit) */149#define B53_SOFTRESET 0x79150#define SW_RST BIT(7)151#define EN_CH_RST BIT(6)152#define EN_SW_RST BIT(4)153 154/* Fast Aging Control register (8 bit) */155#define B53_FAST_AGE_CTRL 0x88156#define FAST_AGE_STATIC BIT(0)157#define FAST_AGE_DYNAMIC BIT(1)158#define FAST_AGE_PORT BIT(2)159#define FAST_AGE_VLAN BIT(3)160#define FAST_AGE_STP BIT(4)161#define FAST_AGE_MC BIT(5)162#define FAST_AGE_DONE BIT(7)163 164/* Fast Aging Port Control register (8 bit) */165#define B53_FAST_AGE_PORT_CTRL 0x89166 167/* Fast Aging VID Control register (16 bit) */168#define B53_FAST_AGE_VID_CTRL 0x8a169 170/*************************************************************************171 * Status Page registers172 *************************************************************************/173 174/* Link Status Summary Register (16bit) */175#define B53_LINK_STAT 0x00176 177/* Link Status Change Register (16 bit) */178#define B53_LINK_STAT_CHANGE 0x02179 180/* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */181#define B53_SPEED_STAT 0x04182#define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1)183#define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3)184#define SPEED_STAT_10M 0185#define SPEED_STAT_100M 1186#define SPEED_STAT_1000M 2187 188/* Duplex Status Summary (16 bit) */189#define B53_DUPLEX_STAT_FE 0x06190#define B53_DUPLEX_STAT_GE 0x08191#define B53_DUPLEX_STAT_63XX 0x0c192 193/* Revision ID register for BCM5325 */194#define B53_REV_ID_25 0x50195 196/* Strap Value (48 bit) */197#define B53_STRAP_VALUE 0x70198#define SV_GMII_CTRL_115 BIT(27)199 200/*************************************************************************201 * Management Mode Page Registers202 *************************************************************************/203 204/* Global Management Config Register (8 bit) */205#define B53_GLOBAL_CONFIG 0x00206#define GC_RESET_MIB 0x01207#define GC_RX_BPDU_EN 0x02208#define GC_MIB_AC_HDR_EN 0x10209#define GC_MIB_AC_EN 0x20210#define GC_FRM_MGMT_PORT_M 0xC0211#define GC_FRM_MGMT_PORT_04 0x00212#define GC_FRM_MGMT_PORT_MII 0x80213 214/* Broadcom Header control register (8 bit) */215#define B53_BRCM_HDR 0x03216#define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */217#define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */218#define BRCM_HDR_P7_EN BIT(2) /* Enable tagging on port 7 */219 220/* Mirror capture control register (16 bit) */221#define B53_MIR_CAP_CTL 0x10222#define CAP_PORT_MASK 0xf223#define BLK_NOT_MIR BIT(14)224#define MIRROR_EN BIT(15)225 226/* Ingress mirror control register (16 bit) */227#define B53_IG_MIR_CTL 0x12228#define MIRROR_MASK 0x1ff229#define DIV_EN BIT(13)230#define MIRROR_FILTER_MASK 0x3231#define MIRROR_FILTER_SHIFT 14232#define MIRROR_ALL 0233#define MIRROR_DA 1234#define MIRROR_SA 2235 236/* Ingress mirror divider register (16 bit) */237#define B53_IG_MIR_DIV 0x14238#define IN_MIRROR_DIV_MASK 0x3ff239 240/* Ingress mirror MAC address register (48 bit) */241#define B53_IG_MIR_MAC 0x16242 243/* Egress mirror control register (16 bit) */244#define B53_EG_MIR_CTL 0x1C245 246/* Egress mirror divider register (16 bit) */247#define B53_EG_MIR_DIV 0x1E248 249/* Egress mirror MAC address register (48 bit) */250#define B53_EG_MIR_MAC 0x20251 252/* Device ID register (8 or 32 bit) */253#define B53_DEVICE_ID 0x30254 255/* Revision ID register (8 bit) */256#define B53_REV_ID 0x40257 258/* Broadcom header RX control (16 bit) */259#define B53_BRCM_HDR_RX_DIS 0x60260 261/* Broadcom header TX control (16 bit) */262#define B53_BRCM_HDR_TX_DIS 0x62263 264/*************************************************************************265 * ARL Access Page Registers266 *************************************************************************/267 268/* VLAN Table Access Register (8 bit) */269#define B53_VT_ACCESS 0x80270#define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */271#define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */272#define VTA_CMD_WRITE 0273#define VTA_CMD_READ 1274#define VTA_CMD_CLEAR 2275#define VTA_START_CMD BIT(7)276 277/* VLAN Table Index Register (16 bit) */278#define B53_VT_INDEX 0x81279#define B53_VT_INDEX_9798 0x61280#define B53_VT_INDEX_63XX 0x62281 282/* VLAN Table Entry Register (32 bit) */283#define B53_VT_ENTRY 0x83284#define B53_VT_ENTRY_9798 0x63285#define B53_VT_ENTRY_63XX 0x64286#define VTE_MEMBERS 0x1ff287#define VTE_UNTAG_S 9288#define VTE_UNTAG (0x1ff << 9)289 290/*************************************************************************291 * ARL I/O Registers292 *************************************************************************/293 294/* ARL Table Read/Write Register (8 bit) */295#define B53_ARLTBL_RW_CTRL 0x00296#define ARLTBL_RW BIT(0)297#define ARLTBL_IVL_SVL_SELECT BIT(6)298#define ARLTBL_START_DONE BIT(7)299 300/* MAC Address Index Register (48 bit) */301#define B53_MAC_ADDR_IDX 0x02302 303/* VLAN ID Index Register (16 bit) */304#define B53_VLAN_ID_IDX 0x08305 306/* ARL Table MAC/VID Entry N Registers (64 bit)307 *308 * BCM5325 and BCM5365 share most definitions below309 */310#define B53_ARLTBL_MAC_VID_ENTRY(n) ((0x10 * (n)) + 0x10)311#define ARLTBL_MAC_MASK 0xffffffffffffULL312#define ARLTBL_VID_S 48313#define ARLTBL_VID_MASK_25 0xff314#define ARLTBL_VID_MASK 0xfff315#define ARLTBL_DATA_PORT_ID_S_25 48316#define ARLTBL_DATA_PORT_ID_MASK_25 0xf317#define ARLTBL_AGE_25 BIT(61)318#define ARLTBL_STATIC_25 BIT(62)319#define ARLTBL_VALID_25 BIT(63)320 321/* ARL Table Data Entry N Registers (32 bit) */322#define B53_ARLTBL_DATA_ENTRY(n) ((0x10 * (n)) + 0x18)323#define ARLTBL_DATA_PORT_ID_MASK 0x1ff324#define ARLTBL_TC(tc) ((3 & tc) << 11)325#define ARLTBL_AGE BIT(14)326#define ARLTBL_STATIC BIT(15)327#define ARLTBL_VALID BIT(16)328 329/* Maximum number of bin entries in the ARL for all switches */330#define B53_ARLTBL_MAX_BIN_ENTRIES 4331 332/* ARL Search Control Register (8 bit) */333#define B53_ARL_SRCH_CTL 0x50334#define B53_ARL_SRCH_CTL_25 0x20335#define ARL_SRCH_VLID BIT(0)336#define ARL_SRCH_STDN BIT(7)337 338/* ARL Search Address Register (16 bit) */339#define B53_ARL_SRCH_ADDR 0x51340#define B53_ARL_SRCH_ADDR_25 0x22341#define B53_ARL_SRCH_ADDR_65 0x24342#define ARL_ADDR_MASK GENMASK(14, 0)343 344/* ARL Search MAC/VID Result (64 bit) */345#define B53_ARL_SRCH_RSTL_0_MACVID 0x60346 347/* Single register search result on 5325 */348#define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24349/* Single register search result on 5365 */350#define B53_ARL_SRCH_RSTL_0_MACVID_65 0x30351 352/* ARL Search Data Result (32 bit) */353#define B53_ARL_SRCH_RSTL_0 0x68354 355#define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10))356#define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10))357 358/*************************************************************************359 * Port VLAN Registers360 *************************************************************************/361 362/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */363#define B53_PVLAN_PORT_MASK(i) ((i) * 2)364 365/* Join all VLANs register (16 bit) */366#define B53_JOIN_ALL_VLAN_EN 0x50367 368/*************************************************************************369 * 802.1Q Page Registers370 *************************************************************************/371 372/* Global QoS Control (8 bit) */373#define B53_QOS_GLOBAL_CTL 0x00374 375/* Enable 802.1Q for individual Ports (16 bit) */376#define B53_802_1P_EN 0x04377 378/*************************************************************************379 * VLAN Page Registers380 *************************************************************************/381 382/* VLAN Control 0 (8 bit) */383#define B53_VLAN_CTRL0 0x00384#define VC0_8021PF_CTRL_MASK 0x3385#define VC0_8021PF_CTRL_NONE 0x0386#define VC0_8021PF_CTRL_CHANGE_PRI 0x1387#define VC0_8021PF_CTRL_CHANGE_VID 0x2388#define VC0_8021PF_CTRL_CHANGE_BOTH 0x3389#define VC0_8021QF_CTRL_MASK 0xc390#define VC0_8021QF_CTRL_CHANGE_PRI 0x1391#define VC0_8021QF_CTRL_CHANGE_VID 0x2392#define VC0_8021QF_CTRL_CHANGE_BOTH 0x3393#define VC0_RESERVED_1 BIT(1)394#define VC0_DROP_VID_MISS BIT(4)395#define VC0_VID_HASH_VID BIT(5)396#define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */397#define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */398 399/* VLAN Control 1 (8 bit) */400#define B53_VLAN_CTRL1 0x01401#define VC1_RX_MCST_TAG_EN BIT(1)402#define VC1_RX_MCST_FWD_EN BIT(2)403#define VC1_RX_MCST_UNTAG_EN BIT(3)404 405/* VLAN Control 2 (8 bit) */406#define B53_VLAN_CTRL2 0x02407 408/* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */409#define B53_VLAN_CTRL3 0x03410#define B53_VLAN_CTRL3_63XX 0x04411#define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */412#define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */413 414/* VLAN Control 4 (8 bit) */415#define B53_VLAN_CTRL4 0x05416#define B53_VLAN_CTRL4_25 0x04417#define B53_VLAN_CTRL4_63XX 0x06418#define VC4_ING_VID_CHECK_S 6419#define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S)420#define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */421#define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */422#define VC4_NO_ING_VID_CHK 2 /* do not check */423#define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */424 425/* VLAN Control 5 (8 bit) */426#define B53_VLAN_CTRL5 0x06427#define B53_VLAN_CTRL5_25 0x05428#define B53_VLAN_CTRL5_63XX 0x07429#define VC5_VID_FFF_EN BIT(2)430#define VC5_DROP_VTABLE_MISS BIT(3)431 432/* VLAN Control 6 (8 bit) */433#define B53_VLAN_CTRL6 0x07434#define B53_VLAN_CTRL6_63XX 0x08435 436/* VLAN Table Access Register (16 bit) */437#define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */438#define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */439#define VTA_VID_LOW_MASK_25 0xf440#define VTA_VID_LOW_MASK_65 0xff441#define VTA_VID_HIGH_S_25 4442#define VTA_VID_HIGH_S_65 8443#define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E)444#define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65)445#define VTA_RW_STATE BIT(12)446#define VTA_RW_STATE_RD 0447#define VTA_RW_STATE_WR BIT(12)448#define VTA_RW_OP_EN BIT(13)449 450/* VLAN Read/Write Registers for (16/32 bit) */451#define B53_VLAN_WRITE_25 0x08452#define B53_VLAN_WRITE_65 0x0a453#define B53_VLAN_READ 0x0c454#define VA_MEMBER_MASK 0x3f455#define VA_UNTAG_S_25 6456#define VA_UNTAG_MASK_25 0x3f457#define VA_UNTAG_S_65 7458#define VA_UNTAG_MASK_65 0x1f459#define VA_VID_HIGH_S 12460#define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S)461#define VA_VALID_25 BIT(20)462#define VA_VALID_25_R4 BIT(24)463#define VA_VALID_65 BIT(14)464 465/* VLAN Port Default Tag (16 bit) */466#define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i))467 468/*************************************************************************469 * Jumbo Frame Page Registers470 *************************************************************************/471 472/* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */473#define B53_JUMBO_PORT_MASK 0x01474#define B53_JUMBO_PORT_MASK_63XX 0x04475#define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */476 477/* Good Frame Max Size without 802.1Q TAG (16 bit) */478#define B53_JUMBO_MAX_SIZE 0x05479#define B53_JUMBO_MAX_SIZE_63XX 0x08480#define JMS_MIN_SIZE 1518481#define JMS_MAX_SIZE 9724482 483/*************************************************************************484 * EEE Configuration Page Registers485 *************************************************************************/486 487/* EEE Enable control register (16 bit) */488#define B53_EEE_EN_CTRL 0x00489 490/* EEE LPI assert status register (16 bit) */491#define B53_EEE_LPI_ASSERT_STS 0x02492 493/* EEE LPI indicate status register (16 bit) */494#define B53_EEE_LPI_INDICATE 0x4495 496/* EEE Receiving idle symbols status register (16 bit) */497#define B53_EEE_RX_IDLE_SYM_STS 0x6498 499/* EEE Pipeline timer register (32 bit) */500#define B53_EEE_PIP_TIMER 0xC501 502/* EEE Sleep timer Gig register (32 bit) */503#define B53_EEE_SLEEP_TIMER_GIG(i) (0x10 + 4 * (i))504 505/* EEE Sleep timer FE register (32 bit) */506#define B53_EEE_SLEEP_TIMER_FE(i) (0x34 + 4 * (i))507 508/* EEE Minimum LP timer Gig register (32 bit) */509#define B53_EEE_MIN_LP_TIMER_GIG(i) (0x58 + 4 * (i))510 511/* EEE Minimum LP timer FE register (32 bit) */512#define B53_EEE_MIN_LP_TIMER_FE(i) (0x7c + 4 * (i))513 514/* EEE Wake timer Gig register (16 bit) */515#define B53_EEE_WAKE_TIMER_GIG(i) (0xa0 + 2 * (i))516 517/* EEE Wake timer FE register (16 bit) */518#define B53_EEE_WAKE_TIMER_FE(i) (0xb2 + 2 * (i))519 520 521/*************************************************************************522 * CFP Configuration Page Registers523 *************************************************************************/524 525/* CFP Control Register with ports map (8 bit) */526#define B53_CFP_CTRL 0x00527 528#endif /* !__B53_REGS_H */529