800 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Microchip KSZ8XXX series register definitions4 *5 * The base for these definitions is KSZ8795 but unless indicated6 * differently by their prefix, they apply to all KSZ8 series7 * devices. Registers and masks that do change are defined in8 * dedicated structures in ksz_common.c.9 *10 * Copyright (c) 2017 Microchip Technology Inc.11 * Tristram Ha <Tristram.Ha@microchip.com>12 */13 14#ifndef __KSZ8_REG_H15#define __KSZ8_REG_H16 17#define KS_PORT_M 0x1F18 19#define KS_PRIO_M 0x320#define KS_PRIO_S 221 22#define SW_REVISION_M 0x0E23#define SW_REVISION_S 124 25#define KSZ8863_REG_SW_RESET 0x4326 27#define KSZ8863_GLOBAL_SOFTWARE_RESET BIT(4)28#define KSZ8863_PCS_RESET BIT(0)29 30#define KSZ88X3_REG_FVID_AND_HOST_MODE 0xC631#define KSZ88X3_PORT3_RMII_CLK_INTERNAL BIT(3)32 33#define REG_SW_CTRL_0 0x0234 35#define SW_NEW_BACKOFF BIT(7)36#define SW_GLOBAL_RESET BIT(6)37#define SW_FLUSH_DYN_MAC_TABLE BIT(5)38#define SW_FLUSH_STA_MAC_TABLE BIT(4)39#define SW_LINK_AUTO_AGING BIT(0)40 41#define REG_SW_CTRL_1 0x0342 43#define SW_HUGE_PACKET BIT(6)44#define SW_TX_FLOW_CTRL_DISABLE BIT(5)45#define SW_RX_FLOW_CTRL_DISABLE BIT(4)46#define SW_CHECK_LENGTH BIT(3)47#define SW_AGING_ENABLE BIT(2)48#define SW_FAST_AGING BIT(1)49#define SW_AGGR_BACKOFF BIT(0)50 51#define REG_SW_CTRL_2 0x0452 53#define UNICAST_VLAN_BOUNDARY BIT(7)54#define SW_BACK_PRESSURE BIT(5)55#define FAIR_FLOW_CTRL BIT(4)56#define NO_EXC_COLLISION_DROP BIT(3)57#define SW_LEGAL_PACKET_DISABLE BIT(1)58 59#define KSZ8863_HUGE_PACKET_ENABLE BIT(2)60#define KSZ8863_LEGAL_PACKET_ENABLE BIT(1)61 62#define REG_SW_CTRL_3 0x0563 #define WEIGHTED_FAIR_QUEUE_ENABLE BIT(3)64 65#define SW_VLAN_ENABLE BIT(7)66#define SW_IGMP_SNOOP BIT(6)67#define SW_MIRROR_RX_TX BIT(0)68 69#define REG_SW_CTRL_4 0x0670 71#define SW_HALF_DUPLEX_FLOW_CTRL BIT(7)72#define SW_HALF_DUPLEX BIT(6)73#define SW_FLOW_CTRL BIT(5)74#define SW_10_MBIT BIT(4)75#define SW_REPLACE_VID BIT(3)76 77#define REG_SW_CTRL_5 0x0778 79#define REG_SW_CTRL_6 0x0880 81#define SW_MIB_COUNTER_FLUSH BIT(7)82#define SW_MIB_COUNTER_FREEZE BIT(6)83#define SW_MIB_COUNTER_CTRL_ENABLE KS_PORT_M84 85#define REG_SW_CTRL_9 0x0B86 87#define SPI_CLK_125_MHZ 0x8088#define SPI_CLK_62_5_MHZ 0x4089#define SPI_CLK_31_25_MHZ 0x0090 91#define SW_LED_MODE_M 0x392#define SW_LED_MODE_S 493#define SW_LED_LINK_ACT_SPEED 094#define SW_LED_LINK_ACT 195#define SW_LED_LINK_ACT_DUPLEX 296#define SW_LED_LINK_DUPLEX 397 98#define REG_SW_CTRL_10 0x0C99 100#define SW_PASS_PAUSE BIT(0)101 102#define REG_SW_CTRL_11 0x0D103 104#define REG_POWER_MANAGEMENT_1 0x0E105 106#define SW_PLL_POWER_DOWN BIT(5)107#define SW_POWER_MANAGEMENT_MODE_M 0x3108#define SW_POWER_MANAGEMENT_MODE_S 3109#define SW_POWER_NORMAL 0110#define SW_ENERGY_DETECTION 1111#define SW_SOFTWARE_POWER_DOWN 2112 113#define REG_POWER_MANAGEMENT_2 0x0F114 115#define REG_PORT_1_CTRL_0 0x10116#define REG_PORT_2_CTRL_0 0x20117#define REG_PORT_3_CTRL_0 0x30118#define REG_PORT_4_CTRL_0 0x40119#define REG_PORT_5_CTRL_0 0x50120 121#define PORT_BROADCAST_STORM BIT(7)122#define PORT_DIFFSERV_ENABLE BIT(6)123#define PORT_802_1P_ENABLE BIT(5)124#define PORT_BASED_PRIO_S 3125#define PORT_BASED_PRIO_M KS_PRIO_M126#define PORT_BASED_PRIO_0 0127#define PORT_BASED_PRIO_1 1128#define PORT_BASED_PRIO_2 2129#define PORT_BASED_PRIO_3 3130#define PORT_INSERT_TAG BIT(2)131#define PORT_REMOVE_TAG BIT(1)132#define KSZ8795_PORT_2QUEUE_SPLIT_EN BIT(0)133#define KSZ8873_PORT_4QUEUE_SPLIT_EN BIT(0)134 135#define REG_PORT_1_CTRL_1 0x11136#define REG_PORT_2_CTRL_1 0x21137#define REG_PORT_3_CTRL_1 0x31138#define REG_PORT_4_CTRL_1 0x41139#define REG_PORT_5_CTRL_1 0x51140 141#define PORT_MIRROR_SNIFFER BIT(7)142#define PORT_MIRROR_RX BIT(6)143#define PORT_MIRROR_TX BIT(5)144#define PORT_VLAN_MEMBERSHIP KS_PORT_M145 146#define REG_PORT_1_CTRL_2 0x12147#define REG_PORT_2_CTRL_2 0x22148#define REG_PORT_3_CTRL_2 0x32149#define REG_PORT_4_CTRL_2 0x42150#define REG_PORT_5_CTRL_2 0x52151 152#define KSZ8873_PORT_2QUEUE_SPLIT_EN BIT(7)153#define PORT_INGRESS_FILTER BIT(6)154#define PORT_DISCARD_NON_VID BIT(5)155#define PORT_FORCE_FLOW_CTRL BIT(4)156#define PORT_BACK_PRESSURE BIT(3)157 158#define REG_PORT_1_CTRL_3 0x13159#define REG_PORT_2_CTRL_3 0x23160#define REG_PORT_3_CTRL_3 0x33161#define REG_PORT_4_CTRL_3 0x43162#define REG_PORT_5_CTRL_3 0x53163#define REG_PORT_1_CTRL_4 0x14164#define REG_PORT_2_CTRL_4 0x24165#define REG_PORT_3_CTRL_4 0x34166#define REG_PORT_4_CTRL_4 0x44167#define REG_PORT_5_CTRL_4 0x54168 169#define PORT_DEFAULT_VID 0x0001170 171#define REG_PORT_1_CTRL_5 0x15172#define REG_PORT_2_CTRL_5 0x25173#define REG_PORT_3_CTRL_5 0x35174#define REG_PORT_4_CTRL_5 0x45175#define REG_PORT_5_CTRL_5 0x55176 177#define PORT_ACL_ENABLE BIT(2)178#define PORT_AUTHEN_MODE 0x3179#define PORT_AUTHEN_PASS 0180#define PORT_AUTHEN_BLOCK 1181#define PORT_AUTHEN_TRAP 2182 183#define REG_PORT_5_CTRL_6 0x56184 185#define PORT_MII_INTERNAL_CLOCK BIT(7)186#define PORT_GMII_MAC_MODE BIT(2)187 188#define REG_PORT_1_CTRL_7 0x17189#define REG_PORT_2_CTRL_7 0x27190#define REG_PORT_3_CTRL_7 0x37191#define REG_PORT_4_CTRL_7 0x47192 193#define PORT_AUTO_NEG_ASYM_PAUSE BIT(5)194#define PORT_AUTO_NEG_SYM_PAUSE BIT(4)195#define PORT_AUTO_NEG_100BTX_FD BIT(3)196#define PORT_AUTO_NEG_100BTX BIT(2)197#define PORT_AUTO_NEG_10BT_FD BIT(1)198#define PORT_AUTO_NEG_10BT BIT(0)199 200#define REG_PORT_1_STATUS_0 0x18201#define REG_PORT_2_STATUS_0 0x28202#define REG_PORT_3_STATUS_0 0x38203#define REG_PORT_4_STATUS_0 0x48204 205/* For KSZ8765. */206#define PORT_REMOTE_ASYM_PAUSE BIT(5)207#define PORT_REMOTE_SYM_PAUSE BIT(4)208#define PORT_REMOTE_100BTX_FD BIT(3)209#define PORT_REMOTE_100BTX BIT(2)210#define PORT_REMOTE_10BT_FD BIT(1)211#define PORT_REMOTE_10BT BIT(0)212 213#define REG_PORT_1_STATUS_1 0x19214#define REG_PORT_2_STATUS_1 0x29215#define REG_PORT_3_STATUS_1 0x39216#define REG_PORT_4_STATUS_1 0x49217 218#define PORT_HP_MDIX BIT(7)219#define PORT_REVERSED_POLARITY BIT(5)220#define PORT_TX_FLOW_CTRL BIT(4)221#define PORT_RX_FLOW_CTRL BIT(3)222#define PORT_STAT_SPEED_100MBIT BIT(2)223#define PORT_STAT_FULL_DUPLEX BIT(1)224 225#define PORT_REMOTE_FAULT BIT(0)226 227#define REG_PORT_1_LINK_MD_CTRL 0x1A228#define REG_PORT_2_LINK_MD_CTRL 0x2A229#define REG_PORT_3_LINK_MD_CTRL 0x3A230#define REG_PORT_4_LINK_MD_CTRL 0x4A231 232#define PORT_CABLE_10M_SHORT BIT(7)233#define PORT_CABLE_DIAG_RESULT_M GENMASK(6, 5)234#define PORT_CABLE_DIAG_RESULT_S 5235#define PORT_CABLE_STAT_NORMAL 0236#define PORT_CABLE_STAT_OPEN 1237#define PORT_CABLE_STAT_SHORT 2238#define PORT_CABLE_STAT_FAILED 3239#define PORT_START_CABLE_DIAG BIT(4)240#define PORT_FORCE_LINK BIT(3)241#define PORT_POWER_SAVING BIT(2)242#define PORT_PHY_REMOTE_LOOPBACK BIT(1)243#define PORT_CABLE_FAULT_COUNTER_H 0x01244 245#define REG_PORT_1_LINK_MD_RESULT 0x1B246#define REG_PORT_2_LINK_MD_RESULT 0x2B247#define REG_PORT_3_LINK_MD_RESULT 0x3B248#define REG_PORT_4_LINK_MD_RESULT 0x4B249 250#define PORT_CABLE_FAULT_COUNTER_L 0xFF251#define PORT_CABLE_FAULT_COUNTER 0x1FF252 253#define REG_PORT_1_CTRL_9 0x1C254#define REG_PORT_2_CTRL_9 0x2C255#define REG_PORT_3_CTRL_9 0x3C256#define REG_PORT_4_CTRL_9 0x4C257 258#define PORT_AUTO_NEG_ENABLE BIT(7)259#define PORT_AUTO_NEG_DISABLE BIT(7)260#define PORT_FORCE_100_MBIT BIT(6)261#define PORT_FORCE_FULL_DUPLEX BIT(5)262 263#define REG_PORT_1_CTRL_10 0x1D264#define REG_PORT_2_CTRL_10 0x2D265#define REG_PORT_3_CTRL_10 0x3D266#define REG_PORT_4_CTRL_10 0x4D267 268#define PORT_LED_OFF BIT(7)269#define PORT_TX_DISABLE BIT(6)270#define PORT_AUTO_NEG_RESTART BIT(5)271#define PORT_POWER_DOWN BIT(3)272#define PORT_AUTO_MDIX_DISABLE BIT(2)273#define PORT_FORCE_MDIX BIT(1)274#define PORT_MAC_LOOPBACK BIT(0)275#define KSZ8873_PORT_PHY_LOOPBACK BIT(0)276 277#define REG_PORT_1_STATUS_2 0x1E278#define REG_PORT_2_STATUS_2 0x2E279#define REG_PORT_3_STATUS_2 0x3E280#define REG_PORT_4_STATUS_2 0x4E281 282#define PORT_MDIX_STATUS BIT(7)283#define PORT_AUTO_NEG_COMPLETE BIT(6)284#define PORT_STAT_LINK_GOOD BIT(5)285 286#define REG_PORT_1_STATUS_3 0x1F287#define REG_PORT_2_STATUS_3 0x2F288#define REG_PORT_3_STATUS_3 0x3F289#define REG_PORT_4_STATUS_3 0x4F290 291#define PORT_PHY_LOOPBACK BIT(7)292#define PORT_PHY_ISOLATE BIT(5)293#define PORT_PHY_SOFT_RESET BIT(4)294#define PORT_PHY_FORCE_LINK BIT(3)295#define PORT_PHY_MODE_M 0x7296#define PHY_MODE_IN_AUTO_NEG 1297#define PHY_MODE_10BT_HALF 2298#define PHY_MODE_100BT_HALF 3299#define PHY_MODE_10BT_FULL 5300#define PHY_MODE_100BT_FULL 6301#define PHY_MODE_ISOLDATE 7302 303#define REG_PORT_CTRL_0 0x00304#define REG_PORT_CTRL_1 0x01305#define REG_PORT_CTRL_2 0x02306#define REG_PORT_CTRL_VID 0x03307 308#define REG_PORT_CTRL_5 0x05309 310#define REG_PORT_STATUS_1 0x09311#define REG_PORT_LINK_MD_CTRL 0x0A312#define REG_PORT_LINK_MD_RESULT 0x0B313#define REG_PORT_CTRL_9 0x0C314#define REG_PORT_CTRL_10 0x0D315#define REG_PORT_STATUS_3 0x0F316 317#define REG_PORT_CTRL_12 0xA0318#define REG_PORT_CTRL_13 0xA1319#define REG_PORT_RATE_CTRL_3 0xA2320#define REG_PORT_RATE_CTRL_2 0xA3321#define REG_PORT_RATE_CTRL_1 0xA4322#define REG_PORT_RATE_CTRL_0 0xA5323#define REG_PORT_RATE_LIMIT 0xA6324#define REG_PORT_IN_RATE_0 0xA7325#define REG_PORT_IN_RATE_1 0xA8326#define REG_PORT_IN_RATE_2 0xA9327#define REG_PORT_IN_RATE_3 0xAA328#define REG_PORT_OUT_RATE_0 0xAB329#define REG_PORT_OUT_RATE_1 0xAC330#define REG_PORT_OUT_RATE_2 0xAD331#define REG_PORT_OUT_RATE_3 0xAE332 333#define PORT_CTRL_ADDR(port, addr) \334 ((addr) + REG_PORT_1_CTRL_0 + (port) * \335 (REG_PORT_2_CTRL_0 - REG_PORT_1_CTRL_0))336 337#define TABLE_EXT_SELECT_S 5338#define TABLE_EEE_V 1339#define TABLE_ACL_V 2340#define TABLE_PME_V 4341#define TABLE_LINK_MD_V 5342#define TABLE_EEE (TABLE_EEE_V << TABLE_EXT_SELECT_S)343#define TABLE_ACL (TABLE_ACL_V << TABLE_EXT_SELECT_S)344#define TABLE_PME (TABLE_PME_V << TABLE_EXT_SELECT_S)345#define TABLE_LINK_MD (TABLE_LINK_MD << TABLE_EXT_SELECT_S)346#define TABLE_READ BIT(4)347#define TABLE_SELECT_S 2348#define TABLE_STATIC_MAC_V 0349#define TABLE_VLAN_V 1350#define TABLE_DYNAMIC_MAC_V 2351#define TABLE_MIB_V 3352#define TABLE_STATIC_MAC (TABLE_STATIC_MAC_V << TABLE_SELECT_S)353#define TABLE_VLAN (TABLE_VLAN_V << TABLE_SELECT_S)354#define TABLE_DYNAMIC_MAC (TABLE_DYNAMIC_MAC_V << TABLE_SELECT_S)355#define TABLE_MIB (TABLE_MIB_V << TABLE_SELECT_S)356 357#define REG_IND_CTRL_1 0x6F358 359#define TABLE_ENTRY_MASK 0x03FF360#define TABLE_EXT_ENTRY_MASK 0x0FFF361 362#define REG_IND_DATA_5 0x73363#define REG_IND_DATA_2 0x76364#define REG_IND_DATA_1 0x77365#define REG_IND_DATA_0 0x78366 367#define REG_INT_STATUS 0x7C368#define REG_INT_ENABLE 0x7D369 370#define INT_PME BIT(4)371 372#define REG_ACL_INT_STATUS 0x7E373#define REG_ACL_INT_ENABLE 0x7F374 375#define INT_PORT_5 BIT(4)376#define INT_PORT_4 BIT(3)377#define INT_PORT_3 BIT(2)378#define INT_PORT_2 BIT(1)379#define INT_PORT_1 BIT(0)380 381#define INT_PORT_ALL \382 (INT_PORT_5 | INT_PORT_4 | INT_PORT_3 | INT_PORT_2 | INT_PORT_1)383 384#define REG_SW_CTRL_12 0x80385#define REG_SW_CTRL_13 0x81386 387#define SWITCH_802_1P_MASK 3388#define SWITCH_802_1P_BASE 3389#define SWITCH_802_1P_SHIFT 2390 391#define SW_802_1P_MAP_M KS_PRIO_M392#define SW_802_1P_MAP_S KS_PRIO_S393 394#define REG_SWITCH_CTRL_14 0x82395 396#define SW_PRIO_MAPPING_M KS_PRIO_M397#define SW_PRIO_MAPPING_S 6398#define SW_PRIO_MAP_3_HI 0399#define SW_PRIO_MAP_2_HI 2400#define SW_PRIO_MAP_0_LO 3401 402#define REG_SW_CTRL_15 0x83403#define REG_SW_CTRL_16 0x84404#define REG_SW_CTRL_17 0x85405#define REG_SW_CTRL_18 0x86406 407#define SW_SELF_ADDR_FILTER_ENABLE BIT(6)408 409#define REG_SW_UNK_UCAST_CTRL 0x83410#define REG_SW_UNK_MCAST_CTRL 0x84411#define REG_SW_UNK_VID_CTRL 0x85412#define REG_SW_UNK_IP_MCAST_CTRL 0x86413 414#define SW_UNK_FWD_ENABLE BIT(5)415#define SW_UNK_FWD_MAP KS_PORT_M416 417#define REG_SW_CTRL_19 0x87418 419#define SW_IN_RATE_LIMIT_PERIOD_M 0x3420#define SW_IN_RATE_LIMIT_PERIOD_S 4421#define SW_IN_RATE_LIMIT_16_MS 0422#define SW_IN_RATE_LIMIT_64_MS 1423#define SW_IN_RATE_LIMIT_256_MS 2424#define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)425#define SW_INS_TAG_ENABLE BIT(2)426 427#define REG_TOS_PRIO_CTRL_0 0x90428#define REG_TOS_PRIO_CTRL_1 0x91429#define REG_TOS_PRIO_CTRL_2 0x92430#define REG_TOS_PRIO_CTRL_3 0x93431#define REG_TOS_PRIO_CTRL_4 0x94432#define REG_TOS_PRIO_CTRL_5 0x95433#define REG_TOS_PRIO_CTRL_6 0x96434#define REG_TOS_PRIO_CTRL_7 0x97435#define REG_TOS_PRIO_CTRL_8 0x98436#define REG_TOS_PRIO_CTRL_9 0x99437#define REG_TOS_PRIO_CTRL_10 0x9A438#define REG_TOS_PRIO_CTRL_11 0x9B439#define REG_TOS_PRIO_CTRL_12 0x9C440#define REG_TOS_PRIO_CTRL_13 0x9D441#define REG_TOS_PRIO_CTRL_14 0x9E442#define REG_TOS_PRIO_CTRL_15 0x9F443 444#define TOS_PRIO_M KS_PRIO_M445#define TOS_PRIO_S KS_PRIO_S446 447#define REG_SW_CTRL_21 0xA4448 449#define SW_IPV6_MLD_OPTION BIT(3)450#define SW_IPV6_MLD_SNOOP BIT(2)451 452#define REG_PORT_1_CTRL_12 0xB0453#define REG_PORT_2_CTRL_12 0xC0454#define REG_PORT_3_CTRL_12 0xD0455#define REG_PORT_4_CTRL_12 0xE0456#define REG_PORT_5_CTRL_12 0xF0457 458#define PORT_PASS_ALL BIT(6)459#define PORT_INS_TAG_FOR_PORT_5_S 3460#define PORT_INS_TAG_FOR_PORT_5 BIT(3)461#define PORT_INS_TAG_FOR_PORT_4 BIT(2)462#define PORT_INS_TAG_FOR_PORT_3 BIT(1)463#define PORT_INS_TAG_FOR_PORT_2 BIT(0)464 465#define REG_PORT_1_CTRL_13 0xB1466#define REG_PORT_2_CTRL_13 0xC1467#define REG_PORT_3_CTRL_13 0xD1468#define REG_PORT_4_CTRL_13 0xE1469#define REG_PORT_5_CTRL_13 0xF1470 471#define KSZ8795_PORT_4QUEUE_SPLIT_EN BIT(1)472#define PORT_DROP_TAG BIT(0)473 474#define REG_PORT_1_CTRL_14 0xB2475#define REG_PORT_2_CTRL_14 0xC2476#define REG_PORT_3_CTRL_14 0xD2477#define REG_PORT_4_CTRL_14 0xE2478#define REG_PORT_5_CTRL_14 0xF2479#define REG_PORT_1_CTRL_15 0xB3480#define REG_PORT_2_CTRL_15 0xC3481#define REG_PORT_3_CTRL_15 0xD3482#define REG_PORT_4_CTRL_15 0xE3483#define REG_PORT_5_CTRL_15 0xF3484#define REG_PORT_1_CTRL_16 0xB4485#define REG_PORT_2_CTRL_16 0xC4486#define REG_PORT_3_CTRL_16 0xD4487#define REG_PORT_4_CTRL_16 0xE4488#define REG_PORT_5_CTRL_16 0xF4489#define REG_PORT_1_CTRL_17 0xB5490#define REG_PORT_2_CTRL_17 0xC5491#define REG_PORT_3_CTRL_17 0xD5492#define REG_PORT_4_CTRL_17 0xE5493#define REG_PORT_5_CTRL_17 0xF5494 495#define REG_PORT_1_RATE_CTRL_3 0xB2496#define REG_PORT_1_RATE_CTRL_2 0xB3497#define REG_PORT_1_RATE_CTRL_1 0xB4498#define REG_PORT_1_RATE_CTRL_0 0xB5499#define REG_PORT_2_RATE_CTRL_3 0xC2500#define REG_PORT_2_RATE_CTRL_2 0xC3501#define REG_PORT_2_RATE_CTRL_1 0xC4502#define REG_PORT_2_RATE_CTRL_0 0xC5503#define REG_PORT_3_RATE_CTRL_3 0xD2504#define REG_PORT_3_RATE_CTRL_2 0xD3505#define REG_PORT_3_RATE_CTRL_1 0xD4506#define REG_PORT_3_RATE_CTRL_0 0xD5507#define REG_PORT_4_RATE_CTRL_3 0xE2508#define REG_PORT_4_RATE_CTRL_2 0xE3509#define REG_PORT_4_RATE_CTRL_1 0xE4510#define REG_PORT_4_RATE_CTRL_0 0xE5511#define REG_PORT_5_RATE_CTRL_3 0xF2512#define REG_PORT_5_RATE_CTRL_2 0xF3513#define REG_PORT_5_RATE_CTRL_1 0xF4514#define REG_PORT_5_RATE_CTRL_0 0xF5515 516#define RATE_CTRL_ENABLE BIT(7)517#define RATE_RATIO_M (BIT(7) - 1)518 519#define PORT_OUT_RATE_ENABLE BIT(7)520 521#define REG_PORT_1_RATE_LIMIT 0xB6522#define REG_PORT_2_RATE_LIMIT 0xC6523#define REG_PORT_3_RATE_LIMIT 0xD6524#define REG_PORT_4_RATE_LIMIT 0xE6525#define REG_PORT_5_RATE_LIMIT 0xF6526 527#define PORT_IN_PORT_BASED_S 6528#define PORT_RATE_PACKET_BASED_S 5529#define PORT_IN_FLOW_CTRL_S 4530#define PORT_IN_LIMIT_MODE_M 0x3531#define PORT_IN_LIMIT_MODE_S 2532#define PORT_COUNT_IFG_S 1533#define PORT_COUNT_PREAMBLE_S 0534#define PORT_IN_PORT_BASED BIT(PORT_IN_PORT_BASED_S)535#define PORT_RATE_PACKET_BASED BIT(PORT_RATE_PACKET_BASED_S)536#define PORT_IN_FLOW_CTRL BIT(PORT_IN_FLOW_CTRL_S)537#define PORT_IN_ALL 0538#define PORT_IN_UNICAST 1539#define PORT_IN_MULTICAST 2540#define PORT_IN_BROADCAST 3541#define PORT_COUNT_IFG BIT(PORT_COUNT_IFG_S)542#define PORT_COUNT_PREAMBLE BIT(PORT_COUNT_PREAMBLE_S)543 544#define REG_PORT_1_IN_RATE_0 0xB7545#define REG_PORT_2_IN_RATE_0 0xC7546#define REG_PORT_3_IN_RATE_0 0xD7547#define REG_PORT_4_IN_RATE_0 0xE7548#define REG_PORT_5_IN_RATE_0 0xF7549#define REG_PORT_1_IN_RATE_1 0xB8550#define REG_PORT_2_IN_RATE_1 0xC8551#define REG_PORT_3_IN_RATE_1 0xD8552#define REG_PORT_4_IN_RATE_1 0xE8553#define REG_PORT_5_IN_RATE_1 0xF8554#define REG_PORT_1_IN_RATE_2 0xB9555#define REG_PORT_2_IN_RATE_2 0xC9556#define REG_PORT_3_IN_RATE_2 0xD9557#define REG_PORT_4_IN_RATE_2 0xE9558#define REG_PORT_5_IN_RATE_2 0xF9559#define REG_PORT_1_IN_RATE_3 0xBA560#define REG_PORT_2_IN_RATE_3 0xCA561#define REG_PORT_3_IN_RATE_3 0xDA562#define REG_PORT_4_IN_RATE_3 0xEA563#define REG_PORT_5_IN_RATE_3 0xFA564 565#define PORT_IN_RATE_ENABLE BIT(7)566#define PORT_RATE_LIMIT_M (BIT(7) - 1)567 568#define REG_PORT_1_OUT_RATE_0 0xBB569#define REG_PORT_2_OUT_RATE_0 0xCB570#define REG_PORT_3_OUT_RATE_0 0xDB571#define REG_PORT_4_OUT_RATE_0 0xEB572#define REG_PORT_5_OUT_RATE_0 0xFB573#define REG_PORT_1_OUT_RATE_1 0xBC574#define REG_PORT_2_OUT_RATE_1 0xCC575#define REG_PORT_3_OUT_RATE_1 0xDC576#define REG_PORT_4_OUT_RATE_1 0xEC577#define REG_PORT_5_OUT_RATE_1 0xFC578#define REG_PORT_1_OUT_RATE_2 0xBD579#define REG_PORT_2_OUT_RATE_2 0xCD580#define REG_PORT_3_OUT_RATE_2 0xDD581#define REG_PORT_4_OUT_RATE_2 0xED582#define REG_PORT_5_OUT_RATE_2 0xFD583#define REG_PORT_1_OUT_RATE_3 0xBE584#define REG_PORT_2_OUT_RATE_3 0xCE585#define REG_PORT_3_OUT_RATE_3 0xDE586#define REG_PORT_4_OUT_RATE_3 0xEE587#define REG_PORT_5_OUT_RATE_3 0xFE588 589/* 88x3 specific */590 591#define REG_SW_INSERT_SRC_PVID 0xC2592 593/* PME */594 595#define SW_PME_OUTPUT_ENABLE BIT(1)596#define SW_PME_ACTIVE_HIGH BIT(0)597 598#define PORT_MAGIC_PACKET_DETECT BIT(2)599#define PORT_LINK_UP_DETECT BIT(1)600#define PORT_ENERGY_DETECT BIT(0)601 602/* ACL */603 604#define ACL_FIRST_RULE_M 0xF605 606#define ACL_MODE_M 0x3607#define ACL_MODE_S 4608#define ACL_MODE_DISABLE 0609#define ACL_MODE_LAYER_2 1610#define ACL_MODE_LAYER_3 2611#define ACL_MODE_LAYER_4 3612#define ACL_ENABLE_M 0x3613#define ACL_ENABLE_S 2614#define ACL_ENABLE_2_COUNT 0615#define ACL_ENABLE_2_TYPE 1616#define ACL_ENABLE_2_MAC 2617#define ACL_ENABLE_2_BOTH 3618#define ACL_ENABLE_3_IP 1619#define ACL_ENABLE_3_SRC_DST_COMP 2620#define ACL_ENABLE_4_PROTOCOL 0621#define ACL_ENABLE_4_TCP_PORT_COMP 1622#define ACL_ENABLE_4_UDP_PORT_COMP 2623#define ACL_ENABLE_4_TCP_SEQN_COMP 3624#define ACL_SRC BIT(1)625#define ACL_EQUAL BIT(0)626 627#define ACL_MAX_PORT 0xFFFF628 629#define ACL_MIN_PORT 0xFFFF630#define ACL_IP_ADDR 0xFFFFFFFF631#define ACL_TCP_SEQNUM 0xFFFFFFFF632 633#define ACL_RESERVED 0xF8634#define ACL_PORT_MODE_M 0x3635#define ACL_PORT_MODE_S 1636#define ACL_PORT_MODE_DISABLE 0637#define ACL_PORT_MODE_EITHER 1638#define ACL_PORT_MODE_IN_RANGE 2639#define ACL_PORT_MODE_OUT_OF_RANGE 3640 641#define ACL_TCP_FLAG_ENABLE BIT(0)642 643#define ACL_TCP_FLAG_M 0xFF644 645#define ACL_TCP_FLAG 0xFF646#define ACL_ETH_TYPE 0xFFFF647#define ACL_IP_M 0xFFFFFFFF648 649#define ACL_PRIO_MODE_M 0x3650#define ACL_PRIO_MODE_S 6651#define ACL_PRIO_MODE_DISABLE 0652#define ACL_PRIO_MODE_HIGHER 1653#define ACL_PRIO_MODE_LOWER 2654#define ACL_PRIO_MODE_REPLACE 3655#define ACL_PRIO_M 0x7656#define ACL_PRIO_S 3657#define ACL_VLAN_PRIO_REPLACE BIT(2)658#define ACL_VLAN_PRIO_M 0x7659#define ACL_VLAN_PRIO_HI_M 0x3660 661#define ACL_VLAN_PRIO_LO_M 0x8662#define ACL_VLAN_PRIO_S 7663#define ACL_MAP_MODE_M 0x3664#define ACL_MAP_MODE_S 5665#define ACL_MAP_MODE_DISABLE 0666#define ACL_MAP_MODE_OR 1667#define ACL_MAP_MODE_AND 2668#define ACL_MAP_MODE_REPLACE 3669#define ACL_MAP_PORT_M 0x1F670 671#define ACL_CNT_M (BIT(11) - 1)672#define ACL_CNT_S 5673#define ACL_MSEC_UNIT BIT(4)674#define ACL_INTR_MODE BIT(3)675 676#define REG_PORT_ACL_BYTE_EN_MSB 0x10677 678#define ACL_BYTE_EN_MSB_M 0x3F679 680#define REG_PORT_ACL_BYTE_EN_LSB 0x11681 682#define ACL_ACTION_START 0xA683#define ACL_ACTION_LEN 2684#define ACL_INTR_CNT_START 0xB685#define ACL_RULESET_START 0xC686#define ACL_RULESET_LEN 2687#define ACL_TABLE_LEN 14688 689#define ACL_ACTION_ENABLE 0x000C690#define ACL_MATCH_ENABLE 0x1FF0691#define ACL_RULESET_ENABLE 0x2003692#define ACL_BYTE_ENABLE ((ACL_BYTE_EN_MSB_M << 8) | 0xFF)693#define ACL_MODE_ENABLE (0x10 << 8)694 695#define REG_PORT_ACL_CTRL_0 0x12696 697#define PORT_ACL_WRITE_DONE BIT(6)698#define PORT_ACL_READ_DONE BIT(5)699#define PORT_ACL_WRITE BIT(4)700#define PORT_ACL_INDEX_M 0xF701 702#define REG_PORT_ACL_CTRL_1 0x13703 704#define PORT_ACL_FORCE_DLR_MISS BIT(0)705 706#define KSZ8795_ID_HI 0x0022707#define KSZ8795_ID_LO 0x1550708#define KSZ8863_ID_LO 0x1430709 710#define PHY_REG_LINK_MD 0x1D711 712#define PHY_START_CABLE_DIAG BIT(15)713#define PHY_CABLE_DIAG_RESULT_M GENMASK(14, 13)714#define PHY_CABLE_DIAG_RESULT 0x6000715#define PHY_CABLE_STAT_NORMAL 0x0000716#define PHY_CABLE_STAT_OPEN 0x2000717#define PHY_CABLE_STAT_SHORT 0x4000718#define PHY_CABLE_STAT_FAILED 0x6000719#define PHY_CABLE_10M_SHORT BIT(12)720#define PHY_CABLE_FAULT_COUNTER_M GENMASK(8, 0)721 722#define PHY_REG_PHY_CTRL 0x1F723 724#define PHY_MODE_M 0x7725#define PHY_MODE_S 8726#define PHY_STAT_REVERSED_POLARITY BIT(5)727#define PHY_STAT_MDIX BIT(4)728#define PHY_FORCE_LINK BIT(3)729#define PHY_POWER_SAVING_ENABLE BIT(2)730#define PHY_REMOTE_LOOPBACK BIT(1)731 732/* Chip resource */733 734#define PRIO_QUEUES 4735 736#define KS_PRIO_IN_REG 4737 738#define MIB_COUNTER_NUM 0x20739 740/* Common names used by other drivers */741 742#define P_BCAST_STORM_CTRL REG_PORT_CTRL_0743#define P_PRIO_CTRL REG_PORT_CTRL_0744#define P_TAG_CTRL REG_PORT_CTRL_0745#define P_MIRROR_CTRL REG_PORT_CTRL_1746#define P_802_1P_CTRL REG_PORT_CTRL_2747#define P_PASS_ALL_CTRL REG_PORT_CTRL_12748#define P_INS_SRC_PVID_CTRL REG_PORT_CTRL_12749#define P_DROP_TAG_CTRL REG_PORT_CTRL_13750#define P_RATE_LIMIT_CTRL REG_PORT_RATE_LIMIT751 752#define S_UNKNOWN_DA_CTRL REG_SWITCH_CTRL_12753#define S_FORWARD_INVALID_VID_CTRL REG_FORWARD_INVALID_VID754 755#define S_FLUSH_TABLE_CTRL REG_SW_CTRL_0756#define S_LINK_AGING_CTRL REG_SW_CTRL_0757#define S_HUGE_PACKET_CTRL REG_SW_CTRL_1758#define S_MIRROR_CTRL REG_SW_CTRL_3759#define S_REPLACE_VID_CTRL REG_SW_CTRL_4760#define S_PASS_PAUSE_CTRL REG_SW_CTRL_10761#define S_802_1P_PRIO_CTRL REG_SW_CTRL_12762#define S_TOS_PRIO_CTRL REG_TOS_PRIO_CTRL_0763#define S_IPV6_MLD_CTRL REG_SW_CTRL_21764 765#define IND_ACC_TABLE(table) ((table) << 8)766 767/* */768#define REG_IND_EEE_GLOB2_LO 0x34769#define REG_IND_EEE_GLOB2_HI 0x35770 771/**772 * MIB_COUNTER_VALUE 00-00000000-3FFFFFFF773 * MIB_TOTAL_BYTES 00-0000000F-FFFFFFFF774 * MIB_PACKET_DROPPED 00-00000000-0000FFFF775 * MIB_COUNTER_VALID 00-00000020-00000000776 * MIB_COUNTER_OVERFLOW 00-00000040-00000000777 */778 779#define MIB_COUNTER_VALUE 0x3FFFFFFF780 781#define KSZ8795_MIB_TOTAL_RX_0 0x100782#define KSZ8795_MIB_TOTAL_TX_0 0x101783#define KSZ8795_MIB_TOTAL_RX_1 0x104784#define KSZ8795_MIB_TOTAL_TX_1 0x105785 786#define KSZ8863_MIB_PACKET_DROPPED_TX_0 0x100787#define KSZ8863_MIB_PACKET_DROPPED_RX_0 0x105788 789#define MIB_PACKET_DROPPED 0x0000FFFF790 791#define MIB_TOTAL_BYTES_H 0x0000000F792 793#define TAIL_TAG_OVERRIDE BIT(6)794#define TAIL_TAG_LOOKUP BIT(7)795 796#define FID_ENTRIES 128797#define KSZ8_DYN_MAC_ENTRIES 1024798 799#endif800