1575 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Microchip KSZ9477 register definitions4 *5 * Copyright (C) 2017-2018 Microchip Technology Inc.6 */7 8#ifndef __KSZ9477_REGS_H9#define __KSZ9477_REGS_H10 11#define KS_PRIO_M 0x712#define KS_PRIO_S 413 14/* 0 - Operation */15#define REG_CHIP_ID0__1 0x000016 17#define REG_CHIP_ID1__1 0x000118 19#define FAMILY_ID 0x9520#define FAMILY_ID_94 0x9421#define FAMILY_ID_95 0x9522#define FAMILY_ID_85 0x8523#define FAMILY_ID_98 0x9824#define FAMILY_ID_88 0x8825 26#define REG_CHIP_ID2__1 0x000227 28#define CHIP_ID_66 0x6629#define CHIP_ID_67 0x6730#define CHIP_ID_77 0x7731#define CHIP_ID_93 0x9332#define CHIP_ID_96 0x9633#define CHIP_ID_97 0x9734 35#define REG_CHIP_ID3__1 0x000336 37#define SWITCH_REVISION_M 0x0F38#define SWITCH_REVISION_S 439#define SWITCH_RESET 0x0140 41#define REG_GLOBAL_OPTIONS 0x000F42 43#define SW_GIGABIT_ABLE BIT(6)44#define SW_REDUNDANCY_ABLE BIT(5)45#define SW_AVB_ABLE BIT(4)46#define SW_9567_RL_5_2 0xC47#define SW_9477_SL_5_2 0xD48 49#define SW_9896_GL_5_1 0xB50#define SW_9896_RL_5_1 0x851#define SW_9896_SL_5_1 0x952 53#define SW_9895_GL_4_1 0x754#define SW_9895_RL_4_1 0x455#define SW_9895_SL_4_1 0x556 57#define SW_9896_RL_4_2 0x658 59#define SW_9893_RL_2_1 0x060#define SW_9893_SL_2_1 0x161#define SW_9893_GL_2_1 0x362 63#define SW_QW_ABLE BIT(5)64#define SW_9893_RN_2_1 0xC65 66#define REG_SW_INT_STATUS__4 0x001067#define REG_SW_INT_MASK__4 0x001468 69#define LUE_INT BIT(31)70#define TRIG_TS_INT BIT(30)71#define APB_TIMEOUT_INT BIT(29)72 73#define SWITCH_INT_MASK (TRIG_TS_INT | APB_TIMEOUT_INT)74 75#define REG_SW_PORT_INT_STATUS__4 0x001876#define REG_SW_PORT_INT_MASK__4 0x001C77#define REG_SW_PHY_INT_STATUS 0x002078#define REG_SW_PHY_INT_ENABLE 0x002479 80/* 1 - Global */81#define REG_SW_GLOBAL_SERIAL_CTRL_0 0x010082#define SW_SPARE_REG_2 BIT(7)83#define SW_SPARE_REG_1 BIT(6)84#define SW_SPARE_REG_0 BIT(5)85#define SW_BIG_ENDIAN BIT(4)86#define SPI_AUTO_EDGE_DETECTION BIT(1)87#define SPI_CLOCK_OUT_RISING_EDGE BIT(0)88 89#define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x010390#define SW_ENABLE_REFCLKO BIT(1)91#define SW_REFCLKO_IS_125MHZ BIT(0)92 93#define REG_SW_IBA__4 0x010494 95#define SW_IBA_ENABLE BIT(31)96#define SW_IBA_DA_MATCH BIT(30)97#define SW_IBA_INIT BIT(29)98#define SW_IBA_QID_M 0xF99#define SW_IBA_QID_S 22100#define SW_IBA_PORT_M 0x2F101#define SW_IBA_PORT_S 16102#define SW_IBA_FRAME_TPID_M 0xFFFF103 104#define REG_SW_APB_TIMEOUT_ADDR__4 0x0108105 106#define APB_TIMEOUT_ACKNOWLEDGE BIT(31)107 108#define REG_SW_IBA_SYNC__1 0x010C109 110#define REG_SW_IBA_STATUS__4 0x0110111 112#define SW_IBA_REQ BIT(31)113#define SW_IBA_RESP BIT(30)114#define SW_IBA_DA_MISMATCH BIT(14)115#define SW_IBA_FMT_MISMATCH BIT(13)116#define SW_IBA_CODE_ERROR BIT(12)117#define SW_IBA_CMD_ERROR BIT(11)118#define SW_IBA_CMD_LOC_M (BIT(6) - 1)119 120#define REG_SW_IBA_STATES__4 0x0114121 122#define SW_IBA_BUF_STATE_S 30123#define SW_IBA_CMD_STATE_S 28124#define SW_IBA_RESP_STATE_S 26125#define SW_IBA_STATE_M 0x3126#define SW_IBA_PACKET_SIZE_M 0x7F127#define SW_IBA_PACKET_SIZE_S 16128#define SW_IBA_FMT_ID_M 0xFFFF129 130#define REG_SW_IBA_RESULT__4 0x0118131 132#define SW_IBA_SIZE_S 24133 134#define SW_IBA_RETRY_CNT_M (BIT(5) - 1)135 136/* 2 - PHY */137#define REG_SW_POWER_MANAGEMENT_CTRL 0x0201138 139#define SW_PLL_POWER_DOWN BIT(5)140#define SW_POWER_DOWN_MODE 0x3141#define SW_ENERGY_DETECTION 1142#define SW_SOFT_POWER_DOWN 2143#define SW_POWER_SAVING 3144 145/* 3 - Operation Control */146#define REG_SW_OPERATION 0x0300147 148#define SW_DOUBLE_TAG BIT(7)149#define SW_RESET BIT(1)150 151#define REG_SW_MTU__2 0x0308152#define REG_SW_MTU_MASK GENMASK(13, 0)153 154#define REG_SW_ISP_TPID__2 0x030A155 156#define REG_SW_HSR_TPID__2 0x030C157 158#define REG_AVB_STRATEGY__2 0x030E159 160#define SW_SHAPING_CREDIT_ACCT BIT(1)161#define SW_POLICING_CREDIT_ACCT BIT(0)162 163#define REG_SW_LUE_CTRL_0 0x0310164 165#define SW_VLAN_ENABLE BIT(7)166#define SW_DROP_INVALID_VID BIT(6)167#define SW_AGE_CNT_M GENMASK(5, 3)168#define SW_AGE_CNT_S 3169#define SW_AGE_PERIOD_10_8_M GENMASK(10, 8)170#define SW_RESV_MCAST_ENABLE BIT(2)171#define SW_HASH_OPTION_M 0x03172#define SW_HASH_OPTION_CRC 1173#define SW_HASH_OPTION_XOR 2174#define SW_HASH_OPTION_DIRECT 3175 176#define REG_SW_LUE_CTRL_1 0x0311177 178#define UNICAST_LEARN_DISABLE BIT(7)179#define SW_SRC_ADDR_FILTER BIT(6)180#define SW_FLUSH_STP_TABLE BIT(5)181#define SW_FLUSH_MSTP_TABLE BIT(4)182#define SW_FWD_MCAST_SRC_ADDR BIT(3)183#define SW_AGING_ENABLE BIT(2)184#define SW_FAST_AGING BIT(1)185#define SW_LINK_AUTO_AGING BIT(0)186 187#define REG_SW_LUE_CTRL_2 0x0312188 189#define SW_TRAP_DOUBLE_TAG BIT(6)190#define SW_EGRESS_VLAN_FILTER_DYN BIT(5)191#define SW_EGRESS_VLAN_FILTER_STA BIT(4)192#define SW_FLUSH_OPTION_M 0x3193#define SW_FLUSH_OPTION_S 2194#define SW_FLUSH_OPTION_DYN_MAC 1195#define SW_FLUSH_OPTION_STA_MAC 2196#define SW_FLUSH_OPTION_BOTH 3197#define SW_PRIO_M 0x3198#define SW_PRIO_DA 0199#define SW_PRIO_SA 1200#define SW_PRIO_HIGHEST_DA_SA 2201#define SW_PRIO_LOWEST_DA_SA 3202 203#define REG_SW_LUE_CTRL_3 0x0313204#define SW_AGE_PERIOD_7_0_M GENMASK(7, 0)205 206#define REG_SW_LUE_INT_STATUS 0x0314207#define REG_SW_LUE_INT_ENABLE 0x0315208 209#define LEARN_FAIL_INT BIT(2)210#define ALMOST_FULL_INT BIT(1)211#define WRITE_FAIL_INT BIT(0)212 213#define REG_SW_LUE_INDEX_0__2 0x0316214 215#define ENTRY_INDEX_M 0x0FFF216 217#define REG_SW_LUE_INDEX_1__2 0x0318218 219#define FAIL_INDEX_M 0x03FF220 221#define REG_SW_LUE_INDEX_2__2 0x031A222 223#define REG_SW_LUE_UNK_UCAST_CTRL__4 0x0320224 225#define SW_UNK_UCAST_ENABLE BIT(31)226 227#define REG_SW_LUE_UNK_MCAST_CTRL__4 0x0324228 229#define SW_UNK_MCAST_ENABLE BIT(31)230 231#define REG_SW_LUE_UNK_VID_CTRL__4 0x0328232 233#define SW_UNK_VID_ENABLE BIT(31)234 235#define REG_SW_MAC_CTRL_0 0x0330236 237#define SW_NEW_BACKOFF BIT(7)238#define SW_CHECK_LENGTH BIT(3)239#define SW_PAUSE_UNH_MODE BIT(1)240#define SW_AGGR_BACKOFF BIT(0)241 242#define REG_SW_MAC_CTRL_1 0x0331243 244#define SW_BACK_PRESSURE BIT(5)245#define SW_BACK_PRESSURE_COLLISION 0246#define FAIR_FLOW_CTRL BIT(4)247#define NO_EXC_COLLISION_DROP BIT(3)248#define SW_JUMBO_PACKET BIT(2)249#define SW_LEGAL_PACKET_DISABLE BIT(1)250#define SW_PASS_SHORT_FRAME BIT(0)251 252#define REG_SW_MAC_CTRL_2 0x0332253 254#define SW_REPLACE_VID BIT(3)255 256#define REG_SW_MAC_CTRL_3 0x0333257 258#define REG_SW_MAC_CTRL_4 0x0334259 260#define SW_PASS_PAUSE BIT(3)261 262#define REG_SW_MAC_CTRL_5 0x0335263 264#define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)265 266#define REG_SW_MAC_CTRL_6 0x0336267 268#define SW_MIB_COUNTER_FLUSH BIT(7)269#define SW_MIB_COUNTER_FREEZE BIT(6)270 271#define REG_SW_MAC_802_1P_MAP_0 0x0338272#define REG_SW_MAC_802_1P_MAP_1 0x0339273#define REG_SW_MAC_802_1P_MAP_2 0x033A274#define REG_SW_MAC_802_1P_MAP_3 0x033B275 276#define SW_802_1P_MAP_M KS_PRIO_M277#define SW_802_1P_MAP_S KS_PRIO_S278 279#define REG_SW_MAC_ISP_CTRL 0x033C280 281#define REG_SW_MAC_TOS_CTRL 0x033E282 283#define SW_TOS_DSCP_REMARK BIT(1)284#define SW_TOS_DSCP_REMAP BIT(0)285 286#define REG_SW_MAC_TOS_PRIO_0 0x0340287#define REG_SW_MAC_TOS_PRIO_1 0x0341288#define REG_SW_MAC_TOS_PRIO_2 0x0342289#define REG_SW_MAC_TOS_PRIO_3 0x0343290#define REG_SW_MAC_TOS_PRIO_4 0x0344291#define REG_SW_MAC_TOS_PRIO_5 0x0345292#define REG_SW_MAC_TOS_PRIO_6 0x0346293#define REG_SW_MAC_TOS_PRIO_7 0x0347294#define REG_SW_MAC_TOS_PRIO_8 0x0348295#define REG_SW_MAC_TOS_PRIO_9 0x0349296#define REG_SW_MAC_TOS_PRIO_10 0x034A297#define REG_SW_MAC_TOS_PRIO_11 0x034B298#define REG_SW_MAC_TOS_PRIO_12 0x034C299#define REG_SW_MAC_TOS_PRIO_13 0x034D300#define REG_SW_MAC_TOS_PRIO_14 0x034E301#define REG_SW_MAC_TOS_PRIO_15 0x034F302#define REG_SW_MAC_TOS_PRIO_16 0x0350303#define REG_SW_MAC_TOS_PRIO_17 0x0351304#define REG_SW_MAC_TOS_PRIO_18 0x0352305#define REG_SW_MAC_TOS_PRIO_19 0x0353306#define REG_SW_MAC_TOS_PRIO_20 0x0354307#define REG_SW_MAC_TOS_PRIO_21 0x0355308#define REG_SW_MAC_TOS_PRIO_22 0x0356309#define REG_SW_MAC_TOS_PRIO_23 0x0357310#define REG_SW_MAC_TOS_PRIO_24 0x0358311#define REG_SW_MAC_TOS_PRIO_25 0x0359312#define REG_SW_MAC_TOS_PRIO_26 0x035A313#define REG_SW_MAC_TOS_PRIO_27 0x035B314#define REG_SW_MAC_TOS_PRIO_28 0x035C315#define REG_SW_MAC_TOS_PRIO_29 0x035D316#define REG_SW_MAC_TOS_PRIO_30 0x035E317#define REG_SW_MAC_TOS_PRIO_31 0x035F318 319#define REG_SW_MRI_CTRL_0 0x0370320 321#define SW_IGMP_SNOOP BIT(6)322#define SW_IPV6_MLD_OPTION BIT(3)323#define SW_IPV6_MLD_SNOOP BIT(2)324#define SW_MIRROR_RX_TX BIT(0)325 326#define REG_SW_CLASS_D_IP_CTRL__4 0x0374327 328#define SW_CLASS_D_IP_ENABLE BIT(31)329 330#define REG_SW_MRI_CTRL_8 0x0378331 332#define SW_NO_COLOR_S 6333#define SW_RED_COLOR_S 4334#define SW_YELLOW_COLOR_S 2335#define SW_GREEN_COLOR_S 0336#define SW_COLOR_M 0x3337 338#define REG_SW_QM_CTRL__4 0x0390339 340#define PRIO_SCHEME_SELECT_M KS_PRIO_M341#define PRIO_SCHEME_SELECT_S 6342#define PRIO_MAP_3_HI 0343#define PRIO_MAP_2_HI 2344#define PRIO_MAP_0_LO 3345#define UNICAST_VLAN_BOUNDARY BIT(1)346 347#define REG_SW_EEE_QM_CTRL__2 0x03C0348 349#define REG_SW_EEE_TXQ_WAIT_TIME__2 0x03C2350 351/* 4 - */352#define REG_SW_VLAN_ENTRY__4 0x0400353 354#define VLAN_VALID BIT(31)355#define VLAN_FORWARD_OPTION BIT(27)356#define VLAN_PRIO_M KS_PRIO_M357#define VLAN_PRIO_S 24358#define VLAN_MSTP_M 0x7359#define VLAN_MSTP_S 12360#define VLAN_FID_M 0x7F361 362#define REG_SW_VLAN_ENTRY_UNTAG__4 0x0404363#define REG_SW_VLAN_ENTRY_PORTS__4 0x0408364 365#define REG_SW_VLAN_ENTRY_INDEX__2 0x040C366 367#define VLAN_INDEX_M 0x0FFF368 369#define REG_SW_VLAN_CTRL 0x040E370 371#define VLAN_START BIT(7)372#define VLAN_ACTION 0x3373#define VLAN_WRITE 1374#define VLAN_READ 2375#define VLAN_CLEAR 3376 377#define REG_SW_ALU_INDEX_0 0x0410378 379#define ALU_FID_INDEX_S 16380#define ALU_MAC_ADDR_HI 0xFFFF381 382#define REG_SW_ALU_INDEX_1 0x0414383 384#define ALU_DIRECT_INDEX_M (BIT(12) - 1)385 386#define REG_SW_ALU_CTRL__4 0x0418387 388#define ALU_VALID_CNT_M (BIT(14) - 1)389#define ALU_VALID_CNT_S 16390#define ALU_START BIT(7)391#define ALU_VALID BIT(6)392#define ALU_DIRECT BIT(2)393#define ALU_ACTION 0x3394#define ALU_WRITE 1395#define ALU_READ 2396#define ALU_SEARCH 3397 398#define REG_SW_ALU_STAT_CTRL__4 0x041C399 400#define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1)401#define ALU_STAT_START BIT(7)402#define ALU_RESV_MCAST_ADDR BIT(1)403 404#define REG_SW_ALU_VAL_A 0x0420405 406#define ALU_V_STATIC_VALID BIT(31)407#define ALU_V_SRC_FILTER BIT(30)408#define ALU_V_DST_FILTER BIT(29)409#define ALU_V_PRIO_AGE_CNT_M (BIT(3) - 1)410#define ALU_V_PRIO_AGE_CNT_S 26411#define ALU_V_MSTP_M 0x7412 413#define REG_SW_ALU_VAL_B 0x0424414 415#define ALU_V_OVERRIDE BIT(31)416#define ALU_V_USE_FID BIT(30)417#define ALU_V_PORT_MAP (BIT(24) - 1)418 419#define REG_SW_ALU_VAL_C 0x0428420 421#define ALU_V_FID_M (BIT(16) - 1)422#define ALU_V_FID_S 16423#define ALU_V_MAC_ADDR_HI 0xFFFF424 425#define REG_SW_ALU_VAL_D 0x042C426 427#define REG_HSR_ALU_INDEX_0 0x0440428 429#define REG_HSR_ALU_INDEX_1 0x0444430 431#define HSR_DST_MAC_INDEX_LO_S 16432#define HSR_SRC_MAC_INDEX_HI 0xFFFF433 434#define REG_HSR_ALU_INDEX_2 0x0448435 436#define HSR_INDEX_MAX BIT(9)437#define HSR_DIRECT_INDEX_M (HSR_INDEX_MAX - 1)438 439#define REG_HSR_ALU_INDEX_3 0x044C440 441#define HSR_PATH_INDEX_M (BIT(4) - 1)442 443#define REG_HSR_ALU_CTRL__4 0x0450444 445#define HSR_VALID_CNT_M (BIT(14) - 1)446#define HSR_VALID_CNT_S 16447#define HSR_START BIT(7)448#define HSR_VALID BIT(6)449#define HSR_SEARCH_END BIT(5)450#define HSR_DIRECT BIT(2)451#define HSR_ACTION 0x3452#define HSR_WRITE 1453#define HSR_READ 2454#define HSR_SEARCH 3455 456#define REG_HSR_ALU_VAL_A 0x0454457 458#define HSR_V_STATIC_VALID BIT(31)459#define HSR_V_AGE_CNT_M (BIT(3) - 1)460#define HSR_V_AGE_CNT_S 26461#define HSR_V_PATH_ID_M (BIT(4) - 1)462 463#define REG_HSR_ALU_VAL_B 0x0458464 465#define REG_HSR_ALU_VAL_C 0x045C466 467#define HSR_V_DST_MAC_ADDR_LO_S 16468#define HSR_V_SRC_MAC_ADDR_HI 0xFFFF469 470#define REG_HSR_ALU_VAL_D 0x0460471 472#define REG_HSR_ALU_VAL_E 0x0464473 474#define HSR_V_START_SEQ_1_S 16475#define HSR_V_START_SEQ_2_S 0476 477#define REG_HSR_ALU_VAL_F 0x0468478 479#define HSR_V_EXP_SEQ_1_S 16480#define HSR_V_EXP_SEQ_2_S 0481 482#define REG_HSR_ALU_VAL_G 0x046C483 484#define HSR_V_SEQ_CNT_1_S 16485#define HSR_V_SEQ_CNT_2_S 0486 487#define HSR_V_SEQ_M (BIT(16) - 1)488 489/* 5 - PTP Clock */490#define REG_PTP_CLK_CTRL 0x0500491 492#define PTP_STEP_ADJ BIT(6)493#define PTP_STEP_DIR BIT(5)494#define PTP_READ_TIME BIT(4)495#define PTP_LOAD_TIME BIT(3)496#define PTP_CLK_ADJ_ENABLE BIT(2)497#define PTP_CLK_ENABLE BIT(1)498#define PTP_CLK_RESET BIT(0)499 500#define REG_PTP_RTC_SUB_NANOSEC__2 0x0502501 502#define PTP_RTC_SUB_NANOSEC_M 0x0007503 504#define REG_PTP_RTC_NANOSEC 0x0504505#define REG_PTP_RTC_NANOSEC_H 0x0504506#define REG_PTP_RTC_NANOSEC_L 0x0506507 508#define REG_PTP_RTC_SEC 0x0508509#define REG_PTP_RTC_SEC_H 0x0508510#define REG_PTP_RTC_SEC_L 0x050A511 512#define REG_PTP_SUBNANOSEC_RATE 0x050C513#define REG_PTP_SUBNANOSEC_RATE_H 0x050C514 515#define PTP_RATE_DIR BIT(31)516#define PTP_TMP_RATE_ENABLE BIT(30)517 518#define REG_PTP_SUBNANOSEC_RATE_L 0x050E519 520#define REG_PTP_RATE_DURATION 0x0510521#define REG_PTP_RATE_DURATION_H 0x0510522#define REG_PTP_RATE_DURATION_L 0x0512523 524#define REG_PTP_MSG_CONF1 0x0514525 526#define PTP_802_1AS BIT(7)527#define PTP_ENABLE BIT(6)528#define PTP_ETH_ENABLE BIT(5)529#define PTP_IPV4_UDP_ENABLE BIT(4)530#define PTP_IPV6_UDP_ENABLE BIT(3)531#define PTP_TC_P2P BIT(2)532#define PTP_MASTER BIT(1)533#define PTP_1STEP BIT(0)534 535#define REG_PTP_MSG_CONF2 0x0516536 537#define PTP_UNICAST_ENABLE BIT(12)538#define PTP_ALTERNATE_MASTER BIT(11)539#define PTP_ALL_HIGH_PRIO BIT(10)540#define PTP_SYNC_CHECK BIT(9)541#define PTP_DELAY_CHECK BIT(8)542#define PTP_PDELAY_CHECK BIT(7)543#define PTP_DROP_SYNC_DELAY_REQ BIT(5)544#define PTP_DOMAIN_CHECK BIT(4)545#define PTP_UDP_CHECKSUM BIT(2)546 547#define REG_PTP_DOMAIN_VERSION 0x0518548#define PTP_VERSION_M 0xFF00549#define PTP_DOMAIN_M 0x00FF550 551#define REG_PTP_UNIT_INDEX__4 0x0520552 553#define PTP_UNIT_M 0xF554 555#define PTP_GPIO_INDEX_S 16556#define PTP_TSI_INDEX_S 8557#define PTP_TOU_INDEX_S 0558 559#define REG_PTP_TRIG_STATUS__4 0x0524560 561#define TRIG_ERROR_S 16562#define TRIG_DONE_S 0563 564#define REG_PTP_INT_STATUS__4 0x0528565 566#define TRIG_INT_S 16567#define TS_INT_S 0568 569#define TRIG_UNIT_M 0x7570#define TS_UNIT_M 0x3571 572#define REG_PTP_CTRL_STAT__4 0x052C573 574#define GPIO_IN BIT(7)575#define GPIO_OUT BIT(6)576#define TS_INT_ENABLE BIT(5)577#define TRIG_ACTIVE BIT(4)578#define TRIG_ENABLE BIT(3)579#define TRIG_RESET BIT(2)580#define TS_ENABLE BIT(1)581#define TS_RESET BIT(0)582 583#define GPIO_CTRL_M (GPIO_IN | GPIO_OUT)584 585#define TRIG_CTRL_M \586 (TRIG_ACTIVE | TRIG_ENABLE | TRIG_RESET)587 588#define TS_CTRL_M \589 (TS_INT_ENABLE | TS_ENABLE | TS_RESET)590 591#define REG_TRIG_TARGET_NANOSEC 0x0530592#define REG_TRIG_TARGET_SEC 0x0534593 594#define REG_TRIG_CTRL__4 0x0538595 596#define TRIG_CASCADE_ENABLE BIT(31)597#define TRIG_CASCADE_TAIL BIT(30)598#define TRIG_CASCADE_UPS_M 0xF599#define TRIG_CASCADE_UPS_S 26600#define TRIG_NOW BIT(25)601#define TRIG_NOTIFY BIT(24)602#define TRIG_EDGE BIT(23)603#define TRIG_PATTERN_S 20604#define TRIG_PATTERN_M 0x7605#define TRIG_NEG_EDGE 0606#define TRIG_POS_EDGE 1607#define TRIG_NEG_PULSE 2608#define TRIG_POS_PULSE 3609#define TRIG_NEG_PERIOD 4610#define TRIG_POS_PERIOD 5611#define TRIG_REG_OUTPUT 6612#define TRIG_GPO_S 16613#define TRIG_GPO_M 0xF614#define TRIG_CASCADE_ITERATE_CNT_M 0xFFFF615 616#define REG_TRIG_CYCLE_WIDTH 0x053C617 618#define REG_TRIG_CYCLE_CNT 0x0540619 620#define TRIG_CYCLE_CNT_M 0xFFFF621#define TRIG_CYCLE_CNT_S 16622#define TRIG_BIT_PATTERN_M 0xFFFF623 624#define REG_TRIG_ITERATE_TIME 0x0544625 626#define REG_TRIG_PULSE_WIDTH__4 0x0548627 628#define TRIG_PULSE_WIDTH_M 0x00FFFFFF629 630#define REG_TS_CTRL_STAT__4 0x0550631 632#define TS_EVENT_DETECT_M 0xF633#define TS_EVENT_DETECT_S 17634#define TS_EVENT_OVERFLOW BIT(16)635#define TS_GPI_M 0xF636#define TS_GPI_S 8637#define TS_DETECT_RISE BIT(7)638#define TS_DETECT_FALL BIT(6)639#define TS_DETECT_S 6640#define TS_CASCADE_TAIL BIT(5)641#define TS_CASCADE_UPS_M 0xF642#define TS_CASCADE_UPS_S 1643#define TS_CASCADE_ENABLE BIT(0)644 645#define DETECT_RISE (TS_DETECT_RISE >> TS_DETECT_S)646#define DETECT_FALL (TS_DETECT_FALL >> TS_DETECT_S)647 648#define REG_TS_EVENT_0_NANOSEC 0x0554649#define REG_TS_EVENT_0_SEC 0x0558650#define REG_TS_EVENT_0_SUB_NANOSEC 0x055C651 652#define REG_TS_EVENT_1_NANOSEC 0x0560653#define REG_TS_EVENT_1_SEC 0x0564654#define REG_TS_EVENT_1_SUB_NANOSEC 0x0568655 656#define REG_TS_EVENT_2_NANOSEC 0x056C657#define REG_TS_EVENT_2_SEC 0x0570658#define REG_TS_EVENT_2_SUB_NANOSEC 0x0574659 660#define REG_TS_EVENT_3_NANOSEC 0x0578661#define REG_TS_EVENT_3_SEC 0x057C662#define REG_TS_EVENT_3_SUB_NANOSEC 0x0580663 664#define REG_TS_EVENT_4_NANOSEC 0x0584665#define REG_TS_EVENT_4_SEC 0x0588666#define REG_TS_EVENT_4_SUB_NANOSEC 0x058C667 668#define REG_TS_EVENT_5_NANOSEC 0x0590669#define REG_TS_EVENT_5_SEC 0x0594670#define REG_TS_EVENT_5_SUB_NANOSEC 0x0598671 672#define REG_TS_EVENT_6_NANOSEC 0x059C673#define REG_TS_EVENT_6_SEC 0x05A0674#define REG_TS_EVENT_6_SUB_NANOSEC 0x05A4675 676#define REG_TS_EVENT_7_NANOSEC 0x05A8677#define REG_TS_EVENT_7_SEC 0x05AC678#define REG_TS_EVENT_7_SUB_NANOSEC 0x05B0679 680#define TS_EVENT_EDGE_M 0x1681#define TS_EVENT_EDGE_S 30682#define TS_EVENT_NANOSEC_M (BIT(30) - 1)683 684#define TS_EVENT_SUB_NANOSEC_M 0x7685 686#define TS_EVENT_SAMPLE \687 (REG_TS_EVENT_1_NANOSEC - REG_TS_EVENT_0_NANOSEC)688 689#define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))690 691#define REG_GLOBAL_RR_INDEX__1 0x0600692 693/* DLR */694#define REG_DLR_SRC_PORT__4 0x0604695 696#define DLR_SRC_PORT_UNICAST BIT(31)697#define DLR_SRC_PORT_M 0x3698#define DLR_SRC_PORT_BOTH 0699#define DLR_SRC_PORT_EACH 1700 701#define REG_DLR_IP_ADDR__4 0x0608702 703#define REG_DLR_CTRL__1 0x0610704 705#define DLR_RESET_SEQ_ID BIT(3)706#define DLR_BACKUP_AUTO_ON BIT(2)707#define DLR_BEACON_TX_ENABLE BIT(1)708#define DLR_ASSIST_ENABLE BIT(0)709 710#define REG_DLR_STATE__1 0x0611711 712#define DLR_NODE_STATE_M 0x3713#define DLR_NODE_STATE_S 1714#define DLR_NODE_STATE_IDLE 0715#define DLR_NODE_STATE_FAULT 1716#define DLR_NODE_STATE_NORMAL 2717#define DLR_RING_STATE_FAULT 0718#define DLR_RING_STATE_NORMAL 1719 720#define REG_DLR_PRECEDENCE__1 0x0612721 722#define REG_DLR_BEACON_INTERVAL__4 0x0614723 724#define REG_DLR_BEACON_TIMEOUT__4 0x0618725 726#define REG_DLR_TIMEOUT_WINDOW__4 0x061C727 728#define DLR_TIMEOUT_WINDOW_M (BIT(22) - 1)729 730#define REG_DLR_VLAN_ID__2 0x0620731 732#define DLR_VLAN_ID_M (BIT(12) - 1)733 734#define REG_DLR_DEST_ADDR_0 0x0622735#define REG_DLR_DEST_ADDR_1 0x0623736#define REG_DLR_DEST_ADDR_2 0x0624737#define REG_DLR_DEST_ADDR_3 0x0625738#define REG_DLR_DEST_ADDR_4 0x0626739#define REG_DLR_DEST_ADDR_5 0x0627740 741#define REG_DLR_PORT_MAP__4 0x0628742 743#define REG_DLR_CLASS__1 0x062C744 745#define DLR_FRAME_QID_M 0x3746 747/* HSR */748#define REG_HSR_PORT_MAP__4 0x0640749 750#define REG_HSR_ALU_CTRL_0__1 0x0644751 752#define HSR_DUPLICATE_DISCARD BIT(7)753#define HSR_NODE_UNICAST BIT(6)754#define HSR_AGE_CNT_DEFAULT_M 0x7755#define HSR_AGE_CNT_DEFAULT_S 3756#define HSR_LEARN_MCAST_DISABLE BIT(2)757#define HSR_HASH_OPTION_M 0x3758#define HSR_HASH_DISABLE 0759#define HSR_HASH_UPPER_BITS 1760#define HSR_HASH_LOWER_BITS 2761#define HSR_HASH_XOR_BOTH_BITS 3762 763#define REG_HSR_ALU_CTRL_1__1 0x0645764 765#define HSR_LEARN_UCAST_DISABLE BIT(7)766#define HSR_FLUSH_TABLE BIT(5)767#define HSR_PROC_MCAST_SRC BIT(3)768#define HSR_AGING_ENABLE BIT(2)769 770#define REG_HSR_ALU_CTRL_2__2 0x0646771 772#define REG_HSR_ALU_AGE_PERIOD__4 0x0648773 774#define REG_HSR_ALU_INT_STATUS__1 0x064C775#define REG_HSR_ALU_INT_MASK__1 0x064D776 777#define HSR_WINDOW_OVERFLOW_INT BIT(3)778#define HSR_LEARN_FAIL_INT BIT(2)779#define HSR_ALMOST_FULL_INT BIT(1)780#define HSR_WRITE_FAIL_INT BIT(0)781 782#define REG_HSR_ALU_ENTRY_0__2 0x0650783 784#define HSR_ENTRY_INDEX_M (BIT(10) - 1)785#define HSR_FAIL_INDEX_M (BIT(8) - 1)786 787#define REG_HSR_ALU_ENTRY_1__2 0x0652788 789#define HSR_FAIL_LEARN_INDEX_M (BIT(8) - 1)790 791#define REG_HSR_ALU_ENTRY_3__2 0x0654792 793#define HSR_CPU_ACCESS_ENTRY_INDEX_M (BIT(8) - 1)794 795/* 0 - Operation */796#define REG_PORT_DEFAULT_VID 0x0000797 798#define REG_PORT_CUSTOM_VID 0x0002799#define REG_PORT_AVB_SR_1_VID 0x0004800#define REG_PORT_AVB_SR_2_VID 0x0006801 802#define REG_PORT_AVB_SR_1_TYPE 0x0008803#define REG_PORT_AVB_SR_2_TYPE 0x000A804 805#define REG_PORT_INT_STATUS 0x001B806#define REG_PORT_INT_MASK 0x001F807 808#define PORT_SGMII_INT BIT(3)809#define PORT_PTP_INT BIT(2)810#define PORT_PHY_INT BIT(1)811#define PORT_ACL_INT BIT(0)812 813#define PORT_INT_MASK \814 (PORT_SGMII_INT | PORT_PTP_INT | PORT_PHY_INT | PORT_ACL_INT)815 816#define REG_PORT_CTRL_0 0x0020817 818#define PORT_MAC_LOOPBACK BIT(7)819#define PORT_FORCE_TX_FLOW_CTRL BIT(4)820#define PORT_FORCE_RX_FLOW_CTRL BIT(3)821#define PORT_TAIL_TAG_ENABLE BIT(2)822#define PORT_QUEUE_SPLIT_MASK GENMASK(1, 0)823#define PORT_EIGHT_QUEUE 0x3824#define PORT_FOUR_QUEUE 0x2825#define PORT_TWO_QUEUE 0x1826#define PORT_SINGLE_QUEUE 0x0827 828#define REG_PORT_CTRL_1 0x0021829 830#define PORT_SRP_ENABLE 0x3831 832#define REG_PORT_STATUS_0 0x0030833 834#define PORT_INTF_SPEED_MASK GENMASK(4, 3)835#define PORT_INTF_SPEED_NONE GENMASK(1, 0)836#define PORT_INTF_FULL_DUPLEX BIT(2)837#define PORT_TX_FLOW_CTRL BIT(1)838#define PORT_RX_FLOW_CTRL BIT(0)839 840#define REG_PORT_STATUS_1 0x0034841 842/* 1 - PHY */843#define REG_PORT_PHY_CTRL 0x0100844 845#define PORT_PHY_RESET BIT(15)846#define PORT_PHY_LOOPBACK BIT(14)847#define PORT_SPEED_100MBIT BIT(13)848#define PORT_AUTO_NEG_ENABLE BIT(12)849#define PORT_POWER_DOWN BIT(11)850#define PORT_ISOLATE BIT(10)851#define PORT_AUTO_NEG_RESTART BIT(9)852#define PORT_FULL_DUPLEX BIT(8)853#define PORT_COLLISION_TEST BIT(7)854#define PORT_SPEED_1000MBIT BIT(6)855 856#define REG_PORT_PHY_STATUS 0x0102857 858#define PORT_100BT4_CAPABLE BIT(15)859#define PORT_100BTX_FD_CAPABLE BIT(14)860#define PORT_100BTX_CAPABLE BIT(13)861#define PORT_10BT_FD_CAPABLE BIT(12)862#define PORT_10BT_CAPABLE BIT(11)863#define PORT_EXTENDED_STATUS BIT(8)864#define PORT_MII_SUPPRESS_CAPABLE BIT(6)865#define PORT_AUTO_NEG_ACKNOWLEDGE BIT(5)866#define PORT_REMOTE_FAULT BIT(4)867#define PORT_AUTO_NEG_CAPABLE BIT(3)868#define PORT_LINK_STATUS BIT(2)869#define PORT_JABBER_DETECT BIT(1)870#define PORT_EXTENDED_CAPABILITY BIT(0)871 872#define REG_PORT_PHY_ID_HI 0x0104873#define REG_PORT_PHY_ID_LO 0x0106874 875#define KSZ9477_ID_HI 0x0022876#define KSZ9477_ID_LO 0x1622877 878#define REG_PORT_PHY_AUTO_NEGOTIATION 0x0108879 880#define PORT_AUTO_NEG_NEXT_PAGE BIT(15)881#define PORT_AUTO_NEG_REMOTE_FAULT BIT(13)882#define PORT_AUTO_NEG_ASYM_PAUSE BIT(11)883#define PORT_AUTO_NEG_SYM_PAUSE BIT(10)884#define PORT_AUTO_NEG_100BT4 BIT(9)885#define PORT_AUTO_NEG_100BTX_FD BIT(8)886#define PORT_AUTO_NEG_100BTX BIT(7)887#define PORT_AUTO_NEG_10BT_FD BIT(6)888#define PORT_AUTO_NEG_10BT BIT(5)889#define PORT_AUTO_NEG_SELECTOR 0x001F890#define PORT_AUTO_NEG_802_3 0x0001891 892#define PORT_AUTO_NEG_PAUSE \893 (PORT_AUTO_NEG_ASYM_PAUSE | PORT_AUTO_NEG_SYM_PAUSE)894 895#define REG_PORT_PHY_REMOTE_CAPABILITY 0x010A896 897#define PORT_REMOTE_NEXT_PAGE BIT(15)898#define PORT_REMOTE_ACKNOWLEDGE BIT(14)899#define PORT_REMOTE_REMOTE_FAULT BIT(13)900#define PORT_REMOTE_ASYM_PAUSE BIT(11)901#define PORT_REMOTE_SYM_PAUSE BIT(10)902#define PORT_REMOTE_100BTX_FD BIT(8)903#define PORT_REMOTE_100BTX BIT(7)904#define PORT_REMOTE_10BT_FD BIT(6)905#define PORT_REMOTE_10BT BIT(5)906 907#define REG_PORT_PHY_1000_CTRL 0x0112908 909#define PORT_AUTO_NEG_MANUAL BIT(12)910#define PORT_AUTO_NEG_MASTER BIT(11)911#define PORT_AUTO_NEG_MASTER_PREFERRED BIT(10)912#define PORT_AUTO_NEG_1000BT_FD BIT(9)913#define PORT_AUTO_NEG_1000BT BIT(8)914 915#define REG_PORT_PHY_1000_STATUS 0x0114916 917#define PORT_MASTER_FAULT BIT(15)918#define PORT_LOCAL_MASTER BIT(14)919#define PORT_LOCAL_RX_OK BIT(13)920#define PORT_REMOTE_RX_OK BIT(12)921#define PORT_REMOTE_1000BT_FD BIT(11)922#define PORT_REMOTE_1000BT BIT(10)923#define PORT_REMOTE_IDLE_CNT_M 0x0F924 925#define PORT_PHY_1000_STATIC_STATUS \926 (PORT_LOCAL_RX_OK | \927 PORT_REMOTE_RX_OK | \928 PORT_REMOTE_1000BT_FD | \929 PORT_REMOTE_1000BT)930 931#define REG_PORT_PHY_MMD_SETUP 0x011A932 933#define PORT_MMD_OP_MODE_M 0x3934#define PORT_MMD_OP_MODE_S 14935#define PORT_MMD_OP_INDEX 0936#define PORT_MMD_OP_DATA_NO_INCR 1937#define PORT_MMD_OP_DATA_INCR_RW 2938#define PORT_MMD_OP_DATA_INCR_W 3939#define PORT_MMD_DEVICE_ID_M 0x1F940 941#define MMD_SETUP(mode, dev) \942 (((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev))943 944#define REG_PORT_PHY_MMD_INDEX_DATA 0x011C945 946#define MMD_DEVICE_ID_DSP 1947 948#define MMD_DSP_SQI_CHAN_A 0xAC949#define MMD_DSP_SQI_CHAN_B 0xAD950#define MMD_DSP_SQI_CHAN_C 0xAE951#define MMD_DSP_SQI_CHAN_D 0xAF952 953#define DSP_SQI_ERR_DETECTED BIT(15)954#define DSP_SQI_AVG_ERR 0x7FFF955 956#define MMD_DEVICE_ID_COMMON 2957 958#define MMD_DEVICE_ID_EEE_ADV 7959 960#define MMD_EEE_ADV 0x3C961#define EEE_ADV_100MBIT BIT(1)962#define EEE_ADV_1GBIT BIT(2)963 964#define MMD_EEE_LP_ADV 0x3D965#define MMD_EEE_MSG_CODE 0x3F966 967#define MMD_DEVICE_ID_AFED 0x1C968 969#define REG_PORT_PHY_EXTENDED_STATUS 0x011E970 971#define PORT_100BTX_FD_ABLE BIT(15)972#define PORT_100BTX_ABLE BIT(14)973#define PORT_10BT_FD_ABLE BIT(13)974#define PORT_10BT_ABLE BIT(12)975 976#define REG_PORT_SGMII_ADDR__4 0x0200977#define PORT_SGMII_AUTO_INCR BIT(23)978#define PORT_SGMII_DEVICE_ID_M 0x1F979#define PORT_SGMII_DEVICE_ID_S 16980#define PORT_SGMII_ADDR_M (BIT(21) - 1)981 982#define REG_PORT_SGMII_DATA__4 0x0204983#define PORT_SGMII_DATA_M (BIT(16) - 1)984 985#define MMD_DEVICE_ID_PMA 0x01986#define MMD_DEVICE_ID_PCS 0x03987#define MMD_DEVICE_ID_PHY_XS 0x04988#define MMD_DEVICE_ID_DTE_XS 0x05989#define MMD_DEVICE_ID_AN 0x07990#define MMD_DEVICE_ID_VENDOR_CTRL 0x1E991#define MMD_DEVICE_ID_VENDOR_MII 0x1F992 993#define SR_MII MMD_DEVICE_ID_VENDOR_MII994 995#define MMD_SR_MII_CTRL 0x0000996 997#define SR_MII_RESET BIT(15)998#define SR_MII_LOOPBACK BIT(14)999#define SR_MII_SPEED_100MBIT BIT(13)1000#define SR_MII_AUTO_NEG_ENABLE BIT(12)1001#define SR_MII_POWER_DOWN BIT(11)1002#define SR_MII_AUTO_NEG_RESTART BIT(9)1003#define SR_MII_FULL_DUPLEX BIT(8)1004#define SR_MII_SPEED_1000MBIT BIT(6)1005 1006#define MMD_SR_MII_STATUS 0x00011007#define MMD_SR_MII_ID_1 0x00021008#define MMD_SR_MII_ID_2 0x00031009#define MMD_SR_MII_AUTO_NEGOTIATION 0x00041010 1011#define SR_MII_AUTO_NEG_NEXT_PAGE BIT(15)1012#define SR_MII_AUTO_NEG_REMOTE_FAULT_M 0x31013#define SR_MII_AUTO_NEG_REMOTE_FAULT_S 121014#define SR_MII_AUTO_NEG_NO_ERROR 01015#define SR_MII_AUTO_NEG_OFFLINE 11016#define SR_MII_AUTO_NEG_LINK_FAILURE 21017#define SR_MII_AUTO_NEG_ERROR 31018#define SR_MII_AUTO_NEG_PAUSE_M 0x31019#define SR_MII_AUTO_NEG_PAUSE_S 71020#define SR_MII_AUTO_NEG_NO_PAUSE 01021#define SR_MII_AUTO_NEG_ASYM_PAUSE_TX 11022#define SR_MII_AUTO_NEG_SYM_PAUSE 21023#define SR_MII_AUTO_NEG_ASYM_PAUSE_RX 31024#define SR_MII_AUTO_NEG_HALF_DUPLEX BIT(6)1025#define SR_MII_AUTO_NEG_FULL_DUPLEX BIT(5)1026 1027#define MMD_SR_MII_REMOTE_CAPABILITY 0x00051028#define MMD_SR_MII_AUTO_NEG_EXP 0x00061029#define MMD_SR_MII_AUTO_NEG_EXT 0x000F1030 1031#define MMD_SR_MII_DIGITAL_CTRL_1 0x80001032 1033#define MMD_SR_MII_AUTO_NEG_CTRL 0x80011034 1035#define SR_MII_8_BIT BIT(8)1036#define SR_MII_SGMII_LINK_UP BIT(4)1037#define SR_MII_TX_CFG_PHY_MASTER BIT(3)1038#define SR_MII_PCS_MODE_M 0x31039#define SR_MII_PCS_MODE_S 11040#define SR_MII_PCS_SGMII 21041#define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0)1042 1043#define MMD_SR_MII_AUTO_NEG_STATUS 0x80021044 1045#define SR_MII_STAT_LINK_UP BIT(4)1046#define SR_MII_STAT_M 0x31047#define SR_MII_STAT_S 21048#define SR_MII_STAT_10_MBPS 01049#define SR_MII_STAT_100_MBPS 11050#define SR_MII_STAT_1000_MBPS 21051#define SR_MII_STAT_FULL_DUPLEX BIT(1)1052 1053#define MMD_SR_MII_PHY_CTRL 0x80A01054 1055#define SR_MII_PHY_LANE_SEL_M 0xF1056#define SR_MII_PHY_LANE_SEL_S 81057#define SR_MII_PHY_WRITE BIT(1)1058#define SR_MII_PHY_START_BUSY BIT(0)1059 1060#define MMD_SR_MII_PHY_ADDR 0x80A11061 1062#define SR_MII_PHY_ADDR_M (BIT(16) - 1)1063 1064#define MMD_SR_MII_PHY_DATA 0x80A21065 1066#define SR_MII_PHY_DATA_M (BIT(16) - 1)1067 1068#define SR_MII_PHY_JTAG_CHIP_ID_HI 0x000C1069#define SR_MII_PHY_JTAG_CHIP_ID_LO 0x000D1070 1071#define REG_PORT_PHY_REMOTE_LB_LED 0x01221072 1073#define PORT_REMOTE_LOOPBACK BIT(8)1074#define PORT_LED_SELECT (3 << 6)1075#define PORT_LED_CTRL (3 << 4)1076#define PORT_LED_CTRL_TEST BIT(3)1077#define PORT_10BT_PREAMBLE BIT(2)1078#define PORT_LINK_MD_10BT_ENABLE BIT(1)1079#define PORT_LINK_MD_PASS BIT(0)1080 1081#define REG_PORT_PHY_LINK_MD 0x01241082 1083#define PORT_START_CABLE_DIAG BIT(15)1084#define PORT_TX_DISABLE BIT(14)1085#define PORT_CABLE_DIAG_PAIR_M 0x31086#define PORT_CABLE_DIAG_PAIR_S 121087#define PORT_CABLE_DIAG_SELECT_M 0x31088#define PORT_CABLE_DIAG_SELECT_S 101089#define PORT_CABLE_DIAG_RESULT_M 0x31090#define PORT_CABLE_DIAG_RESULT_S 81091#define PORT_CABLE_STAT_NORMAL 01092#define PORT_CABLE_STAT_OPEN 11093#define PORT_CABLE_STAT_SHORT 21094#define PORT_CABLE_STAT_FAILED 31095#define PORT_CABLE_FAULT_COUNTER 0x00FF1096 1097#define REG_PORT_PHY_PMA_STATUS 0x01261098 1099#define PORT_1000_LINK_GOOD BIT(1)1100#define PORT_100_LINK_GOOD BIT(0)1101 1102#define REG_PORT_PHY_DIGITAL_STATUS 0x01281103 1104#define PORT_LINK_DETECT BIT(14)1105#define PORT_SIGNAL_DETECT BIT(13)1106#define PORT_PHY_STAT_MDI BIT(12)1107#define PORT_PHY_STAT_MASTER BIT(11)1108 1109#define REG_PORT_PHY_RXER_COUNTER 0x012A1110 1111#define REG_PORT_PHY_INT_ENABLE 0x01361112#define REG_PORT_PHY_INT_STATUS 0x01371113 1114#define JABBER_INT BIT(7)1115#define RX_ERR_INT BIT(6)1116#define PAGE_RX_INT BIT(5)1117#define PARALLEL_DETECT_FAULT_INT BIT(4)1118#define LINK_PARTNER_ACK_INT BIT(3)1119#define LINK_DOWN_INT BIT(2)1120#define REMOTE_FAULT_INT BIT(1)1121#define LINK_UP_INT BIT(0)1122 1123#define REG_PORT_PHY_DIGITAL_DEBUG_1 0x01381124 1125#define PORT_REG_CLK_SPEED_25_MHZ BIT(14)1126#define PORT_PHY_FORCE_MDI BIT(7)1127#define PORT_PHY_AUTO_MDIX_DISABLE BIT(6)1128 1129/* Same as PORT_PHY_LOOPBACK */1130#define PORT_PHY_PCS_LOOPBACK BIT(0)1131 1132#define REG_PORT_PHY_DIGITAL_DEBUG_2 0x013A1133 1134#define REG_PORT_PHY_DIGITAL_DEBUG_3 0x013C1135 1136#define PORT_100BT_FIXED_LATENCY BIT(15)1137 1138#define REG_PORT_PHY_PHY_CTRL 0x013E1139 1140#define PORT_INT_PIN_HIGH BIT(14)1141#define PORT_ENABLE_JABBER BIT(9)1142#define PORT_STAT_SPEED_1000MBIT BIT(6)1143#define PORT_STAT_SPEED_100MBIT BIT(5)1144#define PORT_STAT_SPEED_10MBIT BIT(4)1145#define PORT_STAT_FULL_DUPLEX BIT(3)1146 1147/* Same as PORT_PHY_STAT_MASTER */1148#define PORT_STAT_MASTER BIT(2)1149#define PORT_RESET BIT(1)1150#define PORT_LINK_STATUS_FAIL BIT(0)1151 1152/* 3 - xMII */1153#define PORT_SGMII_SEL BIT(7)1154#define PORT_GRXC_ENABLE BIT(0)1155 1156#define PORT_RMII_CLK_SEL BIT(7)1157#define PORT_MII_SEL_EDGE BIT(5)1158 1159#define REG_PMAVBC 0x03AC1160 1161#define PMAVBC_MASK GENMASK(26, 16)1162#define PMAVBC_MIN 0x5801163 1164/* 4 - MAC */1165#define REG_PORT_MAC_CTRL_0 0x04001166 1167#define PORT_BROADCAST_STORM BIT(1)1168#define PORT_JUMBO_FRAME BIT(0)1169 1170#define REG_PORT_MAC_CTRL_1 0x04011171 1172#define PORT_BACK_PRESSURE BIT(3)1173#define PORT_PASS_ALL BIT(0)1174 1175#define REG_PORT_MAC_CTRL_2 0x04021176 1177#define PORT_100BT_EEE_DISABLE BIT(7)1178#define PORT_1000BT_EEE_DISABLE BIT(6)1179 1180#define REG_PORT_MAC_IN_RATE_LIMIT 0x04031181 1182#define PORT_IN_PORT_BASED_S 61183#define PORT_RATE_PACKET_BASED_S 51184#define PORT_IN_FLOW_CTRL_S 41185#define PORT_COUNT_IFG_S 11186#define PORT_COUNT_PREAMBLE_S 01187#define PORT_IN_PORT_BASED BIT(6)1188#define PORT_IN_PACKET_BASED BIT(5)1189#define PORT_IN_FLOW_CTRL BIT(4)1190#define PORT_IN_LIMIT_MODE_M 0x31191#define PORT_IN_LIMIT_MODE_S 21192#define PORT_IN_ALL 01193#define PORT_IN_UNICAST 11194#define PORT_IN_MULTICAST 21195#define PORT_IN_BROADCAST 31196#define PORT_COUNT_IFG BIT(1)1197#define PORT_COUNT_PREAMBLE BIT(0)1198 1199#define REG_PORT_IN_RATE_0 0x04101200#define REG_PORT_IN_RATE_1 0x04111201#define REG_PORT_IN_RATE_2 0x04121202#define REG_PORT_IN_RATE_3 0x04131203#define REG_PORT_IN_RATE_4 0x04141204#define REG_PORT_IN_RATE_5 0x04151205#define REG_PORT_IN_RATE_6 0x04161206#define REG_PORT_IN_RATE_7 0x04171207 1208#define REG_PORT_OUT_RATE_0 0x04201209#define REG_PORT_OUT_RATE_1 0x04211210#define REG_PORT_OUT_RATE_2 0x04221211#define REG_PORT_OUT_RATE_3 0x04231212 1213#define PORT_RATE_LIMIT_M (BIT(7) - 1)1214 1215/* 5 - MIB Counters */1216#define REG_PORT_MIB_CTRL_STAT__4 0x05001217 1218#define MIB_COUNTER_READ BIT(25)1219#define MIB_COUNTER_FLUSH_FREEZE BIT(24)1220#define MIB_COUNTER_INDEX_M (BIT(8) - 1)1221#define MIB_COUNTER_INDEX_S 161222#define MIB_COUNTER_DATA_HI_M 0xF1223 1224#define REG_PORT_MIB_DATA 0x05041225 1226/* 6 - ACL */1227#define REG_PORT_ACL_0 0x06001228 1229#define ACL_FIRST_RULE_M 0xF1230 1231#define REG_PORT_ACL_1 0x06011232 1233#define ACL_MODE_M 0x31234#define ACL_MODE_S 41235#define ACL_MODE_DISABLE 01236#define ACL_MODE_LAYER_2 11237#define ACL_MODE_LAYER_3 21238#define ACL_MODE_LAYER_4 31239#define ACL_ENABLE_M 0x31240#define ACL_ENABLE_S 21241#define ACL_ENABLE_2_COUNT 01242#define ACL_ENABLE_2_TYPE 11243#define ACL_ENABLE_2_MAC 21244#define ACL_ENABLE_2_BOTH 31245#define ACL_ENABLE_3_IP 11246#define ACL_ENABLE_3_SRC_DST_COMP 21247#define ACL_ENABLE_4_PROTOCOL 01248#define ACL_ENABLE_4_TCP_PORT_COMP 11249#define ACL_ENABLE_4_UDP_PORT_COMP 21250#define ACL_ENABLE_4_TCP_SEQN_COMP 31251#define ACL_SRC BIT(1)1252#define ACL_EQUAL BIT(0)1253 1254#define REG_PORT_ACL_2 0x06021255#define REG_PORT_ACL_3 0x06031256 1257#define ACL_MAX_PORT 0xFFFF1258 1259#define REG_PORT_ACL_4 0x06041260#define REG_PORT_ACL_5 0x06051261 1262#define ACL_MIN_PORT 0xFFFF1263#define ACL_IP_ADDR 0xFFFFFFFF1264#define ACL_TCP_SEQNUM 0xFFFFFFFF1265 1266#define REG_PORT_ACL_6 0x06061267 1268#define ACL_RESERVED 0xF81269#define ACL_PORT_MODE_M 0x31270#define ACL_PORT_MODE_S 11271#define ACL_PORT_MODE_DISABLE 01272#define ACL_PORT_MODE_EITHER 11273#define ACL_PORT_MODE_IN_RANGE 21274#define ACL_PORT_MODE_OUT_OF_RANGE 31275 1276#define REG_PORT_ACL_7 0x06071277 1278#define ACL_TCP_FLAG_ENABLE BIT(0)1279 1280#define REG_PORT_ACL_8 0x06081281 1282#define ACL_TCP_FLAG_M 0xFF1283 1284#define REG_PORT_ACL_9 0x06091285 1286#define ACL_TCP_FLAG 0xFF1287#define ACL_ETH_TYPE 0xFFFF1288#define ACL_IP_M 0xFFFFFFFF1289 1290#define REG_PORT_ACL_A 0x060A1291 1292#define ACL_PRIO_MODE_M 0x31293#define ACL_PRIO_MODE_S 61294#define ACL_PRIO_MODE_DISABLE 01295#define ACL_PRIO_MODE_HIGHER 11296#define ACL_PRIO_MODE_LOWER 21297#define ACL_PRIO_MODE_REPLACE 31298#define ACL_PRIO_M KS_PRIO_M1299#define ACL_PRIO_S 31300#define ACL_VLAN_PRIO_REPLACE BIT(2)1301#define ACL_VLAN_PRIO_M KS_PRIO_M1302#define ACL_VLAN_PRIO_HI_M 0x31303 1304#define REG_PORT_ACL_B 0x060B1305 1306#define ACL_VLAN_PRIO_LO_M 0x81307#define ACL_VLAN_PRIO_S 71308#define ACL_MAP_MODE_M 0x31309#define ACL_MAP_MODE_S 51310#define ACL_MAP_MODE_DISABLE 01311#define ACL_MAP_MODE_OR 11312#define ACL_MAP_MODE_AND 21313#define ACL_MAP_MODE_REPLACE 31314 1315#define ACL_CNT_M (BIT(11) - 1)1316#define ACL_CNT_S 51317 1318#define REG_PORT_ACL_C 0x060C1319 1320#define REG_PORT_ACL_D 0x060D1321#define ACL_MSEC_UNIT BIT(6)1322#define ACL_INTR_MODE BIT(5)1323#define ACL_PORT_MAP 0x7F1324 1325#define REG_PORT_ACL_E 0x060E1326#define REG_PORT_ACL_F 0x060F1327 1328#define REG_PORT_ACL_BYTE_EN_MSB 0x06101329#define REG_PORT_ACL_BYTE_EN_LSB 0x06111330 1331#define ACL_ACTION_START 0xA1332#define ACL_ACTION_LEN 41333#define ACL_INTR_CNT_START 0xD1334#define ACL_RULESET_START 0xE1335#define ACL_RULESET_LEN 21336#define ACL_TABLE_LEN 161337 1338#define ACL_ACTION_ENABLE 0x003C1339#define ACL_MATCH_ENABLE 0x7FC31340#define ACL_RULESET_ENABLE 0x80031341#define ACL_BYTE_ENABLE 0xFFFF1342 1343#define REG_PORT_ACL_CTRL_0 0x06121344 1345#define PORT_ACL_WRITE_DONE BIT(6)1346#define PORT_ACL_READ_DONE BIT(5)1347#define PORT_ACL_WRITE BIT(4)1348#define PORT_ACL_INDEX_M 0xF1349 1350#define REG_PORT_ACL_CTRL_1 0x06131351 1352/* 8 - Classification and Policing */1353#define REG_PORT_MRI_MIRROR_CTRL 0x08001354 1355#define PORT_MIRROR_RX BIT(6)1356#define PORT_MIRROR_TX BIT(5)1357#define PORT_MIRROR_SNIFFER BIT(1)1358 1359#define REG_PORT_MRI_PRIO_CTRL 0x08011360 1361#define PORT_HIGHEST_PRIO BIT(7)1362#define PORT_OR_PRIO BIT(6)1363#define PORT_MAC_PRIO_ENABLE BIT(4)1364#define PORT_VLAN_PRIO_ENABLE BIT(3)1365#define PORT_802_1P_PRIO_ENABLE BIT(2)1366#define PORT_DIFFSERV_PRIO_ENABLE BIT(1)1367#define PORT_ACL_PRIO_ENABLE BIT(0)1368 1369#define REG_PORT_MRI_MAC_CTRL 0x08021370 1371#define PORT_USER_PRIO_CEILING BIT(7)1372#define PORT_DROP_NON_VLAN BIT(4)1373#define PORT_DROP_TAG BIT(3)1374#define PORT_BASED_PRIO_M KS_PRIO_M1375#define PORT_BASED_PRIO_S 01376 1377#define REG_PORT_MRI_AUTHEN_CTRL 0x08031378 1379#define PORT_ACL_ENABLE BIT(2)1380#define PORT_AUTHEN_MODE 0x31381#define PORT_AUTHEN_PASS 01382#define PORT_AUTHEN_BLOCK 11383#define PORT_AUTHEN_TRAP 21384 1385#define REG_PORT_MRI_INDEX__4 0x08041386 1387#define MRI_INDEX_P_M 0x71388#define MRI_INDEX_P_S 161389#define MRI_INDEX_Q_M 0x31390#define MRI_INDEX_Q_S 01391 1392#define REG_PORT_MRI_TC_MAP__4 0x08081393 1394#define PORT_TC_MAP_M 0xf1395#define PORT_TC_MAP_S 41396 1397#define REG_PORT_MRI_POLICE_CTRL__4 0x080C1398 1399#define POLICE_DROP_ALL BIT(10)1400#define POLICE_PACKET_TYPE_M 0x31401#define POLICE_PACKET_TYPE_S 81402#define POLICE_PACKET_DROPPED 01403#define POLICE_PACKET_GREEN 11404#define POLICE_PACKET_YELLOW 21405#define POLICE_PACKET_RED 31406#define PORT_BASED_POLICING BIT(7)1407#define NON_DSCP_COLOR_M 0x31408#define NON_DSCP_COLOR_S 51409#define COLOR_MARK_ENABLE BIT(4)1410#define COLOR_REMAP_ENABLE BIT(3)1411#define POLICE_DROP_SRP BIT(2)1412#define POLICE_COLOR_NOT_AWARE BIT(1)1413#define POLICE_ENABLE BIT(0)1414 1415#define REG_PORT_POLICE_COLOR_0__4 0x08101416#define REG_PORT_POLICE_COLOR_1__4 0x08141417#define REG_PORT_POLICE_COLOR_2__4 0x08181418#define REG_PORT_POLICE_COLOR_3__4 0x081C1419 1420#define POLICE_COLOR_MAP_S 21421#define POLICE_COLOR_MAP_M (BIT(POLICE_COLOR_MAP_S) - 1)1422 1423#define REG_PORT_POLICE_RATE__4 0x08201424 1425#define POLICE_CIR_S 161426#define POLICE_PIR_S 01427 1428#define REG_PORT_POLICE_BURST_SIZE__4 0x08241429 1430#define POLICE_BURST_SIZE_M 0x3FFF1431#define POLICE_CBS_S 161432#define POLICE_PBS_S 01433 1434#define REG_PORT_WRED_PM_CTRL_0__4 0x08301435 1436#define WRED_PM_CTRL_M (BIT(11) - 1)1437 1438#define WRED_PM_MAX_THRESHOLD_S 161439#define WRED_PM_MIN_THRESHOLD_S 01440 1441#define REG_PORT_WRED_PM_CTRL_1__4 0x08341442 1443#define WRED_PM_MULTIPLIER_S 161444#define WRED_PM_AVG_QUEUE_SIZE_S 01445 1446#define REG_PORT_WRED_QUEUE_CTRL_0__4 0x08401447#define REG_PORT_WRED_QUEUE_CTRL_1__4 0x08441448 1449#define REG_PORT_WRED_QUEUE_PMON__4 0x08481450 1451#define WRED_RANDOM_DROP_ENABLE BIT(31)1452#define WRED_PMON_FLUSH BIT(30)1453#define WRED_DROP_GYR_DISABLE BIT(29)1454#define WRED_DROP_YR_DISABLE BIT(28)1455#define WRED_DROP_R_DISABLE BIT(27)1456#define WRED_DROP_ALL BIT(26)1457#define WRED_PMON_M (BIT(24) - 1)1458 1459/* 9 - Shaping */1460 1461#define REG_PORT_MTI_QUEUE_CTRL_0__4 0x09041462 1463#define MTI_PVID_REPLACE BIT(0)1464 1465#define REG_PORT_MTI_CREDIT_INCREMENT 0x091A1466 1467/* A - QM */1468 1469#define REG_PORT_QM_CTRL__4 0x0A001470 1471#define PORT_QM_DROP_PRIO_M 0x31472 1473#define REG_PORT_VLAN_MEMBERSHIP__4 0x0A041474 1475#define REG_PORT_QM_QUEUE_INDEX__4 0x0A081476 1477#define PORT_QM_QUEUE_INDEX_S 241478#define PORT_QM_BURST_SIZE_S 161479#define PORT_QM_MIN_RESV_SPACE_M (BIT(11) - 1)1480 1481#define REG_PORT_QM_WATER_MARK__4 0x0A0C1482 1483#define PORT_QM_HI_WATER_MARK_S 161484#define PORT_QM_LO_WATER_MARK_S 01485#define PORT_QM_WATER_MARK_M (BIT(11) - 1)1486 1487#define REG_PORT_QM_TX_CNT_0__4 0x0A101488 1489#define PORT_QM_TX_CNT_USED_S 01490#define PORT_QM_TX_CNT_M (BIT(11) - 1)1491#define PORT_QM_TX_CNT_MAX 0x2001492 1493#define REG_PORT_QM_TX_CNT_1__4 0x0A141494 1495#define PORT_QM_TX_CNT_CALCULATED_S 161496#define PORT_QM_TX_CNT_AVAIL_S 01497 1498/* B - LUE */1499#define REG_PORT_LUE_CTRL 0x0B001500 1501#define PORT_VLAN_LOOKUP_VID_0 BIT(7)1502#define PORT_INGRESS_FILTER BIT(6)1503#define PORT_DISCARD_NON_VID BIT(5)1504#define PORT_MAC_BASED_802_1X BIT(4)1505#define PORT_SRC_ADDR_FILTER BIT(3)1506 1507#define REG_PORT_LUE_MSTP_INDEX 0x0B011508 1509#define REG_PORT_LUE_MSTP_STATE 0x0B041510 1511/* C - PTP */1512 1513#define REG_PTP_PORT_RX_DELAY__2 0x0C001514#define REG_PTP_PORT_TX_DELAY__2 0x0C021515#define REG_PTP_PORT_ASYM_DELAY__2 0x0C041516 1517#define REG_PTP_PORT_XDELAY_TS 0x0C081518#define REG_PTP_PORT_XDELAY_TS_H 0x0C081519#define REG_PTP_PORT_XDELAY_TS_L 0x0C0A1520 1521#define REG_PTP_PORT_SYNC_TS 0x0C0C1522#define REG_PTP_PORT_SYNC_TS_H 0x0C0C1523#define REG_PTP_PORT_SYNC_TS_L 0x0C0E1524 1525#define REG_PTP_PORT_PDRESP_TS 0x0C101526#define REG_PTP_PORT_PDRESP_TS_H 0x0C101527#define REG_PTP_PORT_PDRESP_TS_L 0x0C121528 1529#define REG_PTP_PORT_TX_INT_STATUS__2 0x0C141530#define REG_PTP_PORT_TX_INT_ENABLE__2 0x0C161531 1532#define PTP_PORT_SYNC_INT BIT(15)1533#define PTP_PORT_XDELAY_REQ_INT BIT(14)1534#define PTP_PORT_PDELAY_RESP_INT BIT(13)1535 1536#define REG_PTP_PORT_LINK_DELAY__4 0x0C181537 1538#define PRIO_QUEUES 41539#define RX_PRIO_QUEUES 81540 1541#define KS_PRIO_IN_REG 21542 1543#define TOTAL_PORT_NUM 71544 1545#define KSZ9477_COUNTER_NUM 0x201546#define TOTAL_KSZ9477_COUNTER_NUM (KSZ9477_COUNTER_NUM + 2 + 2)1547 1548#define SWITCH_COUNTER_NUM KSZ9477_COUNTER_NUM1549#define TOTAL_SWITCH_COUNTER_NUM TOTAL_KSZ9477_COUNTER_NUM1550 1551#define P_BCAST_STORM_CTRL REG_PORT_MAC_CTRL_01552#define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL1553#define P_MIRROR_CTRL REG_PORT_MRI_MIRROR_CTRL1554#define P_PHY_CTRL REG_PORT_PHY_CTRL1555#define P_RATE_LIMIT_CTRL REG_PORT_MAC_IN_RATE_LIMIT1556 1557#define S_LINK_AGING_CTRL REG_SW_LUE_CTRL_11558#define S_MIRROR_CTRL REG_SW_MRI_CTRL_01559#define S_REPLACE_VID_CTRL REG_SW_MAC_CTRL_21560#define S_802_1P_PRIO_CTRL REG_SW_MAC_802_1P_MAP_01561#define S_TOS_PRIO_CTRL REG_SW_MAC_TOS_PRIO_01562#define S_FLUSH_TABLE_CTRL REG_SW_LUE_CTRL_11563 1564#define SW_FLUSH_DYN_MAC_TABLE SW_FLUSH_MSTP_TABLE1565 1566#define MAX_TIMESTAMP_UNIT 21567#define MAX_TRIG_UNIT 31568#define MAX_TIMESTAMP_EVENT_UNIT 81569#define MAX_GPIO 41570 1571#define PTP_TRIG_UNIT_M (BIT(MAX_TRIG_UNIT) - 1)1572#define PTP_TS_UNIT_M (BIT(MAX_TIMESTAMP_UNIT) - 1)1573 1574#endif /* KSZ9477_REGS_H */1575