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1/* SPDX-License-Identifier: GPL-2.0 */2/* Microchip LAN937X switch register definitions3 * Copyright (C) 2019-2021 Microchip Technology Inc.4 */5#ifndef __LAN937X_REG_H6#define __LAN937X_REG_H7 8#define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12))9 10/* 0 - Operation */11#define REG_GLOBAL_CTRL_0 0x000712 13#define SW_PHY_REG_BLOCK BIT(7)14#define SW_FAST_MODE BIT(3)15#define SW_FAST_MODE_OVERRIDE BIT(2)16 17#define REG_SW_INT_STATUS__4 0x001018#define REG_SW_INT_MASK__4 0x001419 20#define LUE_INT BIT(31)21#define TRIG_TS_INT BIT(30)22#define APB_TIMEOUT_INT BIT(29)23#define OVER_TEMP_INT BIT(28)24#define HSR_INT BIT(27)25#define PIO_INT BIT(26)26#define POR_READY_INT BIT(25)27 28#define SWITCH_INT_MASK \29 (LUE_INT | TRIG_TS_INT | APB_TIMEOUT_INT | OVER_TEMP_INT | HSR_INT | \30 PIO_INT | POR_READY_INT)31 32#define REG_SW_PORT_INT_STATUS__4 0x001833#define REG_SW_PORT_INT_MASK__4 0x001C34 35/* 1 - Global */36#define REG_SW_GLOBAL_OUTPUT_CTRL__1 0x010337#define SW_CLK125_ENB BIT(1)38#define SW_CLK25_ENB BIT(0)39 40/* 2 - PHY Control */41#define REG_SW_CFG_STRAP_OVR 0x021442#define SW_VPHY_DISABLE BIT(31)43 44/* 3 - Operation Control */45#define REG_SW_OPERATION 0x030046 47#define SW_DOUBLE_TAG BIT(7)48#define SW_OVER_TEMP_ENABLE BIT(2)49#define SW_RESET BIT(1)50 51#define REG_SW_LUE_CTRL_0 0x031052 53#define SW_VLAN_ENABLE BIT(7)54#define SW_DROP_INVALID_VID BIT(6)55#define SW_AGE_CNT_M 0x756#define SW_AGE_CNT_S 357#define SW_RESV_MCAST_ENABLE BIT(2)58 59#define REG_SW_LUE_CTRL_1 0x031160 61#define UNICAST_LEARN_DISABLE BIT(7)62#define SW_FLUSH_STP_TABLE BIT(5)63#define SW_FLUSH_MSTP_TABLE BIT(4)64#define SW_SRC_ADDR_FILTER BIT(3)65#define SW_AGING_ENABLE BIT(2)66#define SW_FAST_AGING BIT(1)67#define SW_LINK_AUTO_AGING BIT(0)68 69#define REG_SW_AGE_PERIOD__1 0x031370#define SW_AGE_PERIOD_7_0_M GENMASK(7, 0)71 72#define REG_SW_AGE_PERIOD__2 0x032073#define SW_AGE_PERIOD_19_8_M GENMASK(19, 8)74 75#define REG_SW_MAC_CTRL_0 0x033076#define SW_NEW_BACKOFF BIT(7)77#define SW_PAUSE_UNH_MODE BIT(1)78#define SW_AGGR_BACKOFF BIT(0)79 80#define REG_SW_MAC_CTRL_1 0x033181#define SW_SHORT_IFG BIT(7)82#define MULTICAST_STORM_DISABLE BIT(6)83#define SW_BACK_PRESSURE BIT(5)84#define FAIR_FLOW_CTRL BIT(4)85#define NO_EXC_COLLISION_DROP BIT(3)86#define SW_LEGAL_PACKET_DISABLE BIT(1)87#define SW_PASS_SHORT_FRAME BIT(0)88 89#define REG_SW_MAC_CTRL_6 0x033690#define SW_MIB_COUNTER_FLUSH BIT(7)91#define SW_MIB_COUNTER_FREEZE BIT(6)92 93/* 4 - LUE */94#define REG_SW_ALU_STAT_CTRL__4 0x041C95 96#define REG_SW_ALU_VAL_B 0x042497#define ALU_V_OVERRIDE BIT(31)98#define ALU_V_USE_FID BIT(30)99#define ALU_V_PORT_MAP 0xFF100 101/* 7 - VPhy */102#define REG_VPHY_IND_ADDR__2 0x075C103#define REG_VPHY_IND_DATA__2 0x0760104 105#define REG_VPHY_IND_CTRL__2 0x0768106 107#define VPHY_IND_WRITE BIT(1)108#define VPHY_IND_BUSY BIT(0)109 110#define REG_VPHY_SPECIAL_CTRL__2 0x077C111#define VPHY_SMI_INDIRECT_ENABLE BIT(15)112#define VPHY_SW_LOOPBACK BIT(14)113#define VPHY_MDIO_INTERNAL_ENABLE BIT(13)114#define VPHY_SPI_INDIRECT_ENABLE BIT(12)115#define VPHY_PORT_MODE_M 0x3116#define VPHY_PORT_MODE_S 8117#define VPHY_MODE_RGMII 0118#define VPHY_MODE_MII_PHY 1119#define VPHY_MODE_SGMII 2120#define VPHY_MODE_RMII_PHY 3121#define VPHY_SW_COLLISION_TEST BIT(7)122#define VPHY_SPEED_DUPLEX_STAT_M 0x7123#define VPHY_SPEED_DUPLEX_STAT_S 2124#define VPHY_SPEED_1000 BIT(4)125#define VPHY_SPEED_100 BIT(3)126#define VPHY_FULL_DUPLEX BIT(2)127 128/* Port Registers */129 130/* 0 - Operation */131#define REG_PORT_INT_STATUS 0x001B132#define REG_PORT_INT_MASK 0x001F133 134#define PORT_TAS_INT BIT(5)135#define PORT_QCI_INT BIT(4)136#define PORT_SGMII_INT BIT(3)137#define PORT_PTP_INT BIT(2)138#define PORT_PHY_INT BIT(1)139#define PORT_ACL_INT BIT(0)140 141#define PORT_SRC_PHY_INT 1142 143#define REG_PORT_CTRL_0 0x0020144 145#define PORT_MAC_LOOPBACK BIT(7)146#define PORT_MAC_REMOTE_LOOPBACK BIT(6)147#define PORT_K2L_INSERT_ENABLE BIT(5)148#define PORT_K2L_DEBUG_ENABLE BIT(4)149#define PORT_TAIL_TAG_ENABLE BIT(2)150#define PORT_QUEUE_SPLIT_ENABLE 0x3151 152/* 1 - Phy */153#define REG_PORT_T1_PHY_CTRL_BASE 0x0100154#define REG_PORT_TX_PHY_CTRL_BASE 0x0280155 156/* 3 - xMII */157#define PORT_SGMII_SEL BIT(7)158#define PORT_GRXC_ENABLE BIT(0)159 160#define PORT_MII_SEL_EDGE BIT(5)161 162#define REG_PORT_XMII_CTRL_4 0x0304163#define REG_PORT_XMII_CTRL_5 0x0306164 165#define PORT_DLL_RESET BIT(15)166#define PORT_TUNE_ADJ GENMASK(13, 7)167 168/* 4 - MAC */169#define REG_PORT_MAC_CTRL_0 0x0400170#define PORT_CHECK_LENGTH BIT(2)171#define PORT_BROADCAST_STORM BIT(1)172#define PORT_JUMBO_PACKET BIT(0)173 174#define REG_PORT_MAC_CTRL_1 0x0401175#define PORT_BACK_PRESSURE BIT(3)176#define PORT_PASS_ALL BIT(0)177 178#define PORT_MAX_FR_SIZE 0x404179#define FR_MIN_SIZE 1522180 181/* 8 - Classification and Policing */182#define REG_PORT_MRI_PRIO_CTRL 0x0801183#define PORT_HIGHEST_PRIO BIT(7)184#define PORT_OR_PRIO BIT(6)185#define PORT_MAC_PRIO_ENABLE BIT(4)186#define PORT_VLAN_PRIO_ENABLE BIT(3)187#define PORT_802_1P_PRIO_ENABLE BIT(2)188#define PORT_DIFFSERV_PRIO_ENABLE BIT(1)189#define PORT_ACL_PRIO_ENABLE BIT(0)190 191#define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL192 193/* 9 - Shaping */194#define REG_PORT_MTI_CREDIT_INCREMENT 0x091C195 196/* The port number as per the datasheet */197#define RGMII_2_PORT_NUM 5198#define RGMII_1_PORT_NUM 6199 200#define LAN937X_RGMII_2_PORT (RGMII_2_PORT_NUM - 1)201#define LAN937X_RGMII_1_PORT (RGMII_1_PORT_NUM - 1)202 203#define RGMII_1_TX_DELAY_2NS 2204#define RGMII_2_TX_DELAY_2NS 0205#define RGMII_1_RX_DELAY_2NS 0x1B206#define RGMII_2_RX_DELAY_2NS 0x14207 208#define LAN937X_TAG_LEN 2209 210#endif211