369 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Marvell 88E6xxx Switch Global (1) Registers support4 *5 * Copyright (c) 2008 Marvell Semiconductor6 *7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>9 */10 11#ifndef _MV88E6XXX_GLOBAL1_H12#define _MV88E6XXX_GLOBAL1_H13 14#include "chip.h"15 16/* Offset 0x00: Switch Global Status Register */17#define MV88E6XXX_G1_STS 0x0018#define MV88E6352_G1_STS_PPU_STATE 0x800019#define MV88E6185_G1_STS_PPU_STATE_MASK 0xc00020#define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x000021#define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x400022#define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x800023#define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc00024#define MV88E6XXX_G1_STS_INIT_READY 0x080025#define MV88E6393X_G1_STS_IRQ_DEVICE_2 926#define MV88E6XXX_G1_STS_IRQ_AVB 827#define MV88E6XXX_G1_STS_IRQ_DEVICE 728#define MV88E6XXX_G1_STS_IRQ_STATS 629#define MV88E6XXX_G1_STS_IRQ_VTU_PROB 530#define MV88E6XXX_G1_STS_IRQ_VTU_DONE 431#define MV88E6XXX_G1_STS_IRQ_ATU_PROB 332#define MV88E6XXX_G1_STS_IRQ_ATU_DONE 233#define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 134#define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 035 36/* Offset 0x01: Switch MAC Address Register Bytes 0 & 137 * Offset 0x02: Switch MAC Address Register Bytes 2 & 338 * Offset 0x03: Switch MAC Address Register Bytes 4 & 539 */40#define MV88E6XXX_G1_MAC_01 0x0141#define MV88E6XXX_G1_MAC_23 0x0242#define MV88E6XXX_G1_MAC_45 0x0343 44/* Offset 0x01: ATU FID Register */45#define MV88E6352_G1_ATU_FID 0x0146 47/* Offset 0x02: VTU FID Register */48#define MV88E6352_G1_VTU_FID 0x0249#define MV88E6352_G1_VTU_FID_VID_POLICY 0x100050#define MV88E6352_G1_VTU_FID_MASK 0x0fff51 52/* Offset 0x03: VTU SID Register */53#define MV88E6352_G1_VTU_SID 0x0354#define MV88E6352_G1_VTU_SID_MASK 0x3f55 56/* Offset 0x04: Switch Global Control Register */57#define MV88E6XXX_G1_CTL1 0x0458#define MV88E6XXX_G1_CTL1_SW_RESET 0x800059#define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x400060#define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x200061#define MV88E6185_G1_CTL1_SCHED_PRIO 0x080062#define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x040063#define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x020064#define MV88E6393X_G1_CTL1_DEVICE2_EN 0x020065#define MV88E6XXX_G1_CTL1_DEVICE_EN 0x008066#define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x004067#define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x002068#define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x001069#define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN 0x000870#define MV88E6XXX_G1_CTL1_ATU_DONE_EN 0x000471#define MV88E6XXX_G1_CTL1_TCAM_EN 0x000272#define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN 0x000173 74/* Offset 0x05: VTU Operation Register */75#define MV88E6XXX_G1_VTU_OP 0x0576#define MV88E6XXX_G1_VTU_OP_BUSY 0x800077#define MV88E6XXX_G1_VTU_OP_MASK 0x700078#define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x100079#define MV88E6XXX_G1_VTU_OP_NOOP 0x200080#define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x300081#define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x400082#define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x500083#define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x600084#define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION 0x700085#define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION BIT(6)86#define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION BIT(5)87#define MV88E6XXX_G1_VTU_OP_SPID_MASK 0xf88 89/* Offset 0x06: VTU VID Register */90#define MV88E6XXX_G1_VTU_VID 0x0691#define MV88E6XXX_G1_VTU_VID_MASK 0x0fff92#define MV88E6390_G1_VTU_VID_PAGE 0x200093#define MV88E6XXX_G1_VTU_VID_VALID 0x100094 95/* Offset 0x07: VTU/STU Data Register 196 * Offset 0x08: VTU/STU Data Register 297 * Offset 0x09: VTU/STU Data Register 398 */99#define MV88E6XXX_G1_VTU_DATA1 0x07100#define MV88E6XXX_G1_VTU_DATA2 0x08101#define MV88E6XXX_G1_VTU_DATA3 0x09102#define MV88E6XXX_G1_VTU_STU_DATA_MASK 0x0003103#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000104#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED 0x0001105#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED 0x0002106#define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x0003107#define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED 0x0000108#define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING 0x0001109#define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING 0x0002110#define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING 0x0003111 112/* Offset 0x0A: ATU Control Register */113#define MV88E6XXX_G1_ATU_CTL 0x0a114#define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008115#define MV88E6161_G1_ATU_CTL_HASH_MASK 0x0003116 117/* Offset 0x0B: ATU Operation Register */118#define MV88E6XXX_G1_ATU_OP 0x0b119#define MV88E6XXX_G1_ATU_OP_BUSY 0x8000120#define MV88E6XXX_G1_ATU_OP_MASK 0x7000121#define MV88E6XXX_G1_ATU_OP_NOOP 0x0000122#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000123#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000124#define MV88E6XXX_G1_ATU_OP_LOAD_DB 0x3000125#define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB 0x4000126#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB 0x5000127#define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB 0x6000128#define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000129#define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION BIT(7)130#define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION BIT(6)131#define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION BIT(5)132#define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION BIT(4)133 134/* Offset 0x0C: ATU Data Register */135#define MV88E6XXX_G1_ATU_DATA 0x0c136#define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000137#define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK 0x00f0138#define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK 0x3ff0139#define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f140#define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED 0x0000141#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST 0x0001142#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2 0x0002143#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3 0x0003144#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4 0x0004145#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5 0x0005146#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6 0x0006147#define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST 0x0007148#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY 0x0008149#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO 0x0009150#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL 0x000a151#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO 0x000b152#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT 0x000c153#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO 0x000d154#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC 0x000e155#define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO 0x000f156#define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED 0x0000157#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY 0x0004158#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL 0x0005159#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT 0x0006160#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC 0x0007161#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO 0x000c162#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO 0x000d163#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO 0x000e164#define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO 0x000f165 166/* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1167 * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3168 * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5169 */170#define MV88E6XXX_G1_ATU_MAC01 0x0d171#define MV88E6XXX_G1_ATU_MAC23 0x0e172#define MV88E6XXX_G1_ATU_MAC45 0x0f173 174/* Offset 0x10: IP-PRI Mapping Register 0175 * Offset 0x11: IP-PRI Mapping Register 1176 * Offset 0x12: IP-PRI Mapping Register 2177 * Offset 0x13: IP-PRI Mapping Register 3178 * Offset 0x14: IP-PRI Mapping Register 4179 * Offset 0x15: IP-PRI Mapping Register 5180 * Offset 0x16: IP-PRI Mapping Register 6181 * Offset 0x17: IP-PRI Mapping Register 7182 */183#define MV88E6XXX_G1_IP_PRI_0 0x10184#define MV88E6XXX_G1_IP_PRI_1 0x11185#define MV88E6XXX_G1_IP_PRI_2 0x12186#define MV88E6XXX_G1_IP_PRI_3 0x13187#define MV88E6XXX_G1_IP_PRI_4 0x14188#define MV88E6XXX_G1_IP_PRI_5 0x15189#define MV88E6XXX_G1_IP_PRI_6 0x16190#define MV88E6XXX_G1_IP_PRI_7 0x17191 192/* Offset 0x18: IEEE-PRI Register */193#define MV88E6XXX_G1_IEEE_PRI 0x18194 195/* Offset 0x19: Core Tag Type */196#define MV88E6185_G1_CORE_TAG_TYPE 0x19197 198/* Offset 0x1A: Monitor Control */199#define MV88E6185_G1_MONITOR_CTL 0x1a200#define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK 0xf000201#define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK 0x0f00202#define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK 0x00f0203#define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK 0x00f0204#define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f205 206/* Offset 0x1A: Monitor & MGMT Control Register */207#define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a208#define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000209#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00210#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO 0x0000211#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI 0x0100212#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO 0x0200213#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI 0x0300214#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000215#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100216#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000217#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_PTP_CPU_DEST 0x3200218#define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI 0x00e0219#define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff220 221/* Offset 0x1C: Global Control 2 */222#define MV88E6XXX_G1_CTL2 0x1c223#define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000224#define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000225#define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000226#define MV88E6352_G1_CTL2_HEADER_TYPE_MASK 0xc000227#define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG 0x0000228#define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT 0x4000229#define MV88E6390_G1_CTL2_HEADER_TYPE_LAG 0x8000230#define MV88E6352_G1_CTL2_RMU_MODE_MASK 0x3000231#define MV88E6352_G1_CTL2_RMU_MODE_DISABLED 0x0000232#define MV88E6352_G1_CTL2_RMU_MODE_PORT_4 0x1000233#define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 0x2000234#define MV88E6352_G1_CTL2_RMU_MODE_PORT_6 0x3000235#define MV88E6085_G1_CTL2_DA_CHECK 0x4000236#define MV88E6085_G1_CTL2_P10RM 0x2000237#define MV88E6085_G1_CTL2_RM_ENABLE 0x1000238#define MV88E6352_G1_CTL2_DA_CHECK 0x0800239#define MV88E6390_G1_CTL2_RMU_MODE_MASK 0x0700240#define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 0x0000241#define MV88E6390_G1_CTL2_RMU_MODE_PORT_1 0x0100242#define MV88E6390_G1_CTL2_RMU_MODE_PORT_9 0x0200243#define MV88E6390_G1_CTL2_RMU_MODE_PORT_10 0x0300244#define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA 0x0600245#define MV88E6390_G1_CTL2_RMU_MODE_DISABLED 0x0700246#define MV88E6390_G1_CTL2_HIST_MODE_MASK 0x00c0247#define MV88E6390_G1_CTL2_HIST_MODE_RX 0x0040248#define MV88E6390_G1_CTL2_HIST_MODE_TX 0x0080249#define MV88E6352_G1_CTL2_CTR_MODE_MASK 0x0060250#define MV88E6390_G1_CTL2_CTR_MODE 0x0020251#define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f252 253/* Offset 0x1D: Stats Operation Register */254#define MV88E6XXX_G1_STATS_OP 0x1d255#define MV88E6XXX_G1_STATS_OP_BUSY 0x8000256#define MV88E6XXX_G1_STATS_OP_NOP 0x0000257#define MV88E6XXX_G1_STATS_OP_FLUSH_ALL 0x1000258#define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000259#define MV88E6XXX_G1_STATS_OP_READ_CAPTURED 0x4000260#define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT 0x5000261#define MV88E6XXX_G1_STATS_OP_HIST_RX 0x0400262#define MV88E6XXX_G1_STATS_OP_HIST_TX 0x0800263#define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00264#define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 0x0200265#define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400266 267/* Offset 0x1E: Stats Counter Register Bytes 3 & 2268 * Offset 0x1F: Stats Counter Register Bytes 1 & 0269 */270#define MV88E6XXX_G1_STATS_COUNTER_32 0x1e271#define MV88E6XXX_G1_STATS_COUNTER_01 0x1f272 273int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);274int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);275int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int276 bit, int val);277int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,278 u16 mask, u16 val);279 280int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);281 282int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);283int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);284int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip);285int mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip);286int mv88e6250_g1_wait_eeprom_done_prereset(struct mv88e6xxx_chip *chip);287 288int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);289int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);290 291int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu);292 293int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);294int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);295int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);296int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);297int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);298void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);299int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip);300int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,301 enum mv88e6xxx_egress_direction direction,302 int port);303int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,304 enum mv88e6xxx_egress_direction direction,305 int port);306int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);307int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);308int mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip *chip, int port);309int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);310 311int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip);312 313int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);314int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);315 316int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);317 318int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);319int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);320int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);321 322int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);323 324int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);325int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,326 unsigned int msecs);327int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,328 struct mv88e6xxx_atu_entry *entry);329int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,330 struct mv88e6xxx_atu_entry *entry);331int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all);332int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,333 bool all);334int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip);335void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip);336int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash);337int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash);338 339int mv88e6xxx_g1_vtu_getnext(struct mv88e6xxx_chip *chip,340 struct mv88e6xxx_vtu_entry *entry);341int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,342 struct mv88e6xxx_vtu_entry *entry);343int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,344 struct mv88e6xxx_vtu_entry *entry);345int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,346 struct mv88e6xxx_vtu_entry *entry);347int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,348 struct mv88e6xxx_vtu_entry *entry);349int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip,350 struct mv88e6xxx_vtu_entry *entry);351int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,352 struct mv88e6xxx_vtu_entry *entry);353int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);354int mv88e6xxx_g1_stu_getnext(struct mv88e6xxx_chip *chip,355 struct mv88e6xxx_stu_entry *entry);356int mv88e6352_g1_stu_getnext(struct mv88e6xxx_chip *chip,357 struct mv88e6xxx_stu_entry *entry);358int mv88e6352_g1_stu_loadpurge(struct mv88e6xxx_chip *chip,359 struct mv88e6xxx_stu_entry *entry);360int mv88e6390_g1_stu_getnext(struct mv88e6xxx_chip *chip,361 struct mv88e6xxx_stu_entry *entry);362int mv88e6390_g1_stu_loadpurge(struct mv88e6xxx_chip *chip,363 struct mv88e6xxx_stu_entry *entry);364int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip);365void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip);366int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid);367 368#endif /* _MV88E6XXX_GLOBAL1_H */369