390 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Marvell 88E6xxx Switch Global 2 Registers support4 *5 * Copyright (c) 2008 Marvell Semiconductor6 *7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>9 */10 11#ifndef _MV88E6XXX_GLOBAL2_H12#define _MV88E6XXX_GLOBAL2_H13 14#include "chip.h"15 16/* Offset 0x00: Interrupt Source Register */17#define MV88E6XXX_G2_INT_SRC 0x0018#define MV88E6XXX_G2_INT_SRC_WDOG 0x800019#define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x400020#define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x200021#define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x100022#define MV88E6352_G2_INT_SRC_SERDES 0x080023#define MV88E6352_G2_INT_SRC_PHY 0x001f24#define MV88E6390_G2_INT_SRC_PHY 0x07fe25 26#define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 1527 28/* Offset 0x01: Interrupt Mask Register */29#define MV88E6XXX_G2_INT_MASK 0x0130#define MV88E6XXX_G2_INT_MASK_WDOG 0x800031#define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x400032#define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x200033#define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x100034#define MV88E6352_G2_INT_MASK_SERDES 0x080035#define MV88E6352_G2_INT_MASK_PHY 0x001f36#define MV88E6390_G2_INT_MASK_PHY 0x07fe37 38/* Offset 0x02: MGMT Enable Register 2x */39#define MV88E6XXX_G2_MGMT_EN_2X 0x0240 41/* Offset 0x02: MAC LINK change IRQ Register for MV88E6393X */42#define MV88E6393X_G2_MACLINK_INT_SRC 0x0243 44/* Offset 0x03: MGMT Enable Register 0x */45#define MV88E6XXX_G2_MGMT_EN_0X 0x0346 47/* Offset 0x03: MAC LINK change IRQ Mask Register for MV88E6393X */48#define MV88E6393X_G2_MACLINK_INT_MASK 0x0349 50/* Offset 0x04: Flow Control Delay Register */51#define MV88E6XXX_G2_FLOW_CTL 0x0452 53/* Offset 0x05: Switch Management Register */54#define MV88E6XXX_G2_SWITCH_MGMT 0x0555#define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x800056#define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x400057#define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x200058#define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x008059#define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x000860 61#define MV88E6393X_G2_EGRESS_MONITOR_DEST 0x0562 63/* Offset 0x06: Device Mapping Table Register */64#define MV88E6XXX_G2_DEVICE_MAPPING 0x0665#define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x800066#define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f0067#define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK 0x000f68#define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK 0x001f69 70/* Offset 0x07: Trunk Mask Table Register */71#define MV88E6XXX_G2_TRUNK_MASK 0x0772#define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x800073#define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x700074#define MV88E6XXX_G2_TRUNK_MASK_HASH 0x080075 76/* Offset 0x08: Trunk Mapping Table Register */77#define MV88E6XXX_G2_TRUNK_MAPPING 0x0878#define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x800079#define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x780080 81/* Offset 0x09: Ingress Rate Command Register */82#define MV88E6XXX_G2_IRL_CMD 0x0983#define MV88E6XXX_G2_IRL_CMD_BUSY 0x800084#define MV88E6352_G2_IRL_CMD_OP_MASK 0x700085#define MV88E6352_G2_IRL_CMD_OP_NOOP 0x000086#define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x100087#define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x200088#define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x300089#define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x400090#define MV88E6390_G2_IRL_CMD_OP_MASK 0x600091#define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x000092#define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x200093#define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x400094#define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x600095#define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f0096#define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f0097#define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e098#define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f99 100/* Offset 0x0A: Ingress Rate Data Register */101#define MV88E6XXX_G2_IRL_DATA 0x0a102#define MV88E6XXX_G2_IRL_DATA_MASK 0xffff103 104/* Offset 0x0B: Cross-chip Port VLAN Register */105#define MV88E6XXX_G2_PVT_ADDR 0x0b106#define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000107#define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000108#define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000109#define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000110#define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000111#define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff112#define MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK 0x1f113 114/* Offset 0x0C: Cross-chip Port VLAN Data Register */115#define MV88E6XXX_G2_PVT_DATA 0x0c116#define MV88E6XXX_G2_PVT_DATA_MASK 0x7f117 118/* Offset 0x0D: Switch MAC/WoL/WoF Register */119#define MV88E6XXX_G2_SWITCH_MAC 0x0d120#define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000121#define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00122#define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff123 124/* Offset 0x0E: ATU Stats Register */125#define MV88E6XXX_G2_ATU_STATS 0x0e126#define MV88E6XXX_G2_ATU_STATS_BIN_0 (0x0 << 14)127#define MV88E6XXX_G2_ATU_STATS_BIN_1 (0x1 << 14)128#define MV88E6XXX_G2_ATU_STATS_BIN_2 (0x2 << 14)129#define MV88E6XXX_G2_ATU_STATS_BIN_3 (0x3 << 14)130#define MV88E6XXX_G2_ATU_STATS_MODE_ALL (0x0 << 12)131#define MV88E6XXX_G2_ATU_STATS_MODE_ALL_DYNAMIC (0x1 << 12)132#define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL (0x2 << 12)133#define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL_DYNAMIC (0x3 << 12)134#define MV88E6XXX_G2_ATU_STATS_MASK 0x0fff135 136/* Offset 0x0F: Priority Override Table */137#define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f138#define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000139#define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000140#define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00141#define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080142#define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030143#define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008144#define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007145 146/* Offset 0x14: EEPROM Command */147#define MV88E6XXX_G2_EEPROM_CMD 0x14148#define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000149#define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000150#define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000151#define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000152#define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000153#define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800154#define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400155#define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff156#define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff157 158/* Offset 0x15: EEPROM Data */159#define MV88E6352_G2_EEPROM_DATA 0x15160#define MV88E6352_G2_EEPROM_DATA_MASK 0xffff161 162/* Offset 0x15: EEPROM Addr */163#define MV88E6390_G2_EEPROM_ADDR 0x15164#define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff165 166/* Offset 0x16: AVB Command Register */167#define MV88E6352_G2_AVB_CMD 0x16168#define MV88E6352_G2_AVB_CMD_BUSY 0x8000169#define MV88E6352_G2_AVB_CMD_OP_READ 0x4000170#define MV88E6352_G2_AVB_CMD_OP_READ_INCR 0x6000171#define MV88E6352_G2_AVB_CMD_OP_WRITE 0x3000172#define MV88E6390_G2_AVB_CMD_OP_READ 0x0000173#define MV88E6390_G2_AVB_CMD_OP_READ_INCR 0x4000174#define MV88E6390_G2_AVB_CMD_OP_WRITE 0x6000175#define MV88E6352_G2_AVB_CMD_PORT_MASK 0x0f00176#define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL 0xe177#define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL 0xf178#define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL 0xf179#define MV88E6390_G2_AVB_CMD_PORT_MASK 0x1f00180#define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL 0x1e181#define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL 0x1f182#define MV88E6352_G2_AVB_CMD_BLOCK_PTP 0183#define MV88E6352_G2_AVB_CMD_BLOCK_AVB 1184#define MV88E6352_G2_AVB_CMD_BLOCK_QAV 2185#define MV88E6352_G2_AVB_CMD_BLOCK_QVB 3186#define MV88E6352_G2_AVB_CMD_BLOCK_MASK 0x00e0187#define MV88E6352_G2_AVB_CMD_ADDR_MASK 0x001f188 189/* Offset 0x17: AVB Data Register */190#define MV88E6352_G2_AVB_DATA 0x17191 192/* Offset 0x18: SMI PHY Command Register */193#define MV88E6XXX_G2_SMI_PHY_CMD 0x18194#define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000195#define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000196#define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000197#define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000198#define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000199#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000200#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000201#define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000202#define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00203#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400204#define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800205#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000206#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400207#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800208#define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00209#define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0210#define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f211#define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff212 213/* Offset 0x19: SMI PHY Data Register */214#define MV88E6XXX_G2_SMI_PHY_DATA 0x19215 216/* Offset 0x1A: Scratch and Misc. Register */217#define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a218#define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000219#define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00220#define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff221 222/* Offset 0x1B: Watch Dog Control Register */223#define MV88E6250_G2_WDOG_CTL 0x1b224#define MV88E6250_G2_WDOG_CTL_QC_HISTORY 0x0100225#define MV88E6250_G2_WDOG_CTL_QC_EVENT 0x0080226#define MV88E6250_G2_WDOG_CTL_QC_ENABLE 0x0040227#define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY 0x0020228#define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT 0x0010229#define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE 0x0008230#define MV88E6250_G2_WDOG_CTL_FORCE_IRQ 0x0004231#define MV88E6250_G2_WDOG_CTL_HISTORY 0x0002232#define MV88E6250_G2_WDOG_CTL_SWRESET 0x0001233 234/* Offset 0x1B: Watch Dog Control Register */235#define MV88E6352_G2_WDOG_CTL 0x1b236#define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080237#define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040238#define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020239#define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010240#define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008241#define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004242#define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002243#define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001244 245/* Offset 0x1B: Watch Dog Control Register */246#define MV88E6390_G2_WDOG_CTL 0x1b247#define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000248#define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00249#define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000250#define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000251#define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100252#define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200253#define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300254#define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff255#define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008256#define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004257#define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002258#define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001259 260/* Offset 0x1C: QoS Weights Register */261#define MV88E6XXX_G2_QOS_WEIGHTS 0x1c262#define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000263#define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00264#define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00265#define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff266 267/* Offset 0x1D: Misc Register */268#define MV88E6XXX_G2_MISC 0x1d269#define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000270#define MV88E6352_G2_NOEGR_POLICY 0x2000271#define MV88E6390_G2_LAG_ID_4 0x2000272 273/* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */274/* Offset 0x02: Misc Configuration */275#define MV88E6352_G2_SCRATCH_MISC_CFG 0x02276#define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80277/* Offset 0x60-0x61: GPIO Configuration */278#define MV88E6352_G2_SCRATCH_GPIO_CFG0 0x60279#define MV88E6352_G2_SCRATCH_GPIO_CFG1 0x61280/* Offset 0x62-0x63: GPIO Direction */281#define MV88E6352_G2_SCRATCH_GPIO_DIR0 0x62282#define MV88E6352_G2_SCRATCH_GPIO_DIR1 0x63283#define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT 0284#define MV88E6352_G2_SCRATCH_GPIO_DIR_IN 1285/* Offset 0x64-0x65: GPIO Data */286#define MV88E6352_G2_SCRATCH_GPIO_DATA0 0x64287#define MV88E6352_G2_SCRATCH_GPIO_DATA1 0x65288/* Offset 0x68-0x6F: GPIO Pin Control */289#define MV88E6352_G2_SCRATCH_GPIO_PCTL0 0x68290#define MV88E6352_G2_SCRATCH_GPIO_PCTL1 0x69291#define MV88E6352_G2_SCRATCH_GPIO_PCTL2 0x6A292#define MV88E6352_G2_SCRATCH_GPIO_PCTL3 0x6B293#define MV88E6352_G2_SCRATCH_GPIO_PCTL4 0x6C294#define MV88E6352_G2_SCRATCH_GPIO_PCTL5 0x6D295#define MV88E6352_G2_SCRATCH_GPIO_PCTL6 0x6E296#define MV88E6352_G2_SCRATCH_GPIO_PCTL7 0x6F297#define MV88E6352_G2_SCRATCH_CONFIG_DATA0 0x70298#define MV88E6352_G2_SCRATCH_CONFIG_DATA1 0x71299#define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2)300#define MV88E6352_G2_SCRATCH_CONFIG_DATA2 0x72301#define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0xf302#define MV88E6352_G2_SCRATCH_CONFIG_DATA3 0x73303#define MV88E6352_G2_SCRATCH_CONFIG_DATA3_S_SEL BIT(1)304 305#define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO 0306#define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG 1307#define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ 2308 309int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);310int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val);311int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg,312 int bit, int val);313 314int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);315int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);316 317int mv88e6xxx_g2_smi_phy_read_c22(struct mv88e6xxx_chip *chip,318 struct mii_bus *bus,319 int addr, int reg, u16 *val);320int mv88e6xxx_g2_smi_phy_write_c22(struct mv88e6xxx_chip *chip,321 struct mii_bus *bus,322 int addr, int reg, u16 val);323int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,324 struct mii_bus *bus,325 int addr, int devad, int reg, u16 *val);326int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,327 struct mii_bus *bus,328 int addr, int devad, int reg, u16 val);329int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);330 331int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,332 struct ethtool_eeprom *eeprom, u8 *data);333int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,334 struct ethtool_eeprom *eeprom, u8 *data);335 336int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,337 struct ethtool_eeprom *eeprom, u8 *data);338int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,339 struct ethtool_eeprom *eeprom, u8 *data);340 341int mv88e6xxx_g2_pvt_read(struct mv88e6xxx_chip *chip, int src_dev,342 int src_port, u16 *data);343int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,344 int src_port, u16 data);345int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip);346 347int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);348void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);349 350int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,351 struct mii_bus *bus);352void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,353 struct mii_bus *bus);354 355int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);356int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);357 358int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip);359 360int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,361 bool hash, u16 mask);362int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,363 u16 map);364int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip);365 366int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,367 int port);368int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip);369 370extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;371extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops;372extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;373extern const struct mv88e6xxx_irq_ops mv88e6393x_watchdog_ops;374 375extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops;376extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops;377extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops;378 379extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;380 381int mv88e6390_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,382 bool external);383int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,384 bool external);385int mv88e6352_g2_scratch_port_has_serdes(struct mv88e6xxx_chip *chip, int port);386int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin);387int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats);388 389#endif /* _MV88E6XXX_GLOBAL2_H */390