391 lines · c
1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Marvell 88E6352 family SERDES PCS support4 *5 * Copyright (c) 2008 Marvell Semiconductor6 *7 * Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch>8 */9#include <linux/phylink.h>10 11#include "global2.h"12#include "port.h"13#include "serdes.h"14 15/* Definitions from drivers/net/phy/marvell.c, which would be good to reuse. */16#define MII_M1011_PHY_STATUS 1717#define MII_M1011_IMASK 1818#define MII_M1011_IMASK_LINK_CHANGE BIT(10)19#define MII_M1011_IEVENT 1920#define MII_M1011_IEVENT_LINK_CHANGE BIT(10)21#define MII_MARVELL_PHY_PAGE 2222#define MII_MARVELL_FIBER_PAGE 123 24struct marvell_c22_pcs {25 struct mdio_device mdio;26 struct phylink_pcs phylink_pcs;27 unsigned int irq;28 char name[64];29 bool (*link_check)(struct marvell_c22_pcs *mpcs);30 struct mv88e6xxx_port *port;31};32 33static struct marvell_c22_pcs *pcs_to_marvell_c22_pcs(struct phylink_pcs *pcs)34{35 return container_of(pcs, struct marvell_c22_pcs, phylink_pcs);36}37 38static int marvell_c22_pcs_set_fiber_page(struct marvell_c22_pcs *mpcs)39{40 u16 page;41 int err;42 43 mutex_lock(&mpcs->mdio.bus->mdio_lock);44 45 err = __mdiodev_read(&mpcs->mdio, MII_MARVELL_PHY_PAGE);46 if (err < 0) {47 dev_err(mpcs->mdio.dev.parent,48 "%s: can't read Serdes page register: %pe\n",49 mpcs->name, ERR_PTR(err));50 return err;51 }52 53 page = err;54 55 err = __mdiodev_write(&mpcs->mdio, MII_MARVELL_PHY_PAGE,56 MII_MARVELL_FIBER_PAGE);57 if (err) {58 dev_err(mpcs->mdio.dev.parent,59 "%s: can't set Serdes page register: %pe\n",60 mpcs->name, ERR_PTR(err));61 return err;62 }63 64 return page;65}66 67static int marvell_c22_pcs_restore_page(struct marvell_c22_pcs *mpcs,68 int oldpage, int ret)69{70 int err;71 72 if (oldpage >= 0) {73 err = __mdiodev_write(&mpcs->mdio, MII_MARVELL_PHY_PAGE,74 oldpage);75 if (err)76 dev_err(mpcs->mdio.dev.parent,77 "%s: can't restore Serdes page register: %pe\n",78 mpcs->name, ERR_PTR(err));79 if (!err || ret < 0)80 err = ret;81 } else {82 err = oldpage;83 }84 mutex_unlock(&mpcs->mdio.bus->mdio_lock);85 86 return err;87}88 89static irqreturn_t marvell_c22_pcs_handle_irq(int irq, void *dev_id)90{91 struct marvell_c22_pcs *mpcs = dev_id;92 irqreturn_t status = IRQ_NONE;93 int err, oldpage;94 95 oldpage = marvell_c22_pcs_set_fiber_page(mpcs);96 if (oldpage < 0)97 goto fail;98 99 err = __mdiodev_read(&mpcs->mdio, MII_M1011_IEVENT);100 if (err >= 0 && err & MII_M1011_IEVENT_LINK_CHANGE) {101 phylink_pcs_change(&mpcs->phylink_pcs, true);102 status = IRQ_HANDLED;103 }104 105fail:106 marvell_c22_pcs_restore_page(mpcs, oldpage, 0);107 108 return status;109}110 111static int marvell_c22_pcs_modify(struct marvell_c22_pcs *mpcs, u8 reg,112 u16 mask, u16 val)113{114 int oldpage, err = 0;115 116 oldpage = marvell_c22_pcs_set_fiber_page(mpcs);117 if (oldpage >= 0)118 err = __mdiodev_modify(&mpcs->mdio, reg, mask, val);119 120 return marvell_c22_pcs_restore_page(mpcs, oldpage, err);121}122 123static int marvell_c22_pcs_power(struct marvell_c22_pcs *mpcs,124 bool on)125{126 u16 val = on ? 0 : BMCR_PDOWN;127 128 return marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_PDOWN, val);129}130 131static int marvell_c22_pcs_control_irq(struct marvell_c22_pcs *mpcs,132 bool enable)133{134 u16 val = enable ? MII_M1011_IMASK_LINK_CHANGE : 0;135 136 return marvell_c22_pcs_modify(mpcs, MII_M1011_IMASK,137 MII_M1011_IMASK_LINK_CHANGE, val);138}139 140static int marvell_c22_pcs_enable(struct phylink_pcs *pcs)141{142 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs);143 int err;144 145 err = marvell_c22_pcs_power(mpcs, true);146 if (err)147 return err;148 149 return marvell_c22_pcs_control_irq(mpcs, !!mpcs->irq);150}151 152static void marvell_c22_pcs_disable(struct phylink_pcs *pcs)153{154 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs);155 156 marvell_c22_pcs_control_irq(mpcs, false);157 marvell_c22_pcs_power(mpcs, false);158}159 160static void marvell_c22_pcs_get_state(struct phylink_pcs *pcs,161 struct phylink_link_state *state)162{163 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs);164 int oldpage, bmsr, lpa, status;165 166 state->link = false;167 168 if (mpcs->link_check && !mpcs->link_check(mpcs))169 return;170 171 oldpage = marvell_c22_pcs_set_fiber_page(mpcs);172 if (oldpage >= 0) {173 bmsr = __mdiodev_read(&mpcs->mdio, MII_BMSR);174 lpa = __mdiodev_read(&mpcs->mdio, MII_LPA);175 status = __mdiodev_read(&mpcs->mdio, MII_M1011_PHY_STATUS);176 }177 178 if (marvell_c22_pcs_restore_page(mpcs, oldpage, 0) >= 0 &&179 bmsr >= 0 && lpa >= 0 && status >= 0)180 mv88e6xxx_pcs_decode_state(mpcs->mdio.dev.parent, bmsr, lpa,181 status, state);182}183 184static int marvell_c22_pcs_config(struct phylink_pcs *pcs,185 unsigned int neg_mode,186 phy_interface_t interface,187 const unsigned long *advertising,188 bool permit_pause_to_mac)189{190 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs);191 int oldpage, adv, err, ret = 0;192 u16 bmcr;193 194 adv = phylink_mii_c22_pcs_encode_advertisement(interface, advertising);195 if (adv < 0)196 return 0;197 198 bmcr = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? BMCR_ANENABLE : 0;199 200 oldpage = marvell_c22_pcs_set_fiber_page(mpcs);201 if (oldpage < 0)202 goto restore;203 204 err = __mdiodev_modify_changed(&mpcs->mdio, MII_ADVERTISE, 0xffff, adv);205 ret = err;206 if (err < 0)207 goto restore;208 209 err = __mdiodev_modify_changed(&mpcs->mdio, MII_BMCR, BMCR_ANENABLE,210 bmcr);211 if (err < 0) {212 ret = err;213 goto restore;214 }215 216 /* If the ANENABLE bit was changed, the PHY will restart negotiation,217 * so we don't need to flag a change to trigger its own restart.218 */219 if (err)220 ret = 0;221 222restore:223 return marvell_c22_pcs_restore_page(mpcs, oldpage, ret);224}225 226static void marvell_c22_pcs_an_restart(struct phylink_pcs *pcs)227{228 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs);229 230 marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_ANRESTART, BMCR_ANRESTART);231}232 233static void marvell_c22_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,234 phy_interface_t interface, int speed,235 int duplex)236{237 struct marvell_c22_pcs *mpcs = pcs_to_marvell_c22_pcs(pcs);238 u16 bmcr;239 int err;240 241 if (phylink_autoneg_inband(mode))242 return;243 244 bmcr = mii_bmcr_encode_fixed(speed, duplex);245 246 err = marvell_c22_pcs_modify(mpcs, MII_BMCR, BMCR_SPEED100 |247 BMCR_FULLDPLX | BMCR_SPEED1000, bmcr);248 if (err)249 dev_err(mpcs->mdio.dev.parent,250 "%s: failed to configure mpcs: %pe\n", mpcs->name,251 ERR_PTR(err));252}253 254static const struct phylink_pcs_ops marvell_c22_pcs_ops = {255 .pcs_enable = marvell_c22_pcs_enable,256 .pcs_disable = marvell_c22_pcs_disable,257 .pcs_get_state = marvell_c22_pcs_get_state,258 .pcs_config = marvell_c22_pcs_config,259 .pcs_an_restart = marvell_c22_pcs_an_restart,260 .pcs_link_up = marvell_c22_pcs_link_up,261};262 263static struct marvell_c22_pcs *marvell_c22_pcs_alloc(struct device *dev,264 struct mii_bus *bus,265 unsigned int addr)266{267 struct marvell_c22_pcs *mpcs;268 269 mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);270 if (!mpcs)271 return NULL;272 273 mpcs->mdio.dev.parent = dev;274 mpcs->mdio.bus = bus;275 mpcs->mdio.addr = addr;276 mpcs->phylink_pcs.ops = &marvell_c22_pcs_ops;277 mpcs->phylink_pcs.neg_mode = true;278 279 return mpcs;280}281 282static int marvell_c22_pcs_setup_irq(struct marvell_c22_pcs *mpcs,283 unsigned int irq)284{285 int err;286 287 mpcs->phylink_pcs.poll = !irq;288 mpcs->irq = irq;289 290 if (irq) {291 err = request_threaded_irq(irq, NULL,292 marvell_c22_pcs_handle_irq,293 IRQF_ONESHOT, mpcs->name, mpcs);294 if (err)295 return err;296 }297 298 return 0;299}300 301/* mv88e6352 specifics */302 303static bool mv88e6352_pcs_link_check(struct marvell_c22_pcs *mpcs)304{305 struct mv88e6xxx_port *port = mpcs->port;306 struct mv88e6xxx_chip *chip = port->chip;307 u8 cmode;308 309 /* Port 4 can be in auto-media mode. Check that the port is310 * associated with the mpcs.311 */312 mv88e6xxx_reg_lock(chip);313 chip->info->ops->port_get_cmode(chip, port->port, &cmode);314 mv88e6xxx_reg_unlock(chip);315 316 return cmode == MV88E6XXX_PORT_STS_CMODE_100BASEX ||317 cmode == MV88E6XXX_PORT_STS_CMODE_1000BASEX ||318 cmode == MV88E6XXX_PORT_STS_CMODE_SGMII;319}320 321static int mv88e6352_pcs_init(struct mv88e6xxx_chip *chip, int port)322{323 struct marvell_c22_pcs *mpcs;324 struct mii_bus *bus;325 struct device *dev;326 unsigned int irq;327 int err;328 329 mv88e6xxx_reg_lock(chip);330 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);331 mv88e6xxx_reg_unlock(chip);332 if (err <= 0)333 return err;334 335 irq = mv88e6xxx_serdes_irq_mapping(chip, port);336 bus = mv88e6xxx_default_mdio_bus(chip);337 dev = chip->dev;338 339 mpcs = marvell_c22_pcs_alloc(dev, bus, MV88E6352_ADDR_SERDES);340 if (!mpcs)341 return -ENOMEM;342 343 snprintf(mpcs->name, sizeof(mpcs->name),344 "mv88e6xxx-%s-serdes-%d", dev_name(dev), port);345 346 mpcs->link_check = mv88e6352_pcs_link_check;347 mpcs->port = &chip->ports[port];348 349 err = marvell_c22_pcs_setup_irq(mpcs, irq);350 if (err) {351 kfree(mpcs);352 return err;353 }354 355 chip->ports[port].pcs_private = &mpcs->phylink_pcs;356 357 return 0;358}359 360static void mv88e6352_pcs_teardown(struct mv88e6xxx_chip *chip, int port)361{362 struct marvell_c22_pcs *mpcs;363 struct phylink_pcs *pcs;364 365 pcs = chip->ports[port].pcs_private;366 if (!pcs)367 return;368 369 mpcs = pcs_to_marvell_c22_pcs(pcs);370 371 if (mpcs->irq)372 free_irq(mpcs->irq, mpcs);373 374 kfree(mpcs);375 376 chip->ports[port].pcs_private = NULL;377}378 379static struct phylink_pcs *mv88e6352_pcs_select(struct mv88e6xxx_chip *chip,380 int port,381 phy_interface_t interface)382{383 return chip->ports[port].pcs_private;384}385 386const struct mv88e6xxx_pcs_ops mv88e6352_pcs_ops = {387 .pcs_init = mv88e6352_pcs_init,388 .pcs_teardown = mv88e6352_pcs_teardown,389 .pcs_select = mv88e6352_pcs_select,390};391