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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Marvell 88E6xxx Switch Port Registers support4 *5 * Copyright (c) 2008 Marvell Semiconductor6 *7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>9 */10 11#ifndef _MV88E6XXX_PORT_H12#define _MV88E6XXX_PORT_H13 14#include "chip.h"15 16/* Offset 0x00: Port Status Register */17#define MV88E6XXX_PORT_STS 0x0018#define MV88E6XXX_PORT_STS_PAUSE_EN 0x800019#define MV88E6XXX_PORT_STS_MY_PAUSE 0x400020#define MV88E6XXX_PORT_STS_HD_FLOW 0x200021#define MV88E6XXX_PORT_STS_PHY_DETECT 0x100022#define MV88E6250_PORT_STS_LINK 0x100023#define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f0024#define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x080025#define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x090026#define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL 0x0a0027#define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL 0x0b0028/* - Modes with PHY suffix use output instead of input clock29 * - Modes without RMII or RGMII use MII30 * - Modes without speed do not have a fixed speed specified in the manual31 * ("DC to x MHz" - variable clock support?)32 */33#define MV88E6250_PORT_STS_PORTMODE_MII_DISABLED 0x000034#define MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII 0x010035#define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY 0x020036#define MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY 0x040037#define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL 0x060038#define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL 0x070039#define MV88E6250_PORT_STS_PORTMODE_MII_HALF 0x080040#define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY 0x090041#define MV88E6250_PORT_STS_PORTMODE_MII_FULL 0x0a0042#define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY 0x0b0043#define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY 0x0c0044#define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY 0x0d0045#define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY 0x0e0046#define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY 0x0f0047#define MV88E6XXX_PORT_STS_LINK 0x080048#define MV88E6XXX_PORT_STS_DUPLEX 0x040049#define MV88E6XXX_PORT_STS_SPEED_MASK 0x030050#define MV88E6XXX_PORT_STS_SPEED_10 0x000051#define MV88E6XXX_PORT_STS_SPEED_100 0x010052#define MV88E6XXX_PORT_STS_SPEED_1000 0x020053#define MV88E6XXX_PORT_STS_SPEED_10000 0x030054#define MV88E6352_PORT_STS_EEE 0x004055#define MV88E6165_PORT_STS_AM_DIS 0x004056#define MV88E6185_PORT_STS_MGMII 0x004057#define MV88E6XXX_PORT_STS_TX_PAUSED 0x002058#define MV88E6XXX_PORT_STS_FLOW_CTL 0x001059#define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f60#define MV88E6XXX_PORT_STS_CMODE_MII_PHY 0x000161#define MV88E6XXX_PORT_STS_CMODE_MII 0x000262#define MV88E6XXX_PORT_STS_CMODE_GMII 0x000363#define MV88E6XXX_PORT_STS_CMODE_RMII_PHY 0x000464#define MV88E6XXX_PORT_STS_CMODE_RMII 0x000565#define MV88E6XXX_PORT_STS_CMODE_RGMII 0x000766#define MV88E6XXX_PORT_STS_CMODE_100BASEX 0x000867#define MV88E6XXX_PORT_STS_CMODE_1000BASEX 0x000968#define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a69#define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b70#define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c71#define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d72#define MV88E6393X_PORT_STS_CMODE_5GBASER 0x000c73#define MV88E6393X_PORT_STS_CMODE_10GBASER 0x000d74#define MV88E6393X_PORT_STS_CMODE_USXGMII 0x000e75#define MV88E6185_PORT_STS_CDUPLEX 0x000876#define MV88E6185_PORT_STS_CMODE_MASK 0x000777#define MV88E6185_PORT_STS_CMODE_GMII_FD 0x000078#define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS 0x000179#define MV88E6185_PORT_STS_CMODE_MII_100 0x000280#define MV88E6185_PORT_STS_CMODE_MII_10 0x000381#define MV88E6185_PORT_STS_CMODE_SERDES 0x000482#define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x000583#define MV88E6185_PORT_STS_CMODE_PHY 0x000684#define MV88E6185_PORT_STS_CMODE_DISABLED 0x000785 86/* Offset 0x01: MAC (or PCS or Physical) Control Register */87#define MV88E6XXX_PORT_MAC_CTL 0x0188#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x800089#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x400090#define MV88E6185_PORT_MAC_CTL_SYNC_OK 0x400091#define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x200092#define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x100093#define MV88E6352_PORT_MAC_CTL_200BASE 0x100094#define MV88E6XXX_PORT_MAC_CTL_EEE 0x020095#define MV88E6XXX_PORT_MAC_CTL_FORCE_EEE 0x010096#define MV88E6185_PORT_MAC_CTL_AN_EN 0x040097#define MV88E6185_PORT_MAC_CTL_AN_RESTART 0x020098#define MV88E6185_PORT_MAC_CTL_AN_DONE 0x010099#define MV88E6XXX_PORT_MAC_CTL_FC 0x0080100#define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040101#define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020102#define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010103#define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008104#define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004105#define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003106#define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000107#define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001108#define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002109#define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002110#define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003111#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003112 113/* Offset 0x02: Jamming Control Register */114#define MV88E6097_PORT_JAM_CTL 0x02115#define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00116#define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff117 118/* Offset 0x02: Flow Control Register */119#define MV88E6390_PORT_FLOW_CTL 0x02120#define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000121#define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00122#define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000123#define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100124#define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff125 126/* Offset 0x03: Switch Identifier Register */127#define MV88E6XXX_PORT_SWITCH_ID 0x03128#define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0129#define MV88E6XXX_PORT_SWITCH_ID_PROD_6020 0x0200130#define MV88E6XXX_PORT_SWITCH_ID_PROD_6071 0x0710131#define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0132#define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950133#define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990134#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00135#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10136#define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060137#define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150138#define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210139#define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610140#define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650141#define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710142#define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720143#define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750144#define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760145#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900146#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910147#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191X 0x1920148#define MV88E6XXX_PORT_SWITCH_ID_PROD_6193X 0x1930149#define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70150#define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200151#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400152#define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500153#define MV88E6XXX_PORT_SWITCH_ID_PROD_6361 0x2610154#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900155#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100156#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400157#define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410158#define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520159#define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710160#define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750161#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900162#define MV88E6XXX_PORT_SWITCH_ID_PROD_6393X 0x3930163#define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f164 165/* Offset 0x04: Port Control Register */166#define MV88E6XXX_PORT_CTL0 0x04167#define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000168#define MV88E6XXX_PORT_CTL0_SA_FILT_MASK 0xc000169#define MV88E6XXX_PORT_CTL0_SA_FILT_DISABLED 0x0000170#define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK 0x4000171#define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_UNLOCK 0x8000172#define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_CPU 0xc000173#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000174#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000175#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000176#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000177#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000178#define MV88E6XXX_PORT_CTL0_HEADER 0x0800179#define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400180#define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200181#define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300182#define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000183#define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100184#define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200185#define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300186#define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100187#define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080188#define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040189#define MV88E6185_PORT_CTL0_USE_IP 0x0020190#define MV88E6185_PORT_CTL0_USE_TAG 0x0010191#define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004192#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC 0x0004193#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC 0x0008194#define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003195#define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000196#define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001197#define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002198#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003199 200/* Offset 0x05: Port Control 1 */201#define MV88E6XXX_PORT_CTL1 0x05202#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000203#define MV88E6XXX_PORT_CTL1_TRUNK_PORT 0x4000204#define MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK 0x0f00205#define MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT 8206#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff207 208/* Offset 0x06: Port Based VLAN Map */209#define MV88E6XXX_PORT_BASE_VLAN 0x06210#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000211 212/* Offset 0x07: Default Port VLAN ID & Priority */213#define MV88E6XXX_PORT_DEFAULT_VLAN 0x07214#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff215 216/* Offset 0x08: Port Control 2 Register */217#define MV88E6XXX_PORT_CTL2 0x08218#define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000219#define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000220#define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000221#define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000222#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000223#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000224#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000225#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000226#define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00227#define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000228#define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400229#define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800230#define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00231#define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200232#define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100233#define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080234#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040235#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020236#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010237#define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f238 239/* Offset 0x09: Egress Rate Control */240#define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09241 242/* Offset 0x0A: Egress Rate Control 2 */243#define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a244 245/* Offset 0x0B: Port Association Vector */246#define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b247#define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000248#define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000249#define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000250#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000251#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800252 253/* Offset 0x0C: Port ATU Control */254#define MV88E6XXX_PORT_ATU_CTL 0x0c255 256/* Offset 0x0D: Priority Override Register */257#define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d258 259/* Offset 0x0E: Policy Control Register */260#define MV88E6XXX_PORT_POLICY_CTL 0x0e261#define MV88E6XXX_PORT_POLICY_CTL_DA_MASK 0xc000262#define MV88E6XXX_PORT_POLICY_CTL_SA_MASK 0x3000263#define MV88E6XXX_PORT_POLICY_CTL_VTU_MASK 0x0c00264#define MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK 0x0300265#define MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK 0x00c0266#define MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK 0x0030267#define MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK 0x000c268#define MV88E6XXX_PORT_POLICY_CTL_UDP_MASK 0x0003269#define MV88E6XXX_PORT_POLICY_CTL_NORMAL 0x0000270#define MV88E6XXX_PORT_POLICY_CTL_MIRROR 0x0001271#define MV88E6XXX_PORT_POLICY_CTL_TRAP 0x0002272#define MV88E6XXX_PORT_POLICY_CTL_DISCARD 0x0003273 274/* Offset 0x0E: Policy & MGMT Control Register (FAMILY_6393X) */275#define MV88E6393X_PORT_POLICY_MGMT_CTL 0x0e276#define MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE 0x8000277#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_MASK 0x3f00278#define MV88E6393X_PORT_POLICY_MGMT_CTL_DATA_MASK 0x00ff279#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO 0x2000280#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI 0x2100281#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO 0x2400282#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI 0x2500283#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST 0x3000284#define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST 0x3800285#define MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI 0x00e0286 287/* Offset 0x0F: Port Special Ether Type */288#define MV88E6XXX_PORT_ETH_TYPE 0x0f289#define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100290 291/* Offset 0x10: InDiscards Low Counter */292#define MV88E6XXX_PORT_IN_DISCARD_LO 0x10293 294/* Offset 0x10: Extended Port Control Command */295#define MV88E6393X_PORT_EPC_CMD 0x10296#define MV88E6393X_PORT_EPC_CMD_BUSY 0x8000297#define MV88E6393X_PORT_EPC_CMD_WRITE 0x3000298#define MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE 0x02299 300/* Offset 0x11: Extended Port Control Data */301#define MV88E6393X_PORT_EPC_DATA 0x11302 303/* Offset 0x11: InDiscards High Counter */304#define MV88E6XXX_PORT_IN_DISCARD_HI 0x11305 306/* Offset 0x12: InFiltered Counter */307#define MV88E6XXX_PORT_IN_FILTERED 0x12308 309/* Offset 0x13: OutFiltered Counter */310#define MV88E6XXX_PORT_OUT_FILTERED 0x13311 312/* Offset 0x18: IEEE Priority Mapping Table */313#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18314#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000315#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000316#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000317#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000318#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000319#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000320#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000321#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000322#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000323#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00324#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff325 326/* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */327#define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18328 329/* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */330#define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19331 332/* Offset 0x1a: Magic undocumented errata register */333#define MV88E6XXX_PORT_RESERVED_1A 0x1a334#define MV88E6XXX_PORT_RESERVED_1A_BUSY 0x8000335#define MV88E6XXX_PORT_RESERVED_1A_WRITE 0x4000336#define MV88E6XXX_PORT_RESERVED_1A_READ 0x0000337#define MV88E6XXX_PORT_RESERVED_1A_PORT_SHIFT 5338#define MV88E6XXX_PORT_RESERVED_1A_BLOCK_SHIFT 10339#define MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT 0x04340#define MV88E6XXX_PORT_RESERVED_1A_DATA_PORT 0x05341#define MV88E6341_PORT_RESERVED_1A_FORCE_CMODE 0x8000342#define MV88E6341_PORT_RESERVED_1A_SGMII_AN 0x2000343 344int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,345 u16 *val);346int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,347 u16 val);348int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg,349 int bit, int val);350 351int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,352 int pause);353int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,354 phy_interface_t mode);355int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,356 phy_interface_t mode);357int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,358 phy_interface_t mode);359 360int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);361 362int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);363int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);364 365int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,366 int speed, int duplex);367int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,368 int speed, int duplex);369int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,370 int speed, int duplex);371int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,372 int speed, int duplex);373int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,374 int speed, int duplex);375int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,376 int speed, int duplex);377int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port,378 int speed, int duplex);379 380phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip,381 int port);382phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip,383 int port);384phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip,385 int port);386phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip,387 int port);388 389int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);390 391int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);392 393int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid);394int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);395 396int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid);397int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);398 399int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port,400 bool locked);401 402int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,403 u16 mode);404int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);405int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);406int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,407 enum mv88e6xxx_egress_mode mode);408int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,409 enum mv88e6xxx_frame_mode mode);410int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,411 enum mv88e6xxx_frame_mode mode);412int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip,413 int port, bool unicast);414int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip,415 int port, bool multicast);416int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port,417 bool unicast);418int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port,419 bool multicast);420int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port,421 enum mv88e6xxx_policy_mapping mapping,422 enum mv88e6xxx_policy_action action);423int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port,424 enum mv88e6xxx_policy_mapping mapping,425 enum mv88e6xxx_policy_action action);426int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,427 u16 etype);428int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip,429 enum mv88e6xxx_egress_direction direction,430 int port);431int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,432 int upstream_port);433int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);434int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,435 u16 etype);436int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,437 bool message_port);438int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port,439 bool trunk, u8 id);440int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,441 size_t size);442int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);443int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);444int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port,445 u16 pav);446int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,447 u8 out);448int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,449 u8 out);450int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,451 phy_interface_t mode);452int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,453 phy_interface_t mode);454int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,455 phy_interface_t mode);456int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,457 phy_interface_t mode);458int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);459int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);460int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port,461 bool drop_untagged);462int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map);463int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,464 int upstream_port);465int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port,466 enum mv88e6xxx_egress_direction direction,467 bool mirror);468 469int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);470int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);471 472int mv88e6xxx_port_hidden_write(struct mv88e6xxx_chip *chip, int block,473 int port, int reg, u16 val);474int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip);475int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port,476 int reg, u16 *val);477 478#endif /* _MV88E6XXX_PORT_H */479