2210 lines · c
1// SPDX-License-Identifier: GPL-2.02/* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.3 *4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>6 *7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 48 * integrated PHYs for the user facing ports, and an extension interface which9 * can be connected to the CPU - or another PHY - via either MII, RMII, or10 * RGMII. The switch is configured via the Realtek Simple Management Interface11 * (SMI), which uses the MDIO/MDC lines.12 *13 * Below is a simplified block diagram of the chip and its relevant interfaces.14 *15 * .-----------------------------------.16 * | |17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC |20 * UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC |21 * | |22 * CPU/PHY <-MII/RMII/RGMII---> Extension <---> Extension |23 * | interface 1 GMAC 1 |24 * | |25 * SMI driver/ <-MDC/SCL---> Management ~~~~~~~~~~~~~~ |26 * EEPROM <-MDIO/SDA--> interface ~REALTEK ~~~~~ |27 * | ~RTL8365MB ~~~ |28 * | ~GXXXC TAIWAN~ |29 * GPIO <--------------> Reset ~~~~~~~~~~~~~~ |30 * | |31 * Interrupt <----------> Link UP/DOWN events |32 * controller | |33 * '-----------------------------------'34 *35 * The driver uses DSA to integrate the 4 user and 1 extension ports into the36 * kernel. Netdevices are created for the user ports, as are PHY devices for37 * their integrated PHYs. The device tree firmware should also specify the link38 * partner of the extension port - either via a fixed-link or other phy-handle.39 * See the device tree bindings for more detailed information. Note that the40 * driver has only been tested with a fixed-link, but in principle it should not41 * matter.42 *43 * NOTE: Currently, only the RGMII interface is implemented in this driver.44 *45 * The interrupt line is asserted on link UP/DOWN events. The driver creates a46 * custom irqchip to handle this interrupt and demultiplex the events by reading47 * the status registers via SMI. Interrupts are then propagated to the relevant48 * PHY device.49 *50 * The EEPROM contains initial register values which the chip will read over I2C51 * upon hardware reset. It is also possible to omit the EEPROM. In both cases,52 * the driver will manually reprogram some registers using jam tables to reach53 * an initial state defined by the vendor driver.54 *55 * This Linux driver is written based on an OS-agnostic vendor driver from56 * Realtek. The reference GPL-licensed sources can be found in the OpenWrt57 * source tree under the name rtl8367c. The vendor driver claims to support a58 * number of similar switch controllers from Realtek, but the only hardware we59 * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under60 * the name RTL8367C. Although one wishes that the 'C' stood for some kind of61 * common hardware revision, there exist examples of chips with the suffix -VC62 * which are explicitly not supported by the rtl8367c driver and which instead63 * require the rtl8367d vendor driver. With all this uncertainty, the driver has64 * been modestly named rtl8365mb. Future implementors may wish to rename things65 * accordingly.66 *67 * In the same family of chips, some carry up to 8 user ports and up to 268 * extension ports. Where possible this driver tries to make things generic, but69 * more work must be done to support these configurations. According to70 * documentation from Realtek, the family should include the following chips:71 *72 * - RTL8363NB73 * - RTL8363NB-VB74 * - RTL8363SC75 * - RTL8363SC-VB76 * - RTL8364NB77 * - RTL8364NB-VB78 * - RTL8365MB-VC79 * - RTL8366SC80 * - RTL8367RB-VB81 * - RTL8367SB82 * - RTL8367S83 * - RTL8370MB84 * - RTL8310SR85 *86 * Some of the register logic for these additional chips has been skipped over87 * while implementing this driver. It is therefore not possible to assume that88 * things will work out-of-the-box for other chips, and a careful review of the89 * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be90 * one of the simpler chips.91 */92 93#include <linux/bitfield.h>94#include <linux/bitops.h>95#include <linux/interrupt.h>96#include <linux/irqdomain.h>97#include <linux/mutex.h>98#include <linux/of_irq.h>99#include <linux/regmap.h>100#include <linux/if_bridge.h>101#include <linux/if_vlan.h>102 103#include "realtek.h"104#include "realtek-smi.h"105#include "realtek-mdio.h"106#include "rtl83xx.h"107 108/* Family-specific data and limits */109#define RTL8365MB_PHYADDRMAX 7110#define RTL8365MB_NUM_PHYREGS 32111#define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1)112#define RTL8365MB_MAX_NUM_PORTS 11113#define RTL8365MB_MAX_NUM_EXTINTS 3114#define RTL8365MB_LEARN_LIMIT_MAX 2112115 116/* Chip identification registers */117#define RTL8365MB_CHIP_ID_REG 0x1300118 119#define RTL8365MB_CHIP_VER_REG 0x1301120 121#define RTL8365MB_MAGIC_REG 0x13C2122#define RTL8365MB_MAGIC_VALUE 0x0249123 124/* Chip reset register */125#define RTL8365MB_CHIP_RESET_REG 0x1322126#define RTL8365MB_CHIP_RESET_SW_MASK 0x0002127#define RTL8365MB_CHIP_RESET_HW_MASK 0x0001128 129/* Interrupt polarity register */130#define RTL8365MB_INTR_POLARITY_REG 0x1100131#define RTL8365MB_INTR_POLARITY_MASK 0x0001132#define RTL8365MB_INTR_POLARITY_HIGH 0133#define RTL8365MB_INTR_POLARITY_LOW 1134 135/* Interrupt control/status register - enable/check specific interrupt types */136#define RTL8365MB_INTR_CTRL_REG 0x1101137#define RTL8365MB_INTR_STATUS_REG 0x1102138#define RTL8365MB_INTR_SLIENT_START_2_MASK 0x1000139#define RTL8365MB_INTR_SLIENT_START_MASK 0x0800140#define RTL8365MB_INTR_ACL_ACTION_MASK 0x0200141#define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0x0100142#define RTL8365MB_INTR_INTERRUPT_8051_MASK 0x0080143#define RTL8365MB_INTR_LOOP_DETECTION_MASK 0x0040144#define RTL8365MB_INTR_GREEN_TIMER_MASK 0x0020145#define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0x0010146#define RTL8365MB_INTR_SPEED_CHANGE_MASK 0x0008147#define RTL8365MB_INTR_LEARN_OVER_MASK 0x0004148#define RTL8365MB_INTR_METER_EXCEEDED_MASK 0x0002149#define RTL8365MB_INTR_LINK_CHANGE_MASK 0x0001150#define RTL8365MB_INTR_ALL_MASK \151 (RTL8365MB_INTR_SLIENT_START_2_MASK | \152 RTL8365MB_INTR_SLIENT_START_MASK | \153 RTL8365MB_INTR_ACL_ACTION_MASK | \154 RTL8365MB_INTR_CABLE_DIAG_FIN_MASK | \155 RTL8365MB_INTR_INTERRUPT_8051_MASK | \156 RTL8365MB_INTR_LOOP_DETECTION_MASK | \157 RTL8365MB_INTR_GREEN_TIMER_MASK | \158 RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \159 RTL8365MB_INTR_SPEED_CHANGE_MASK | \160 RTL8365MB_INTR_LEARN_OVER_MASK | \161 RTL8365MB_INTR_METER_EXCEEDED_MASK | \162 RTL8365MB_INTR_LINK_CHANGE_MASK)163 164/* Per-port interrupt type status registers */165#define RTL8365MB_PORT_LINKDOWN_IND_REG 0x1106166#define RTL8365MB_PORT_LINKDOWN_IND_MASK 0x07FF167 168#define RTL8365MB_PORT_LINKUP_IND_REG 0x1107169#define RTL8365MB_PORT_LINKUP_IND_MASK 0x07FF170 171/* PHY indirect access registers */172#define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0x1F00173#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002174#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0175#define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1176#define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001177#define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1178#define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01179#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02180#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0)181#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5)182#define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8)183#define RTL8365MB_PHY_BASE 0x2000184#define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03185#define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0x1F04186 187/* PHY OCP address prefix register */188#define RTL8365MB_GPHY_OCP_MSB_0_REG 0x1D15189#define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0190#define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00191 192/* The PHY OCP addresses of PHY registers 0~31 start here */193#define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400194 195/* External interface port mode values - used in DIGITAL_INTERFACE_SELECT */196#define RTL8365MB_EXT_PORT_MODE_DISABLE 0197#define RTL8365MB_EXT_PORT_MODE_RGMII 1198#define RTL8365MB_EXT_PORT_MODE_MII_MAC 2199#define RTL8365MB_EXT_PORT_MODE_MII_PHY 3200#define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4201#define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5202#define RTL8365MB_EXT_PORT_MODE_GMII 6203#define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7204#define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8205#define RTL8365MB_EXT_PORT_MODE_SGMII 9206#define RTL8365MB_EXT_PORT_MODE_HSGMII 10207#define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11208#define RTL8365MB_EXT_PORT_MODE_1000X 12209#define RTL8365MB_EXT_PORT_MODE_100FX 13210 211/* External interface mode configuration registers 0~1 */212#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305 /* EXT0,EXT1 */213#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 /* EXT2 */214#define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \215 ((_extint) <= 1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \216 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \217 0x0)218#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \219 (0xF << (((_extint) % 2)))220#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \221 (((_extint) % 2) * 4)222 223/* External interface RGMII TX/RX delay configuration registers 0~2 */224#define RTL8365MB_EXT_RGMXF_REG0 0x1306 /* EXT0 */225#define RTL8365MB_EXT_RGMXF_REG1 0x1307 /* EXT1 */226#define RTL8365MB_EXT_RGMXF_REG2 0x13C5 /* EXT2 */227#define RTL8365MB_EXT_RGMXF_REG(_extint) \228 ((_extint) == 0 ? RTL8365MB_EXT_RGMXF_REG0 : \229 (_extint) == 1 ? RTL8365MB_EXT_RGMXF_REG1 : \230 (_extint) == 2 ? RTL8365MB_EXT_RGMXF_REG2 : \231 0x0)232#define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0x0007233#define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0x0008234 235/* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */236#define RTL8365MB_PORT_SPEED_10M 0237#define RTL8365MB_PORT_SPEED_100M 1238#define RTL8365MB_PORT_SPEED_1000M 2239 240/* External interface force configuration registers 0~2 */241#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */242#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311 /* EXT1 */243#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 /* EXT2 */244#define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extint) \245 ((_extint) == 0 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 : \246 (_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \247 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 : \248 0x0)249#define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000250#define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080251#define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040252#define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020253#define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010254#define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004255#define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003256 257/* CPU port mask register - controls which ports are treated as CPU ports */258#define RTL8365MB_CPU_PORT_MASK_REG 0x1219259#define RTL8365MB_CPU_PORT_MASK_MASK 0x07FF260 261/* CPU control register */262#define RTL8365MB_CPU_CTRL_REG 0x121A263#define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400264#define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0x0200265#define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0x0080266#define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0x0040267#define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0x0038268#define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0x0006269#define RTL8365MB_CPU_CTRL_EN_MASK 0x0001270 271/* Maximum packet length register */272#define RTL8365MB_CFG0_MAX_LEN_REG 0x088C273#define RTL8365MB_CFG0_MAX_LEN_MASK 0x3FFF274#define RTL8365MB_CFG0_MAX_LEN_MAX 0x3FFF275 276/* Port learning limit registers */277#define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0x0A20278#define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \279 (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport))280 281/* Port isolation (forwarding mask) registers */282#define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2283#define RTL8365MB_PORT_ISOLATION_REG(_physport) \284 (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport))285#define RTL8365MB_PORT_ISOLATION_MASK 0x07FF286 287/* MSTP port state registers - indexed by tree instance */288#define RTL8365MB_MSTI_CTRL_BASE 0x0A00289#define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \290 (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3))291#define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1)292#define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \293 (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport)))294 295/* MIB counter value registers */296#define RTL8365MB_MIB_COUNTER_BASE 0x1000297#define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x))298 299/* MIB counter address register */300#define RTL8365MB_MIB_ADDRESS_REG 0x1004301#define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0x007C302#define RTL8365MB_MIB_ADDRESS(_p, _x) \303 (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2)304 305#define RTL8365MB_MIB_CTRL0_REG 0x1005306#define RTL8365MB_MIB_CTRL0_RESET_MASK 0x0002307#define RTL8365MB_MIB_CTRL0_BUSY_MASK 0x0001308 309/* The DSA callback .get_stats64 runs in atomic context, so we are not allowed310 * to block. On the other hand, accessing MIB counters absolutely requires us to311 * block. The solution is thus to schedule work which polls the MIB counters312 * asynchronously and updates some private data, which the callback can then313 * fetch atomically. Three seconds should be a good enough polling interval.314 */315#define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ)316 317enum rtl8365mb_mib_counter_index {318 RTL8365MB_MIB_ifInOctets,319 RTL8365MB_MIB_dot3StatsFCSErrors,320 RTL8365MB_MIB_dot3StatsSymbolErrors,321 RTL8365MB_MIB_dot3InPauseFrames,322 RTL8365MB_MIB_dot3ControlInUnknownOpcodes,323 RTL8365MB_MIB_etherStatsFragments,324 RTL8365MB_MIB_etherStatsJabbers,325 RTL8365MB_MIB_ifInUcastPkts,326 RTL8365MB_MIB_etherStatsDropEvents,327 RTL8365MB_MIB_ifInMulticastPkts,328 RTL8365MB_MIB_ifInBroadcastPkts,329 RTL8365MB_MIB_inMldChecksumError,330 RTL8365MB_MIB_inIgmpChecksumError,331 RTL8365MB_MIB_inMldSpecificQuery,332 RTL8365MB_MIB_inMldGeneralQuery,333 RTL8365MB_MIB_inIgmpSpecificQuery,334 RTL8365MB_MIB_inIgmpGeneralQuery,335 RTL8365MB_MIB_inMldLeaves,336 RTL8365MB_MIB_inIgmpLeaves,337 RTL8365MB_MIB_etherStatsOctets,338 RTL8365MB_MIB_etherStatsUnderSizePkts,339 RTL8365MB_MIB_etherOversizeStats,340 RTL8365MB_MIB_etherStatsPkts64Octets,341 RTL8365MB_MIB_etherStatsPkts65to127Octets,342 RTL8365MB_MIB_etherStatsPkts128to255Octets,343 RTL8365MB_MIB_etherStatsPkts256to511Octets,344 RTL8365MB_MIB_etherStatsPkts512to1023Octets,345 RTL8365MB_MIB_etherStatsPkts1024to1518Octets,346 RTL8365MB_MIB_ifOutOctets,347 RTL8365MB_MIB_dot3StatsSingleCollisionFrames,348 RTL8365MB_MIB_dot3StatsMultipleCollisionFrames,349 RTL8365MB_MIB_dot3StatsDeferredTransmissions,350 RTL8365MB_MIB_dot3StatsLateCollisions,351 RTL8365MB_MIB_etherStatsCollisions,352 RTL8365MB_MIB_dot3StatsExcessiveCollisions,353 RTL8365MB_MIB_dot3OutPauseFrames,354 RTL8365MB_MIB_ifOutDiscards,355 RTL8365MB_MIB_dot1dTpPortInDiscards,356 RTL8365MB_MIB_ifOutUcastPkts,357 RTL8365MB_MIB_ifOutMulticastPkts,358 RTL8365MB_MIB_ifOutBroadcastPkts,359 RTL8365MB_MIB_outOampduPkts,360 RTL8365MB_MIB_inOampduPkts,361 RTL8365MB_MIB_inIgmpJoinsSuccess,362 RTL8365MB_MIB_inIgmpJoinsFail,363 RTL8365MB_MIB_inMldJoinsSuccess,364 RTL8365MB_MIB_inMldJoinsFail,365 RTL8365MB_MIB_inReportSuppressionDrop,366 RTL8365MB_MIB_inLeaveSuppressionDrop,367 RTL8365MB_MIB_outIgmpReports,368 RTL8365MB_MIB_outIgmpLeaves,369 RTL8365MB_MIB_outIgmpGeneralQuery,370 RTL8365MB_MIB_outIgmpSpecificQuery,371 RTL8365MB_MIB_outMldReports,372 RTL8365MB_MIB_outMldLeaves,373 RTL8365MB_MIB_outMldGeneralQuery,374 RTL8365MB_MIB_outMldSpecificQuery,375 RTL8365MB_MIB_inKnownMulticastPkts,376 RTL8365MB_MIB_END,377};378 379struct rtl8365mb_mib_counter {380 u32 offset;381 u32 length;382 const char *name;383};384 385#define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \386 [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name }387 388static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = {389 RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets),390 RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors),391 RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors),392 RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames),393 RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes),394 RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments),395 RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers),396 RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts),397 RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents),398 RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts),399 RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts),400 RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError),401 RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError),402 RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery),403 RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery),404 RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery),405 RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery),406 RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves),407 RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves),408 RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets),409 RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts),410 RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats),411 RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets),412 RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets),413 RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets),414 RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets),415 RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets),416 RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets),417 RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets),418 RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames),419 RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames),420 RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions),421 RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions),422 RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions),423 RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions),424 RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames),425 RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards),426 RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards),427 RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts),428 RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts),429 RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts),430 RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts),431 RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts),432 RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess),433 RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail),434 RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess),435 RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail),436 RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop),437 RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop),438 RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports),439 RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves),440 RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery),441 RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery),442 RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports),443 RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves),444 RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery),445 RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery),446 RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts),447};448 449static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END);450 451struct rtl8365mb_jam_tbl_entry {452 u16 reg;453 u16 val;454};455 456/* Lifted from the vendor driver sources */457static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = {458 { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 },459 { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA },460 { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 },461 { 0x1239, 0x0084 }, { 0x0301, 0x1000 }, { 0x1349, 0x001F },462 { 0x18E0, 0x4004 }, { 0x122B, 0x241C }, { 0x1305, 0xC000 },463 { 0x13F0, 0x0000 },464};465 466static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = {467 { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 },468 { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E },469 { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 },470 { 0x1D32, 0x0002 },471};472 473enum rtl8365mb_phy_interface_mode {474 RTL8365MB_PHY_INTERFACE_MODE_INVAL = 0,475 RTL8365MB_PHY_INTERFACE_MODE_INTERNAL = BIT(0),476 RTL8365MB_PHY_INTERFACE_MODE_MII = BIT(1),477 RTL8365MB_PHY_INTERFACE_MODE_TMII = BIT(2),478 RTL8365MB_PHY_INTERFACE_MODE_RMII = BIT(3),479 RTL8365MB_PHY_INTERFACE_MODE_RGMII = BIT(4),480 RTL8365MB_PHY_INTERFACE_MODE_SGMII = BIT(5),481 RTL8365MB_PHY_INTERFACE_MODE_HSGMII = BIT(6),482};483 484/**485 * struct rtl8365mb_extint - external interface info486 * @port: the port with an external interface487 * @id: the external interface ID, which is either 0, 1, or 2488 * @supported_interfaces: a bitmask of supported PHY interface modes489 *490 * Represents a mapping: port -> { id, supported_interfaces }. To be embedded491 * in &struct rtl8365mb_chip_info for every port with an external interface.492 */493struct rtl8365mb_extint {494 int port;495 int id;496 unsigned int supported_interfaces;497};498 499/**500 * struct rtl8365mb_chip_info - static chip-specific info501 * @name: human-readable chip name502 * @chip_id: chip identifier503 * @chip_ver: chip silicon revision504 * @extints: available external interfaces505 * @jam_table: chip-specific initialization jam table506 * @jam_size: size of the chip's jam table507 *508 * These data are specific to a given chip in the family of switches supported509 * by this driver. When adding support for another chip in the family, a new510 * chip info should be added to the rtl8365mb_chip_infos array.511 */512struct rtl8365mb_chip_info {513 const char *name;514 u32 chip_id;515 u32 chip_ver;516 const struct rtl8365mb_extint extints[RTL8365MB_MAX_NUM_EXTINTS];517 const struct rtl8365mb_jam_tbl_entry *jam_table;518 size_t jam_size;519};520 521/* Chip info for each supported switch in the family */522#define PHY_INTF(_mode) (RTL8365MB_PHY_INTERFACE_MODE_ ## _mode)523static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = {524 {525 .name = "RTL8365MB-VC",526 .chip_id = 0x6367,527 .chip_ver = 0x0040,528 .extints = {529 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) |530 PHY_INTF(RMII) | PHY_INTF(RGMII) },531 },532 .jam_table = rtl8365mb_init_jam_8365mb_vc,533 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),534 },535 {536 .name = "RTL8367S",537 .chip_id = 0x6367,538 .chip_ver = 0x00A0,539 .extints = {540 { 6, 1, PHY_INTF(SGMII) | PHY_INTF(HSGMII) },541 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) |542 PHY_INTF(RMII) | PHY_INTF(RGMII) },543 },544 .jam_table = rtl8365mb_init_jam_8365mb_vc,545 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),546 },547 {548 .name = "RTL8367RB-VB",549 .chip_id = 0x6367,550 .chip_ver = 0x0020,551 .extints = {552 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) |553 PHY_INTF(RMII) | PHY_INTF(RGMII) },554 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) |555 PHY_INTF(RMII) | PHY_INTF(RGMII) },556 },557 .jam_table = rtl8365mb_init_jam_8365mb_vc,558 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc),559 },560};561 562enum rtl8365mb_stp_state {563 RTL8365MB_STP_STATE_DISABLED = 0,564 RTL8365MB_STP_STATE_BLOCKING = 1,565 RTL8365MB_STP_STATE_LEARNING = 2,566 RTL8365MB_STP_STATE_FORWARDING = 3,567};568 569enum rtl8365mb_cpu_insert {570 RTL8365MB_CPU_INSERT_TO_ALL = 0,571 RTL8365MB_CPU_INSERT_TO_TRAPPING = 1,572 RTL8365MB_CPU_INSERT_TO_NONE = 2,573};574 575enum rtl8365mb_cpu_position {576 RTL8365MB_CPU_POS_AFTER_SA = 0,577 RTL8365MB_CPU_POS_BEFORE_CRC = 1,578};579 580enum rtl8365mb_cpu_format {581 RTL8365MB_CPU_FORMAT_8BYTES = 0,582 RTL8365MB_CPU_FORMAT_4BYTES = 1,583};584 585enum rtl8365mb_cpu_rxlen {586 RTL8365MB_CPU_RXLEN_72BYTES = 0,587 RTL8365MB_CPU_RXLEN_64BYTES = 1,588};589 590/**591 * struct rtl8365mb_cpu - CPU port configuration592 * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames593 * @mask: port mask of ports that parse should parse CPU tags594 * @trap_port: forward trapped frames to this port595 * @insert: CPU tag insertion mode in switch->CPU frames596 * @position: position of CPU tag in frame597 * @rx_length: minimum CPU RX length598 * @format: CPU tag format599 *600 * Represents the CPU tagging and CPU port configuration of the switch. These601 * settings are configurable at runtime.602 */603struct rtl8365mb_cpu {604 bool enable;605 u32 mask;606 u32 trap_port;607 enum rtl8365mb_cpu_insert insert;608 enum rtl8365mb_cpu_position position;609 enum rtl8365mb_cpu_rxlen rx_length;610 enum rtl8365mb_cpu_format format;611};612 613/**614 * struct rtl8365mb_port - private per-port data615 * @priv: pointer to parent realtek_priv data616 * @index: DSA port index, same as dsa_port::index617 * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic618 * access via rtl8365mb_get_stats64619 * @stats_lock: protect the stats structure during read/update620 * @mib_work: delayed work for polling MIB counters621 */622struct rtl8365mb_port {623 struct realtek_priv *priv;624 unsigned int index;625 struct rtnl_link_stats64 stats;626 spinlock_t stats_lock;627 struct delayed_work mib_work;628};629 630/**631 * struct rtl8365mb - driver private data632 * @priv: pointer to parent realtek_priv data633 * @irq: registered IRQ or zero634 * @chip_info: chip-specific info about the attached switch635 * @cpu: CPU tagging and CPU port configuration for this chip636 * @mib_lock: prevent concurrent reads of MIB counters637 * @ports: per-port data638 *639 * Private data for this driver.640 */641struct rtl8365mb {642 struct realtek_priv *priv;643 int irq;644 const struct rtl8365mb_chip_info *chip_info;645 struct rtl8365mb_cpu cpu;646 struct mutex mib_lock;647 struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS];648};649 650static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv)651{652 u32 val;653 654 return regmap_read_poll_timeout(priv->map_nolock,655 RTL8365MB_INDIRECT_ACCESS_STATUS_REG,656 val, !val, 10, 100);657}658 659static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy,660 u32 ocp_addr)661{662 u32 val;663 int ret;664 665 /* Set OCP prefix */666 val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr);667 ret = regmap_update_bits(668 priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG,669 RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK,670 FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val));671 if (ret)672 return ret;673 674 /* Set PHY register address */675 val = RTL8365MB_PHY_BASE;676 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy);677 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK,678 ocp_addr >> 1);679 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK,680 ocp_addr >> 6);681 ret = regmap_write(priv->map_nolock,682 RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, val);683 if (ret)684 return ret;685 686 return 0;687}688 689static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy,690 u32 ocp_addr, u16 *data)691{692 u32 val;693 int ret;694 695 rtl83xx_lock(priv);696 697 ret = rtl8365mb_phy_poll_busy(priv);698 if (ret)699 goto out;700 701 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);702 if (ret)703 goto out;704 705 /* Execute read operation */706 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,707 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |708 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,709 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ);710 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,711 val);712 if (ret)713 goto out;714 715 ret = rtl8365mb_phy_poll_busy(priv);716 if (ret)717 goto out;718 719 /* Get PHY register data */720 ret = regmap_read(priv->map_nolock,721 RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, &val);722 if (ret)723 goto out;724 725 *data = val & 0xFFFF;726 727out:728 rtl83xx_unlock(priv);729 730 return ret;731}732 733static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy,734 u32 ocp_addr, u16 data)735{736 u32 val;737 int ret;738 739 rtl83xx_lock(priv);740 741 ret = rtl8365mb_phy_poll_busy(priv);742 if (ret)743 goto out;744 745 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr);746 if (ret)747 goto out;748 749 /* Set PHY register data */750 ret = regmap_write(priv->map_nolock,751 RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, data);752 if (ret)753 goto out;754 755 /* Execute write operation */756 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK,757 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) |758 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK,759 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE);760 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,761 val);762 if (ret)763 goto out;764 765 ret = rtl8365mb_phy_poll_busy(priv);766 if (ret)767 goto out;768 769out:770 rtl83xx_unlock(priv);771 772 return 0;773}774 775static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum)776{777 u32 ocp_addr;778 u16 val;779 int ret;780 781 if (phy > RTL8365MB_PHYADDRMAX)782 return -EINVAL;783 784 if (regnum > RTL8365MB_PHYREGMAX)785 return -EINVAL;786 787 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2;788 789 ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val);790 if (ret) {791 dev_err(priv->dev,792 "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy,793 regnum, ocp_addr, ret);794 return ret;795 }796 797 dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n",798 phy, regnum, ocp_addr, val);799 800 return val;801}802 803static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum,804 u16 val)805{806 u32 ocp_addr;807 int ret;808 809 if (phy > RTL8365MB_PHYADDRMAX)810 return -EINVAL;811 812 if (regnum > RTL8365MB_PHYREGMAX)813 return -EINVAL;814 815 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2;816 817 ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val);818 if (ret) {819 dev_err(priv->dev,820 "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy,821 regnum, ocp_addr, ret);822 return ret;823 }824 825 dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n",826 phy, regnum, ocp_addr, val);827 828 return 0;829}830 831static const struct rtl8365mb_extint *832rtl8365mb_get_port_extint(struct realtek_priv *priv, int port)833{834 struct rtl8365mb *mb = priv->chip_data;835 int i;836 837 for (i = 0; i < RTL8365MB_MAX_NUM_EXTINTS; i++) {838 const struct rtl8365mb_extint *extint =839 &mb->chip_info->extints[i];840 841 if (!extint->supported_interfaces)842 continue;843 844 if (extint->port == port)845 return extint;846 }847 848 return NULL;849}850 851static enum dsa_tag_protocol852rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port,853 enum dsa_tag_protocol mp)854{855 struct realtek_priv *priv = ds->priv;856 struct rtl8365mb_cpu *cpu;857 struct rtl8365mb *mb;858 859 mb = priv->chip_data;860 cpu = &mb->cpu;861 862 if (cpu->position == RTL8365MB_CPU_POS_BEFORE_CRC)863 return DSA_TAG_PROTO_RTL8_4T;864 865 return DSA_TAG_PROTO_RTL8_4;866}867 868static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port,869 phy_interface_t interface)870{871 const struct rtl8365mb_extint *extint =872 rtl8365mb_get_port_extint(priv, port);873 struct dsa_switch *ds = &priv->ds;874 struct device_node *dn;875 struct dsa_port *dp;876 int tx_delay = 0;877 int rx_delay = 0;878 u32 val;879 int ret;880 881 if (!extint)882 return -ENODEV;883 884 dp = dsa_to_port(ds, port);885 dn = dp->dn;886 887 /* Set the RGMII TX/RX delay888 *889 * The Realtek vendor driver indicates the following possible890 * configuration settings:891 *892 * TX delay:893 * 0 = no delay, 1 = 2 ns delay894 * RX delay:895 * 0 = no delay, 7 = maximum delay896 * Each step is approximately 0.3 ns, so the maximum delay is about897 * 2.1 ns.898 *899 * The vendor driver also states that this must be configured *before*900 * forcing the external interface into a particular mode, which is done901 * in the rtl8365mb_phylink_mac_link_{up,down} functions.902 *903 * Only configure an RGMII TX (resp. RX) delay if the904 * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is905 * specified. We ignore the detail of the RGMII interface mode906 * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only907 * property.908 */909 if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) {910 val = val / 1000; /* convert to ns */911 912 if (val == 0 || val == 2)913 tx_delay = val / 2;914 else915 dev_warn(priv->dev,916 "RGMII TX delay must be 0 or 2 ns\n");917 }918 919 if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) {920 val = DIV_ROUND_CLOSEST(val, 300); /* convert to 0.3 ns step */921 922 if (val <= 7)923 rx_delay = val;924 else925 dev_warn(priv->dev,926 "RGMII RX delay must be 0 to 2.1 ns\n");927 }928 929 ret = regmap_update_bits(930 priv->map, RTL8365MB_EXT_RGMXF_REG(extint->id),931 RTL8365MB_EXT_RGMXF_TXDELAY_MASK |932 RTL8365MB_EXT_RGMXF_RXDELAY_MASK,933 FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) |934 FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay));935 if (ret)936 return ret;937 938 ret = regmap_update_bits(939 priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(extint->id),940 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(extint->id),941 RTL8365MB_EXT_PORT_MODE_RGMII942 << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(943 extint->id));944 if (ret)945 return ret;946 947 return 0;948}949 950static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port,951 bool link, int speed, int duplex,952 bool tx_pause, bool rx_pause)953{954 const struct rtl8365mb_extint *extint =955 rtl8365mb_get_port_extint(priv, port);956 u32 r_tx_pause;957 u32 r_rx_pause;958 u32 r_duplex;959 u32 r_speed;960 u32 r_link;961 int val;962 int ret;963 964 if (!extint)965 return -ENODEV;966 967 if (link) {968 /* Force the link up with the desired configuration */969 r_link = 1;970 r_rx_pause = rx_pause ? 1 : 0;971 r_tx_pause = tx_pause ? 1 : 0;972 973 if (speed == SPEED_1000) {974 r_speed = RTL8365MB_PORT_SPEED_1000M;975 } else if (speed == SPEED_100) {976 r_speed = RTL8365MB_PORT_SPEED_100M;977 } else if (speed == SPEED_10) {978 r_speed = RTL8365MB_PORT_SPEED_10M;979 } else {980 dev_err(priv->dev, "unsupported port speed %s\n",981 phy_speed_to_str(speed));982 return -EINVAL;983 }984 985 if (duplex == DUPLEX_FULL) {986 r_duplex = 1;987 } else if (duplex == DUPLEX_HALF) {988 r_duplex = 0;989 } else {990 dev_err(priv->dev, "unsupported duplex %s\n",991 phy_duplex_to_str(duplex));992 return -EINVAL;993 }994 } else {995 /* Force the link down and reset any programmed configuration */996 r_link = 0;997 r_tx_pause = 0;998 r_rx_pause = 0;999 r_speed = 0;1000 r_duplex = 0;1001 }1002 1003 val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) |1004 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK,1005 r_tx_pause) |1006 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK,1007 r_rx_pause) |1008 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) |1009 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK,1010 r_duplex) |1011 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed);1012 ret = regmap_write(priv->map,1013 RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id),1014 val);1015 if (ret)1016 return ret;1017 1018 return 0;1019}1020 1021static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port,1022 struct phylink_config *config)1023{1024 const struct rtl8365mb_extint *extint =1025 rtl8365mb_get_port_extint(ds->priv, port);1026 1027 config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |1028 MAC_10 | MAC_100 | MAC_1000FD;1029 1030 if (!extint) {1031 __set_bit(PHY_INTERFACE_MODE_INTERNAL,1032 config->supported_interfaces);1033 1034 /* GMII is the default interface mode for phylib, so1035 * we have to support it for ports with integrated PHY.1036 */1037 __set_bit(PHY_INTERFACE_MODE_GMII,1038 config->supported_interfaces);1039 return;1040 }1041 1042 /* Populate according to the modes supported by _this driver_,1043 * not necessarily the modes supported by the hardware, some of1044 * which remain unimplemented.1045 */1046 1047 if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII)1048 phy_interface_set_rgmii(config->supported_interfaces);1049}1050 1051static void rtl8365mb_phylink_mac_config(struct phylink_config *config,1052 unsigned int mode,1053 const struct phylink_link_state *state)1054{1055 struct dsa_port *dp = dsa_phylink_to_port(config);1056 struct realtek_priv *priv = dp->ds->priv;1057 u8 port = dp->index;1058 int ret;1059 1060 if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) {1061 dev_err(priv->dev,1062 "port %d supports only conventional PHY or fixed-link\n",1063 port);1064 return;1065 }1066 1067 if (phy_interface_mode_is_rgmii(state->interface)) {1068 ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface);1069 if (ret)1070 dev_err(priv->dev,1071 "failed to configure RGMII mode on port %d: %d\n",1072 port, ret);1073 return;1074 }1075 1076 /* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also1077 * supports1078 */1079}1080 1081static void rtl8365mb_phylink_mac_link_down(struct phylink_config *config,1082 unsigned int mode,1083 phy_interface_t interface)1084{1085 struct dsa_port *dp = dsa_phylink_to_port(config);1086 struct realtek_priv *priv = dp->ds->priv;1087 struct rtl8365mb_port *p;1088 struct rtl8365mb *mb;1089 u8 port = dp->index;1090 int ret;1091 1092 mb = priv->chip_data;1093 p = &mb->ports[port];1094 cancel_delayed_work_sync(&p->mib_work);1095 1096 if (phy_interface_mode_is_rgmii(interface)) {1097 ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0,1098 false, false);1099 if (ret)1100 dev_err(priv->dev,1101 "failed to reset forced mode on port %d: %d\n",1102 port, ret);1103 1104 return;1105 }1106}1107 1108static void rtl8365mb_phylink_mac_link_up(struct phylink_config *config,1109 struct phy_device *phydev,1110 unsigned int mode,1111 phy_interface_t interface,1112 int speed, int duplex, bool tx_pause,1113 bool rx_pause)1114{1115 struct dsa_port *dp = dsa_phylink_to_port(config);1116 struct realtek_priv *priv = dp->ds->priv;1117 struct rtl8365mb_port *p;1118 struct rtl8365mb *mb;1119 u8 port = dp->index;1120 int ret;1121 1122 mb = priv->chip_data;1123 p = &mb->ports[port];1124 schedule_delayed_work(&p->mib_work, 0);1125 1126 if (phy_interface_mode_is_rgmii(interface)) {1127 ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed,1128 duplex, tx_pause,1129 rx_pause);1130 if (ret)1131 dev_err(priv->dev,1132 "failed to force mode on port %d: %d\n", port,1133 ret);1134 1135 return;1136 }1137}1138 1139static int rtl8365mb_port_change_mtu(struct dsa_switch *ds, int port,1140 int new_mtu)1141{1142 struct realtek_priv *priv = ds->priv;1143 int frame_size;1144 1145 /* When a new MTU is set, DSA always sets the CPU port's MTU to the1146 * largest MTU of the user ports. Because the switch only has a global1147 * RX length register, only allowing CPU port here is enough.1148 */1149 if (!dsa_is_cpu_port(ds, port))1150 return 0;1151 1152 frame_size = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;1153 1154 dev_dbg(priv->dev, "changing mtu to %d (frame size: %d)\n",1155 new_mtu, frame_size);1156 1157 return regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG,1158 RTL8365MB_CFG0_MAX_LEN_MASK,1159 FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK,1160 frame_size));1161}1162 1163static int rtl8365mb_port_max_mtu(struct dsa_switch *ds, int port)1164{1165 return RTL8365MB_CFG0_MAX_LEN_MAX - VLAN_ETH_HLEN - ETH_FCS_LEN;1166}1167 1168static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port,1169 u8 state)1170{1171 struct realtek_priv *priv = ds->priv;1172 enum rtl8365mb_stp_state val;1173 int msti = 0;1174 1175 switch (state) {1176 case BR_STATE_DISABLED:1177 val = RTL8365MB_STP_STATE_DISABLED;1178 break;1179 case BR_STATE_BLOCKING:1180 case BR_STATE_LISTENING:1181 val = RTL8365MB_STP_STATE_BLOCKING;1182 break;1183 case BR_STATE_LEARNING:1184 val = RTL8365MB_STP_STATE_LEARNING;1185 break;1186 case BR_STATE_FORWARDING:1187 val = RTL8365MB_STP_STATE_FORWARDING;1188 break;1189 default:1190 dev_err(priv->dev, "invalid STP state: %u\n", state);1191 return;1192 }1193 1194 regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port),1195 RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port),1196 val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port));1197}1198 1199static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port,1200 bool enable)1201{1202 /* Enable/disable learning by limiting the number of L2 addresses the1203 * port can learn. Realtek documentation states that a limit of zero1204 * disables learning. When enabling learning, set it to the chip's1205 * maximum.1206 */1207 return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port),1208 enable ? RTL8365MB_LEARN_LIMIT_MAX : 0);1209}1210 1211static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port,1212 u32 mask)1213{1214 return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask);1215}1216 1217static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port,1218 u32 offset, u32 length, u64 *mibvalue)1219{1220 u64 tmpvalue = 0;1221 u32 val;1222 int ret;1223 int i;1224 1225 /* The MIB address is an SRAM address. We request a particular address1226 * and then poll the control register before reading the value from some1227 * counter registers.1228 */1229 ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG,1230 RTL8365MB_MIB_ADDRESS(port, offset));1231 if (ret)1232 return ret;1233 1234 /* Poll for completion */1235 ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val,1236 !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK),1237 10, 100);1238 if (ret)1239 return ret;1240 1241 /* Presumably this indicates a MIB counter read failure */1242 if (val & RTL8365MB_MIB_CTRL0_RESET_MASK)1243 return -EIO;1244 1245 /* There are four MIB counter registers each holding a 16 bit word of a1246 * MIB counter. Depending on the offset, we should read from the upper1247 * two or lower two registers. In case the MIB counter is 4 words, we1248 * read from all four registers.1249 */1250 if (length == 4)1251 offset = 3;1252 else1253 offset = (offset + 1) % 4;1254 1255 /* Read the MIB counter 16 bits at a time */1256 for (i = 0; i < length; i++) {1257 ret = regmap_read(priv->map,1258 RTL8365MB_MIB_COUNTER_REG(offset - i), &val);1259 if (ret)1260 return ret;1261 1262 tmpvalue = ((tmpvalue) << 16) | (val & 0xFFFF);1263 }1264 1265 /* Only commit the result if no error occurred */1266 *mibvalue = tmpvalue;1267 1268 return 0;1269}1270 1271static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data)1272{1273 struct realtek_priv *priv = ds->priv;1274 struct rtl8365mb *mb;1275 int ret;1276 int i;1277 1278 mb = priv->chip_data;1279 1280 mutex_lock(&mb->mib_lock);1281 for (i = 0; i < RTL8365MB_MIB_END; i++) {1282 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];1283 1284 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,1285 mib->length, &data[i]);1286 if (ret) {1287 dev_err(priv->dev,1288 "failed to read port %d counters: %d\n", port,1289 ret);1290 break;1291 }1292 }1293 mutex_unlock(&mb->mib_lock);1294}1295 1296static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data)1297{1298 int i;1299 1300 if (stringset != ETH_SS_STATS)1301 return;1302 1303 for (i = 0; i < RTL8365MB_MIB_END; i++) {1304 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];1305 ethtool_puts(&data, mib->name);1306 }1307}1308 1309static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset)1310{1311 if (sset != ETH_SS_STATS)1312 return -EOPNOTSUPP;1313 1314 return RTL8365MB_MIB_END;1315}1316 1317static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port,1318 struct ethtool_eth_phy_stats *phy_stats)1319{1320 struct realtek_priv *priv = ds->priv;1321 struct rtl8365mb_mib_counter *mib;1322 struct rtl8365mb *mb;1323 1324 mb = priv->chip_data;1325 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors];1326 1327 mutex_lock(&mb->mib_lock);1328 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length,1329 &phy_stats->SymbolErrorDuringCarrier);1330 mutex_unlock(&mb->mib_lock);1331}1332 1333static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port,1334 struct ethtool_eth_mac_stats *mac_stats)1335{1336 u64 cnt[RTL8365MB_MIB_END] = {1337 [RTL8365MB_MIB_ifOutOctets] = 1,1338 [RTL8365MB_MIB_ifOutUcastPkts] = 1,1339 [RTL8365MB_MIB_ifOutMulticastPkts] = 1,1340 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1,1341 [RTL8365MB_MIB_dot3OutPauseFrames] = 1,1342 [RTL8365MB_MIB_ifOutDiscards] = 1,1343 [RTL8365MB_MIB_ifInOctets] = 1,1344 [RTL8365MB_MIB_ifInUcastPkts] = 1,1345 [RTL8365MB_MIB_ifInMulticastPkts] = 1,1346 [RTL8365MB_MIB_ifInBroadcastPkts] = 1,1347 [RTL8365MB_MIB_dot3InPauseFrames] = 1,1348 [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1,1349 [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1,1350 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1,1351 [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1,1352 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1,1353 [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1,1354 1355 };1356 struct realtek_priv *priv = ds->priv;1357 struct rtl8365mb *mb;1358 int ret;1359 int i;1360 1361 mb = priv->chip_data;1362 1363 mutex_lock(&mb->mib_lock);1364 for (i = 0; i < RTL8365MB_MIB_END; i++) {1365 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i];1366 1367 /* Only fetch required MIB counters (marked = 1 above) */1368 if (!cnt[i])1369 continue;1370 1371 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,1372 mib->length, &cnt[i]);1373 if (ret)1374 break;1375 }1376 mutex_unlock(&mb->mib_lock);1377 1378 /* The RTL8365MB-VC exposes MIB objects, which we have to translate into1379 * IEEE 802.3 Managed Objects. This is not always completely faithful,1380 * but we try out best. See RFC 3635 for a detailed treatment of the1381 * subject.1382 */1383 1384 mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] +1385 cnt[RTL8365MB_MIB_ifOutMulticastPkts] +1386 cnt[RTL8365MB_MIB_ifOutBroadcastPkts] +1387 cnt[RTL8365MB_MIB_dot3OutPauseFrames] -1388 cnt[RTL8365MB_MIB_ifOutDiscards];1389 mac_stats->SingleCollisionFrames =1390 cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames];1391 mac_stats->MultipleCollisionFrames =1392 cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames];1393 mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] +1394 cnt[RTL8365MB_MIB_ifInMulticastPkts] +1395 cnt[RTL8365MB_MIB_ifInBroadcastPkts] +1396 cnt[RTL8365MB_MIB_dot3InPauseFrames];1397 mac_stats->FrameCheckSequenceErrors =1398 cnt[RTL8365MB_MIB_dot3StatsFCSErrors];1399 mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] -1400 18 * mac_stats->FramesTransmittedOK;1401 mac_stats->FramesWithDeferredXmissions =1402 cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions];1403 mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];1404 mac_stats->FramesAbortedDueToXSColls =1405 cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions];1406 mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] -1407 18 * mac_stats->FramesReceivedOK;1408 mac_stats->MulticastFramesXmittedOK =1409 cnt[RTL8365MB_MIB_ifOutMulticastPkts];1410 mac_stats->BroadcastFramesXmittedOK =1411 cnt[RTL8365MB_MIB_ifOutBroadcastPkts];1412 mac_stats->MulticastFramesReceivedOK =1413 cnt[RTL8365MB_MIB_ifInMulticastPkts];1414 mac_stats->BroadcastFramesReceivedOK =1415 cnt[RTL8365MB_MIB_ifInBroadcastPkts];1416}1417 1418static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port,1419 struct ethtool_eth_ctrl_stats *ctrl_stats)1420{1421 struct realtek_priv *priv = ds->priv;1422 struct rtl8365mb_mib_counter *mib;1423 struct rtl8365mb *mb;1424 1425 mb = priv->chip_data;1426 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes];1427 1428 mutex_lock(&mb->mib_lock);1429 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length,1430 &ctrl_stats->UnsupportedOpcodesReceived);1431 mutex_unlock(&mb->mib_lock);1432}1433 1434static void rtl8365mb_stats_update(struct realtek_priv *priv, int port)1435{1436 u64 cnt[RTL8365MB_MIB_END] = {1437 [RTL8365MB_MIB_ifOutOctets] = 1,1438 [RTL8365MB_MIB_ifOutUcastPkts] = 1,1439 [RTL8365MB_MIB_ifOutMulticastPkts] = 1,1440 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1,1441 [RTL8365MB_MIB_ifOutDiscards] = 1,1442 [RTL8365MB_MIB_ifInOctets] = 1,1443 [RTL8365MB_MIB_ifInUcastPkts] = 1,1444 [RTL8365MB_MIB_ifInMulticastPkts] = 1,1445 [RTL8365MB_MIB_ifInBroadcastPkts] = 1,1446 [RTL8365MB_MIB_etherStatsDropEvents] = 1,1447 [RTL8365MB_MIB_etherStatsCollisions] = 1,1448 [RTL8365MB_MIB_etherStatsFragments] = 1,1449 [RTL8365MB_MIB_etherStatsJabbers] = 1,1450 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1,1451 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1,1452 };1453 struct rtl8365mb *mb = priv->chip_data;1454 struct rtnl_link_stats64 *stats;1455 int ret;1456 int i;1457 1458 stats = &mb->ports[port].stats;1459 1460 mutex_lock(&mb->mib_lock);1461 for (i = 0; i < RTL8365MB_MIB_END; i++) {1462 struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i];1463 1464 /* Only fetch required MIB counters (marked = 1 above) */1465 if (!cnt[i])1466 continue;1467 1468 ret = rtl8365mb_mib_counter_read(priv, port, c->offset,1469 c->length, &cnt[i]);1470 if (ret)1471 break;1472 }1473 mutex_unlock(&mb->mib_lock);1474 1475 /* Don't update statistics if there was an error reading the counters */1476 if (ret)1477 return;1478 1479 spin_lock(&mb->ports[port].stats_lock);1480 1481 stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] +1482 cnt[RTL8365MB_MIB_ifInMulticastPkts] +1483 cnt[RTL8365MB_MIB_ifInBroadcastPkts] -1484 cnt[RTL8365MB_MIB_ifOutDiscards];1485 1486 stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] +1487 cnt[RTL8365MB_MIB_ifOutMulticastPkts] +1488 cnt[RTL8365MB_MIB_ifOutBroadcastPkts];1489 1490 /* if{In,Out}Octets includes FCS - remove it */1491 stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets;1492 stats->tx_bytes =1493 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets;1494 1495 stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents];1496 stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards];1497 1498 stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts];1499 stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions];1500 1501 stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] +1502 cnt[RTL8365MB_MIB_etherStatsJabbers];1503 stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors];1504 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors;1505 1506 stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards];1507 stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];1508 stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors;1509 1510 spin_unlock(&mb->ports[port].stats_lock);1511}1512 1513static void rtl8365mb_stats_poll(struct work_struct *work)1514{1515 struct rtl8365mb_port *p = container_of(to_delayed_work(work),1516 struct rtl8365mb_port,1517 mib_work);1518 struct realtek_priv *priv = p->priv;1519 1520 rtl8365mb_stats_update(priv, p->index);1521 1522 schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES);1523}1524 1525static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port,1526 struct rtnl_link_stats64 *s)1527{1528 struct realtek_priv *priv = ds->priv;1529 struct rtl8365mb_port *p;1530 struct rtl8365mb *mb;1531 1532 mb = priv->chip_data;1533 p = &mb->ports[port];1534 1535 spin_lock(&p->stats_lock);1536 memcpy(s, &p->stats, sizeof(*s));1537 spin_unlock(&p->stats_lock);1538}1539 1540static void rtl8365mb_stats_setup(struct realtek_priv *priv)1541{1542 struct rtl8365mb *mb = priv->chip_data;1543 struct dsa_switch *ds = &priv->ds;1544 int i;1545 1546 /* Per-chip global mutex to protect MIB counter access, since doing1547 * so requires accessing a series of registers in a particular order.1548 */1549 mutex_init(&mb->mib_lock);1550 1551 for (i = 0; i < priv->num_ports; i++) {1552 struct rtl8365mb_port *p = &mb->ports[i];1553 1554 if (dsa_is_unused_port(ds, i))1555 continue;1556 1557 /* Per-port spinlock to protect the stats64 data */1558 spin_lock_init(&p->stats_lock);1559 1560 /* This work polls the MIB counters and keeps the stats64 data1561 * up-to-date.1562 */1563 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll);1564 }1565}1566 1567static void rtl8365mb_stats_teardown(struct realtek_priv *priv)1568{1569 struct rtl8365mb *mb = priv->chip_data;1570 struct dsa_switch *ds = &priv->ds;1571 int i;1572 1573 for (i = 0; i < priv->num_ports; i++) {1574 struct rtl8365mb_port *p = &mb->ports[i];1575 1576 if (dsa_is_unused_port(ds, i))1577 continue;1578 1579 cancel_delayed_work_sync(&p->mib_work);1580 }1581}1582 1583static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg,1584 u32 *val)1585{1586 int ret;1587 1588 ret = regmap_read(priv->map, reg, val);1589 if (ret)1590 return ret;1591 1592 return regmap_write(priv->map, reg, *val);1593}1594 1595static irqreturn_t rtl8365mb_irq(int irq, void *data)1596{1597 struct realtek_priv *priv = data;1598 unsigned long line_changes = 0;1599 u32 stat;1600 int line;1601 int ret;1602 1603 ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG,1604 &stat);1605 if (ret)1606 goto out_error;1607 1608 if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) {1609 u32 linkdown_ind;1610 u32 linkup_ind;1611 u32 val;1612 1613 ret = rtl8365mb_get_and_clear_status_reg(1614 priv, RTL8365MB_PORT_LINKUP_IND_REG, &val);1615 if (ret)1616 goto out_error;1617 1618 linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val);1619 1620 ret = rtl8365mb_get_and_clear_status_reg(1621 priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val);1622 if (ret)1623 goto out_error;1624 1625 linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val);1626 1627 line_changes = linkup_ind | linkdown_ind;1628 }1629 1630 if (!line_changes)1631 goto out_none;1632 1633 for_each_set_bit(line, &line_changes, priv->num_ports) {1634 int child_irq = irq_find_mapping(priv->irqdomain, line);1635 1636 handle_nested_irq(child_irq);1637 }1638 1639 return IRQ_HANDLED;1640 1641out_error:1642 dev_err(priv->dev, "failed to read interrupt status: %d\n", ret);1643 1644out_none:1645 return IRQ_NONE;1646}1647 1648static struct irq_chip rtl8365mb_irq_chip = {1649 .name = "rtl8365mb",1650 /* The hardware doesn't support masking IRQs on a per-port basis */1651};1652 1653static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq,1654 irq_hw_number_t hwirq)1655{1656 irq_set_chip_data(irq, domain->host_data);1657 irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq);1658 irq_set_nested_thread(irq, 1);1659 irq_set_noprobe(irq);1660 1661 return 0;1662}1663 1664static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq)1665{1666 irq_set_nested_thread(irq, 0);1667 irq_set_chip_and_handler(irq, NULL, NULL);1668 irq_set_chip_data(irq, NULL);1669}1670 1671static const struct irq_domain_ops rtl8365mb_irqdomain_ops = {1672 .map = rtl8365mb_irq_map,1673 .unmap = rtl8365mb_irq_unmap,1674 .xlate = irq_domain_xlate_onecell,1675};1676 1677static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable)1678{1679 return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG,1680 RTL8365MB_INTR_LINK_CHANGE_MASK,1681 FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK,1682 enable ? 1 : 0));1683}1684 1685static int rtl8365mb_irq_enable(struct realtek_priv *priv)1686{1687 return rtl8365mb_set_irq_enable(priv, true);1688}1689 1690static int rtl8365mb_irq_disable(struct realtek_priv *priv)1691{1692 return rtl8365mb_set_irq_enable(priv, false);1693}1694 1695static int rtl8365mb_irq_setup(struct realtek_priv *priv)1696{1697 struct rtl8365mb *mb = priv->chip_data;1698 struct device_node *intc;1699 u32 irq_trig;1700 int virq;1701 int irq;1702 u32 val;1703 int ret;1704 int i;1705 1706 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");1707 if (!intc) {1708 dev_err(priv->dev, "missing child interrupt-controller node\n");1709 return -EINVAL;1710 }1711 1712 /* rtl8365mb IRQs cascade off this one */1713 irq = of_irq_get(intc, 0);1714 if (irq <= 0) {1715 if (irq != -EPROBE_DEFER)1716 dev_err(priv->dev, "failed to get parent irq: %d\n",1717 irq);1718 ret = irq ? irq : -EINVAL;1719 goto out_put_node;1720 }1721 1722 priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports,1723 &rtl8365mb_irqdomain_ops, priv);1724 if (!priv->irqdomain) {1725 dev_err(priv->dev, "failed to add irq domain\n");1726 ret = -ENOMEM;1727 goto out_put_node;1728 }1729 1730 for (i = 0; i < priv->num_ports; i++) {1731 virq = irq_create_mapping(priv->irqdomain, i);1732 if (!virq) {1733 dev_err(priv->dev,1734 "failed to create irq domain mapping\n");1735 ret = -EINVAL;1736 goto out_remove_irqdomain;1737 }1738 1739 irq_set_parent(virq, irq);1740 }1741 1742 /* Configure chip interrupt signal polarity */1743 irq_trig = irq_get_trigger_type(irq);1744 switch (irq_trig) {1745 case IRQF_TRIGGER_RISING:1746 case IRQF_TRIGGER_HIGH:1747 val = RTL8365MB_INTR_POLARITY_HIGH;1748 break;1749 case IRQF_TRIGGER_FALLING:1750 case IRQF_TRIGGER_LOW:1751 val = RTL8365MB_INTR_POLARITY_LOW;1752 break;1753 default:1754 dev_err(priv->dev, "unsupported irq trigger type %u\n",1755 irq_trig);1756 ret = -EINVAL;1757 goto out_remove_irqdomain;1758 }1759 1760 ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG,1761 RTL8365MB_INTR_POLARITY_MASK,1762 FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val));1763 if (ret)1764 goto out_remove_irqdomain;1765 1766 /* Disable the interrupt in case the chip has it enabled on reset */1767 ret = rtl8365mb_irq_disable(priv);1768 if (ret)1769 goto out_remove_irqdomain;1770 1771 /* Clear the interrupt status register */1772 ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG,1773 RTL8365MB_INTR_ALL_MASK);1774 if (ret)1775 goto out_remove_irqdomain;1776 1777 ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT,1778 "rtl8365mb", priv);1779 if (ret) {1780 dev_err(priv->dev, "failed to request irq: %d\n", ret);1781 goto out_remove_irqdomain;1782 }1783 1784 /* Store the irq so that we know to free it during teardown */1785 mb->irq = irq;1786 1787 ret = rtl8365mb_irq_enable(priv);1788 if (ret)1789 goto out_free_irq;1790 1791 of_node_put(intc);1792 1793 return 0;1794 1795out_free_irq:1796 free_irq(mb->irq, priv);1797 mb->irq = 0;1798 1799out_remove_irqdomain:1800 for (i = 0; i < priv->num_ports; i++) {1801 virq = irq_find_mapping(priv->irqdomain, i);1802 irq_dispose_mapping(virq);1803 }1804 1805 irq_domain_remove(priv->irqdomain);1806 priv->irqdomain = NULL;1807 1808out_put_node:1809 of_node_put(intc);1810 1811 return ret;1812}1813 1814static void rtl8365mb_irq_teardown(struct realtek_priv *priv)1815{1816 struct rtl8365mb *mb = priv->chip_data;1817 int virq;1818 int i;1819 1820 if (mb->irq) {1821 free_irq(mb->irq, priv);1822 mb->irq = 0;1823 }1824 1825 if (priv->irqdomain) {1826 for (i = 0; i < priv->num_ports; i++) {1827 virq = irq_find_mapping(priv->irqdomain, i);1828 irq_dispose_mapping(virq);1829 }1830 1831 irq_domain_remove(priv->irqdomain);1832 priv->irqdomain = NULL;1833 }1834}1835 1836static int rtl8365mb_cpu_config(struct realtek_priv *priv)1837{1838 struct rtl8365mb *mb = priv->chip_data;1839 struct rtl8365mb_cpu *cpu = &mb->cpu;1840 u32 val;1841 int ret;1842 1843 ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG,1844 RTL8365MB_CPU_PORT_MASK_MASK,1845 FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK,1846 cpu->mask));1847 if (ret)1848 return ret;1849 1850 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) |1851 FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) |1852 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) |1853 FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) |1854 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) |1855 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) |1856 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK,1857 cpu->trap_port >> 3 & 0x1);1858 ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val);1859 if (ret)1860 return ret;1861 1862 return 0;1863}1864 1865static int rtl8365mb_change_tag_protocol(struct dsa_switch *ds,1866 enum dsa_tag_protocol proto)1867{1868 struct realtek_priv *priv = ds->priv;1869 struct rtl8365mb_cpu *cpu;1870 struct rtl8365mb *mb;1871 1872 mb = priv->chip_data;1873 cpu = &mb->cpu;1874 1875 switch (proto) {1876 case DSA_TAG_PROTO_RTL8_4:1877 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES;1878 cpu->position = RTL8365MB_CPU_POS_AFTER_SA;1879 break;1880 case DSA_TAG_PROTO_RTL8_4T:1881 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES;1882 cpu->position = RTL8365MB_CPU_POS_BEFORE_CRC;1883 break;1884 /* The switch also supports a 4-byte format, similar to rtl4a but with1885 * the same 0x04 8-bit version and probably 8-bit port source/dest.1886 * There is no public doc about it. Not supported yet and it will probably1887 * never be.1888 */1889 default:1890 return -EPROTONOSUPPORT;1891 }1892 1893 return rtl8365mb_cpu_config(priv);1894}1895 1896static int rtl8365mb_switch_init(struct realtek_priv *priv)1897{1898 struct rtl8365mb *mb = priv->chip_data;1899 const struct rtl8365mb_chip_info *ci;1900 int ret;1901 int i;1902 1903 ci = mb->chip_info;1904 1905 /* Do any chip-specific init jam before getting to the common stuff */1906 if (ci->jam_table) {1907 for (i = 0; i < ci->jam_size; i++) {1908 ret = regmap_write(priv->map, ci->jam_table[i].reg,1909 ci->jam_table[i].val);1910 if (ret)1911 return ret;1912 }1913 }1914 1915 /* Common init jam */1916 for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) {1917 ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg,1918 rtl8365mb_init_jam_common[i].val);1919 if (ret)1920 return ret;1921 }1922 1923 return 0;1924}1925 1926static int rtl8365mb_reset_chip(struct realtek_priv *priv)1927{1928 u32 val;1929 1930 priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG,1931 FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1));1932 1933 /* Realtek documentation says the chip needs 1 second to reset. Sleep1934 * for 100 ms before accessing any registers to prevent ACK timeouts.1935 */1936 msleep(100);1937 return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val,1938 !(val & RTL8365MB_CHIP_RESET_HW_MASK),1939 20000, 1e6);1940}1941 1942static int rtl8365mb_setup(struct dsa_switch *ds)1943{1944 struct realtek_priv *priv = ds->priv;1945 struct rtl8365mb_cpu *cpu;1946 struct dsa_port *cpu_dp;1947 struct rtl8365mb *mb;1948 int ret;1949 int i;1950 1951 mb = priv->chip_data;1952 cpu = &mb->cpu;1953 1954 ret = rtl8365mb_reset_chip(priv);1955 if (ret) {1956 dev_err(priv->dev, "failed to reset chip: %d\n", ret);1957 goto out_error;1958 }1959 1960 /* Configure switch to vendor-defined initial state */1961 ret = rtl8365mb_switch_init(priv);1962 if (ret) {1963 dev_err(priv->dev, "failed to initialize switch: %d\n", ret);1964 goto out_error;1965 }1966 1967 /* Set up cascading IRQs */1968 ret = rtl8365mb_irq_setup(priv);1969 if (ret == -EPROBE_DEFER)1970 return ret;1971 else if (ret)1972 dev_info(priv->dev, "no interrupt support\n");1973 1974 /* Configure CPU tagging */1975 dsa_switch_for_each_cpu_port(cpu_dp, ds) {1976 cpu->mask |= BIT(cpu_dp->index);1977 1978 if (cpu->trap_port == RTL8365MB_MAX_NUM_PORTS)1979 cpu->trap_port = cpu_dp->index;1980 }1981 cpu->enable = cpu->mask > 0;1982 ret = rtl8365mb_cpu_config(priv);1983 if (ret)1984 goto out_teardown_irq;1985 1986 /* Configure ports */1987 for (i = 0; i < priv->num_ports; i++) {1988 struct rtl8365mb_port *p = &mb->ports[i];1989 1990 if (dsa_is_unused_port(ds, i))1991 continue;1992 1993 /* Forward only to the CPU */1994 ret = rtl8365mb_port_set_isolation(priv, i, cpu->mask);1995 if (ret)1996 goto out_teardown_irq;1997 1998 /* Disable learning */1999 ret = rtl8365mb_port_set_learning(priv, i, false);2000 if (ret)2001 goto out_teardown_irq;2002 2003 /* Set the initial STP state of all ports to DISABLED, otherwise2004 * ports will still forward frames to the CPU despite being2005 * administratively down by default.2006 */2007 rtl8365mb_port_stp_state_set(ds, i, BR_STATE_DISABLED);2008 2009 /* Set up per-port private data */2010 p->priv = priv;2011 p->index = i;2012 }2013 2014 ret = rtl8365mb_port_change_mtu(ds, cpu->trap_port, ETH_DATA_LEN);2015 if (ret)2016 goto out_teardown_irq;2017 2018 ret = rtl83xx_setup_user_mdio(ds);2019 if (ret) {2020 dev_err(priv->dev, "could not set up MDIO bus\n");2021 goto out_teardown_irq;2022 }2023 2024 /* Start statistics counter polling */2025 rtl8365mb_stats_setup(priv);2026 2027 return 0;2028 2029out_teardown_irq:2030 rtl8365mb_irq_teardown(priv);2031 2032out_error:2033 return ret;2034}2035 2036static void rtl8365mb_teardown(struct dsa_switch *ds)2037{2038 struct realtek_priv *priv = ds->priv;2039 2040 rtl8365mb_stats_teardown(priv);2041 rtl8365mb_irq_teardown(priv);2042}2043 2044static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver)2045{2046 int ret;2047 2048 /* For some reason we have to write a magic value to an arbitrary2049 * register whenever accessing the chip ID/version registers.2050 */2051 ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE);2052 if (ret)2053 return ret;2054 2055 ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id);2056 if (ret)2057 return ret;2058 2059 ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver);2060 if (ret)2061 return ret;2062 2063 /* Reset magic register */2064 ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0);2065 if (ret)2066 return ret;2067 2068 return 0;2069}2070 2071static int rtl8365mb_detect(struct realtek_priv *priv)2072{2073 struct rtl8365mb *mb = priv->chip_data;2074 u32 chip_id;2075 u32 chip_ver;2076 int ret;2077 int i;2078 2079 ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver);2080 if (ret) {2081 dev_err(priv->dev, "failed to read chip id and version: %d\n",2082 ret);2083 return ret;2084 }2085 2086 for (i = 0; i < ARRAY_SIZE(rtl8365mb_chip_infos); i++) {2087 const struct rtl8365mb_chip_info *ci = &rtl8365mb_chip_infos[i];2088 2089 if (ci->chip_id == chip_id && ci->chip_ver == chip_ver) {2090 mb->chip_info = ci;2091 break;2092 }2093 }2094 2095 if (!mb->chip_info) {2096 dev_err(priv->dev,2097 "unrecognized switch (id=0x%04x, ver=0x%04x)", chip_id,2098 chip_ver);2099 return -ENODEV;2100 }2101 2102 dev_info(priv->dev, "found an %s switch\n", mb->chip_info->name);2103 2104 priv->num_ports = RTL8365MB_MAX_NUM_PORTS;2105 mb->priv = priv;2106 mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS;2107 mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;2108 mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA;2109 mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES;2110 mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES;2111 2112 return 0;2113}2114 2115static const struct phylink_mac_ops rtl8365mb_phylink_mac_ops = {2116 .mac_config = rtl8365mb_phylink_mac_config,2117 .mac_link_down = rtl8365mb_phylink_mac_link_down,2118 .mac_link_up = rtl8365mb_phylink_mac_link_up,2119};2120 2121static const struct dsa_switch_ops rtl8365mb_switch_ops = {2122 .get_tag_protocol = rtl8365mb_get_tag_protocol,2123 .change_tag_protocol = rtl8365mb_change_tag_protocol,2124 .setup = rtl8365mb_setup,2125 .teardown = rtl8365mb_teardown,2126 .phylink_get_caps = rtl8365mb_phylink_get_caps,2127 .port_stp_state_set = rtl8365mb_port_stp_state_set,2128 .get_strings = rtl8365mb_get_strings,2129 .get_ethtool_stats = rtl8365mb_get_ethtool_stats,2130 .get_sset_count = rtl8365mb_get_sset_count,2131 .get_eth_phy_stats = rtl8365mb_get_phy_stats,2132 .get_eth_mac_stats = rtl8365mb_get_mac_stats,2133 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats,2134 .get_stats64 = rtl8365mb_get_stats64,2135 .port_change_mtu = rtl8365mb_port_change_mtu,2136 .port_max_mtu = rtl8365mb_port_max_mtu,2137};2138 2139static const struct realtek_ops rtl8365mb_ops = {2140 .detect = rtl8365mb_detect,2141 .phy_read = rtl8365mb_phy_read,2142 .phy_write = rtl8365mb_phy_write,2143};2144 2145const struct realtek_variant rtl8365mb_variant = {2146 .ds_ops = &rtl8365mb_switch_ops,2147 .ops = &rtl8365mb_ops,2148 .phylink_mac_ops = &rtl8365mb_phylink_mac_ops,2149 .clk_delay = 10,2150 .cmd_read = 0xb9,2151 .cmd_write = 0xb8,2152 .chip_data_sz = sizeof(struct rtl8365mb),2153};2154 2155static const struct of_device_id rtl8365mb_of_match[] = {2156 { .compatible = "realtek,rtl8365mb", .data = &rtl8365mb_variant, },2157 { /* sentinel */ },2158};2159MODULE_DEVICE_TABLE(of, rtl8365mb_of_match);2160 2161static struct platform_driver rtl8365mb_smi_driver = {2162 .driver = {2163 .name = "rtl8365mb-smi",2164 .of_match_table = rtl8365mb_of_match,2165 },2166 .probe = realtek_smi_probe,2167 .remove_new = realtek_smi_remove,2168 .shutdown = realtek_smi_shutdown,2169};2170 2171static struct mdio_driver rtl8365mb_mdio_driver = {2172 .mdiodrv.driver = {2173 .name = "rtl8365mb-mdio",2174 .of_match_table = rtl8365mb_of_match,2175 },2176 .probe = realtek_mdio_probe,2177 .remove = realtek_mdio_remove,2178 .shutdown = realtek_mdio_shutdown,2179};2180 2181static int rtl8365mb_init(void)2182{2183 int ret;2184 2185 ret = realtek_mdio_driver_register(&rtl8365mb_mdio_driver);2186 if (ret)2187 return ret;2188 2189 ret = realtek_smi_driver_register(&rtl8365mb_smi_driver);2190 if (ret) {2191 realtek_mdio_driver_unregister(&rtl8365mb_mdio_driver);2192 return ret;2193 }2194 2195 return 0;2196}2197module_init(rtl8365mb_init);2198 2199static void __exit rtl8365mb_exit(void)2200{2201 realtek_smi_driver_unregister(&rtl8365mb_smi_driver);2202 realtek_mdio_driver_unregister(&rtl8365mb_mdio_driver);2203}2204module_exit(rtl8365mb_exit);2205 2206MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>");2207MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch");2208MODULE_LICENSE("GPL");2209MODULE_IMPORT_NS(REALTEK_DSA);2210