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1// SPDX-License-Identifier: GPL-2.02/* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch3 *4 * This is a sparsely documented chip, the only viable documentation seems5 * to be a patched up code drop from the vendor that appear in various6 * GPL source trees.7 *8 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>10 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>11 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>12 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>13 */14 15#include <linux/bitops.h>16#include <linux/etherdevice.h>17#include <linux/if_bridge.h>18#include <linux/if_vlan.h>19#include <linux/interrupt.h>20#include <linux/irqdomain.h>21#include <linux/irqchip/chained_irq.h>22#include <linux/of_irq.h>23#include <linux/regmap.h>24 25#include "realtek.h"26#include "realtek-smi.h"27#include "realtek-mdio.h"28#include "rtl83xx.h"29 30#define RTL8366RB_PORT_NUM_CPU 531#define RTL8366RB_NUM_PORTS 632#define RTL8366RB_PHY_NO_MAX 433#define RTL8366RB_PHY_ADDR_MAX 3134 35/* Switch Global Configuration register */36#define RTL8366RB_SGCR 0x000037#define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)38#define RTL8366RB_SGCR_MAX_LENGTH(a) ((a) << 4)39#define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)40#define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)41#define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)42#define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)43#define RTL8366RB_SGCR_MAX_LENGTH_16000 RTL8366RB_SGCR_MAX_LENGTH(0x3)44#define RTL8366RB_SGCR_EN_VLAN BIT(13)45#define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)46 47/* Port Enable Control register */48#define RTL8366RB_PECR 0x000149 50/* Switch per-port learning disablement register */51#define RTL8366RB_PORT_LEARNDIS_CTRL 0x000252 53/* Security control, actually aging register */54#define RTL8366RB_SECURITY_CTRL 0x000355 56#define RTL8366RB_SSCR2 0x000457#define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)58 59/* Port Mode Control registers */60#define RTL8366RB_PMC0 0x000561#define RTL8366RB_PMC0_SPI BIT(0)62#define RTL8366RB_PMC0_EN_AUTOLOAD BIT(1)63#define RTL8366RB_PMC0_PROBE BIT(2)64#define RTL8366RB_PMC0_DIS_BISR BIT(3)65#define RTL8366RB_PMC0_ADCTEST BIT(4)66#define RTL8366RB_PMC0_SRAM_DIAG BIT(5)67#define RTL8366RB_PMC0_EN_SCAN BIT(6)68#define RTL8366RB_PMC0_P4_IOMODE_SHIFT 769#define RTL8366RB_PMC0_P4_IOMODE_MASK GENMASK(9, 7)70#define RTL8366RB_PMC0_P5_IOMODE_SHIFT 1071#define RTL8366RB_PMC0_P5_IOMODE_MASK GENMASK(12, 10)72#define RTL8366RB_PMC0_SDSMODE_SHIFT 1373#define RTL8366RB_PMC0_SDSMODE_MASK GENMASK(15, 13)74#define RTL8366RB_PMC1 0x000675 76/* Port Mirror Control Register */77#define RTL8366RB_PMCR 0x000778#define RTL8366RB_PMCR_SOURCE_PORT(a) (a)79#define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f80#define RTL8366RB_PMCR_MONITOR_PORT(a) ((a) << 4)81#define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f082#define RTL8366RB_PMCR_MIRROR_RX BIT(8)83#define RTL8366RB_PMCR_MIRROR_TX BIT(9)84#define RTL8366RB_PMCR_MIRROR_SPC BIT(10)85#define RTL8366RB_PMCR_MIRROR_ISO BIT(11)86 87/* bits 0..7 = port 0, bits 8..15 = port 1 */88#define RTL8366RB_PAACR0 0x001089/* bits 0..7 = port 2, bits 8..15 = port 3 */90#define RTL8366RB_PAACR1 0x001191/* bits 0..7 = port 4, bits 8..15 = port 5 */92#define RTL8366RB_PAACR2 0x001293#define RTL8366RB_PAACR_SPEED_10M 094#define RTL8366RB_PAACR_SPEED_100M 195#define RTL8366RB_PAACR_SPEED_1000M 296#define RTL8366RB_PAACR_FULL_DUPLEX BIT(2)97#define RTL8366RB_PAACR_LINK_UP BIT(4)98#define RTL8366RB_PAACR_TX_PAUSE BIT(5)99#define RTL8366RB_PAACR_RX_PAUSE BIT(6)100#define RTL8366RB_PAACR_AN BIT(7)101 102/* bits 0..7 = port 0, bits 8..15 = port 1 */103#define RTL8366RB_PSTAT0 0x0014104/* bits 0..7 = port 2, bits 8..15 = port 3 */105#define RTL8366RB_PSTAT1 0x0015106/* bits 0..7 = port 4, bits 8..15 = port 5 */107#define RTL8366RB_PSTAT2 0x0016108 109#define RTL8366RB_POWER_SAVING_REG 0x0021110 111/* Spanning tree status (STP) control, two bits per port per FID */112#define RTL8366RB_STP_STATE_BASE 0x0050 /* 0x0050..0x0057 */113#define RTL8366RB_STP_STATE_DISABLED 0x0114#define RTL8366RB_STP_STATE_BLOCKING 0x1115#define RTL8366RB_STP_STATE_LEARNING 0x2116#define RTL8366RB_STP_STATE_FORWARDING 0x3117#define RTL8366RB_STP_MASK GENMASK(1, 0)118#define RTL8366RB_STP_STATE(port, state) \119 ((state) << ((port) * 2))120#define RTL8366RB_STP_STATE_MASK(port) \121 RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)122 123/* CPU port control reg */124#define RTL8366RB_CPU_CTRL_REG 0x0061125#define RTL8366RB_CPU_PORTS_MSK 0x00FF126/* Disables inserting custom tag length/type 0x8899 */127#define RTL8366RB_CPU_NO_TAG BIT(15)128#define RTL8366RB_CPU_TAG_SIZE 4129 130#define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */131#define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */132#define RTL8366RB_SMAR2 0x0072 /* bits 32..47 */133 134#define RTL8366RB_RESET_CTRL_REG 0x0100135#define RTL8366RB_CHIP_CTRL_RESET_HW BIT(0)136#define RTL8366RB_CHIP_CTRL_RESET_SW BIT(1)137 138#define RTL8366RB_CHIP_ID_REG 0x0509139#define RTL8366RB_CHIP_ID_8366 0x5937140#define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A141#define RTL8366RB_CHIP_VERSION_MASK 0xf142 143/* PHY registers control */144#define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000145#define RTL8366RB_PHY_CTRL_READ BIT(0)146#define RTL8366RB_PHY_CTRL_WRITE 0147#define RTL8366RB_PHY_ACCESS_BUSY_REG 0x8001148#define RTL8366RB_PHY_INT_BUSY BIT(0)149#define RTL8366RB_PHY_EXT_BUSY BIT(4)150#define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002151#define RTL8366RB_PHY_EXT_CTRL_REG 0x8010152#define RTL8366RB_PHY_EXT_WRDATA_REG 0x8011153#define RTL8366RB_PHY_EXT_RDDATA_REG 0x8012154 155#define RTL8366RB_PHY_REG_MASK 0x1f156#define RTL8366RB_PHY_PAGE_OFFSET 5157#define RTL8366RB_PHY_PAGE_MASK (0xf << 5)158#define RTL8366RB_PHY_NO_OFFSET 9159#define RTL8366RB_PHY_NO_MASK (0x1f << 9)160 161/* VLAN Ingress Control Register 1, one bit per port.162 * bit 0 .. 5 will make the switch drop ingress frames without163 * VID such as untagged or priority-tagged frames for respective164 * port.165 * bit 6 .. 11 will make the switch drop ingress frames carrying166 * a C-tag with VID != 0 for respective port.167 */168#define RTL8366RB_VLAN_INGRESS_CTRL1_REG 0x037E169#define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) (BIT((port)) | BIT((port) + 6))170 171/* VLAN Ingress Control Register 2, one bit per port.172 * bit0 .. bit5 will make the switch drop all ingress frames with173 * a VLAN classification that does not include the port is in its174 * member set.175 */176#define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f177 178/* LED control registers */179/* The LED blink rate is global; it is used by all triggers in all groups. */180#define RTL8366RB_LED_BLINKRATE_REG 0x0430181#define RTL8366RB_LED_BLINKRATE_MASK 0x0007182#define RTL8366RB_LED_BLINKRATE_28MS 0x0000183#define RTL8366RB_LED_BLINKRATE_56MS 0x0001184#define RTL8366RB_LED_BLINKRATE_84MS 0x0002185#define RTL8366RB_LED_BLINKRATE_111MS 0x0003186#define RTL8366RB_LED_BLINKRATE_222MS 0x0004187#define RTL8366RB_LED_BLINKRATE_446MS 0x0005188 189/* LED trigger event for each group */190#define RTL8366RB_LED_CTRL_REG 0x0431191#define RTL8366RB_LED_CTRL_OFFSET(led_group) \192 (4 * (led_group))193#define RTL8366RB_LED_CTRL_MASK(led_group) \194 (0xf << RTL8366RB_LED_CTRL_OFFSET(led_group))195 196/* The RTL8366RB_LED_X_X registers are used to manually set the LED state only197 * when the corresponding LED group in RTL8366RB_LED_CTRL_REG is198 * RTL8366RB_LEDGROUP_FORCE. Otherwise, it is ignored.199 */200#define RTL8366RB_LED_0_1_CTRL_REG 0x0432201#define RTL8366RB_LED_2_3_CTRL_REG 0x0433202#define RTL8366RB_LED_X_X_CTRL_REG(led_group) \203 ((led_group) <= 1 ? \204 RTL8366RB_LED_0_1_CTRL_REG : \205 RTL8366RB_LED_2_3_CTRL_REG)206#define RTL8366RB_LED_0_X_CTRL_MASK GENMASK(5, 0)207#define RTL8366RB_LED_X_1_CTRL_MASK GENMASK(11, 6)208#define RTL8366RB_LED_2_X_CTRL_MASK GENMASK(5, 0)209#define RTL8366RB_LED_X_3_CTRL_MASK GENMASK(11, 6)210 211#define RTL8366RB_MIB_COUNT 33212#define RTL8366RB_GLOBAL_MIB_COUNT 1213#define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050214#define RTL8366RB_MIB_COUNTER_BASE 0x1000215#define RTL8366RB_MIB_CTRL_REG 0x13F0216#define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC217#define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)218#define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)219#define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))220#define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)221 222#define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063223#define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \224 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)225#define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf226#define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))227 228#define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C229#define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185230 231#define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180232#define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01233#define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01234 235#define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3)236 237#define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014238#define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003239#define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004240#define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010241#define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020242#define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040243#define RTL8366RB_PORT_STATUS_AN_MASK 0x0080244 245#define RTL8366RB_NUM_VLANS 16246#define RTL8366RB_NUM_LEDGROUPS 4247#define RTL8366RB_NUM_VIDS 4096248#define RTL8366RB_PRIORITYMAX 7249#define RTL8366RB_NUM_FIDS 8250#define RTL8366RB_FIDMAX 7251 252#define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */253#define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */254#define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */255#define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */256#define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */257 258#define RTL8366RB_PORT_CPU BIT(5) /* CPU port */259 260#define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \261 RTL8366RB_PORT_2 | \262 RTL8366RB_PORT_3 | \263 RTL8366RB_PORT_4 | \264 RTL8366RB_PORT_5 | \265 RTL8366RB_PORT_CPU)266 267#define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \268 RTL8366RB_PORT_2 | \269 RTL8366RB_PORT_3 | \270 RTL8366RB_PORT_4 | \271 RTL8366RB_PORT_5)272 273#define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \274 RTL8366RB_PORT_2 | \275 RTL8366RB_PORT_3 | \276 RTL8366RB_PORT_4)277 278#define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU279 280/* First configuration word per member config, VID and prio */281#define RTL8366RB_VLAN_VID_MASK 0xfff282#define RTL8366RB_VLAN_PRIORITY_SHIFT 12283#define RTL8366RB_VLAN_PRIORITY_MASK 0x7284/* Second configuration word per member config, member and untagged */285#define RTL8366RB_VLAN_UNTAG_SHIFT 8286#define RTL8366RB_VLAN_UNTAG_MASK 0xff287#define RTL8366RB_VLAN_MEMBER_MASK 0xff288/* Third config word per member config, STAG currently unused */289#define RTL8366RB_VLAN_STAG_MBR_MASK 0xff290#define RTL8366RB_VLAN_STAG_MBR_SHIFT 8291#define RTL8366RB_VLAN_STAG_IDX_MASK 0x7292#define RTL8366RB_VLAN_STAG_IDX_SHIFT 5293#define RTL8366RB_VLAN_FID_MASK 0x7294 295/* Port ingress bandwidth control */296#define RTL8366RB_IB_BASE 0x0200297#define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + (pnum))298#define RTL8366RB_IB_BDTH_MASK 0x3fff299#define RTL8366RB_IB_PREIFG BIT(14)300 301/* Port egress bandwidth control */302#define RTL8366RB_EB_BASE 0x02d1303#define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + (pnum))304#define RTL8366RB_EB_BDTH_MASK 0x3fff305#define RTL8366RB_EB_PREIFG_REG 0x02f8306#define RTL8366RB_EB_PREIFG BIT(9)307 308#define RTL8366RB_BDTH_SW_MAX 1048512 /* 1048576? */309#define RTL8366RB_BDTH_UNIT 64310#define RTL8366RB_BDTH_REG_DEFAULT 16383311 312/* QOS */313#define RTL8366RB_QOS BIT(15)314/* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */315#define RTL8366RB_QOS_DEFAULT_PREIFG 1316 317/* Interrupt handling */318#define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440319#define RTL8366RB_INTERRUPT_POLARITY BIT(0)320#define RTL8366RB_P4_RGMII_LED BIT(2)321#define RTL8366RB_INTERRUPT_MASK_REG 0x0441322#define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0)323#define RTL8366RB_INTERRUPT_ACLEXCEED BIT(8)324#define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9)325#define RTL8366RB_INTERRUPT_P4_FIBER BIT(12)326#define RTL8366RB_INTERRUPT_P4_UTP BIT(13)327#define RTL8366RB_INTERRUPT_VALID (RTL8366RB_INTERRUPT_LINK_CHGALL | \328 RTL8366RB_INTERRUPT_ACLEXCEED | \329 RTL8366RB_INTERRUPT_STORMEXCEED | \330 RTL8366RB_INTERRUPT_P4_FIBER | \331 RTL8366RB_INTERRUPT_P4_UTP)332#define RTL8366RB_INTERRUPT_STATUS_REG 0x0442333#define RTL8366RB_NUM_INTERRUPT 14 /* 0..13 */334 335/* Port isolation registers */336#define RTL8366RB_PORT_ISO_BASE 0x0F08337#define RTL8366RB_PORT_ISO(pnum) (RTL8366RB_PORT_ISO_BASE + (pnum))338#define RTL8366RB_PORT_ISO_EN BIT(0)339#define RTL8366RB_PORT_ISO_PORTS_MASK GENMASK(7, 1)340#define RTL8366RB_PORT_ISO_PORTS(pmask) ((pmask) << 1)341 342/* bits 0..5 enable force when cleared */343#define RTL8366RB_MAC_FORCE_CTRL_REG 0x0F11344 345#define RTL8366RB_OAM_PARSER_REG 0x0F14346#define RTL8366RB_OAM_MULTIPLEXER_REG 0x0F15347 348#define RTL8366RB_GREEN_FEATURE_REG 0x0F51349#define RTL8366RB_GREEN_FEATURE_MSK 0x0007350#define RTL8366RB_GREEN_FEATURE_TX BIT(0)351#define RTL8366RB_GREEN_FEATURE_RX BIT(2)352 353enum rtl8366_ledgroup_mode {354 RTL8366RB_LEDGROUP_OFF = 0x0,355 RTL8366RB_LEDGROUP_DUP_COL = 0x1,356 RTL8366RB_LEDGROUP_LINK_ACT = 0x2,357 RTL8366RB_LEDGROUP_SPD1000 = 0x3,358 RTL8366RB_LEDGROUP_SPD100 = 0x4,359 RTL8366RB_LEDGROUP_SPD10 = 0x5,360 RTL8366RB_LEDGROUP_SPD1000_ACT = 0x6,361 RTL8366RB_LEDGROUP_SPD100_ACT = 0x7,362 RTL8366RB_LEDGROUP_SPD10_ACT = 0x8,363 RTL8366RB_LEDGROUP_SPD100_10_ACT = 0x9,364 RTL8366RB_LEDGROUP_FIBER = 0xa,365 RTL8366RB_LEDGROUP_AN_FAULT = 0xb,366 RTL8366RB_LEDGROUP_LINK_RX = 0xc,367 RTL8366RB_LEDGROUP_LINK_TX = 0xd,368 RTL8366RB_LEDGROUP_MASTER = 0xe,369 RTL8366RB_LEDGROUP_FORCE = 0xf,370 371 __RTL8366RB_LEDGROUP_MODE_MAX372};373 374struct rtl8366rb_led {375 u8 port_num;376 u8 led_group;377 struct realtek_priv *priv;378 struct led_classdev cdev;379};380 381/**382 * struct rtl8366rb - RTL8366RB-specific data383 * @max_mtu: per-port max MTU setting384 * @pvid_enabled: if PVID is set for respective port385 * @leds: per-port and per-ledgroup led info386 */387struct rtl8366rb {388 unsigned int max_mtu[RTL8366RB_NUM_PORTS];389 bool pvid_enabled[RTL8366RB_NUM_PORTS];390 struct rtl8366rb_led leds[RTL8366RB_NUM_PORTS][RTL8366RB_NUM_LEDGROUPS];391};392 393static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {394 { 0, 0, 4, "IfInOctets" },395 { 0, 4, 4, "EtherStatsOctets" },396 { 0, 8, 2, "EtherStatsUnderSizePkts" },397 { 0, 10, 2, "EtherFragments" },398 { 0, 12, 2, "EtherStatsPkts64Octets" },399 { 0, 14, 2, "EtherStatsPkts65to127Octets" },400 { 0, 16, 2, "EtherStatsPkts128to255Octets" },401 { 0, 18, 2, "EtherStatsPkts256to511Octets" },402 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },403 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },404 { 0, 24, 2, "EtherOversizeStats" },405 { 0, 26, 2, "EtherStatsJabbers" },406 { 0, 28, 2, "IfInUcastPkts" },407 { 0, 30, 2, "EtherStatsMulticastPkts" },408 { 0, 32, 2, "EtherStatsBroadcastPkts" },409 { 0, 34, 2, "EtherStatsDropEvents" },410 { 0, 36, 2, "Dot3StatsFCSErrors" },411 { 0, 38, 2, "Dot3StatsSymbolErrors" },412 { 0, 40, 2, "Dot3InPauseFrames" },413 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },414 { 0, 44, 4, "IfOutOctets" },415 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },416 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },417 { 0, 52, 2, "Dot3sDeferredTransmissions" },418 { 0, 54, 2, "Dot3StatsLateCollisions" },419 { 0, 56, 2, "EtherStatsCollisions" },420 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },421 { 0, 60, 2, "Dot3OutPauseFrames" },422 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },423 { 0, 64, 2, "Dot1dTpPortInDiscards" },424 { 0, 66, 2, "IfOutUcastPkts" },425 { 0, 68, 2, "IfOutMulticastPkts" },426 { 0, 70, 2, "IfOutBroadcastPkts" },427};428 429static int rtl8366rb_get_mib_counter(struct realtek_priv *priv,430 int port,431 struct rtl8366_mib_counter *mib,432 u64 *mibvalue)433{434 u32 addr, val;435 int ret;436 int i;437 438 addr = RTL8366RB_MIB_COUNTER_BASE +439 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +440 mib->offset;441 442 /* Writing access counter address first443 * then ASIC will prepare 64bits counter wait for being retrived444 */445 ret = regmap_write(priv->map, addr, 0); /* Write whatever */446 if (ret)447 return ret;448 449 /* Read MIB control register */450 ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val);451 if (ret)452 return -EIO;453 454 if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)455 return -EBUSY;456 457 if (val & RTL8366RB_MIB_CTRL_RESET_MASK)458 return -EIO;459 460 /* Read each individual MIB 16 bits at the time */461 *mibvalue = 0;462 for (i = mib->length; i > 0; i--) {463 ret = regmap_read(priv->map, addr + (i - 1), &val);464 if (ret)465 return ret;466 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF);467 }468 return 0;469}470 471static u32 rtl8366rb_get_irqmask(struct irq_data *d)472{473 int line = irqd_to_hwirq(d);474 u32 val;475 476 /* For line interrupts we combine link down in bits477 * 6..11 with link up in bits 0..5 into one interrupt.478 */479 if (line < 12)480 val = BIT(line) | BIT(line + 6);481 else482 val = BIT(line);483 return val;484}485 486static void rtl8366rb_mask_irq(struct irq_data *d)487{488 struct realtek_priv *priv = irq_data_get_irq_chip_data(d);489 int ret;490 491 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,492 rtl8366rb_get_irqmask(d), 0);493 if (ret)494 dev_err(priv->dev, "could not mask IRQ\n");495}496 497static void rtl8366rb_unmask_irq(struct irq_data *d)498{499 struct realtek_priv *priv = irq_data_get_irq_chip_data(d);500 int ret;501 502 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,503 rtl8366rb_get_irqmask(d),504 rtl8366rb_get_irqmask(d));505 if (ret)506 dev_err(priv->dev, "could not unmask IRQ\n");507}508 509static irqreturn_t rtl8366rb_irq(int irq, void *data)510{511 struct realtek_priv *priv = data;512 u32 stat;513 int ret;514 515 /* This clears the IRQ status register */516 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,517 &stat);518 if (ret) {519 dev_err(priv->dev, "can't read interrupt status\n");520 return IRQ_NONE;521 }522 stat &= RTL8366RB_INTERRUPT_VALID;523 if (!stat)524 return IRQ_NONE;525 while (stat) {526 int line = __ffs(stat);527 int child_irq;528 529 stat &= ~BIT(line);530 /* For line interrupts we combine link down in bits531 * 6..11 with link up in bits 0..5 into one interrupt.532 */533 if (line < 12 && line > 5)534 line -= 5;535 child_irq = irq_find_mapping(priv->irqdomain, line);536 handle_nested_irq(child_irq);537 }538 return IRQ_HANDLED;539}540 541static struct irq_chip rtl8366rb_irq_chip = {542 .name = "RTL8366RB",543 .irq_mask = rtl8366rb_mask_irq,544 .irq_unmask = rtl8366rb_unmask_irq,545};546 547static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,548 irq_hw_number_t hwirq)549{550 irq_set_chip_data(irq, domain->host_data);551 irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq);552 irq_set_nested_thread(irq, 1);553 irq_set_noprobe(irq);554 555 return 0;556}557 558static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)559{560 irq_set_nested_thread(irq, 0);561 irq_set_chip_and_handler(irq, NULL, NULL);562 irq_set_chip_data(irq, NULL);563}564 565static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {566 .map = rtl8366rb_irq_map,567 .unmap = rtl8366rb_irq_unmap,568 .xlate = irq_domain_xlate_onecell,569};570 571static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv)572{573 struct device_node *intc;574 unsigned long irq_trig;575 int irq;576 int ret;577 u32 val;578 int i;579 580 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");581 if (!intc) {582 dev_err(priv->dev, "missing child interrupt-controller node\n");583 return -EINVAL;584 }585 /* RB8366RB IRQs cascade off this one */586 irq = of_irq_get(intc, 0);587 if (irq <= 0) {588 dev_err(priv->dev, "failed to get parent IRQ\n");589 ret = irq ? irq : -EINVAL;590 goto out_put_node;591 }592 593 /* This clears the IRQ status register */594 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,595 &val);596 if (ret) {597 dev_err(priv->dev, "can't read interrupt status\n");598 goto out_put_node;599 }600 601 /* Fetch IRQ edge information from the descriptor */602 irq_trig = irq_get_trigger_type(irq);603 switch (irq_trig) {604 case IRQF_TRIGGER_RISING:605 case IRQF_TRIGGER_HIGH:606 dev_info(priv->dev, "active high/rising IRQ\n");607 val = 0;608 break;609 case IRQF_TRIGGER_FALLING:610 case IRQF_TRIGGER_LOW:611 dev_info(priv->dev, "active low/falling IRQ\n");612 val = RTL8366RB_INTERRUPT_POLARITY;613 break;614 }615 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG,616 RTL8366RB_INTERRUPT_POLARITY,617 val);618 if (ret) {619 dev_err(priv->dev, "could not configure IRQ polarity\n");620 goto out_put_node;621 }622 623 ret = devm_request_threaded_irq(priv->dev, irq, NULL,624 rtl8366rb_irq, IRQF_ONESHOT,625 "RTL8366RB", priv);626 if (ret) {627 dev_err(priv->dev, "unable to request irq: %d\n", ret);628 goto out_put_node;629 }630 priv->irqdomain = irq_domain_add_linear(intc,631 RTL8366RB_NUM_INTERRUPT,632 &rtl8366rb_irqdomain_ops,633 priv);634 if (!priv->irqdomain) {635 dev_err(priv->dev, "failed to create IRQ domain\n");636 ret = -EINVAL;637 goto out_put_node;638 }639 for (i = 0; i < priv->num_ports; i++)640 irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq);641 642out_put_node:643 of_node_put(intc);644 return ret;645}646 647static int rtl8366rb_set_addr(struct realtek_priv *priv)648{649 u8 addr[ETH_ALEN];650 u16 val;651 int ret;652 653 eth_random_addr(addr);654 655 dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",656 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);657 val = addr[0] << 8 | addr[1];658 ret = regmap_write(priv->map, RTL8366RB_SMAR0, val);659 if (ret)660 return ret;661 val = addr[2] << 8 | addr[3];662 ret = regmap_write(priv->map, RTL8366RB_SMAR1, val);663 if (ret)664 return ret;665 val = addr[4] << 8 | addr[5];666 ret = regmap_write(priv->map, RTL8366RB_SMAR2, val);667 if (ret)668 return ret;669 670 return 0;671}672 673/* Found in a vendor driver */674 675/* Struct for handling the jam tables' entries */676struct rtl8366rb_jam_tbl_entry {677 u16 reg;678 u16 val;679};680 681/* For the "version 0" early silicon, appear in most source releases */682static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = {683 {0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF},684 {0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF},685 {0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688},686 {0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830},687 {0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8},688 {0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000},689 {0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A},690 {0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A},691 {0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A},692 {0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A},693 {0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A},694 {0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A},695 {0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961},696 {0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146},697 {0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146},698 {0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320},699 {0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146},700 {0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146},701 {0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146},702 {0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294},703 {0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294},704 {0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294},705 {0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294},706 {0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448},707 {0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B},708 {0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD},709 {0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C},710 {0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13},711 {0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF},712};713 714/* This v1 init sequence is from Belkin F5D8235 U-Boot release */715static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = {716 {0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C},717 {0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},718 {0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585},719 {0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135},720 {0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F},721 {0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20},722 {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000},723 {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140},724 {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A},725 {0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0},726 {0xBE79, 0x3C3C}, {0xBE00, 0x1340},727};728 729/* This v2 init sequence is from Belkin F5D8235 U-Boot release */730static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = {731 {0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},732 {0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14},733 {0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85},734 {0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881},735 {0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885},736 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},737 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320},738 {0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},739 {0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007},740 {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140},741 {0xBE00, 0x1340}, {0x0F51, 0x0010},742};743 744/* Appears in a DDWRT code dump */745static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = {746 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},747 {0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},748 {0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B},749 {0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B},750 {0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185},751 {0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585},752 {0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185},753 {0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51},754 {0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800},755 {0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60},756 {0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000},757 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},758 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320},759 {0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},760 {0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140},761 {0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160},762 {0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000},763};764 765/* Belkin F5D8235 v1, "belkin,f5d8235-v1" */766static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = {767 {0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF},768 {0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F},769 {0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F},770 {0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F},771 {0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3},772 {0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304},773 {0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500},774 {0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00},775 {0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF},776};777 778/* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */779static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = {780 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017},781 {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000},782 {0x0401, 0x0000}, {0x0431, 0x0960},783};784 785/* This jam table activates "green ethernet", which means low power mode786 * and is claimed to detect the cable length and not use more power than787 * necessary, and the ports should enter power saving mode 10 seconds after788 * a cable is disconnected. Seems to always be the same.789 */790static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = {791 {0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},792 {0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},793 {0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},794};795 796/* Function that jams the tables in the proper registers */797static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table,798 int jam_size, struct realtek_priv *priv,799 bool write_dbg)800{801 u32 val;802 int ret;803 int i;804 805 for (i = 0; i < jam_size; i++) {806 if ((jam_table[i].reg & 0xBE00) == 0xBE00) {807 ret = regmap_read(priv->map,808 RTL8366RB_PHY_ACCESS_BUSY_REG,809 &val);810 if (ret)811 return ret;812 if (!(val & RTL8366RB_PHY_INT_BUSY)) {813 ret = regmap_write(priv->map,814 RTL8366RB_PHY_ACCESS_CTRL_REG,815 RTL8366RB_PHY_CTRL_WRITE);816 if (ret)817 return ret;818 }819 }820 if (write_dbg)821 dev_dbg(priv->dev, "jam %04x into register %04x\n",822 jam_table[i].val,823 jam_table[i].reg);824 ret = regmap_write(priv->map,825 jam_table[i].reg,826 jam_table[i].val);827 if (ret)828 return ret;829 }830 return 0;831}832 833static int rb8366rb_set_ledgroup_mode(struct realtek_priv *priv,834 u8 led_group,835 enum rtl8366_ledgroup_mode mode)836{837 int ret;838 u32 val;839 840 val = mode << RTL8366RB_LED_CTRL_OFFSET(led_group);841 842 ret = regmap_update_bits(priv->map,843 RTL8366RB_LED_CTRL_REG,844 RTL8366RB_LED_CTRL_MASK(led_group),845 val);846 if (ret)847 return ret;848 849 return 0;850}851 852static inline u32 rtl8366rb_led_group_port_mask(u8 led_group, u8 port)853{854 switch (led_group) {855 case 0:856 return FIELD_PREP(RTL8366RB_LED_0_X_CTRL_MASK, BIT(port));857 case 1:858 return FIELD_PREP(RTL8366RB_LED_0_X_CTRL_MASK, BIT(port));859 case 2:860 return FIELD_PREP(RTL8366RB_LED_0_X_CTRL_MASK, BIT(port));861 case 3:862 return FIELD_PREP(RTL8366RB_LED_0_X_CTRL_MASK, BIT(port));863 default:864 return 0;865 }866}867 868static int rb8366rb_get_port_led(struct rtl8366rb_led *led)869{870 struct realtek_priv *priv = led->priv;871 u8 led_group = led->led_group;872 u8 port_num = led->port_num;873 int ret;874 u32 val;875 876 ret = regmap_read(priv->map, RTL8366RB_LED_X_X_CTRL_REG(led_group),877 &val);878 if (ret) {879 dev_err(priv->dev, "error reading LED on port %d group %d\n",880 led_group, port_num);881 return ret;882 }883 884 return !!(val & rtl8366rb_led_group_port_mask(led_group, port_num));885}886 887static int rb8366rb_set_port_led(struct rtl8366rb_led *led, bool enable)888{889 struct realtek_priv *priv = led->priv;890 u8 led_group = led->led_group;891 u8 port_num = led->port_num;892 int ret;893 894 ret = regmap_update_bits(priv->map,895 RTL8366RB_LED_X_X_CTRL_REG(led_group),896 rtl8366rb_led_group_port_mask(led_group,897 port_num),898 enable ? 0xffff : 0);899 if (ret) {900 dev_err(priv->dev, "error updating LED on port %d group %d\n",901 led_group, port_num);902 return ret;903 }904 905 /* Change the LED group to manual controlled LEDs if required */906 ret = rb8366rb_set_ledgroup_mode(priv, led_group,907 RTL8366RB_LEDGROUP_FORCE);908 909 if (ret) {910 dev_err(priv->dev, "error updating LED GROUP group %d\n",911 led_group);912 return ret;913 }914 915 return 0;916}917 918static int919rtl8366rb_cled_brightness_set_blocking(struct led_classdev *ldev,920 enum led_brightness brightness)921{922 struct rtl8366rb_led *led = container_of(ldev, struct rtl8366rb_led,923 cdev);924 925 return rb8366rb_set_port_led(led, brightness == LED_ON);926}927 928static int rtl8366rb_setup_led(struct realtek_priv *priv, struct dsa_port *dp,929 struct fwnode_handle *led_fwnode)930{931 struct rtl8366rb *rb = priv->chip_data;932 struct led_init_data init_data = { };933 enum led_default_state state;934 struct rtl8366rb_led *led;935 u32 led_group;936 int ret;937 938 ret = fwnode_property_read_u32(led_fwnode, "reg", &led_group);939 if (ret)940 return ret;941 942 if (led_group >= RTL8366RB_NUM_LEDGROUPS) {943 dev_warn(priv->dev, "Invalid LED reg %d defined for port %d",944 led_group, dp->index);945 return -EINVAL;946 }947 948 led = &rb->leds[dp->index][led_group];949 led->port_num = dp->index;950 led->led_group = led_group;951 led->priv = priv;952 953 state = led_init_default_state_get(led_fwnode);954 switch (state) {955 case LEDS_DEFSTATE_ON:956 led->cdev.brightness = 1;957 rb8366rb_set_port_led(led, 1);958 break;959 case LEDS_DEFSTATE_KEEP:960 led->cdev.brightness =961 rb8366rb_get_port_led(led);962 break;963 case LEDS_DEFSTATE_OFF:964 default:965 led->cdev.brightness = 0;966 rb8366rb_set_port_led(led, 0);967 }968 969 led->cdev.max_brightness = 1;970 led->cdev.brightness_set_blocking =971 rtl8366rb_cled_brightness_set_blocking;972 init_data.fwnode = led_fwnode;973 init_data.devname_mandatory = true;974 975 init_data.devicename = kasprintf(GFP_KERNEL, "Realtek-%d:0%d:%d",976 dp->ds->index, dp->index, led_group);977 if (!init_data.devicename)978 return -ENOMEM;979 980 ret = devm_led_classdev_register_ext(priv->dev, &led->cdev, &init_data);981 if (ret) {982 dev_warn(priv->dev, "Failed to init LED %d for port %d",983 led_group, dp->index);984 return ret;985 }986 987 return 0;988}989 990static int rtl8366rb_setup_all_leds_off(struct realtek_priv *priv)991{992 int ret = 0;993 int i;994 995 regmap_update_bits(priv->map,996 RTL8366RB_INTERRUPT_CONTROL_REG,997 RTL8366RB_P4_RGMII_LED,998 0);999 1000 for (i = 0; i < RTL8366RB_NUM_LEDGROUPS; i++) {1001 ret = rb8366rb_set_ledgroup_mode(priv, i,1002 RTL8366RB_LEDGROUP_OFF);1003 if (ret)1004 return ret;1005 }1006 1007 return ret;1008}1009 1010static int rtl8366rb_setup_leds(struct realtek_priv *priv)1011{1012 struct dsa_switch *ds = &priv->ds;1013 struct device_node *leds_np;1014 struct dsa_port *dp;1015 int ret = 0;1016 1017 dsa_switch_for_each_port(dp, ds) {1018 if (!dp->dn)1019 continue;1020 1021 leds_np = of_get_child_by_name(dp->dn, "leds");1022 if (!leds_np) {1023 dev_dbg(priv->dev, "No leds defined for port %d",1024 dp->index);1025 continue;1026 }1027 1028 for_each_child_of_node_scoped(leds_np, led_np) {1029 ret = rtl8366rb_setup_led(priv, dp,1030 of_fwnode_handle(led_np));1031 if (ret)1032 break;1033 }1034 1035 of_node_put(leds_np);1036 if (ret)1037 return ret;1038 }1039 return 0;1040}1041 1042static int rtl8366rb_setup(struct dsa_switch *ds)1043{1044 struct realtek_priv *priv = ds->priv;1045 const struct rtl8366rb_jam_tbl_entry *jam_table;1046 struct rtl8366rb *rb;1047 u32 chip_ver = 0;1048 u32 chip_id = 0;1049 int jam_size;1050 int ret;1051 int i;1052 1053 rb = priv->chip_data;1054 1055 ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id);1056 if (ret) {1057 dev_err(priv->dev, "unable to read chip id\n");1058 return ret;1059 }1060 1061 switch (chip_id) {1062 case RTL8366RB_CHIP_ID_8366:1063 break;1064 default:1065 dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id);1066 return -ENODEV;1067 }1068 1069 ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG,1070 &chip_ver);1071 if (ret) {1072 dev_err(priv->dev, "unable to read chip version\n");1073 return ret;1074 }1075 1076 dev_info(priv->dev, "RTL%04x ver %u chip found\n",1077 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);1078 1079 /* Do the init dance using the right jam table */1080 switch (chip_ver) {1081 case 0:1082 jam_table = rtl8366rb_init_jam_ver_0;1083 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);1084 break;1085 case 1:1086 jam_table = rtl8366rb_init_jam_ver_1;1087 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);1088 break;1089 case 2:1090 jam_table = rtl8366rb_init_jam_ver_2;1091 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);1092 break;1093 default:1094 jam_table = rtl8366rb_init_jam_ver_3;1095 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);1096 break;1097 }1098 1099 /* Special jam tables for special routers1100 * TODO: are these necessary? Maintainers, please test1101 * without them, using just the off-the-shelf tables.1102 */1103 if (of_machine_is_compatible("belkin,f5d8235-v1")) {1104 jam_table = rtl8366rb_init_jam_f5d8235;1105 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);1106 }1107 if (of_machine_is_compatible("netgear,dgn3500") ||1108 of_machine_is_compatible("netgear,dgn3500b")) {1109 jam_table = rtl8366rb_init_jam_dgn3500;1110 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);1111 }1112 1113 ret = rtl8366rb_jam_table(jam_table, jam_size, priv, true);1114 if (ret)1115 return ret;1116 1117 /* Isolate all user ports so they can only send packets to itself and the CPU port */1118 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {1119 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i),1120 RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) |1121 RTL8366RB_PORT_ISO_EN);1122 if (ret)1123 return ret;1124 }1125 /* CPU port can send packets to all ports */1126 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU),1127 RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) |1128 RTL8366RB_PORT_ISO_EN);1129 if (ret)1130 return ret;1131 1132 /* Set up the "green ethernet" feature */1133 ret = rtl8366rb_jam_table(rtl8366rb_green_jam,1134 ARRAY_SIZE(rtl8366rb_green_jam), priv, false);1135 if (ret)1136 return ret;1137 1138 ret = regmap_write(priv->map,1139 RTL8366RB_GREEN_FEATURE_REG,1140 (chip_ver == 1) ? 0x0007 : 0x0003);1141 if (ret)1142 return ret;1143 1144 /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */1145 ret = regmap_write(priv->map, 0x0c, 0x240);1146 if (ret)1147 return ret;1148 ret = regmap_write(priv->map, 0x0d, 0x240);1149 if (ret)1150 return ret;1151 1152 /* Set some random MAC address */1153 ret = rtl8366rb_set_addr(priv);1154 if (ret)1155 return ret;1156 1157 /* Enable CPU port with custom DSA tag 8899.1158 *1159 * If you set RTL8366RB_CPU_NO_TAG (bit 15) in this register1160 * the custom tag is turned off.1161 */1162 ret = regmap_update_bits(priv->map, RTL8366RB_CPU_CTRL_REG,1163 0xFFFF,1164 BIT(priv->cpu_port));1165 if (ret)1166 return ret;1167 1168 /* Make sure we default-enable the fixed CPU port */1169 ret = regmap_update_bits(priv->map, RTL8366RB_PECR,1170 BIT(priv->cpu_port),1171 0);1172 if (ret)1173 return ret;1174 1175 /* Set default maximum packet length to 1536 bytes */1176 ret = regmap_update_bits(priv->map, RTL8366RB_SGCR,1177 RTL8366RB_SGCR_MAX_LENGTH_MASK,1178 RTL8366RB_SGCR_MAX_LENGTH_1536);1179 if (ret)1180 return ret;1181 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {1182 if (i == priv->cpu_port)1183 /* CPU port need to also accept the tag */1184 rb->max_mtu[i] = ETH_DATA_LEN + RTL8366RB_CPU_TAG_SIZE;1185 else1186 rb->max_mtu[i] = ETH_DATA_LEN;1187 }1188 1189 /* Disable learning for all ports */1190 ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,1191 RTL8366RB_PORT_ALL);1192 if (ret)1193 return ret;1194 1195 /* Enable auto ageing for all ports */1196 ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0);1197 if (ret)1198 return ret;1199 1200 /* Port 4 setup: this enables Port 4, usually the WAN port,1201 * common PHY IO mode is apparently mode 0, and this is not what1202 * the port is initialized to. There is no explanation of the1203 * IO modes in the Realtek source code, if your WAN port is1204 * connected to something exotic such as fiber, then this might1205 * be worth experimenting with.1206 */1207 ret = regmap_update_bits(priv->map, RTL8366RB_PMC0,1208 RTL8366RB_PMC0_P4_IOMODE_MASK,1209 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);1210 if (ret)1211 return ret;1212 1213 /* Accept all packets by default, we enable filtering on-demand */1214 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,1215 0);1216 if (ret)1217 return ret;1218 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,1219 0);1220 if (ret)1221 return ret;1222 1223 /* Don't drop packets whose DA has not been learned */1224 ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2,1225 RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);1226 if (ret)1227 return ret;1228 1229 /* Set blinking, used by all LED groups using HW triggers.1230 * TODO: make this configurable1231 */1232 ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG,1233 RTL8366RB_LED_BLINKRATE_MASK,1234 RTL8366RB_LED_BLINKRATE_56MS);1235 if (ret)1236 return ret;1237 1238 /* Set up LED activity:1239 * Each port has 4 LEDs on fixed groups. Each group shares the same1240 * hardware trigger across all ports. LEDs can only be indiviually1241 * controlled setting the LED group to fixed mode and using the driver1242 * to toggle them LEDs on/off.1243 */1244 if (priv->leds_disabled) {1245 ret = rtl8366rb_setup_all_leds_off(priv);1246 if (ret)1247 return ret;1248 } else {1249 ret = rtl8366rb_setup_leds(priv);1250 if (ret)1251 return ret;1252 }1253 1254 ret = rtl8366_reset_vlan(priv);1255 if (ret)1256 return ret;1257 1258 ret = rtl8366rb_setup_cascaded_irq(priv);1259 if (ret)1260 dev_info(priv->dev, "no interrupt support\n");1261 1262 ret = rtl83xx_setup_user_mdio(ds);1263 if (ret) {1264 dev_err(priv->dev, "could not set up MDIO bus\n");1265 return -ENODEV;1266 }1267 1268 return 0;1269}1270 1271static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,1272 int port,1273 enum dsa_tag_protocol mp)1274{1275 /* This switch uses the 4 byte protocol A Realtek DSA tag */1276 return DSA_TAG_PROTO_RTL4_A;1277}1278 1279static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port,1280 struct phylink_config *config)1281{1282 unsigned long *interfaces = config->supported_interfaces;1283 struct realtek_priv *priv = ds->priv;1284 1285 if (port == priv->cpu_port) {1286 __set_bit(PHY_INTERFACE_MODE_MII, interfaces);1287 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);1288 /* REVMII only supports 100M FD */1289 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);1290 /* RGMII only supports 1G FD */1291 phy_interface_set_rgmii(interfaces);1292 1293 config->mac_capabilities = MAC_1000 | MAC_100 |1294 MAC_SYM_PAUSE;1295 } else {1296 /* RSGMII port, but we don't have that, and we don't1297 * specify in DT, so phylib uses the default of GMII1298 */1299 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);1300 config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 |1301 MAC_SYM_PAUSE | MAC_ASYM_PAUSE;1302 }1303}1304 1305static void1306rtl8366rb_mac_config(struct phylink_config *config, unsigned int mode,1307 const struct phylink_link_state *state)1308{1309}1310 1311static void1312rtl8366rb_mac_link_up(struct phylink_config *config, struct phy_device *phydev,1313 unsigned int mode, phy_interface_t interface,1314 int speed, int duplex, bool tx_pause, bool rx_pause)1315{1316 struct dsa_port *dp = dsa_phylink_to_port(config);1317 struct realtek_priv *priv = dp->ds->priv;1318 int port = dp->index;1319 unsigned int val;1320 int ret;1321 1322 /* Allow forcing the mode on the fixed CPU port, no autonegotiation.1323 * We assume autonegotiation works on the PHY-facing ports.1324 */1325 if (port != priv->cpu_port)1326 return;1327 1328 dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);1329 1330 ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG,1331 BIT(port), BIT(port));1332 if (ret) {1333 dev_err(priv->dev, "failed to force CPU port\n");1334 return;1335 }1336 1337 /* Conjure port config */1338 switch (speed) {1339 case SPEED_10:1340 val = RTL8366RB_PAACR_SPEED_10M;1341 break;1342 case SPEED_100:1343 val = RTL8366RB_PAACR_SPEED_100M;1344 break;1345 case SPEED_1000:1346 val = RTL8366RB_PAACR_SPEED_1000M;1347 break;1348 default:1349 val = RTL8366RB_PAACR_SPEED_1000M;1350 break;1351 }1352 1353 if (duplex == DUPLEX_FULL)1354 val |= RTL8366RB_PAACR_FULL_DUPLEX;1355 1356 if (tx_pause)1357 val |= RTL8366RB_PAACR_TX_PAUSE;1358 1359 if (rx_pause)1360 val |= RTL8366RB_PAACR_RX_PAUSE;1361 1362 val |= RTL8366RB_PAACR_LINK_UP;1363 1364 ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2,1365 0xFF00U,1366 val << 8);1367 if (ret) {1368 dev_err(priv->dev, "failed to set PAACR on CPU port\n");1369 return;1370 }1371 1372 dev_dbg(priv->dev, "set PAACR to %04x\n", val);1373 1374 /* Enable the CPU port */1375 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),1376 0);1377 if (ret) {1378 dev_err(priv->dev, "failed to enable the CPU port\n");1379 return;1380 }1381}1382 1383static void1384rtl8366rb_mac_link_down(struct phylink_config *config, unsigned int mode,1385 phy_interface_t interface)1386{1387 struct dsa_port *dp = dsa_phylink_to_port(config);1388 struct realtek_priv *priv = dp->ds->priv;1389 int port = dp->index;1390 int ret;1391 1392 if (port != priv->cpu_port)1393 return;1394 1395 dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port);1396 1397 /* Disable the CPU port */1398 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),1399 BIT(port));1400 if (ret) {1401 dev_err(priv->dev, "failed to disable the CPU port\n");1402 return;1403 }1404}1405 1406static int1407rtl8366rb_port_enable(struct dsa_switch *ds, int port,1408 struct phy_device *phy)1409{1410 struct realtek_priv *priv = ds->priv;1411 int ret;1412 1413 dev_dbg(priv->dev, "enable port %d\n", port);1414 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),1415 0);1416 if (ret)1417 return ret;1418 1419 return 0;1420}1421 1422static void1423rtl8366rb_port_disable(struct dsa_switch *ds, int port)1424{1425 struct realtek_priv *priv = ds->priv;1426 int ret;1427 1428 dev_dbg(priv->dev, "disable port %d\n", port);1429 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),1430 BIT(port));1431 if (ret)1432 return;1433}1434 1435static int1436rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port,1437 struct dsa_bridge bridge,1438 bool *tx_fwd_offload,1439 struct netlink_ext_ack *extack)1440{1441 struct realtek_priv *priv = ds->priv;1442 unsigned int port_bitmap = 0;1443 int ret, i;1444 1445 /* Loop over all other ports than the current one */1446 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {1447 /* Current port handled last */1448 if (i == port)1449 continue;1450 /* Not on this bridge */1451 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))1452 continue;1453 /* Join this port to each other port on the bridge */1454 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),1455 RTL8366RB_PORT_ISO_PORTS(BIT(port)),1456 RTL8366RB_PORT_ISO_PORTS(BIT(port)));1457 if (ret)1458 dev_err(priv->dev, "failed to join port %d\n", port);1459 1460 port_bitmap |= BIT(i);1461 }1462 1463 /* Set the bits for the ports we can access */1464 return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),1465 RTL8366RB_PORT_ISO_PORTS(port_bitmap),1466 RTL8366RB_PORT_ISO_PORTS(port_bitmap));1467}1468 1469static void1470rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port,1471 struct dsa_bridge bridge)1472{1473 struct realtek_priv *priv = ds->priv;1474 unsigned int port_bitmap = 0;1475 int ret, i;1476 1477 /* Loop over all other ports than this one */1478 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {1479 /* Current port handled last */1480 if (i == port)1481 continue;1482 /* Not on this bridge */1483 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))1484 continue;1485 /* Remove this port from any other port on the bridge */1486 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),1487 RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0);1488 if (ret)1489 dev_err(priv->dev, "failed to leave port %d\n", port);1490 1491 port_bitmap |= BIT(i);1492 }1493 1494 /* Clear the bits for the ports we can not access, leave ourselves */1495 regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),1496 RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0);1497}1498 1499/**1500 * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames1501 * @priv: SMI state container1502 * @port: the port to drop untagged and C-tagged frames on1503 * @drop: whether to drop or pass untagged and C-tagged frames1504 *1505 * Return: zero for success, a negative number on error.1506 */1507static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop)1508{1509 return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,1510 RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port),1511 drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0);1512}1513 1514static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port,1515 bool vlan_filtering,1516 struct netlink_ext_ack *extack)1517{1518 struct realtek_priv *priv = ds->priv;1519 struct rtl8366rb *rb;1520 int ret;1521 1522 rb = priv->chip_data;1523 1524 dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,1525 vlan_filtering ? "enable" : "disable");1526 1527 /* If the port is not in the member set, the frame will be dropped */1528 ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,1529 BIT(port), vlan_filtering ? BIT(port) : 0);1530 if (ret)1531 return ret;1532 1533 /* If VLAN filtering is enabled and PVID is also enabled, we must1534 * not drop any untagged or C-tagged frames. If we turn off VLAN1535 * filtering on a port, we need to accept any frames.1536 */1537 if (vlan_filtering)1538 ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]);1539 else1540 ret = rtl8366rb_drop_untagged(priv, port, false);1541 1542 return ret;1543}1544 1545static int1546rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,1547 struct switchdev_brport_flags flags,1548 struct netlink_ext_ack *extack)1549{1550 /* We support enabling/disabling learning */1551 if (flags.mask & ~(BR_LEARNING))1552 return -EINVAL;1553 1554 return 0;1555}1556 1557static int1558rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port,1559 struct switchdev_brport_flags flags,1560 struct netlink_ext_ack *extack)1561{1562 struct realtek_priv *priv = ds->priv;1563 int ret;1564 1565 if (flags.mask & BR_LEARNING) {1566 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,1567 BIT(port),1568 (flags.val & BR_LEARNING) ? 0 : BIT(port));1569 if (ret)1570 return ret;1571 }1572 1573 return 0;1574}1575 1576static void1577rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)1578{1579 struct realtek_priv *priv = ds->priv;1580 u32 val;1581 int i;1582 1583 switch (state) {1584 case BR_STATE_DISABLED:1585 val = RTL8366RB_STP_STATE_DISABLED;1586 break;1587 case BR_STATE_BLOCKING:1588 case BR_STATE_LISTENING:1589 val = RTL8366RB_STP_STATE_BLOCKING;1590 break;1591 case BR_STATE_LEARNING:1592 val = RTL8366RB_STP_STATE_LEARNING;1593 break;1594 case BR_STATE_FORWARDING:1595 val = RTL8366RB_STP_STATE_FORWARDING;1596 break;1597 default:1598 dev_err(priv->dev, "unknown bridge state requested\n");1599 return;1600 }1601 1602 /* Set the same status for the port on all the FIDs */1603 for (i = 0; i < RTL8366RB_NUM_FIDS; i++) {1604 regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i,1605 RTL8366RB_STP_STATE_MASK(port),1606 RTL8366RB_STP_STATE(port, val));1607 }1608}1609 1610static void1611rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)1612{1613 struct realtek_priv *priv = ds->priv;1614 1615 /* This will age out any learned L2 entries */1616 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,1617 BIT(port), BIT(port));1618 /* Restore the normal state of things */1619 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,1620 BIT(port), 0);1621}1622 1623static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)1624{1625 struct realtek_priv *priv = ds->priv;1626 struct rtl8366rb *rb;1627 unsigned int max_mtu;1628 u32 len;1629 int i;1630 1631 /* Cache the per-port MTU setting */1632 rb = priv->chip_data;1633 rb->max_mtu[port] = new_mtu;1634 1635 /* Roof out the MTU for the entire switch to the greatest1636 * common denominator: the biggest set for any one port will1637 * be the biggest MTU for the switch.1638 */1639 max_mtu = ETH_DATA_LEN;1640 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {1641 if (rb->max_mtu[i] > max_mtu)1642 max_mtu = rb->max_mtu[i];1643 }1644 1645 /* Translate to layer 2 size.1646 * Add ethernet and (possible) VLAN headers, and checksum to the size.1647 * For ETH_DATA_LEN (1500 bytes) this will add up to 1522 bytes.1648 */1649 max_mtu += VLAN_ETH_HLEN;1650 max_mtu += ETH_FCS_LEN;1651 1652 if (max_mtu <= 1522)1653 len = RTL8366RB_SGCR_MAX_LENGTH_1522;1654 else if (max_mtu > 1522 && max_mtu <= 1536)1655 /* This will be the most common default if using VLAN and1656 * CPU tagging on a port as both VLAN and CPU tag will1657 * result in 1518 + 4 + 4 = 1526 bytes.1658 */1659 len = RTL8366RB_SGCR_MAX_LENGTH_1536;1660 else if (max_mtu > 1536 && max_mtu <= 1552)1661 len = RTL8366RB_SGCR_MAX_LENGTH_1552;1662 else1663 len = RTL8366RB_SGCR_MAX_LENGTH_16000;1664 1665 return regmap_update_bits(priv->map, RTL8366RB_SGCR,1666 RTL8366RB_SGCR_MAX_LENGTH_MASK,1667 len);1668}1669 1670static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)1671{1672 /* The max MTU is 16000 bytes, so we subtract the ethernet1673 * headers with VLAN and checksum and arrive at1674 * 16000 - 18 - 4 = 15978. This does not include the CPU tag1675 * since that is added to the requested MTU by the DSA framework.1676 */1677 return 16000 - VLAN_ETH_HLEN - ETH_FCS_LEN;1678}1679 1680static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid,1681 struct rtl8366_vlan_4k *vlan4k)1682{1683 u32 data[3];1684 int ret;1685 int i;1686 1687 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));1688 1689 if (vid >= RTL8366RB_NUM_VIDS)1690 return -EINVAL;1691 1692 /* write VID */1693 ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,1694 vid & RTL8366RB_VLAN_VID_MASK);1695 if (ret)1696 return ret;1697 1698 /* write table access control word */1699 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,1700 RTL8366RB_TABLE_VLAN_READ_CTRL);1701 if (ret)1702 return ret;1703 1704 for (i = 0; i < 3; i++) {1705 ret = regmap_read(priv->map,1706 RTL8366RB_VLAN_TABLE_READ_BASE + i,1707 &data[i]);1708 if (ret)1709 return ret;1710 }1711 1712 vlan4k->vid = vid;1713 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &1714 RTL8366RB_VLAN_UNTAG_MASK;1715 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;1716 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;1717 1718 return 0;1719}1720 1721static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv,1722 const struct rtl8366_vlan_4k *vlan4k)1723{1724 u32 data[3];1725 int ret;1726 int i;1727 1728 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||1729 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||1730 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||1731 vlan4k->fid > RTL8366RB_FIDMAX)1732 return -EINVAL;1733 1734 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;1735 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |1736 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<1737 RTL8366RB_VLAN_UNTAG_SHIFT);1738 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;1739 1740 for (i = 0; i < 3; i++) {1741 ret = regmap_write(priv->map,1742 RTL8366RB_VLAN_TABLE_WRITE_BASE + i,1743 data[i]);1744 if (ret)1745 return ret;1746 }1747 1748 /* write table access control word */1749 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,1750 RTL8366RB_TABLE_VLAN_WRITE_CTRL);1751 1752 return ret;1753}1754 1755static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index,1756 struct rtl8366_vlan_mc *vlanmc)1757{1758 u32 data[3];1759 int ret;1760 int i;1761 1762 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));1763 1764 if (index >= RTL8366RB_NUM_VLANS)1765 return -EINVAL;1766 1767 for (i = 0; i < 3; i++) {1768 ret = regmap_read(priv->map,1769 RTL8366RB_VLAN_MC_BASE(index) + i,1770 &data[i]);1771 if (ret)1772 return ret;1773 }1774 1775 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;1776 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &1777 RTL8366RB_VLAN_PRIORITY_MASK;1778 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &1779 RTL8366RB_VLAN_UNTAG_MASK;1780 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;1781 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;1782 1783 return 0;1784}1785 1786static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index,1787 const struct rtl8366_vlan_mc *vlanmc)1788{1789 u32 data[3];1790 int ret;1791 int i;1792 1793 if (index >= RTL8366RB_NUM_VLANS ||1794 vlanmc->vid >= RTL8366RB_NUM_VIDS ||1795 vlanmc->priority > RTL8366RB_PRIORITYMAX ||1796 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||1797 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||1798 vlanmc->fid > RTL8366RB_FIDMAX)1799 return -EINVAL;1800 1801 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |1802 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<1803 RTL8366RB_VLAN_PRIORITY_SHIFT);1804 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |1805 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<1806 RTL8366RB_VLAN_UNTAG_SHIFT);1807 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;1808 1809 for (i = 0; i < 3; i++) {1810 ret = regmap_write(priv->map,1811 RTL8366RB_VLAN_MC_BASE(index) + i,1812 data[i]);1813 if (ret)1814 return ret;1815 }1816 1817 return 0;1818}1819 1820static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val)1821{1822 u32 data;1823 int ret;1824 1825 if (port >= priv->num_ports)1826 return -EINVAL;1827 1828 ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),1829 &data);1830 if (ret)1831 return ret;1832 1833 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &1834 RTL8366RB_PORT_VLAN_CTRL_MASK;1835 1836 return 0;1837}1838 1839static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index)1840{1841 struct dsa_switch *ds = &priv->ds;1842 struct rtl8366rb *rb;1843 bool pvid_enabled;1844 int ret;1845 1846 rb = priv->chip_data;1847 pvid_enabled = !!index;1848 1849 if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS)1850 return -EINVAL;1851 1852 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),1853 RTL8366RB_PORT_VLAN_CTRL_MASK <<1854 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),1855 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<1856 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));1857 if (ret)1858 return ret;1859 1860 rb->pvid_enabled[port] = pvid_enabled;1861 1862 /* If VLAN filtering is enabled and PVID is also enabled, we must1863 * not drop any untagged or C-tagged frames. Make sure to update the1864 * filtering setting.1865 */1866 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))1867 ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled);1868 1869 return ret;1870}1871 1872static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan)1873{1874 unsigned int max = RTL8366RB_NUM_VLANS - 1;1875 1876 if (priv->vlan4k_enabled)1877 max = RTL8366RB_NUM_VIDS - 1;1878 1879 if (vlan > max)1880 return false;1881 1882 return true;1883}1884 1885static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable)1886{1887 dev_dbg(priv->dev, "%s VLAN\n", enable ? "enable" : "disable");1888 return regmap_update_bits(priv->map,1889 RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,1890 enable ? RTL8366RB_SGCR_EN_VLAN : 0);1891}1892 1893static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable)1894{1895 dev_dbg(priv->dev, "%s VLAN 4k\n", enable ? "enable" : "disable");1896 return regmap_update_bits(priv->map, RTL8366RB_SGCR,1897 RTL8366RB_SGCR_EN_VLAN_4KTB,1898 enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);1899}1900 1901static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum)1902{1903 u32 val;1904 u32 reg;1905 int ret;1906 1907 if (phy > RTL8366RB_PHY_NO_MAX)1908 return -EINVAL;1909 1910 rtl83xx_lock(priv);1911 1912 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,1913 RTL8366RB_PHY_CTRL_READ);1914 if (ret)1915 goto out;1916 1917 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;1918 1919 ret = regmap_write(priv->map_nolock, reg, 0);1920 if (ret) {1921 dev_err(priv->dev,1922 "failed to write PHY%d reg %04x @ %04x, ret %d\n",1923 phy, regnum, reg, ret);1924 goto out;1925 }1926 1927 ret = regmap_read(priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG,1928 &val);1929 if (ret)1930 goto out;1931 1932 ret = val;1933 1934 dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",1935 phy, regnum, reg, val);1936 1937out:1938 rtl83xx_unlock(priv);1939 1940 return ret;1941}1942 1943static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum,1944 u16 val)1945{1946 u32 reg;1947 int ret;1948 1949 if (phy > RTL8366RB_PHY_NO_MAX)1950 return -EINVAL;1951 1952 rtl83xx_lock(priv);1953 1954 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,1955 RTL8366RB_PHY_CTRL_WRITE);1956 if (ret)1957 goto out;1958 1959 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;1960 1961 dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",1962 phy, regnum, reg, val);1963 1964 ret = regmap_write(priv->map_nolock, reg, val);1965 if (ret)1966 goto out;1967 1968out:1969 rtl83xx_unlock(priv);1970 1971 return ret;1972}1973 1974static int rtl8366rb_reset_chip(struct realtek_priv *priv)1975{1976 int timeout = 10;1977 u32 val;1978 int ret;1979 1980 priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG,1981 RTL8366RB_CHIP_CTRL_RESET_HW);1982 do {1983 usleep_range(20000, 25000);1984 ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val);1985 if (ret)1986 return ret;1987 1988 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))1989 break;1990 } while (--timeout);1991 1992 if (!timeout) {1993 dev_err(priv->dev, "timeout waiting for the switch to reset\n");1994 return -EIO;1995 }1996 1997 return 0;1998}1999 2000static int rtl8366rb_detect(struct realtek_priv *priv)2001{2002 struct device *dev = priv->dev;2003 int ret;2004 u32 val;2005 2006 /* Detect device */2007 ret = regmap_read(priv->map, 0x5c, &val);2008 if (ret) {2009 dev_err(dev, "can't get chip ID (%d)\n", ret);2010 return ret;2011 }2012 2013 switch (val) {2014 case 0x6027:2015 dev_info(dev, "found an RTL8366S switch\n");2016 dev_err(dev, "this switch is not yet supported, submit patches!\n");2017 return -ENODEV;2018 case 0x5937:2019 dev_info(dev, "found an RTL8366RB switch\n");2020 priv->cpu_port = RTL8366RB_PORT_NUM_CPU;2021 priv->num_ports = RTL8366RB_NUM_PORTS;2022 priv->num_vlan_mc = RTL8366RB_NUM_VLANS;2023 priv->mib_counters = rtl8366rb_mib_counters;2024 priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);2025 break;2026 default:2027 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",2028 val);2029 break;2030 }2031 2032 ret = rtl8366rb_reset_chip(priv);2033 if (ret)2034 return ret;2035 2036 return 0;2037}2038 2039static const struct phylink_mac_ops rtl8366rb_phylink_mac_ops = {2040 .mac_config = rtl8366rb_mac_config,2041 .mac_link_down = rtl8366rb_mac_link_down,2042 .mac_link_up = rtl8366rb_mac_link_up,2043};2044 2045static const struct dsa_switch_ops rtl8366rb_switch_ops = {2046 .get_tag_protocol = rtl8366_get_tag_protocol,2047 .setup = rtl8366rb_setup,2048 .phylink_get_caps = rtl8366rb_phylink_get_caps,2049 .get_strings = rtl8366_get_strings,2050 .get_ethtool_stats = rtl8366_get_ethtool_stats,2051 .get_sset_count = rtl8366_get_sset_count,2052 .port_bridge_join = rtl8366rb_port_bridge_join,2053 .port_bridge_leave = rtl8366rb_port_bridge_leave,2054 .port_vlan_filtering = rtl8366rb_vlan_filtering,2055 .port_vlan_add = rtl8366_vlan_add,2056 .port_vlan_del = rtl8366_vlan_del,2057 .port_enable = rtl8366rb_port_enable,2058 .port_disable = rtl8366rb_port_disable,2059 .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,2060 .port_bridge_flags = rtl8366rb_port_bridge_flags,2061 .port_stp_state_set = rtl8366rb_port_stp_state_set,2062 .port_fast_age = rtl8366rb_port_fast_age,2063 .port_change_mtu = rtl8366rb_change_mtu,2064 .port_max_mtu = rtl8366rb_max_mtu,2065};2066 2067static const struct realtek_ops rtl8366rb_ops = {2068 .detect = rtl8366rb_detect,2069 .get_vlan_mc = rtl8366rb_get_vlan_mc,2070 .set_vlan_mc = rtl8366rb_set_vlan_mc,2071 .get_vlan_4k = rtl8366rb_get_vlan_4k,2072 .set_vlan_4k = rtl8366rb_set_vlan_4k,2073 .get_mc_index = rtl8366rb_get_mc_index,2074 .set_mc_index = rtl8366rb_set_mc_index,2075 .get_mib_counter = rtl8366rb_get_mib_counter,2076 .is_vlan_valid = rtl8366rb_is_vlan_valid,2077 .enable_vlan = rtl8366rb_enable_vlan,2078 .enable_vlan4k = rtl8366rb_enable_vlan4k,2079 .phy_read = rtl8366rb_phy_read,2080 .phy_write = rtl8366rb_phy_write,2081};2082 2083const struct realtek_variant rtl8366rb_variant = {2084 .ds_ops = &rtl8366rb_switch_ops,2085 .ops = &rtl8366rb_ops,2086 .phylink_mac_ops = &rtl8366rb_phylink_mac_ops,2087 .clk_delay = 10,2088 .cmd_read = 0xa9,2089 .cmd_write = 0xa8,2090 .chip_data_sz = sizeof(struct rtl8366rb),2091};2092 2093static const struct of_device_id rtl8366rb_of_match[] = {2094 { .compatible = "realtek,rtl8366rb", .data = &rtl8366rb_variant, },2095 { /* sentinel */ },2096};2097MODULE_DEVICE_TABLE(of, rtl8366rb_of_match);2098 2099static struct platform_driver rtl8366rb_smi_driver = {2100 .driver = {2101 .name = "rtl8366rb-smi",2102 .of_match_table = rtl8366rb_of_match,2103 },2104 .probe = realtek_smi_probe,2105 .remove_new = realtek_smi_remove,2106 .shutdown = realtek_smi_shutdown,2107};2108 2109static struct mdio_driver rtl8366rb_mdio_driver = {2110 .mdiodrv.driver = {2111 .name = "rtl8366rb-mdio",2112 .of_match_table = rtl8366rb_of_match,2113 },2114 .probe = realtek_mdio_probe,2115 .remove = realtek_mdio_remove,2116 .shutdown = realtek_mdio_shutdown,2117};2118 2119static int rtl8366rb_init(void)2120{2121 int ret;2122 2123 ret = realtek_mdio_driver_register(&rtl8366rb_mdio_driver);2124 if (ret)2125 return ret;2126 2127 ret = realtek_smi_driver_register(&rtl8366rb_smi_driver);2128 if (ret) {2129 realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver);2130 return ret;2131 }2132 2133 return 0;2134}2135module_init(rtl8366rb_init);2136 2137static void __exit rtl8366rb_exit(void)2138{2139 realtek_smi_driver_unregister(&rtl8366rb_smi_driver);2140 realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver);2141}2142module_exit(rtl8366rb_exit);2143 2144MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");2145MODULE_DESCRIPTION("Driver for RTL8366RB ethernet switch");2146MODULE_LICENSE("GPL");2147MODULE_IMPORT_NS(REALTEK_DSA);2148