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1// SPDX-License-Identifier: GPL-2.02/* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>4 */5 6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt7 8#include <linux/delay.h>9#include <linux/module.h>10#include <linux/printk.h>11#include <linux/spi/spi.h>12#include <linux/errno.h>13#include <linux/gpio/consumer.h>14#include <linux/phylink.h>15#include <linux/of.h>16#include <linux/of_net.h>17#include <linux/of_mdio.h>18#include <linux/pcs/pcs-xpcs.h>19#include <linux/netdev_features.h>20#include <linux/netdevice.h>21#include <linux/if_bridge.h>22#include <linux/if_ether.h>23#include <linux/dsa/8021q.h>24#include <linux/units.h>25 26#include "sja1105.h"27#include "sja1105_tas.h"28 29#define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull30 31/* Configure the optional reset pin and bring up switch */32static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len,33 unsigned int startup_delay)34{35 struct gpio_desc *gpio;36 37 gpio = gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);38 if (IS_ERR(gpio))39 return PTR_ERR(gpio);40 41 if (!gpio)42 return 0;43 44 gpiod_set_value_cansleep(gpio, 1);45 /* Wait for minimum reset pulse length */46 msleep(pulse_len);47 gpiod_set_value_cansleep(gpio, 0);48 /* Wait until chip is ready after reset */49 msleep(startup_delay);50 51 gpiod_put(gpio);52 53 return 0;54}55 56static void57sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,58 int from, int to, bool allow)59{60 if (allow)61 l2_fwd[from].reach_port |= BIT(to);62 else63 l2_fwd[from].reach_port &= ~BIT(to);64}65 66static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd,67 int from, int to)68{69 return !!(l2_fwd[from].reach_port & BIT(to));70}71 72static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid)73{74 struct sja1105_vlan_lookup_entry *vlan;75 int count, i;76 77 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;78 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count;79 80 for (i = 0; i < count; i++)81 if (vlan[i].vlanid == vid)82 return i;83 84 /* Return an invalid entry index if not found */85 return -1;86}87 88static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop)89{90 struct sja1105_private *priv = ds->priv;91 struct sja1105_mac_config_entry *mac;92 93 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;94 95 if (mac[port].drpuntag == drop)96 return 0;97 98 mac[port].drpuntag = drop;99 100 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,101 &mac[port], true);102}103 104static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid)105{106 struct sja1105_mac_config_entry *mac;107 108 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;109 110 if (mac[port].vlanid == pvid)111 return 0;112 113 mac[port].vlanid = pvid;114 115 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,116 &mac[port], true);117}118 119static int sja1105_commit_pvid(struct dsa_switch *ds, int port)120{121 struct dsa_port *dp = dsa_to_port(ds, port);122 struct net_device *br = dsa_port_bridge_dev_get(dp);123 struct sja1105_private *priv = ds->priv;124 struct sja1105_vlan_lookup_entry *vlan;125 bool drop_untagged = false;126 int match, rc;127 u16 pvid;128 129 if (br && br_vlan_enabled(br))130 pvid = priv->bridge_pvid[port];131 else132 pvid = priv->tag_8021q_pvid[port];133 134 rc = sja1105_pvid_apply(priv, port, pvid);135 if (rc)136 return rc;137 138 /* Only force dropping of untagged packets when the port is under a139 * VLAN-aware bridge. When the tag_8021q pvid is used, we are140 * deliberately removing the RX VLAN from the port's VMEMB_PORT list,141 * to prevent DSA tag spoofing from the link partner. Untagged packets142 * are the only ones that should be received with tag_8021q, so143 * definitely don't drop them.144 */145 if (pvid == priv->bridge_pvid[port]) {146 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;147 148 match = sja1105_is_vlan_configured(priv, pvid);149 150 if (match < 0 || !(vlan[match].vmemb_port & BIT(port)))151 drop_untagged = true;152 }153 154 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))155 drop_untagged = true;156 157 return sja1105_drop_untagged(ds, port, drop_untagged);158}159 160static int sja1105_init_mac_settings(struct sja1105_private *priv)161{162 struct sja1105_mac_config_entry default_mac = {163 /* Enable all 8 priority queues on egress.164 * Every queue i holds top[i] - base[i] frames.165 * Sum of top[i] - base[i] is 511 (max hardware limit).166 */167 .top = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},168 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},169 .enabled = {true, true, true, true, true, true, true, true},170 /* Keep standard IFG of 12 bytes on egress. */171 .ifg = 0,172 /* Always put the MAC speed in automatic mode, where it can be173 * adjusted at runtime by PHYLINK.174 */175 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO],176 /* No static correction for 1-step 1588 events */177 .tp_delin = 0,178 .tp_delout = 0,179 /* Disable aging for critical TTEthernet traffic */180 .maxage = 0xFF,181 /* Internal VLAN (pvid) to apply to untagged ingress */182 .vlanprio = 0,183 .vlanid = 1,184 .ing_mirr = false,185 .egr_mirr = false,186 /* Don't drop traffic with other EtherType than ETH_P_IP */187 .drpnona664 = false,188 /* Don't drop double-tagged traffic */189 .drpdtag = false,190 /* Don't drop untagged traffic */191 .drpuntag = false,192 /* Don't retag 802.1p (VID 0) traffic with the pvid */193 .retag = false,194 /* Disable learning and I/O on user ports by default -195 * STP will enable it.196 */197 .dyn_learn = false,198 .egress = false,199 .ingress = false,200 };201 struct sja1105_mac_config_entry *mac;202 struct dsa_switch *ds = priv->ds;203 struct sja1105_table *table;204 struct dsa_port *dp;205 206 table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];207 208 /* Discard previous MAC Configuration Table */209 if (table->entry_count) {210 kfree(table->entries);211 table->entry_count = 0;212 }213 214 table->entries = kcalloc(table->ops->max_entry_count,215 table->ops->unpacked_entry_size, GFP_KERNEL);216 if (!table->entries)217 return -ENOMEM;218 219 table->entry_count = table->ops->max_entry_count;220 221 mac = table->entries;222 223 list_for_each_entry(dp, &ds->dst->ports, list) {224 if (dp->ds != ds)225 continue;226 227 mac[dp->index] = default_mac;228 229 /* Let sja1105_bridge_stp_state_set() keep address learning230 * enabled for the DSA ports. CPU ports use software-assisted231 * learning to ensure that only FDB entries belonging to the232 * bridge are learned, and that they are learned towards all233 * CPU ports in a cross-chip topology if multiple CPU ports234 * exist.235 */236 if (dsa_port_is_dsa(dp))237 dp->learning = true;238 239 /* Disallow untagged packets from being received on the240 * CPU and DSA ports.241 */242 if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp))243 mac[dp->index].drpuntag = true;244 }245 246 return 0;247}248 249static int sja1105_init_mii_settings(struct sja1105_private *priv)250{251 struct device *dev = &priv->spidev->dev;252 struct sja1105_xmii_params_entry *mii;253 struct dsa_switch *ds = priv->ds;254 struct sja1105_table *table;255 int i;256 257 table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];258 259 /* Discard previous xMII Mode Parameters Table */260 if (table->entry_count) {261 kfree(table->entries);262 table->entry_count = 0;263 }264 265 table->entries = kcalloc(table->ops->max_entry_count,266 table->ops->unpacked_entry_size, GFP_KERNEL);267 if (!table->entries)268 return -ENOMEM;269 270 /* Override table based on PHYLINK DT bindings */271 table->entry_count = table->ops->max_entry_count;272 273 mii = table->entries;274 275 for (i = 0; i < ds->num_ports; i++) {276 sja1105_mii_role_t role = XMII_MAC;277 278 if (dsa_is_unused_port(priv->ds, i))279 continue;280 281 switch (priv->phy_mode[i]) {282 case PHY_INTERFACE_MODE_INTERNAL:283 if (priv->info->internal_phy[i] == SJA1105_NO_PHY)284 goto unsupported;285 286 mii->xmii_mode[i] = XMII_MODE_MII;287 if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)288 mii->special[i] = true;289 290 break;291 case PHY_INTERFACE_MODE_REVMII:292 role = XMII_PHY;293 fallthrough;294 case PHY_INTERFACE_MODE_MII:295 if (!priv->info->supports_mii[i])296 goto unsupported;297 298 mii->xmii_mode[i] = XMII_MODE_MII;299 break;300 case PHY_INTERFACE_MODE_REVRMII:301 role = XMII_PHY;302 fallthrough;303 case PHY_INTERFACE_MODE_RMII:304 if (!priv->info->supports_rmii[i])305 goto unsupported;306 307 mii->xmii_mode[i] = XMII_MODE_RMII;308 break;309 case PHY_INTERFACE_MODE_RGMII:310 case PHY_INTERFACE_MODE_RGMII_ID:311 case PHY_INTERFACE_MODE_RGMII_RXID:312 case PHY_INTERFACE_MODE_RGMII_TXID:313 if (!priv->info->supports_rgmii[i])314 goto unsupported;315 316 mii->xmii_mode[i] = XMII_MODE_RGMII;317 break;318 case PHY_INTERFACE_MODE_SGMII:319 if (!priv->info->supports_sgmii[i])320 goto unsupported;321 322 mii->xmii_mode[i] = XMII_MODE_SGMII;323 mii->special[i] = true;324 break;325 case PHY_INTERFACE_MODE_2500BASEX:326 if (!priv->info->supports_2500basex[i])327 goto unsupported;328 329 mii->xmii_mode[i] = XMII_MODE_SGMII;330 mii->special[i] = true;331 break;332unsupported:333 default:334 dev_err(dev, "Unsupported PHY mode %s on port %d!\n",335 phy_modes(priv->phy_mode[i]), i);336 return -EINVAL;337 }338 339 mii->phy_mac[i] = role;340 }341 return 0;342}343 344static int sja1105_init_static_fdb(struct sja1105_private *priv)345{346 struct sja1105_l2_lookup_entry *l2_lookup;347 struct sja1105_table *table;348 int port;349 350 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];351 352 /* We only populate the FDB table through dynamic L2 Address Lookup353 * entries, except for a special entry at the end which is a catch-all354 * for unknown multicast and will be used to control flooding domain.355 */356 if (table->entry_count) {357 kfree(table->entries);358 table->entry_count = 0;359 }360 361 if (!priv->info->can_limit_mcast_flood)362 return 0;363 364 table->entries = kcalloc(1, table->ops->unpacked_entry_size,365 GFP_KERNEL);366 if (!table->entries)367 return -ENOMEM;368 369 table->entry_count = 1;370 l2_lookup = table->entries;371 372 /* All L2 multicast addresses have an odd first octet */373 l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST;374 l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST;375 l2_lookup[0].lockeds = true;376 l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1;377 378 /* Flood multicast to every port by default */379 for (port = 0; port < priv->ds->num_ports; port++)380 if (!dsa_is_unused_port(priv->ds, port))381 l2_lookup[0].destports |= BIT(port);382 383 return 0;384}385 386static int sja1105_init_l2_lookup_params(struct sja1105_private *priv)387{388 struct sja1105_l2_lookup_params_entry default_l2_lookup_params = {389 /* Learned FDB entries are forgotten after 300 seconds */390 .maxage = SJA1105_AGEING_TIME_MS(300000),391 /* All entries within a FDB bin are available for learning */392 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE,393 /* And the P/Q/R/S equivalent setting: */394 .start_dynspc = 0,395 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */396 .poly = 0x97,397 /* Always use Independent VLAN Learning (IVL) */398 .shared_learn = false,399 /* Don't discard management traffic based on ENFPORT -400 * we don't perform SMAC port enforcement anyway, so401 * what we are setting here doesn't matter.402 */403 .no_enf_hostprt = false,404 /* Don't learn SMAC for mac_fltres1 and mac_fltres0.405 * Maybe correlate with no_linklocal_learn from bridge driver?406 */407 .no_mgmt_learn = true,408 /* P/Q/R/S only */409 .use_static = true,410 /* Dynamically learned FDB entries can overwrite other (older)411 * dynamic FDB entries412 */413 .owr_dyn = true,414 .drpnolearn = true,415 };416 struct dsa_switch *ds = priv->ds;417 int port, num_used_ports = 0;418 struct sja1105_table *table;419 u64 max_fdb_entries;420 421 for (port = 0; port < ds->num_ports; port++)422 if (!dsa_is_unused_port(ds, port))423 num_used_ports++;424 425 max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports;426 427 for (port = 0; port < ds->num_ports; port++) {428 if (dsa_is_unused_port(ds, port))429 continue;430 431 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries;432 }433 434 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];435 436 if (table->entry_count) {437 kfree(table->entries);438 table->entry_count = 0;439 }440 441 table->entries = kcalloc(table->ops->max_entry_count,442 table->ops->unpacked_entry_size, GFP_KERNEL);443 if (!table->entries)444 return -ENOMEM;445 446 table->entry_count = table->ops->max_entry_count;447 448 /* This table only has a single entry */449 ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] =450 default_l2_lookup_params;451 452 return 0;453}454 455/* Set up a default VLAN for untagged traffic injected from the CPU456 * using management routes (e.g. STP, PTP) as opposed to tag_8021q.457 * All DT-defined ports are members of this VLAN, and there are no458 * restrictions on forwarding (since the CPU selects the destination).459 * Frames from this VLAN will always be transmitted as untagged, and460 * neither the bridge nor the 8021q module cannot create this VLAN ID.461 */462static int sja1105_init_static_vlan(struct sja1105_private *priv)463{464 struct sja1105_table *table;465 struct sja1105_vlan_lookup_entry pvid = {466 .type_entry = SJA1110_VLAN_D_TAG,467 .ving_mirr = 0,468 .vegr_mirr = 0,469 .vmemb_port = 0,470 .vlan_bc = 0,471 .tag_port = 0,472 .vlanid = SJA1105_DEFAULT_VLAN,473 };474 struct dsa_switch *ds = priv->ds;475 int port;476 477 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];478 479 if (table->entry_count) {480 kfree(table->entries);481 table->entry_count = 0;482 }483 484 table->entries = kzalloc(table->ops->unpacked_entry_size,485 GFP_KERNEL);486 if (!table->entries)487 return -ENOMEM;488 489 table->entry_count = 1;490 491 for (port = 0; port < ds->num_ports; port++) {492 if (dsa_is_unused_port(ds, port))493 continue;494 495 pvid.vmemb_port |= BIT(port);496 pvid.vlan_bc |= BIT(port);497 pvid.tag_port &= ~BIT(port);498 499 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {500 priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN;501 priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN;502 }503 }504 505 ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;506 return 0;507}508 509static int sja1105_init_l2_forwarding(struct sja1105_private *priv)510{511 struct sja1105_l2_forwarding_entry *l2fwd;512 struct dsa_switch *ds = priv->ds;513 struct dsa_switch_tree *dst;514 struct sja1105_table *table;515 struct dsa_link *dl;516 int port, tc;517 int from, to;518 519 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];520 521 if (table->entry_count) {522 kfree(table->entries);523 table->entry_count = 0;524 }525 526 table->entries = kcalloc(table->ops->max_entry_count,527 table->ops->unpacked_entry_size, GFP_KERNEL);528 if (!table->entries)529 return -ENOMEM;530 531 table->entry_count = table->ops->max_entry_count;532 533 l2fwd = table->entries;534 535 /* First 5 entries in the L2 Forwarding Table define the forwarding536 * rules and the VLAN PCP to ingress queue mapping.537 * Set up the ingress queue mapping first.538 */539 for (port = 0; port < ds->num_ports; port++) {540 if (dsa_is_unused_port(ds, port))541 continue;542 543 for (tc = 0; tc < SJA1105_NUM_TC; tc++)544 l2fwd[port].vlan_pmap[tc] = tc;545 }546 547 /* Then manage the forwarding domain for user ports. These can forward548 * only to the always-on domain (CPU port and DSA links)549 */550 for (from = 0; from < ds->num_ports; from++) {551 if (!dsa_is_user_port(ds, from))552 continue;553 554 for (to = 0; to < ds->num_ports; to++) {555 if (!dsa_is_cpu_port(ds, to) &&556 !dsa_is_dsa_port(ds, to))557 continue;558 559 l2fwd[from].bc_domain |= BIT(to);560 l2fwd[from].fl_domain |= BIT(to);561 562 sja1105_port_allow_traffic(l2fwd, from, to, true);563 }564 }565 566 /* Then manage the forwarding domain for DSA links and CPU ports (the567 * always-on domain). These can send packets to any enabled port except568 * themselves.569 */570 for (from = 0; from < ds->num_ports; from++) {571 if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from))572 continue;573 574 for (to = 0; to < ds->num_ports; to++) {575 if (dsa_is_unused_port(ds, to))576 continue;577 578 if (from == to)579 continue;580 581 l2fwd[from].bc_domain |= BIT(to);582 l2fwd[from].fl_domain |= BIT(to);583 584 sja1105_port_allow_traffic(l2fwd, from, to, true);585 }586 }587 588 /* In odd topologies ("H" connections where there is a DSA link to589 * another switch which also has its own CPU port), TX packets can loop590 * back into the system (they are flooded from CPU port 1 to the DSA591 * link, and from there to CPU port 2). Prevent this from happening by592 * cutting RX from DSA links towards our CPU port, if the remote switch593 * has its own CPU port and therefore doesn't need ours for network594 * stack termination.595 */596 dst = ds->dst;597 598 list_for_each_entry(dl, &dst->rtable, list) {599 if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp)600 continue;601 602 from = dl->dp->index;603 to = dsa_upstream_port(ds, from);604 605 dev_warn(ds->dev,606 "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",607 from, to);608 609 sja1105_port_allow_traffic(l2fwd, from, to, false);610 611 l2fwd[from].bc_domain &= ~BIT(to);612 l2fwd[from].fl_domain &= ~BIT(to);613 }614 615 /* Finally, manage the egress flooding domain. All ports start up with616 * flooding enabled, including the CPU port and DSA links.617 */618 for (port = 0; port < ds->num_ports; port++) {619 if (dsa_is_unused_port(ds, port))620 continue;621 622 priv->ucast_egress_floods |= BIT(port);623 priv->bcast_egress_floods |= BIT(port);624 }625 626 /* Next 8 entries define VLAN PCP mapping from ingress to egress.627 * Create a one-to-one mapping.628 */629 for (tc = 0; tc < SJA1105_NUM_TC; tc++) {630 for (port = 0; port < ds->num_ports; port++) {631 if (dsa_is_unused_port(ds, port))632 continue;633 634 l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc;635 }636 637 l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true;638 }639 640 return 0;641}642 643static int sja1110_init_pcp_remapping(struct sja1105_private *priv)644{645 struct sja1110_pcp_remapping_entry *pcp_remap;646 struct dsa_switch *ds = priv->ds;647 struct sja1105_table *table;648 int port, tc;649 650 table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING];651 652 /* Nothing to do for SJA1105 */653 if (!table->ops->max_entry_count)654 return 0;655 656 if (table->entry_count) {657 kfree(table->entries);658 table->entry_count = 0;659 }660 661 table->entries = kcalloc(table->ops->max_entry_count,662 table->ops->unpacked_entry_size, GFP_KERNEL);663 if (!table->entries)664 return -ENOMEM;665 666 table->entry_count = table->ops->max_entry_count;667 668 pcp_remap = table->entries;669 670 /* Repeat the configuration done for vlan_pmap */671 for (port = 0; port < ds->num_ports; port++) {672 if (dsa_is_unused_port(ds, port))673 continue;674 675 for (tc = 0; tc < SJA1105_NUM_TC; tc++)676 pcp_remap[port].egrpcp[tc] = tc;677 }678 679 return 0;680}681 682static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)683{684 struct sja1105_l2_forwarding_params_entry *l2fwd_params;685 struct sja1105_table *table;686 687 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];688 689 if (table->entry_count) {690 kfree(table->entries);691 table->entry_count = 0;692 }693 694 table->entries = kcalloc(table->ops->max_entry_count,695 table->ops->unpacked_entry_size, GFP_KERNEL);696 if (!table->entries)697 return -ENOMEM;698 699 table->entry_count = table->ops->max_entry_count;700 701 /* This table only has a single entry */702 l2fwd_params = table->entries;703 704 /* Disallow dynamic reconfiguration of vlan_pmap */705 l2fwd_params->max_dynp = 0;706 /* Use a single memory partition for all ingress queues */707 l2fwd_params->part_spc[0] = priv->info->max_frame_mem;708 709 return 0;710}711 712void sja1105_frame_memory_partitioning(struct sja1105_private *priv)713{714 struct sja1105_l2_forwarding_params_entry *l2_fwd_params;715 struct sja1105_vl_forwarding_params_entry *vl_fwd_params;716 struct sja1105_table *table;717 718 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];719 l2_fwd_params = table->entries;720 l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY;721 722 /* If we have any critical-traffic virtual links, we need to reserve723 * some frame buffer memory for them. At the moment, hardcode the value724 * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks725 * remaining for best-effort traffic. TODO: figure out a more flexible726 * way to perform the frame buffer partitioning.727 */728 if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count)729 return;730 731 table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS];732 vl_fwd_params = table->entries;733 734 l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY;735 vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY;736}737 738/* SJA1110 TDMACONFIGIDX values:739 *740 * | 100 Mbps ports | 1Gbps ports | 2.5Gbps ports | Disabled ports741 * -----+----------------+---------------+---------------+---------------742 * 0 | 0, [5:10] | [1:2] | [3:4] | retag743 * 1 |0, [5:10], retag| [1:2] | [3:4] | -744 * 2 | 0, [5:10] | [1:3], retag | 4 | -745 * 3 | 0, [5:10] |[1:2], 4, retag| 3 | -746 * 4 | 0, 2, [5:10] | 1, retag | [3:4] | -747 * 5 | 0, 1, [5:10] | 2, retag | [3:4] | -748 * 14 | 0, [5:10] | [1:4], retag | - | -749 * 15 | [5:10] | [0:4], retag | - | -750 */751static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv)752{753 struct sja1105_general_params_entry *general_params;754 struct sja1105_table *table;755 bool port_1_is_base_tx;756 bool port_3_is_2500;757 bool port_4_is_2500;758 u64 tdmaconfigidx;759 760 if (priv->info->device_id != SJA1110_DEVICE_ID)761 return;762 763 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];764 general_params = table->entries;765 766 /* All the settings below are "as opposed to SGMII", which is the767 * other pinmuxing option.768 */769 port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL;770 port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX;771 port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX;772 773 if (port_1_is_base_tx)774 /* Retagging port will operate at 1 Gbps */775 tdmaconfigidx = 5;776 else if (port_3_is_2500 && port_4_is_2500)777 /* Retagging port will operate at 100 Mbps */778 tdmaconfigidx = 1;779 else if (port_3_is_2500)780 /* Retagging port will operate at 1 Gbps */781 tdmaconfigidx = 3;782 else if (port_4_is_2500)783 /* Retagging port will operate at 1 Gbps */784 tdmaconfigidx = 2;785 else786 /* Retagging port will operate at 1 Gbps */787 tdmaconfigidx = 14;788 789 general_params->tdmaconfigidx = tdmaconfigidx;790}791 792static int sja1105_init_topology(struct sja1105_private *priv,793 struct sja1105_general_params_entry *general_params)794{795 struct dsa_switch *ds = priv->ds;796 int port;797 798 /* The host port is the destination for traffic matching mac_fltres1799 * and mac_fltres0 on all ports except itself. Default to an invalid800 * value.801 */802 general_params->host_port = ds->num_ports;803 804 /* Link-local traffic received on casc_port will be forwarded805 * to host_port without embedding the source port and device ID806 * info in the destination MAC address, and no RX timestamps will be807 * taken either (presumably because it is a cascaded port and a808 * downstream SJA switch already did that).809 * To disable the feature, we need to do different things depending on810 * switch generation. On SJA1105 we need to set an invalid port, while811 * on SJA1110 which support multiple cascaded ports, this field is a812 * bitmask so it must be left zero.813 */814 if (!priv->info->multiple_cascade_ports)815 general_params->casc_port = ds->num_ports;816 817 for (port = 0; port < ds->num_ports; port++) {818 bool is_upstream = dsa_is_upstream_port(ds, port);819 bool is_dsa_link = dsa_is_dsa_port(ds, port);820 821 /* Upstream ports can be dedicated CPU ports or822 * upstream-facing DSA links823 */824 if (is_upstream) {825 if (general_params->host_port == ds->num_ports) {826 general_params->host_port = port;827 } else {828 dev_err(ds->dev,829 "Port %llu is already a host port, configuring %d as one too is not supported\n",830 general_params->host_port, port);831 return -EINVAL;832 }833 }834 835 /* Cascade ports are downstream-facing DSA links */836 if (is_dsa_link && !is_upstream) {837 if (priv->info->multiple_cascade_ports) {838 general_params->casc_port |= BIT(port);839 } else if (general_params->casc_port == ds->num_ports) {840 general_params->casc_port = port;841 } else {842 dev_err(ds->dev,843 "Port %llu is already a cascade port, configuring %d as one too is not supported\n",844 general_params->casc_port, port);845 return -EINVAL;846 }847 }848 }849 850 if (general_params->host_port == ds->num_ports) {851 dev_err(ds->dev, "No host port configured\n");852 return -EINVAL;853 }854 855 return 0;856}857 858static int sja1105_init_general_params(struct sja1105_private *priv)859{860 struct sja1105_general_params_entry default_general_params = {861 /* Allow dynamic changing of the mirror port */862 .mirr_ptacu = true,863 .switchid = priv->ds->index,864 /* Priority queue for link-local management frames865 * (both ingress to and egress from CPU - PTP, STP etc)866 */867 .hostprio = 7,868 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A,869 .mac_flt1 = SJA1105_LINKLOCAL_FILTER_A_MASK,870 .incl_srcpt1 = true,871 .send_meta1 = true,872 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B,873 .mac_flt0 = SJA1105_LINKLOCAL_FILTER_B_MASK,874 .incl_srcpt0 = true,875 .send_meta0 = true,876 /* Default to an invalid value */877 .mirr_port = priv->ds->num_ports,878 /* No TTEthernet */879 .vllupformat = SJA1105_VL_FORMAT_PSFP,880 .vlmarker = 0,881 .vlmask = 0,882 /* Only update correctionField for 1-step PTP (L2 transport) */883 .ignore2stf = 0,884 /* Forcefully disable VLAN filtering by telling885 * the switch that VLAN has a different EtherType.886 */887 .tpid = ETH_P_SJA1105,888 .tpid2 = ETH_P_SJA1105,889 /* Enable the TTEthernet engine on SJA1110 */890 .tte_en = true,891 /* Set up the EtherType for control packets on SJA1110 */892 .header_type = ETH_P_SJA1110,893 };894 struct sja1105_general_params_entry *general_params;895 struct sja1105_table *table;896 int rc;897 898 rc = sja1105_init_topology(priv, &default_general_params);899 if (rc)900 return rc;901 902 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];903 904 if (table->entry_count) {905 kfree(table->entries);906 table->entry_count = 0;907 }908 909 table->entries = kcalloc(table->ops->max_entry_count,910 table->ops->unpacked_entry_size, GFP_KERNEL);911 if (!table->entries)912 return -ENOMEM;913 914 table->entry_count = table->ops->max_entry_count;915 916 general_params = table->entries;917 918 /* This table only has a single entry */919 general_params[0] = default_general_params;920 921 sja1110_select_tdmaconfigidx(priv);922 923 return 0;924}925 926static int sja1105_init_avb_params(struct sja1105_private *priv)927{928 struct sja1105_avb_params_entry *avb;929 struct sja1105_table *table;930 931 table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];932 933 /* Discard previous AVB Parameters Table */934 if (table->entry_count) {935 kfree(table->entries);936 table->entry_count = 0;937 }938 939 table->entries = kcalloc(table->ops->max_entry_count,940 table->ops->unpacked_entry_size, GFP_KERNEL);941 if (!table->entries)942 return -ENOMEM;943 944 table->entry_count = table->ops->max_entry_count;945 946 avb = table->entries;947 948 /* Configure the MAC addresses for meta frames */949 avb->destmeta = SJA1105_META_DMAC;950 avb->srcmeta = SJA1105_META_SMAC;951 /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by952 * default. This is because there might be boards with a hardware953 * layout where enabling the pin as output might cause an electrical954 * clash. On E/T the pin is always an output, which the board designers955 * probably already knew, so even if there are going to be electrical956 * issues, there's nothing we can do.957 */958 avb->cas_master = false;959 960 return 0;961}962 963/* The L2 policing table is 2-stage. The table is looked up for each frame964 * according to the ingress port, whether it was broadcast or not, and the965 * classified traffic class (given by VLAN PCP). This portion of the lookup is966 * fixed, and gives access to the SHARINDX, an indirection register pointing967 * within the policing table itself, which is used to resolve the policer that968 * will be used for this frame.969 *970 * Stage 1 Stage 2971 * +------------+--------+ +---------------------------------+972 * |Port 0 TC 0 |SHARINDX| | Policer 0: Rate, Burst, MTU |973 * +------------+--------+ +---------------------------------+974 * |Port 0 TC 1 |SHARINDX| | Policer 1: Rate, Burst, MTU |975 * +------------+--------+ +---------------------------------+976 * ... | Policer 2: Rate, Burst, MTU |977 * +------------+--------+ +---------------------------------+978 * |Port 0 TC 7 |SHARINDX| | Policer 3: Rate, Burst, MTU |979 * +------------+--------+ +---------------------------------+980 * |Port 1 TC 0 |SHARINDX| | Policer 4: Rate, Burst, MTU |981 * +------------+--------+ +---------------------------------+982 * ... | Policer 5: Rate, Burst, MTU |983 * +------------+--------+ +---------------------------------+984 * |Port 1 TC 7 |SHARINDX| | Policer 6: Rate, Burst, MTU |985 * +------------+--------+ +---------------------------------+986 * ... | Policer 7: Rate, Burst, MTU |987 * +------------+--------+ +---------------------------------+988 * |Port 4 TC 7 |SHARINDX| ...989 * +------------+--------+990 * |Port 0 BCAST|SHARINDX| ...991 * +------------+--------+992 * |Port 1 BCAST|SHARINDX| ...993 * +------------+--------+994 * ... ...995 * +------------+--------+ +---------------------------------+996 * |Port 4 BCAST|SHARINDX| | Policer 44: Rate, Burst, MTU |997 * +------------+--------+ +---------------------------------+998 *999 * In this driver, we shall use policers 0-4 as statically alocated port1000 * (matchall) policers. So we need to make the SHARINDX for all lookups1001 * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast1002 * lookup) equal.1003 * The remaining policers (40) shall be dynamically allocated for flower1004 * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.1005 */1006#define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)1007 1008static int sja1105_init_l2_policing(struct sja1105_private *priv)1009{1010 struct sja1105_l2_policing_entry *policing;1011 struct dsa_switch *ds = priv->ds;1012 struct sja1105_table *table;1013 int port, tc;1014 1015 table = &priv->static_config.tables[BLK_IDX_L2_POLICING];1016 1017 /* Discard previous L2 Policing Table */1018 if (table->entry_count) {1019 kfree(table->entries);1020 table->entry_count = 0;1021 }1022 1023 table->entries = kcalloc(table->ops->max_entry_count,1024 table->ops->unpacked_entry_size, GFP_KERNEL);1025 if (!table->entries)1026 return -ENOMEM;1027 1028 table->entry_count = table->ops->max_entry_count;1029 1030 policing = table->entries;1031 1032 /* Setup shared indices for the matchall policers */1033 for (port = 0; port < ds->num_ports; port++) {1034 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port;1035 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port;1036 1037 for (tc = 0; tc < SJA1105_NUM_TC; tc++)1038 policing[port * SJA1105_NUM_TC + tc].sharindx = port;1039 1040 policing[bcast].sharindx = port;1041 /* Only SJA1110 has multicast policers */1042 if (mcast < table->ops->max_entry_count)1043 policing[mcast].sharindx = port;1044 }1045 1046 /* Setup the matchall policer parameters */1047 for (port = 0; port < ds->num_ports; port++) {1048 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;1049 1050 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))1051 mtu += VLAN_HLEN;1052 1053 policing[port].smax = 65535; /* Burst size in bytes */1054 policing[port].rate = SJA1105_RATE_MBPS(1000);1055 policing[port].maxlen = mtu;1056 policing[port].partition = 0;1057 }1058 1059 return 0;1060}1061 1062static int sja1105_static_config_load(struct sja1105_private *priv)1063{1064 int rc;1065 1066 sja1105_static_config_free(&priv->static_config);1067 rc = sja1105_static_config_init(&priv->static_config,1068 priv->info->static_ops,1069 priv->info->device_id);1070 if (rc)1071 return rc;1072 1073 /* Build static configuration */1074 rc = sja1105_init_mac_settings(priv);1075 if (rc < 0)1076 return rc;1077 rc = sja1105_init_mii_settings(priv);1078 if (rc < 0)1079 return rc;1080 rc = sja1105_init_static_fdb(priv);1081 if (rc < 0)1082 return rc;1083 rc = sja1105_init_static_vlan(priv);1084 if (rc < 0)1085 return rc;1086 rc = sja1105_init_l2_lookup_params(priv);1087 if (rc < 0)1088 return rc;1089 rc = sja1105_init_l2_forwarding(priv);1090 if (rc < 0)1091 return rc;1092 rc = sja1105_init_l2_forwarding_params(priv);1093 if (rc < 0)1094 return rc;1095 rc = sja1105_init_l2_policing(priv);1096 if (rc < 0)1097 return rc;1098 rc = sja1105_init_general_params(priv);1099 if (rc < 0)1100 return rc;1101 rc = sja1105_init_avb_params(priv);1102 if (rc < 0)1103 return rc;1104 rc = sja1110_init_pcp_remapping(priv);1105 if (rc < 0)1106 return rc;1107 1108 /* Send initial configuration to hardware via SPI */1109 return sja1105_static_config_upload(priv);1110}1111 1112/* This is the "new way" for a MAC driver to configure its RGMII delay lines,1113 * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps"1114 * properties. It has the advantage of working with fixed links and with PHYs1115 * that apply RGMII delays too, and the MAC driver needs not perform any1116 * special checks.1117 *1118 * Previously we were acting upon the "phy-mode" property when we were1119 * operating in fixed-link, basically acting as a PHY, but with a reversed1120 * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should1121 * behave as if it is connected to a PHY which has applied RGMII delays in the1122 * TX direction. So if anything, RX delays should have been added by the MAC,1123 * but we were adding TX delays.1124 *1125 * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall1126 * back to the legacy behavior and apply delays on fixed-link ports based on1127 * the reverse interpretation of the phy-mode. This is a deviation from the1128 * expected default behavior which is to simply apply no delays. To achieve1129 * that behavior with the new bindings, it is mandatory to specify1130 * "{rx,tx}-internal-delay-ps" with a value of 0.1131 */1132static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port,1133 struct device_node *port_dn)1134{1135 phy_interface_t phy_mode = priv->phy_mode[port];1136 struct device *dev = &priv->spidev->dev;1137 int rx_delay = -1, tx_delay = -1;1138 1139 if (!phy_interface_mode_is_rgmii(phy_mode))1140 return 0;1141 1142 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);1143 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);1144 1145 if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) {1146 dev_warn(dev,1147 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "1148 "please update device tree to specify \"rx-internal-delay-ps\" and "1149 "\"tx-internal-delay-ps\"",1150 port);1151 1152 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||1153 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)1154 rx_delay = 2000;1155 1156 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||1157 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)1158 tx_delay = 2000;1159 }1160 1161 if (rx_delay < 0)1162 rx_delay = 0;1163 if (tx_delay < 0)1164 tx_delay = 0;1165 1166 if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) {1167 dev_err(dev, "Chip cannot apply RGMII delays\n");1168 return -EINVAL;1169 }1170 1171 if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||1172 (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||1173 (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) ||1174 (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) {1175 dev_err(dev,1176 "port %d RGMII delay values out of range, must be between %d and %d ps\n",1177 port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS);1178 return -ERANGE;1179 }1180 1181 priv->rgmii_rx_delay_ps[port] = rx_delay;1182 priv->rgmii_tx_delay_ps[port] = tx_delay;1183 1184 return 0;1185}1186 1187static int sja1105_parse_ports_node(struct sja1105_private *priv,1188 struct device_node *ports_node)1189{1190 struct device *dev = &priv->spidev->dev;1191 1192 for_each_available_child_of_node_scoped(ports_node, child) {1193 struct device_node *phy_node;1194 phy_interface_t phy_mode;1195 u32 index;1196 int err;1197 1198 /* Get switch port number from DT */1199 if (of_property_read_u32(child, "reg", &index) < 0) {1200 dev_err(dev, "Port number not defined in device tree "1201 "(property \"reg\")\n");1202 return -ENODEV;1203 }1204 1205 /* Get PHY mode from DT */1206 err = of_get_phy_mode(child, &phy_mode);1207 if (err) {1208 dev_err(dev, "Failed to read phy-mode or "1209 "phy-interface-type property for port %d\n",1210 index);1211 return -ENODEV;1212 }1213 1214 phy_node = of_parse_phandle(child, "phy-handle", 0);1215 if (!phy_node) {1216 if (!of_phy_is_fixed_link(child)) {1217 dev_err(dev, "phy-handle or fixed-link "1218 "properties missing!\n");1219 return -ENODEV;1220 }1221 /* phy-handle is missing, but fixed-link isn't.1222 * So it's a fixed link. Default to PHY role.1223 */1224 priv->fixed_link[index] = true;1225 } else {1226 of_node_put(phy_node);1227 }1228 1229 priv->phy_mode[index] = phy_mode;1230 1231 err = sja1105_parse_rgmii_delays(priv, index, child);1232 if (err)1233 return err;1234 }1235 1236 return 0;1237}1238 1239static int sja1105_parse_dt(struct sja1105_private *priv)1240{1241 struct device *dev = &priv->spidev->dev;1242 struct device_node *switch_node = dev->of_node;1243 struct device_node *ports_node;1244 int rc;1245 1246 ports_node = of_get_child_by_name(switch_node, "ports");1247 if (!ports_node)1248 ports_node = of_get_child_by_name(switch_node, "ethernet-ports");1249 if (!ports_node) {1250 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");1251 return -ENODEV;1252 }1253 1254 rc = sja1105_parse_ports_node(priv, ports_node);1255 of_node_put(ports_node);1256 1257 return rc;1258}1259 1260/* Convert link speed from SJA1105 to ethtool encoding */1261static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv,1262 u64 speed)1263{1264 if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS])1265 return SPEED_10;1266 if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS])1267 return SPEED_100;1268 if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS])1269 return SPEED_1000;1270 if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS])1271 return SPEED_2500;1272 return SPEED_UNKNOWN;1273}1274 1275/* Set link speed in the MAC configuration for a specific port. */1276static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,1277 int speed_mbps)1278{1279 struct sja1105_mac_config_entry *mac;1280 struct device *dev = priv->ds->dev;1281 u64 speed;1282 int rc;1283 1284 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration1285 * tables. On E/T, MAC reconfig tables are not readable, only writable.1286 * We have to *know* what the MAC looks like. For the sake of keeping1287 * the code common, we'll use the static configuration tables as a1288 * reasonable approximation for both E/T and P/Q/R/S.1289 */1290 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;1291 1292 switch (speed_mbps) {1293 case SPEED_UNKNOWN:1294 /* PHYLINK called sja1105_mac_config() to inform us about1295 * the state->interface, but AN has not completed and the1296 * speed is not yet valid. UM10944.pdf says that setting1297 * SJA1105_SPEED_AUTO at runtime disables the port, so that is1298 * ok for power consumption in case AN will never complete -1299 * otherwise PHYLINK should come back with a new update.1300 */1301 speed = priv->info->port_speed[SJA1105_SPEED_AUTO];1302 break;1303 case SPEED_10:1304 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];1305 break;1306 case SPEED_100:1307 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];1308 break;1309 case SPEED_1000:1310 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];1311 break;1312 case SPEED_2500:1313 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];1314 break;1315 default:1316 dev_err(dev, "Invalid speed %iMbps\n", speed_mbps);1317 return -EINVAL;1318 }1319 1320 /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration1321 * table, since this will be used for the clocking setup, and we no1322 * longer need to store it in the static config (already told hardware1323 * we want auto during upload phase).1324 * Actually for the SGMII port, the MAC is fixed at 1 Gbps and1325 * we need to configure the PCS only (if even that).1326 */1327 if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)1328 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];1329 else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)1330 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];1331 else1332 mac[port].speed = speed;1333 1334 /* Write to the dynamic reconfiguration tables */1335 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,1336 &mac[port], true);1337 if (rc < 0) {1338 dev_err(dev, "Failed to write MAC config: %d\n", rc);1339 return rc;1340 }1341 1342 /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at1343 * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and1344 * RMII no change of the clock setup is required. Actually, changing1345 * the clock setup does interrupt the clock signal for a certain time1346 * which causes trouble for all PHYs relying on this signal.1347 */1348 if (!phy_interface_mode_is_rgmii(priv->phy_mode[port]))1349 return 0;1350 1351 return sja1105_clocking_setup_port(priv, port);1352}1353 1354static struct phylink_pcs *1355sja1105_mac_select_pcs(struct phylink_config *config, phy_interface_t iface)1356{1357 struct dsa_port *dp = dsa_phylink_to_port(config);1358 struct sja1105_private *priv = dp->ds->priv;1359 struct dw_xpcs *xpcs = priv->xpcs[dp->index];1360 1361 if (xpcs)1362 return &xpcs->pcs;1363 1364 return NULL;1365}1366 1367static void sja1105_mac_config(struct phylink_config *config,1368 unsigned int mode,1369 const struct phylink_link_state *state)1370{1371}1372 1373static void sja1105_mac_link_down(struct phylink_config *config,1374 unsigned int mode,1375 phy_interface_t interface)1376{1377 struct dsa_port *dp = dsa_phylink_to_port(config);1378 1379 sja1105_inhibit_tx(dp->ds->priv, BIT(dp->index), true);1380}1381 1382static void sja1105_mac_link_up(struct phylink_config *config,1383 struct phy_device *phydev,1384 unsigned int mode,1385 phy_interface_t interface,1386 int speed, int duplex,1387 bool tx_pause, bool rx_pause)1388{1389 struct dsa_port *dp = dsa_phylink_to_port(config);1390 struct sja1105_private *priv = dp->ds->priv;1391 int port = dp->index;1392 1393 sja1105_adjust_port_config(priv, port, speed);1394 1395 sja1105_inhibit_tx(priv, BIT(port), false);1396}1397 1398static void sja1105_phylink_get_caps(struct dsa_switch *ds, int port,1399 struct phylink_config *config)1400{1401 struct sja1105_private *priv = ds->priv;1402 struct sja1105_xmii_params_entry *mii;1403 phy_interface_t phy_mode;1404 1405 phy_mode = priv->phy_mode[port];1406 if (phy_mode == PHY_INTERFACE_MODE_SGMII ||1407 phy_mode == PHY_INTERFACE_MODE_2500BASEX) {1408 /* Changing the PHY mode on SERDES ports is possible and makes1409 * sense, because that is done through the XPCS. We allow1410 * changes between SGMII and 2500base-X.1411 */1412 if (priv->info->supports_sgmii[port])1413 __set_bit(PHY_INTERFACE_MODE_SGMII,1414 config->supported_interfaces);1415 1416 if (priv->info->supports_2500basex[port])1417 __set_bit(PHY_INTERFACE_MODE_2500BASEX,1418 config->supported_interfaces);1419 } else {1420 /* The SJA1105 MAC programming model is through the static1421 * config (the xMII Mode table cannot be dynamically1422 * reconfigured), and we have to program that early.1423 */1424 __set_bit(phy_mode, config->supported_interfaces);1425 }1426 1427 /* The MAC does not support pause frames, and also doesn't1428 * support half-duplex traffic modes.1429 */1430 config->mac_capabilities = MAC_10FD | MAC_100FD;1431 1432 mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;1433 if (mii->xmii_mode[port] == XMII_MODE_RGMII ||1434 mii->xmii_mode[port] == XMII_MODE_SGMII)1435 config->mac_capabilities |= MAC_1000FD;1436 1437 if (priv->info->supports_2500basex[port])1438 config->mac_capabilities |= MAC_2500FD;1439}1440 1441static int1442sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port,1443 const struct sja1105_l2_lookup_entry *requested)1444{1445 struct sja1105_l2_lookup_entry *l2_lookup;1446 struct sja1105_table *table;1447 int i;1448 1449 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];1450 l2_lookup = table->entries;1451 1452 for (i = 0; i < table->entry_count; i++)1453 if (l2_lookup[i].macaddr == requested->macaddr &&1454 l2_lookup[i].vlanid == requested->vlanid &&1455 l2_lookup[i].destports & BIT(port))1456 return i;1457 1458 return -1;1459}1460 1461/* We want FDB entries added statically through the bridge command to persist1462 * across switch resets, which are a common thing during normal SJA11051463 * operation. So we have to back them up in the static configuration tables1464 * and hence apply them on next static config upload... yay!1465 */1466static int1467sja1105_static_fdb_change(struct sja1105_private *priv, int port,1468 const struct sja1105_l2_lookup_entry *requested,1469 bool keep)1470{1471 struct sja1105_l2_lookup_entry *l2_lookup;1472 struct sja1105_table *table;1473 int rc, match;1474 1475 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];1476 1477 match = sja1105_find_static_fdb_entry(priv, port, requested);1478 if (match < 0) {1479 /* Can't delete a missing entry. */1480 if (!keep)1481 return 0;1482 1483 /* No match => new entry */1484 rc = sja1105_table_resize(table, table->entry_count + 1);1485 if (rc)1486 return rc;1487 1488 match = table->entry_count - 1;1489 }1490 1491 /* Assign pointer after the resize (it may be new memory) */1492 l2_lookup = table->entries;1493 1494 /* We have a match.1495 * If the job was to add this FDB entry, it's already done (mostly1496 * anyway, since the port forwarding mask may have changed, case in1497 * which we update it).1498 * Otherwise we have to delete it.1499 */1500 if (keep) {1501 l2_lookup[match] = *requested;1502 return 0;1503 }1504 1505 /* To remove, the strategy is to overwrite the element with1506 * the last one, and then reduce the array size by 11507 */1508 l2_lookup[match] = l2_lookup[table->entry_count - 1];1509 return sja1105_table_resize(table, table->entry_count - 1);1510}1511 1512/* First-generation switches have a 4-way set associative TCAM that1513 * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of1514 * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).1515 * For the placement of a newly learnt FDB entry, the switch selects the bin1516 * based on a hash function, and the way within that bin incrementally.1517 */1518static int sja1105et_fdb_index(int bin, int way)1519{1520 return bin * SJA1105ET_FDB_BIN_SIZE + way;1521}1522 1523static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin,1524 const u8 *addr, u16 vid,1525 struct sja1105_l2_lookup_entry *match,1526 int *last_unused)1527{1528 int way;1529 1530 for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) {1531 struct sja1105_l2_lookup_entry l2_lookup = {0};1532 int index = sja1105et_fdb_index(bin, way);1533 1534 /* Skip unused entries, optionally marking them1535 * into the return value1536 */1537 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,1538 index, &l2_lookup)) {1539 if (last_unused)1540 *last_unused = way;1541 continue;1542 }1543 1544 if (l2_lookup.macaddr == ether_addr_to_u64(addr) &&1545 l2_lookup.vlanid == vid) {1546 if (match)1547 *match = l2_lookup;1548 return way;1549 }1550 }1551 /* Return an invalid entry index if not found */1552 return -1;1553}1554 1555int sja1105et_fdb_add(struct dsa_switch *ds, int port,1556 const unsigned char *addr, u16 vid)1557{1558 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;1559 struct sja1105_private *priv = ds->priv;1560 struct device *dev = ds->dev;1561 int last_unused = -1;1562 int start, end, i;1563 int bin, way, rc;1564 1565 bin = sja1105et_fdb_hash(priv, addr, vid);1566 1567 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,1568 &l2_lookup, &last_unused);1569 if (way >= 0) {1570 /* We have an FDB entry. Is our port in the destination1571 * mask? If yes, we need to do nothing. If not, we need1572 * to rewrite the entry by adding this port to it.1573 */1574 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds)1575 return 0;1576 l2_lookup.destports |= BIT(port);1577 } else {1578 int index = sja1105et_fdb_index(bin, way);1579 1580 /* We don't have an FDB entry. We construct a new one and1581 * try to find a place for it within the FDB table.1582 */1583 l2_lookup.macaddr = ether_addr_to_u64(addr);1584 l2_lookup.destports = BIT(port);1585 l2_lookup.vlanid = vid;1586 1587 if (last_unused >= 0) {1588 way = last_unused;1589 } else {1590 /* Bin is full, need to evict somebody.1591 * Choose victim at random. If you get these messages1592 * often, you may need to consider changing the1593 * distribution function:1594 * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly1595 */1596 get_random_bytes(&way, sizeof(u8));1597 way %= SJA1105ET_FDB_BIN_SIZE;1598 dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",1599 bin, addr, way);1600 /* Evict entry */1601 sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,1602 index, NULL, false);1603 }1604 }1605 l2_lookup.lockeds = true;1606 l2_lookup.index = sja1105et_fdb_index(bin, way);1607 1608 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,1609 l2_lookup.index, &l2_lookup,1610 true);1611 if (rc < 0)1612 return rc;1613 1614 /* Invalidate a dynamically learned entry if that exists */1615 start = sja1105et_fdb_index(bin, 0);1616 end = sja1105et_fdb_index(bin, way);1617 1618 for (i = start; i < end; i++) {1619 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,1620 i, &tmp);1621 if (rc == -ENOENT)1622 continue;1623 if (rc)1624 return rc;1625 1626 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid)1627 continue;1628 1629 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,1630 i, NULL, false);1631 if (rc)1632 return rc;1633 1634 break;1635 }1636 1637 return sja1105_static_fdb_change(priv, port, &l2_lookup, true);1638}1639 1640int sja1105et_fdb_del(struct dsa_switch *ds, int port,1641 const unsigned char *addr, u16 vid)1642{1643 struct sja1105_l2_lookup_entry l2_lookup = {0};1644 struct sja1105_private *priv = ds->priv;1645 int index, bin, way, rc;1646 bool keep;1647 1648 bin = sja1105et_fdb_hash(priv, addr, vid);1649 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,1650 &l2_lookup, NULL);1651 if (way < 0)1652 return 0;1653 index = sja1105et_fdb_index(bin, way);1654 1655 /* We have an FDB entry. Is our port in the destination mask? If yes,1656 * we need to remove it. If the resulting port mask becomes empty, we1657 * need to completely evict the FDB entry.1658 * Otherwise we just write it back.1659 */1660 l2_lookup.destports &= ~BIT(port);1661 1662 if (l2_lookup.destports)1663 keep = true;1664 else1665 keep = false;1666 1667 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,1668 index, &l2_lookup, keep);1669 if (rc < 0)1670 return rc;1671 1672 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);1673}1674 1675int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,1676 const unsigned char *addr, u16 vid)1677{1678 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;1679 struct sja1105_private *priv = ds->priv;1680 int rc, i;1681 1682 /* Search for an existing entry in the FDB table */1683 l2_lookup.macaddr = ether_addr_to_u64(addr);1684 l2_lookup.vlanid = vid;1685 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);1686 l2_lookup.mask_vlanid = VLAN_VID_MASK;1687 l2_lookup.destports = BIT(port);1688 1689 tmp = l2_lookup;1690 1691 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,1692 SJA1105_SEARCH, &tmp);1693 if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) {1694 /* Found a static entry and this port is already in the entry's1695 * port mask => job done1696 */1697 if ((tmp.destports & BIT(port)) && tmp.lockeds)1698 return 0;1699 1700 l2_lookup = tmp;1701 1702 /* l2_lookup.index is populated by the switch in case it1703 * found something.1704 */1705 l2_lookup.destports |= BIT(port);1706 goto skip_finding_an_index;1707 }1708 1709 /* Not found, so try to find an unused spot in the FDB.1710 * This is slightly inefficient because the strategy is knock-knock at1711 * every possible position from 0 to 1023.1712 */1713 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {1714 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,1715 i, NULL);1716 if (rc < 0)1717 break;1718 }1719 if (i == SJA1105_MAX_L2_LOOKUP_COUNT) {1720 dev_err(ds->dev, "FDB is full, cannot add entry.\n");1721 return -EINVAL;1722 }1723 l2_lookup.index = i;1724 1725skip_finding_an_index:1726 l2_lookup.lockeds = true;1727 1728 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,1729 l2_lookup.index, &l2_lookup,1730 true);1731 if (rc < 0)1732 return rc;1733 1734 /* The switch learns dynamic entries and looks up the FDB left to1735 * right. It is possible that our addition was concurrent with the1736 * dynamic learning of the same address, so now that the static entry1737 * has been installed, we are certain that address learning for this1738 * particular address has been turned off, so the dynamic entry either1739 * is in the FDB at an index smaller than the static one, or isn't (it1740 * can also be at a larger index, but in that case it is inactive1741 * because the static FDB entry will match first, and the dynamic one1742 * will eventually age out). Search for a dynamically learned address1743 * prior to our static one and invalidate it.1744 */1745 tmp = l2_lookup;1746 1747 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,1748 SJA1105_SEARCH, &tmp);1749 if (rc < 0) {1750 dev_err(ds->dev,1751 "port %d failed to read back entry for %pM vid %d: %pe\n",1752 port, addr, vid, ERR_PTR(rc));1753 return rc;1754 }1755 1756 if (tmp.index < l2_lookup.index) {1757 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,1758 tmp.index, NULL, false);1759 if (rc < 0)1760 return rc;1761 }1762 1763 return sja1105_static_fdb_change(priv, port, &l2_lookup, true);1764}1765 1766int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,1767 const unsigned char *addr, u16 vid)1768{1769 struct sja1105_l2_lookup_entry l2_lookup = {0};1770 struct sja1105_private *priv = ds->priv;1771 bool keep;1772 int rc;1773 1774 l2_lookup.macaddr = ether_addr_to_u64(addr);1775 l2_lookup.vlanid = vid;1776 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);1777 l2_lookup.mask_vlanid = VLAN_VID_MASK;1778 l2_lookup.destports = BIT(port);1779 1780 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,1781 SJA1105_SEARCH, &l2_lookup);1782 if (rc < 0)1783 return 0;1784 1785 l2_lookup.destports &= ~BIT(port);1786 1787 /* Decide whether we remove just this port from the FDB entry,1788 * or if we remove it completely.1789 */1790 if (l2_lookup.destports)1791 keep = true;1792 else1793 keep = false;1794 1795 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,1796 l2_lookup.index, &l2_lookup, keep);1797 if (rc < 0)1798 return rc;1799 1800 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);1801}1802 1803static int sja1105_fdb_add(struct dsa_switch *ds, int port,1804 const unsigned char *addr, u16 vid,1805 struct dsa_db db)1806{1807 struct sja1105_private *priv = ds->priv;1808 int rc;1809 1810 if (!vid) {1811 switch (db.type) {1812 case DSA_DB_PORT:1813 vid = dsa_tag_8021q_standalone_vid(db.dp);1814 break;1815 case DSA_DB_BRIDGE:1816 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);1817 break;1818 default:1819 return -EOPNOTSUPP;1820 }1821 }1822 1823 mutex_lock(&priv->fdb_lock);1824 rc = priv->info->fdb_add_cmd(ds, port, addr, vid);1825 mutex_unlock(&priv->fdb_lock);1826 1827 return rc;1828}1829 1830static int __sja1105_fdb_del(struct dsa_switch *ds, int port,1831 const unsigned char *addr, u16 vid,1832 struct dsa_db db)1833{1834 struct sja1105_private *priv = ds->priv;1835 1836 if (!vid) {1837 switch (db.type) {1838 case DSA_DB_PORT:1839 vid = dsa_tag_8021q_standalone_vid(db.dp);1840 break;1841 case DSA_DB_BRIDGE:1842 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);1843 break;1844 default:1845 return -EOPNOTSUPP;1846 }1847 }1848 1849 return priv->info->fdb_del_cmd(ds, port, addr, vid);1850}1851 1852static int sja1105_fdb_del(struct dsa_switch *ds, int port,1853 const unsigned char *addr, u16 vid,1854 struct dsa_db db)1855{1856 struct sja1105_private *priv = ds->priv;1857 int rc;1858 1859 mutex_lock(&priv->fdb_lock);1860 rc = __sja1105_fdb_del(ds, port, addr, vid, db);1861 mutex_unlock(&priv->fdb_lock);1862 1863 return rc;1864}1865 1866static int sja1105_fdb_dump(struct dsa_switch *ds, int port,1867 dsa_fdb_dump_cb_t *cb, void *data)1868{1869 struct sja1105_private *priv = ds->priv;1870 struct device *dev = ds->dev;1871 int i;1872 1873 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {1874 struct sja1105_l2_lookup_entry l2_lookup = {0};1875 u8 macaddr[ETH_ALEN];1876 int rc;1877 1878 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,1879 i, &l2_lookup);1880 /* No fdb entry at i, not an issue */1881 if (rc == -ENOENT)1882 continue;1883 if (rc) {1884 dev_err(dev, "Failed to dump FDB: %d\n", rc);1885 return rc;1886 }1887 1888 /* FDB dump callback is per port. This means we have to1889 * disregard a valid entry if it's not for this port, even if1890 * only to revisit it later. This is inefficient because the1891 * 1024-sized FDB table needs to be traversed 4 times through1892 * SPI during a 'bridge fdb show' command.1893 */1894 if (!(l2_lookup.destports & BIT(port)))1895 continue;1896 1897 u64_to_ether_addr(l2_lookup.macaddr, macaddr);1898 1899 /* Hardware FDB is shared for fdb and mdb, "bridge fdb show"1900 * only wants to see unicast1901 */1902 if (is_multicast_ether_addr(macaddr))1903 continue;1904 1905 /* We need to hide the dsa_8021q VLANs from the user. */1906 if (vid_is_dsa_8021q(l2_lookup.vlanid))1907 l2_lookup.vlanid = 0;1908 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data);1909 if (rc)1910 return rc;1911 }1912 return 0;1913}1914 1915static void sja1105_fast_age(struct dsa_switch *ds, int port)1916{1917 struct dsa_port *dp = dsa_to_port(ds, port);1918 struct sja1105_private *priv = ds->priv;1919 struct dsa_db db = {1920 .type = DSA_DB_BRIDGE,1921 .bridge = {1922 .dev = dsa_port_bridge_dev_get(dp),1923 .num = dsa_port_bridge_num_get(dp),1924 },1925 };1926 int i;1927 1928 mutex_lock(&priv->fdb_lock);1929 1930 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {1931 struct sja1105_l2_lookup_entry l2_lookup = {0};1932 u8 macaddr[ETH_ALEN];1933 int rc;1934 1935 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,1936 i, &l2_lookup);1937 /* No fdb entry at i, not an issue */1938 if (rc == -ENOENT)1939 continue;1940 if (rc) {1941 dev_err(ds->dev, "Failed to read FDB: %pe\n",1942 ERR_PTR(rc));1943 break;1944 }1945 1946 if (!(l2_lookup.destports & BIT(port)))1947 continue;1948 1949 /* Don't delete static FDB entries */1950 if (l2_lookup.lockeds)1951 continue;1952 1953 u64_to_ether_addr(l2_lookup.macaddr, macaddr);1954 1955 rc = __sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid, db);1956 if (rc) {1957 dev_err(ds->dev,1958 "Failed to delete FDB entry %pM vid %lld: %pe\n",1959 macaddr, l2_lookup.vlanid, ERR_PTR(rc));1960 break;1961 }1962 }1963 1964 mutex_unlock(&priv->fdb_lock);1965}1966 1967static int sja1105_mdb_add(struct dsa_switch *ds, int port,1968 const struct switchdev_obj_port_mdb *mdb,1969 struct dsa_db db)1970{1971 return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid, db);1972}1973 1974static int sja1105_mdb_del(struct dsa_switch *ds, int port,1975 const struct switchdev_obj_port_mdb *mdb,1976 struct dsa_db db)1977{1978 return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid, db);1979}1980 1981/* Common function for unicast and broadcast flood configuration.1982 * Flooding is configured between each {ingress, egress} port pair, and since1983 * the bridge's semantics are those of "egress flooding", it means we must1984 * enable flooding towards this port from all ingress ports that are in the1985 * same forwarding domain.1986 */1987static int sja1105_manage_flood_domains(struct sja1105_private *priv)1988{1989 struct sja1105_l2_forwarding_entry *l2_fwd;1990 struct dsa_switch *ds = priv->ds;1991 int from, to, rc;1992 1993 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;1994 1995 for (from = 0; from < ds->num_ports; from++) {1996 u64 fl_domain = 0, bc_domain = 0;1997 1998 for (to = 0; to < priv->ds->num_ports; to++) {1999 if (!sja1105_can_forward(l2_fwd, from, to))2000 continue;2001 2002 if (priv->ucast_egress_floods & BIT(to))2003 fl_domain |= BIT(to);2004 if (priv->bcast_egress_floods & BIT(to))2005 bc_domain |= BIT(to);2006 }2007 2008 /* Nothing changed, nothing to do */2009 if (l2_fwd[from].fl_domain == fl_domain &&2010 l2_fwd[from].bc_domain == bc_domain)2011 continue;2012 2013 l2_fwd[from].fl_domain = fl_domain;2014 l2_fwd[from].bc_domain = bc_domain;2015 2016 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,2017 from, &l2_fwd[from], true);2018 if (rc < 0)2019 return rc;2020 }2021 2022 return 0;2023}2024 2025static int sja1105_bridge_member(struct dsa_switch *ds, int port,2026 struct dsa_bridge bridge, bool member)2027{2028 struct sja1105_l2_forwarding_entry *l2_fwd;2029 struct sja1105_private *priv = ds->priv;2030 int i, rc;2031 2032 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;2033 2034 for (i = 0; i < ds->num_ports; i++) {2035 /* Add this port to the forwarding matrix of the2036 * other ports in the same bridge, and viceversa.2037 */2038 if (!dsa_is_user_port(ds, i))2039 continue;2040 /* For the ports already under the bridge, only one thing needs2041 * to be done, and that is to add this port to their2042 * reachability domain. So we can perform the SPI write for2043 * them immediately. However, for this port itself (the one2044 * that is new to the bridge), we need to add all other ports2045 * to its reachability domain. So we do that incrementally in2046 * this loop, and perform the SPI write only at the end, once2047 * the domain contains all other bridge ports.2048 */2049 if (i == port)2050 continue;2051 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))2052 continue;2053 sja1105_port_allow_traffic(l2_fwd, i, port, member);2054 sja1105_port_allow_traffic(l2_fwd, port, i, member);2055 2056 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,2057 i, &l2_fwd[i], true);2058 if (rc < 0)2059 return rc;2060 }2061 2062 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,2063 port, &l2_fwd[port], true);2064 if (rc)2065 return rc;2066 2067 rc = sja1105_commit_pvid(ds, port);2068 if (rc)2069 return rc;2070 2071 return sja1105_manage_flood_domains(priv);2072}2073 2074static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port,2075 u8 state)2076{2077 struct dsa_port *dp = dsa_to_port(ds, port);2078 struct sja1105_private *priv = ds->priv;2079 struct sja1105_mac_config_entry *mac;2080 2081 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;2082 2083 switch (state) {2084 case BR_STATE_DISABLED:2085 case BR_STATE_BLOCKING:2086 /* From UM10944 description of DRPDTAG (why put this there?):2087 * "Management traffic flows to the port regardless of the state2088 * of the INGRESS flag". So BPDUs are still be allowed to pass.2089 * At the moment no difference between DISABLED and BLOCKING.2090 */2091 mac[port].ingress = false;2092 mac[port].egress = false;2093 mac[port].dyn_learn = false;2094 break;2095 case BR_STATE_LISTENING:2096 mac[port].ingress = true;2097 mac[port].egress = false;2098 mac[port].dyn_learn = false;2099 break;2100 case BR_STATE_LEARNING:2101 mac[port].ingress = true;2102 mac[port].egress = false;2103 mac[port].dyn_learn = dp->learning;2104 break;2105 case BR_STATE_FORWARDING:2106 mac[port].ingress = true;2107 mac[port].egress = true;2108 mac[port].dyn_learn = dp->learning;2109 break;2110 default:2111 dev_err(ds->dev, "invalid STP state: %d\n", state);2112 return;2113 }2114 2115 sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,2116 &mac[port], true);2117}2118 2119static int sja1105_bridge_join(struct dsa_switch *ds, int port,2120 struct dsa_bridge bridge,2121 bool *tx_fwd_offload,2122 struct netlink_ext_ack *extack)2123{2124 int rc;2125 2126 rc = sja1105_bridge_member(ds, port, bridge, true);2127 if (rc)2128 return rc;2129 2130 rc = dsa_tag_8021q_bridge_join(ds, port, bridge, tx_fwd_offload,2131 extack);2132 if (rc) {2133 sja1105_bridge_member(ds, port, bridge, false);2134 return rc;2135 }2136 2137 return 0;2138}2139 2140static void sja1105_bridge_leave(struct dsa_switch *ds, int port,2141 struct dsa_bridge bridge)2142{2143 dsa_tag_8021q_bridge_leave(ds, port, bridge);2144 sja1105_bridge_member(ds, port, bridge, false);2145}2146 2147/* Port 0 (the uC port) does not have CBS shapers */2148#define SJA1110_FIXED_CBS(port, prio) ((((port) - 1) * SJA1105_NUM_TC) + (prio))2149 2150static int sja1105_find_cbs_shaper(struct sja1105_private *priv,2151 int port, int prio)2152{2153 int i;2154 2155 if (priv->info->fixed_cbs_mapping) {2156 i = SJA1110_FIXED_CBS(port, prio);2157 if (i >= 0 && i < priv->info->num_cbs_shapers)2158 return i;2159 2160 return -1;2161 }2162 2163 for (i = 0; i < priv->info->num_cbs_shapers; i++)2164 if (priv->cbs[i].port == port && priv->cbs[i].prio == prio)2165 return i;2166 2167 return -1;2168}2169 2170static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv)2171{2172 int i;2173 2174 if (priv->info->fixed_cbs_mapping)2175 return -1;2176 2177 for (i = 0; i < priv->info->num_cbs_shapers; i++)2178 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope)2179 return i;2180 2181 return -1;2182}2183 2184static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port,2185 int prio)2186{2187 int i;2188 2189 for (i = 0; i < priv->info->num_cbs_shapers; i++) {2190 struct sja1105_cbs_entry *cbs = &priv->cbs[i];2191 2192 if (cbs->port == port && cbs->prio == prio) {2193 memset(cbs, 0, sizeof(*cbs));2194 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS,2195 i, cbs, true);2196 }2197 }2198 2199 return 0;2200}2201 2202static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port,2203 struct tc_cbs_qopt_offload *offload)2204{2205 struct sja1105_private *priv = ds->priv;2206 struct sja1105_cbs_entry *cbs;2207 s64 port_transmit_rate_kbps;2208 int index;2209 2210 if (!offload->enable)2211 return sja1105_delete_cbs_shaper(priv, port, offload->queue);2212 2213 /* The user may be replacing an existing shaper */2214 index = sja1105_find_cbs_shaper(priv, port, offload->queue);2215 if (index < 0) {2216 /* That isn't the case - see if we can allocate a new one */2217 index = sja1105_find_unused_cbs_shaper(priv);2218 if (index < 0)2219 return -ENOSPC;2220 }2221 2222 cbs = &priv->cbs[index];2223 cbs->port = port;2224 cbs->prio = offload->queue;2225 /* locredit and sendslope are negative by definition. In hardware,2226 * positive values must be provided, and the negative sign is implicit.2227 */2228 cbs->credit_hi = offload->hicredit;2229 cbs->credit_lo = abs(offload->locredit);2230 /* User space is in kbits/sec, while the hardware in bytes/sec times2231 * link speed. Since the given offload->sendslope is good only for the2232 * current link speed anyway, and user space is likely to reprogram it2233 * when that changes, don't even bother to track the port's link speed,2234 * but deduce the port transmit rate from idleslope - sendslope.2235 */2236 port_transmit_rate_kbps = offload->idleslope - offload->sendslope;2237 cbs->idle_slope = div_s64(offload->idleslope * BYTES_PER_KBIT,2238 port_transmit_rate_kbps);2239 cbs->send_slope = div_s64(abs(offload->sendslope * BYTES_PER_KBIT),2240 port_transmit_rate_kbps);2241 /* Convert the negative values from 64-bit 2's complement2242 * to 32-bit 2's complement (for the case of 0x80000000 whose2243 * negative is still negative).2244 */2245 cbs->credit_lo &= GENMASK_ULL(31, 0);2246 cbs->send_slope &= GENMASK_ULL(31, 0);2247 2248 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs,2249 true);2250}2251 2252static int sja1105_reload_cbs(struct sja1105_private *priv)2253{2254 int rc = 0, i;2255 2256 /* The credit based shapers are only allocated if2257 * CONFIG_NET_SCH_CBS is enabled.2258 */2259 if (!priv->cbs)2260 return 0;2261 2262 for (i = 0; i < priv->info->num_cbs_shapers; i++) {2263 struct sja1105_cbs_entry *cbs = &priv->cbs[i];2264 2265 if (!cbs->idle_slope && !cbs->send_slope)2266 continue;2267 2268 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs,2269 true);2270 if (rc)2271 break;2272 }2273 2274 return rc;2275}2276 2277static const char * const sja1105_reset_reasons[] = {2278 [SJA1105_VLAN_FILTERING] = "VLAN filtering",2279 [SJA1105_AGEING_TIME] = "Ageing time",2280 [SJA1105_SCHEDULING] = "Time-aware scheduling",2281 [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing",2282 [SJA1105_VIRTUAL_LINKS] = "Virtual links",2283};2284 2285/* For situations where we need to change a setting at runtime that is only2286 * available through the static configuration, resetting the switch in order2287 * to upload the new static config is unavoidable. Back up the settings we2288 * modify at runtime (currently only MAC) and restore them after uploading,2289 * such that this operation is relatively seamless.2290 */2291int sja1105_static_config_reload(struct sja1105_private *priv,2292 enum sja1105_reset_reason reason)2293{2294 struct ptp_system_timestamp ptp_sts_before;2295 struct ptp_system_timestamp ptp_sts_after;2296 int speed_mbps[SJA1105_MAX_NUM_PORTS];2297 u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};2298 struct sja1105_mac_config_entry *mac;2299 struct dsa_switch *ds = priv->ds;2300 s64 t1, t2, t3, t4;2301 s64 t12, t34;2302 int rc, i;2303 s64 now;2304 2305 mutex_lock(&priv->fdb_lock);2306 mutex_lock(&priv->mgmt_lock);2307 2308 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;2309 2310 /* Back up the dynamic link speed changed by sja1105_adjust_port_config2311 * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the2312 * switch wants to see in the static config in order to allow us to2313 * change it through the dynamic interface later.2314 */2315 for (i = 0; i < ds->num_ports; i++) {2316 speed_mbps[i] = sja1105_port_speed_to_ethtool(priv,2317 mac[i].speed);2318 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];2319 2320 if (priv->xpcs[i])2321 bmcr[i] = mdiobus_c45_read(priv->mdio_pcs, i,2322 MDIO_MMD_VEND2, MDIO_CTRL1);2323 }2324 2325 /* No PTP operations can run right now */2326 mutex_lock(&priv->ptp_data.lock);2327 2328 rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before);2329 if (rc < 0) {2330 mutex_unlock(&priv->ptp_data.lock);2331 goto out;2332 }2333 2334 /* Reset switch and send updated static configuration */2335 rc = sja1105_static_config_upload(priv);2336 if (rc < 0) {2337 mutex_unlock(&priv->ptp_data.lock);2338 goto out;2339 }2340 2341 rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after);2342 if (rc < 0) {2343 mutex_unlock(&priv->ptp_data.lock);2344 goto out;2345 }2346 2347 t1 = timespec64_to_ns(&ptp_sts_before.pre_ts);2348 t2 = timespec64_to_ns(&ptp_sts_before.post_ts);2349 t3 = timespec64_to_ns(&ptp_sts_after.pre_ts);2350 t4 = timespec64_to_ns(&ptp_sts_after.post_ts);2351 /* Mid point, corresponds to pre-reset PTPCLKVAL */2352 t12 = t1 + (t2 - t1) / 2;2353 /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */2354 t34 = t3 + (t4 - t3) / 2;2355 /* Advance PTPCLKVAL by the time it took since its readout */2356 now += (t34 - t12);2357 2358 __sja1105_ptp_adjtime(ds, now);2359 2360 mutex_unlock(&priv->ptp_data.lock);2361 2362 dev_info(priv->ds->dev,2363 "Reset switch and programmed static config. Reason: %s\n",2364 sja1105_reset_reasons[reason]);2365 2366 /* Configure the CGU (PLLs) for MII and RMII PHYs.2367 * For these interfaces there is no dynamic configuration2368 * needed, since PLLs have same settings at all speeds.2369 */2370 if (priv->info->clocking_setup) {2371 rc = priv->info->clocking_setup(priv);2372 if (rc < 0)2373 goto out;2374 }2375 2376 for (i = 0; i < ds->num_ports; i++) {2377 struct dw_xpcs *xpcs = priv->xpcs[i];2378 unsigned int neg_mode;2379 2380 rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]);2381 if (rc < 0)2382 goto out;2383 2384 if (!xpcs)2385 continue;2386 2387 if (bmcr[i] & BMCR_ANENABLE)2388 neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;2389 else2390 neg_mode = PHYLINK_PCS_NEG_OUTBAND;2391 2392 rc = xpcs_do_config(xpcs, priv->phy_mode[i], NULL, neg_mode);2393 if (rc < 0)2394 goto out;2395 2396 if (neg_mode == PHYLINK_PCS_NEG_OUTBAND) {2397 int speed = SPEED_UNKNOWN;2398 2399 if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX)2400 speed = SPEED_2500;2401 else if (bmcr[i] & BMCR_SPEED1000)2402 speed = SPEED_1000;2403 else if (bmcr[i] & BMCR_SPEED100)2404 speed = SPEED_100;2405 else2406 speed = SPEED_10;2407 2408 xpcs_link_up(&xpcs->pcs, neg_mode, priv->phy_mode[i],2409 speed, DUPLEX_FULL);2410 }2411 }2412 2413 rc = sja1105_reload_cbs(priv);2414 if (rc < 0)2415 goto out;2416out:2417 mutex_unlock(&priv->mgmt_lock);2418 mutex_unlock(&priv->fdb_lock);2419 2420 return rc;2421}2422 2423static enum dsa_tag_protocol2424sja1105_get_tag_protocol(struct dsa_switch *ds, int port,2425 enum dsa_tag_protocol mp)2426{2427 struct sja1105_private *priv = ds->priv;2428 2429 return priv->info->tag_proto;2430}2431 2432/* The TPID setting belongs to the General Parameters table,2433 * which can only be partially reconfigured at runtime (and not the TPID).2434 * So a switch reset is required.2435 */2436int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,2437 struct netlink_ext_ack *extack)2438{2439 struct sja1105_general_params_entry *general_params;2440 struct sja1105_private *priv = ds->priv;2441 struct sja1105_table *table;2442 struct sja1105_rule *rule;2443 u16 tpid, tpid2;2444 int rc;2445 2446 list_for_each_entry(rule, &priv->flow_block.rules, list) {2447 if (rule->type == SJA1105_RULE_VL) {2448 NL_SET_ERR_MSG_MOD(extack,2449 "Cannot change VLAN filtering with active VL rules");2450 return -EBUSY;2451 }2452 }2453 2454 if (enabled) {2455 /* Enable VLAN filtering. */2456 tpid = ETH_P_8021Q;2457 tpid2 = ETH_P_8021AD;2458 } else {2459 /* Disable VLAN filtering. */2460 tpid = ETH_P_SJA1105;2461 tpid2 = ETH_P_SJA1105;2462 }2463 2464 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];2465 general_params = table->entries;2466 /* EtherType used to identify inner tagged (C-tag) VLAN traffic */2467 general_params->tpid = tpid;2468 /* EtherType used to identify outer tagged (S-tag) VLAN traffic */2469 general_params->tpid2 = tpid2;2470 2471 for (port = 0; port < ds->num_ports; port++) {2472 if (dsa_is_unused_port(ds, port))2473 continue;2474 2475 rc = sja1105_commit_pvid(ds, port);2476 if (rc)2477 return rc;2478 }2479 2480 rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING);2481 if (rc)2482 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype");2483 2484 return rc;2485}2486 2487static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid,2488 u16 flags, bool allowed_ingress)2489{2490 struct sja1105_vlan_lookup_entry *vlan;2491 struct sja1105_table *table;2492 int match, rc;2493 2494 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];2495 2496 match = sja1105_is_vlan_configured(priv, vid);2497 if (match < 0) {2498 rc = sja1105_table_resize(table, table->entry_count + 1);2499 if (rc)2500 return rc;2501 match = table->entry_count - 1;2502 }2503 2504 /* Assign pointer after the resize (it's new memory) */2505 vlan = table->entries;2506 2507 vlan[match].type_entry = SJA1110_VLAN_D_TAG;2508 vlan[match].vlanid = vid;2509 vlan[match].vlan_bc |= BIT(port);2510 2511 if (allowed_ingress)2512 vlan[match].vmemb_port |= BIT(port);2513 else2514 vlan[match].vmemb_port &= ~BIT(port);2515 2516 if (flags & BRIDGE_VLAN_INFO_UNTAGGED)2517 vlan[match].tag_port &= ~BIT(port);2518 else2519 vlan[match].tag_port |= BIT(port);2520 2521 return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,2522 &vlan[match], true);2523}2524 2525static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid)2526{2527 struct sja1105_vlan_lookup_entry *vlan;2528 struct sja1105_table *table;2529 bool keep = true;2530 int match, rc;2531 2532 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];2533 2534 match = sja1105_is_vlan_configured(priv, vid);2535 /* Can't delete a missing entry. */2536 if (match < 0)2537 return 0;2538 2539 /* Assign pointer after the resize (it's new memory) */2540 vlan = table->entries;2541 2542 vlan[match].vlanid = vid;2543 vlan[match].vlan_bc &= ~BIT(port);2544 vlan[match].vmemb_port &= ~BIT(port);2545 /* Also unset tag_port, just so we don't have a confusing bitmap2546 * (no practical purpose).2547 */2548 vlan[match].tag_port &= ~BIT(port);2549 2550 /* If there's no port left as member of this VLAN,2551 * it's time for it to go.2552 */2553 if (!vlan[match].vmemb_port)2554 keep = false;2555 2556 rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,2557 &vlan[match], keep);2558 if (rc < 0)2559 return rc;2560 2561 if (!keep)2562 return sja1105_table_delete_entry(table, match);2563 2564 return 0;2565}2566 2567static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port,2568 const struct switchdev_obj_port_vlan *vlan,2569 struct netlink_ext_ack *extack)2570{2571 struct sja1105_private *priv = ds->priv;2572 u16 flags = vlan->flags;2573 int rc;2574 2575 /* Be sure to deny alterations to the configuration done by tag_8021q.2576 */2577 if (vid_is_dsa_8021q(vlan->vid)) {2578 NL_SET_ERR_MSG_MOD(extack,2579 "Range 3072-4095 reserved for dsa_8021q operation");2580 return -EBUSY;2581 }2582 2583 /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */2584 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))2585 flags = 0;2586 2587 rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true);2588 if (rc)2589 return rc;2590 2591 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)2592 priv->bridge_pvid[port] = vlan->vid;2593 2594 return sja1105_commit_pvid(ds, port);2595}2596 2597static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port,2598 const struct switchdev_obj_port_vlan *vlan)2599{2600 struct sja1105_private *priv = ds->priv;2601 int rc;2602 2603 rc = sja1105_vlan_del(priv, port, vlan->vid);2604 if (rc)2605 return rc;2606 2607 /* In case the pvid was deleted, make sure that untagged packets will2608 * be dropped.2609 */2610 return sja1105_commit_pvid(ds, port);2611}2612 2613static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,2614 u16 flags)2615{2616 struct sja1105_private *priv = ds->priv;2617 bool allowed_ingress = true;2618 int rc;2619 2620 /* Prevent attackers from trying to inject a DSA tag from2621 * the outside world.2622 */2623 if (dsa_is_user_port(ds, port))2624 allowed_ingress = false;2625 2626 rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress);2627 if (rc)2628 return rc;2629 2630 if (flags & BRIDGE_VLAN_INFO_PVID)2631 priv->tag_8021q_pvid[port] = vid;2632 2633 return sja1105_commit_pvid(ds, port);2634}2635 2636static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)2637{2638 struct sja1105_private *priv = ds->priv;2639 2640 return sja1105_vlan_del(priv, port, vid);2641}2642 2643static int sja1105_prechangeupper(struct dsa_switch *ds, int port,2644 struct netdev_notifier_changeupper_info *info)2645{2646 struct netlink_ext_ack *extack = info->info.extack;2647 struct net_device *upper = info->upper_dev;2648 struct dsa_switch_tree *dst = ds->dst;2649 struct dsa_port *dp;2650 2651 if (is_vlan_dev(upper)) {2652 NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported");2653 return -EBUSY;2654 }2655 2656 if (netif_is_bridge_master(upper)) {2657 list_for_each_entry(dp, &dst->ports, list) {2658 struct net_device *br = dsa_port_bridge_dev_get(dp);2659 2660 if (br && br != upper && br_vlan_enabled(br)) {2661 NL_SET_ERR_MSG_MOD(extack,2662 "Only one VLAN-aware bridge is supported");2663 return -EBUSY;2664 }2665 }2666 }2667 2668 return 0;2669}2670 2671static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot,2672 struct sk_buff *skb, bool takets)2673{2674 struct sja1105_mgmt_entry mgmt_route = {0};2675 struct sja1105_private *priv = ds->priv;2676 struct ethhdr *hdr;2677 int timeout = 10;2678 int rc;2679 2680 hdr = eth_hdr(skb);2681 2682 mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest);2683 mgmt_route.destports = BIT(port);2684 mgmt_route.enfport = 1;2685 mgmt_route.tsreg = 0;2686 mgmt_route.takets = takets;2687 2688 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,2689 slot, &mgmt_route, true);2690 if (rc < 0) {2691 kfree_skb(skb);2692 return rc;2693 }2694 2695 /* Transfer skb to the host port. */2696 dsa_enqueue_skb(skb, dsa_to_port(ds, port)->user);2697 2698 /* Wait until the switch has processed the frame */2699 do {2700 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE,2701 slot, &mgmt_route);2702 if (rc < 0) {2703 dev_err_ratelimited(priv->ds->dev,2704 "failed to poll for mgmt route\n");2705 continue;2706 }2707 2708 /* UM10944: The ENFPORT flag of the respective entry is2709 * cleared when a match is found. The host can use this2710 * flag as an acknowledgment.2711 */2712 cpu_relax();2713 } while (mgmt_route.enfport && --timeout);2714 2715 if (!timeout) {2716 /* Clean up the management route so that a follow-up2717 * frame may not match on it by mistake.2718 * This is only hardware supported on P/Q/R/S - on E/T it is2719 * a no-op and we are silently discarding the -EOPNOTSUPP.2720 */2721 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,2722 slot, &mgmt_route, false);2723 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n");2724 }2725 2726 return NETDEV_TX_OK;2727}2728 2729#define work_to_xmit_work(w) \2730 container_of((w), struct sja1105_deferred_xmit_work, work)2731 2732/* Deferred work is unfortunately necessary because setting up the management2733 * route cannot be done from atomit context (SPI transfer takes a sleepable2734 * lock on the bus)2735 */2736static void sja1105_port_deferred_xmit(struct kthread_work *work)2737{2738 struct sja1105_deferred_xmit_work *xmit_work = work_to_xmit_work(work);2739 struct sk_buff *clone, *skb = xmit_work->skb;2740 struct dsa_switch *ds = xmit_work->dp->ds;2741 struct sja1105_private *priv = ds->priv;2742 int port = xmit_work->dp->index;2743 2744 clone = SJA1105_SKB_CB(skb)->clone;2745 2746 mutex_lock(&priv->mgmt_lock);2747 2748 sja1105_mgmt_xmit(ds, port, 0, skb, !!clone);2749 2750 /* The clone, if there, was made by dsa_skb_tx_timestamp */2751 if (clone)2752 sja1105_ptp_txtstamp_skb(ds, port, clone);2753 2754 mutex_unlock(&priv->mgmt_lock);2755 2756 kfree(xmit_work);2757}2758 2759static int sja1105_connect_tag_protocol(struct dsa_switch *ds,2760 enum dsa_tag_protocol proto)2761{2762 struct sja1105_private *priv = ds->priv;2763 struct sja1105_tagger_data *tagger_data;2764 2765 if (proto != priv->info->tag_proto)2766 return -EPROTONOSUPPORT;2767 2768 tagger_data = sja1105_tagger_data(ds);2769 tagger_data->xmit_work_fn = sja1105_port_deferred_xmit;2770 tagger_data->meta_tstamp_handler = sja1110_process_meta_tstamp;2771 2772 return 0;2773}2774 2775/* The MAXAGE setting belongs to the L2 Forwarding Parameters table,2776 * which cannot be reconfigured at runtime. So a switch reset is required.2777 */2778static int sja1105_set_ageing_time(struct dsa_switch *ds,2779 unsigned int ageing_time)2780{2781 struct sja1105_l2_lookup_params_entry *l2_lookup_params;2782 struct sja1105_private *priv = ds->priv;2783 struct sja1105_table *table;2784 unsigned int maxage;2785 2786 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];2787 l2_lookup_params = table->entries;2788 2789 maxage = SJA1105_AGEING_TIME_MS(ageing_time);2790 2791 if (l2_lookup_params->maxage == maxage)2792 return 0;2793 2794 l2_lookup_params->maxage = maxage;2795 2796 return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME);2797}2798 2799static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu)2800{2801 struct sja1105_l2_policing_entry *policing;2802 struct sja1105_private *priv = ds->priv;2803 2804 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;2805 2806 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))2807 new_mtu += VLAN_HLEN;2808 2809 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;2810 2811 if (policing[port].maxlen == new_mtu)2812 return 0;2813 2814 policing[port].maxlen = new_mtu;2815 2816 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);2817}2818 2819static int sja1105_get_max_mtu(struct dsa_switch *ds, int port)2820{2821 return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN;2822}2823 2824static int sja1105_port_setup_tc(struct dsa_switch *ds, int port,2825 enum tc_setup_type type,2826 void *type_data)2827{2828 switch (type) {2829 case TC_SETUP_QDISC_TAPRIO:2830 return sja1105_setup_tc_taprio(ds, port, type_data);2831 case TC_SETUP_QDISC_CBS:2832 return sja1105_setup_tc_cbs(ds, port, type_data);2833 default:2834 return -EOPNOTSUPP;2835 }2836}2837 2838/* We have a single mirror (@to) port, but can configure ingress and egress2839 * mirroring on all other (@from) ports.2840 * We need to allow mirroring rules only as long as the @to port is always the2841 * same, and we need to unset the @to port from mirr_port only when there is no2842 * mirroring rule that references it.2843 */2844static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to,2845 bool ingress, bool enabled)2846{2847 struct sja1105_general_params_entry *general_params;2848 struct sja1105_mac_config_entry *mac;2849 struct dsa_switch *ds = priv->ds;2850 struct sja1105_table *table;2851 bool already_enabled;2852 u64 new_mirr_port;2853 int rc;2854 2855 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];2856 general_params = table->entries;2857 2858 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;2859 2860 already_enabled = (general_params->mirr_port != ds->num_ports);2861 if (already_enabled && enabled && general_params->mirr_port != to) {2862 dev_err(priv->ds->dev,2863 "Delete mirroring rules towards port %llu first\n",2864 general_params->mirr_port);2865 return -EBUSY;2866 }2867 2868 new_mirr_port = to;2869 if (!enabled) {2870 bool keep = false;2871 int port;2872 2873 /* Anybody still referencing mirr_port? */2874 for (port = 0; port < ds->num_ports; port++) {2875 if (mac[port].ing_mirr || mac[port].egr_mirr) {2876 keep = true;2877 break;2878 }2879 }2880 /* Unset already_enabled for next time */2881 if (!keep)2882 new_mirr_port = ds->num_ports;2883 }2884 if (new_mirr_port != general_params->mirr_port) {2885 general_params->mirr_port = new_mirr_port;2886 2887 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS,2888 0, general_params, true);2889 if (rc < 0)2890 return rc;2891 }2892 2893 if (ingress)2894 mac[from].ing_mirr = enabled;2895 else2896 mac[from].egr_mirr = enabled;2897 2898 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from,2899 &mac[from], true);2900}2901 2902static int sja1105_mirror_add(struct dsa_switch *ds, int port,2903 struct dsa_mall_mirror_tc_entry *mirror,2904 bool ingress, struct netlink_ext_ack *extack)2905{2906 return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,2907 ingress, true);2908}2909 2910static void sja1105_mirror_del(struct dsa_switch *ds, int port,2911 struct dsa_mall_mirror_tc_entry *mirror)2912{2913 sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,2914 mirror->ingress, false);2915}2916 2917static int sja1105_port_policer_add(struct dsa_switch *ds, int port,2918 struct dsa_mall_policer_tc_entry *policer)2919{2920 struct sja1105_l2_policing_entry *policing;2921 struct sja1105_private *priv = ds->priv;2922 2923 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;2924 2925 /* In hardware, every 8 microseconds the credit level is incremented by2926 * the value of RATE bytes divided by 64, up to a maximum of SMAX2927 * bytes.2928 */2929 policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec,2930 1000000);2931 policing[port].smax = policer->burst;2932 2933 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);2934}2935 2936static void sja1105_port_policer_del(struct dsa_switch *ds, int port)2937{2938 struct sja1105_l2_policing_entry *policing;2939 struct sja1105_private *priv = ds->priv;2940 2941 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;2942 2943 policing[port].rate = SJA1105_RATE_MBPS(1000);2944 policing[port].smax = 65535;2945 2946 sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);2947}2948 2949static int sja1105_port_set_learning(struct sja1105_private *priv, int port,2950 bool enabled)2951{2952 struct sja1105_mac_config_entry *mac;2953 2954 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;2955 2956 mac[port].dyn_learn = enabled;2957 2958 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,2959 &mac[port], true);2960}2961 2962static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to,2963 struct switchdev_brport_flags flags)2964{2965 if (flags.mask & BR_FLOOD) {2966 if (flags.val & BR_FLOOD)2967 priv->ucast_egress_floods |= BIT(to);2968 else2969 priv->ucast_egress_floods &= ~BIT(to);2970 }2971 2972 if (flags.mask & BR_BCAST_FLOOD) {2973 if (flags.val & BR_BCAST_FLOOD)2974 priv->bcast_egress_floods |= BIT(to);2975 else2976 priv->bcast_egress_floods &= ~BIT(to);2977 }2978 2979 return sja1105_manage_flood_domains(priv);2980}2981 2982static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to,2983 struct switchdev_brport_flags flags,2984 struct netlink_ext_ack *extack)2985{2986 struct sja1105_l2_lookup_entry *l2_lookup;2987 struct sja1105_table *table;2988 int match, rc;2989 2990 mutex_lock(&priv->fdb_lock);2991 2992 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];2993 l2_lookup = table->entries;2994 2995 for (match = 0; match < table->entry_count; match++)2996 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST &&2997 l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST)2998 break;2999 3000 if (match == table->entry_count) {3001 NL_SET_ERR_MSG_MOD(extack,3002 "Could not find FDB entry for unknown multicast");3003 rc = -ENOSPC;3004 goto out;3005 }3006 3007 if (flags.val & BR_MCAST_FLOOD)3008 l2_lookup[match].destports |= BIT(to);3009 else3010 l2_lookup[match].destports &= ~BIT(to);3011 3012 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,3013 l2_lookup[match].index,3014 &l2_lookup[match], true);3015out:3016 mutex_unlock(&priv->fdb_lock);3017 3018 return rc;3019}3020 3021static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port,3022 struct switchdev_brport_flags flags,3023 struct netlink_ext_ack *extack)3024{3025 struct sja1105_private *priv = ds->priv;3026 3027 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |3028 BR_BCAST_FLOOD))3029 return -EINVAL;3030 3031 if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) &&3032 !priv->info->can_limit_mcast_flood) {3033 bool multicast = !!(flags.val & BR_MCAST_FLOOD);3034 bool unicast = !!(flags.val & BR_FLOOD);3035 3036 if (unicast != multicast) {3037 NL_SET_ERR_MSG_MOD(extack,3038 "This chip cannot configure multicast flooding independently of unicast");3039 return -EINVAL;3040 }3041 }3042 3043 return 0;3044}3045 3046static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port,3047 struct switchdev_brport_flags flags,3048 struct netlink_ext_ack *extack)3049{3050 struct sja1105_private *priv = ds->priv;3051 int rc;3052 3053 if (flags.mask & BR_LEARNING) {3054 bool learn_ena = !!(flags.val & BR_LEARNING);3055 3056 rc = sja1105_port_set_learning(priv, port, learn_ena);3057 if (rc)3058 return rc;3059 }3060 3061 if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) {3062 rc = sja1105_port_ucast_bcast_flood(priv, port, flags);3063 if (rc)3064 return rc;3065 }3066 3067 /* For chips that can't offload BR_MCAST_FLOOD independently, there3068 * is nothing to do here, we ensured the configuration is in sync by3069 * offloading BR_FLOOD.3070 */3071 if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) {3072 rc = sja1105_port_mcast_flood(priv, port, flags,3073 extack);3074 if (rc)3075 return rc;3076 }3077 3078 return 0;3079}3080 3081/* The programming model for the SJA1105 switch is "all-at-once" via static3082 * configuration tables. Some of these can be dynamically modified at runtime,3083 * but not the xMII mode parameters table.3084 * Furthermode, some PHYs may not have crystals for generating their clocks3085 * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's3086 * ref_clk pin. So port clocking needs to be initialized early, before3087 * connecting to PHYs is attempted, otherwise they won't respond through MDIO.3088 * Setting correct PHY link speed does not matter now.3089 * But dsa_user_phy_setup is called later than sja1105_setup, so the PHY3090 * bindings are not yet parsed by DSA core. We need to parse early so that we3091 * can populate the xMII mode parameters table.3092 */3093static int sja1105_setup(struct dsa_switch *ds)3094{3095 struct sja1105_private *priv = ds->priv;3096 int rc;3097 3098 if (priv->info->disable_microcontroller) {3099 rc = priv->info->disable_microcontroller(priv);3100 if (rc < 0) {3101 dev_err(ds->dev,3102 "Failed to disable microcontroller: %pe\n",3103 ERR_PTR(rc));3104 return rc;3105 }3106 }3107 3108 /* Create and send configuration down to device */3109 rc = sja1105_static_config_load(priv);3110 if (rc < 0) {3111 dev_err(ds->dev, "Failed to load static config: %d\n", rc);3112 return rc;3113 }3114 3115 /* Configure the CGU (PHY link modes and speeds) */3116 if (priv->info->clocking_setup) {3117 rc = priv->info->clocking_setup(priv);3118 if (rc < 0) {3119 dev_err(ds->dev,3120 "Failed to configure MII clocking: %pe\n",3121 ERR_PTR(rc));3122 goto out_static_config_free;3123 }3124 }3125 3126 sja1105_tas_setup(ds);3127 sja1105_flower_setup(ds);3128 3129 rc = sja1105_ptp_clock_register(ds);3130 if (rc < 0) {3131 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);3132 goto out_flower_teardown;3133 }3134 3135 rc = sja1105_mdiobus_register(ds);3136 if (rc < 0) {3137 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",3138 ERR_PTR(rc));3139 goto out_ptp_clock_unregister;3140 }3141 3142 rc = sja1105_devlink_setup(ds);3143 if (rc < 0)3144 goto out_mdiobus_unregister;3145 3146 rtnl_lock();3147 rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));3148 rtnl_unlock();3149 if (rc)3150 goto out_devlink_teardown;3151 3152 /* On SJA1105, VLAN filtering per se is always enabled in hardware.3153 * The only thing we can do to disable it is lie about what the 802.1Q3154 * EtherType is.3155 * So it will still try to apply VLAN filtering, but all ingress3156 * traffic (except frames received with EtherType of ETH_P_SJA1105)3157 * will be internally tagged with a distorted VLAN header where the3158 * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.3159 */3160 ds->vlan_filtering_is_global = true;3161 ds->fdb_isolation = true;3162 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES;3163 3164 /* Advertise the 8 egress queues */3165 ds->num_tx_queues = SJA1105_NUM_TC;3166 3167 ds->mtu_enforcement_ingress = true;3168 ds->assisted_learning_on_cpu_port = true;3169 3170 return 0;3171 3172out_devlink_teardown:3173 sja1105_devlink_teardown(ds);3174out_mdiobus_unregister:3175 sja1105_mdiobus_unregister(ds);3176out_ptp_clock_unregister:3177 sja1105_ptp_clock_unregister(ds);3178out_flower_teardown:3179 sja1105_flower_teardown(ds);3180 sja1105_tas_teardown(ds);3181out_static_config_free:3182 sja1105_static_config_free(&priv->static_config);3183 3184 return rc;3185}3186 3187static void sja1105_teardown(struct dsa_switch *ds)3188{3189 struct sja1105_private *priv = ds->priv;3190 3191 rtnl_lock();3192 dsa_tag_8021q_unregister(ds);3193 rtnl_unlock();3194 3195 sja1105_devlink_teardown(ds);3196 sja1105_mdiobus_unregister(ds);3197 sja1105_ptp_clock_unregister(ds);3198 sja1105_flower_teardown(ds);3199 sja1105_tas_teardown(ds);3200 sja1105_static_config_free(&priv->static_config);3201}3202 3203static const struct phylink_mac_ops sja1105_phylink_mac_ops = {3204 .mac_select_pcs = sja1105_mac_select_pcs,3205 .mac_config = sja1105_mac_config,3206 .mac_link_up = sja1105_mac_link_up,3207 .mac_link_down = sja1105_mac_link_down,3208};3209 3210static const struct dsa_switch_ops sja1105_switch_ops = {3211 .get_tag_protocol = sja1105_get_tag_protocol,3212 .connect_tag_protocol = sja1105_connect_tag_protocol,3213 .setup = sja1105_setup,3214 .teardown = sja1105_teardown,3215 .set_ageing_time = sja1105_set_ageing_time,3216 .port_change_mtu = sja1105_change_mtu,3217 .port_max_mtu = sja1105_get_max_mtu,3218 .phylink_get_caps = sja1105_phylink_get_caps,3219 .get_strings = sja1105_get_strings,3220 .get_ethtool_stats = sja1105_get_ethtool_stats,3221 .get_sset_count = sja1105_get_sset_count,3222 .get_ts_info = sja1105_get_ts_info,3223 .port_fdb_dump = sja1105_fdb_dump,3224 .port_fdb_add = sja1105_fdb_add,3225 .port_fdb_del = sja1105_fdb_del,3226 .port_fast_age = sja1105_fast_age,3227 .port_bridge_join = sja1105_bridge_join,3228 .port_bridge_leave = sja1105_bridge_leave,3229 .port_pre_bridge_flags = sja1105_port_pre_bridge_flags,3230 .port_bridge_flags = sja1105_port_bridge_flags,3231 .port_stp_state_set = sja1105_bridge_stp_state_set,3232 .port_vlan_filtering = sja1105_vlan_filtering,3233 .port_vlan_add = sja1105_bridge_vlan_add,3234 .port_vlan_del = sja1105_bridge_vlan_del,3235 .port_mdb_add = sja1105_mdb_add,3236 .port_mdb_del = sja1105_mdb_del,3237 .port_hwtstamp_get = sja1105_hwtstamp_get,3238 .port_hwtstamp_set = sja1105_hwtstamp_set,3239 .port_rxtstamp = sja1105_port_rxtstamp,3240 .port_txtstamp = sja1105_port_txtstamp,3241 .port_setup_tc = sja1105_port_setup_tc,3242 .port_mirror_add = sja1105_mirror_add,3243 .port_mirror_del = sja1105_mirror_del,3244 .port_policer_add = sja1105_port_policer_add,3245 .port_policer_del = sja1105_port_policer_del,3246 .cls_flower_add = sja1105_cls_flower_add,3247 .cls_flower_del = sja1105_cls_flower_del,3248 .cls_flower_stats = sja1105_cls_flower_stats,3249 .devlink_info_get = sja1105_devlink_info_get,3250 .tag_8021q_vlan_add = sja1105_dsa_8021q_vlan_add,3251 .tag_8021q_vlan_del = sja1105_dsa_8021q_vlan_del,3252 .port_prechangeupper = sja1105_prechangeupper,3253};3254 3255static const struct of_device_id sja1105_dt_ids[];3256 3257static int sja1105_check_device_id(struct sja1105_private *priv)3258{3259 const struct sja1105_regs *regs = priv->info->regs;3260 u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};3261 struct device *dev = &priv->spidev->dev;3262 const struct of_device_id *match;3263 u32 device_id;3264 u64 part_no;3265 int rc;3266 3267 rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,3268 NULL);3269 if (rc < 0)3270 return rc;3271 3272 rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,3273 SJA1105_SIZE_DEVICE_ID);3274 if (rc < 0)3275 return rc;3276 3277 sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID);3278 3279 for (match = sja1105_dt_ids; match->compatible[0]; match++) {3280 const struct sja1105_info *info = match->data;3281 3282 /* Is what's been probed in our match table at all? */3283 if (info->device_id != device_id || info->part_no != part_no)3284 continue;3285 3286 /* But is it what's in the device tree? */3287 if (priv->info->device_id != device_id ||3288 priv->info->part_no != part_no) {3289 dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n",3290 priv->info->name, info->name);3291 /* It isn't. No problem, pick that up. */3292 priv->info = info;3293 }3294 3295 return 0;3296 }3297 3298 dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",3299 device_id, part_no);3300 3301 return -ENODEV;3302}3303 3304static int sja1105_probe(struct spi_device *spi)3305{3306 struct device *dev = &spi->dev;3307 struct sja1105_private *priv;3308 size_t max_xfer, max_msg;3309 struct dsa_switch *ds;3310 int rc;3311 3312 if (!dev->of_node) {3313 dev_err(dev, "No DTS bindings for SJA1105 driver\n");3314 return -EINVAL;3315 }3316 3317 rc = sja1105_hw_reset(dev, 1, 1);3318 if (rc)3319 return rc;3320 3321 priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL);3322 if (!priv)3323 return -ENOMEM;3324 3325 /* Populate our driver private structure (priv) based on3326 * the device tree node that was probed (spi)3327 */3328 priv->spidev = spi;3329 spi_set_drvdata(spi, priv);3330 3331 /* Configure the SPI bus */3332 spi->bits_per_word = 8;3333 rc = spi_setup(spi);3334 if (rc < 0) {3335 dev_err(dev, "Could not init SPI\n");3336 return rc;3337 }3338 3339 /* In sja1105_xfer, we send spi_messages composed of two spi_transfers:3340 * a small one for the message header and another one for the current3341 * chunk of the packed buffer.3342 * Check that the restrictions imposed by the SPI controller are3343 * respected: the chunk buffer is smaller than the max transfer size,3344 * and the total length of the chunk plus its message header is smaller3345 * than the max message size.3346 * We do that during probe time since the maximum transfer size is a3347 * runtime invariant.3348 */3349 max_xfer = spi_max_transfer_size(spi);3350 max_msg = spi_max_message_size(spi);3351 3352 /* We need to send at least one 64-bit word of SPI payload per message3353 * in order to be able to make useful progress.3354 */3355 if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) {3356 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n");3357 return -EINVAL;3358 }3359 3360 priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN;3361 if (priv->max_xfer_len > max_xfer)3362 priv->max_xfer_len = max_xfer;3363 if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER)3364 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER;3365 3366 priv->info = of_device_get_match_data(dev);3367 3368 /* Detect hardware device */3369 rc = sja1105_check_device_id(priv);3370 if (rc < 0) {3371 dev_err(dev, "Device ID check failed: %d\n", rc);3372 return rc;3373 }3374 3375 dev_info(dev, "Probed switch chip: %s\n", priv->info->name);3376 3377 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);3378 if (!ds)3379 return -ENOMEM;3380 3381 ds->dev = dev;3382 ds->num_ports = priv->info->num_ports;3383 ds->ops = &sja1105_switch_ops;3384 ds->phylink_mac_ops = &sja1105_phylink_mac_ops;3385 ds->priv = priv;3386 priv->ds = ds;3387 3388 mutex_init(&priv->ptp_data.lock);3389 mutex_init(&priv->dynamic_config_lock);3390 mutex_init(&priv->mgmt_lock);3391 mutex_init(&priv->fdb_lock);3392 spin_lock_init(&priv->ts_id_lock);3393 3394 rc = sja1105_parse_dt(priv);3395 if (rc < 0) {3396 dev_err(ds->dev, "Failed to parse DT: %d\n", rc);3397 return rc;3398 }3399 3400 if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {3401 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,3402 sizeof(struct sja1105_cbs_entry),3403 GFP_KERNEL);3404 if (!priv->cbs)3405 return -ENOMEM;3406 }3407 3408 return dsa_register_switch(priv->ds);3409}3410 3411static void sja1105_remove(struct spi_device *spi)3412{3413 struct sja1105_private *priv = spi_get_drvdata(spi);3414 3415 if (!priv)3416 return;3417 3418 dsa_unregister_switch(priv->ds);3419}3420 3421static void sja1105_shutdown(struct spi_device *spi)3422{3423 struct sja1105_private *priv = spi_get_drvdata(spi);3424 3425 if (!priv)3426 return;3427 3428 dsa_switch_shutdown(priv->ds);3429 3430 spi_set_drvdata(spi, NULL);3431}3432 3433static const struct of_device_id sja1105_dt_ids[] = {3434 { .compatible = "nxp,sja1105e", .data = &sja1105e_info },3435 { .compatible = "nxp,sja1105t", .data = &sja1105t_info },3436 { .compatible = "nxp,sja1105p", .data = &sja1105p_info },3437 { .compatible = "nxp,sja1105q", .data = &sja1105q_info },3438 { .compatible = "nxp,sja1105r", .data = &sja1105r_info },3439 { .compatible = "nxp,sja1105s", .data = &sja1105s_info },3440 { .compatible = "nxp,sja1110a", .data = &sja1110a_info },3441 { .compatible = "nxp,sja1110b", .data = &sja1110b_info },3442 { .compatible = "nxp,sja1110c", .data = &sja1110c_info },3443 { .compatible = "nxp,sja1110d", .data = &sja1110d_info },3444 { /* sentinel */ },3445};3446MODULE_DEVICE_TABLE(of, sja1105_dt_ids);3447 3448static const struct spi_device_id sja1105_spi_ids[] = {3449 { "sja1105e" },3450 { "sja1105t" },3451 { "sja1105p" },3452 { "sja1105q" },3453 { "sja1105r" },3454 { "sja1105s" },3455 { "sja1110a" },3456 { "sja1110b" },3457 { "sja1110c" },3458 { "sja1110d" },3459 { },3460};3461MODULE_DEVICE_TABLE(spi, sja1105_spi_ids);3462 3463static struct spi_driver sja1105_driver = {3464 .driver = {3465 .name = "sja1105",3466 .of_match_table = of_match_ptr(sja1105_dt_ids),3467 },3468 .id_table = sja1105_spi_ids,3469 .probe = sja1105_probe,3470 .remove = sja1105_remove,3471 .shutdown = sja1105_shutdown,3472};3473 3474module_spi_driver(sja1105_driver);3475 3476MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");3477MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");3478MODULE_DESCRIPTION("SJA1105 Driver");3479MODULE_LICENSE("GPL v2");3480