2417 lines · c
1// SPDX-License-Identifier: GPL-2.02/* DSA driver for:3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch7 *8 * These switches have a built-in 8051 CPU and can download and execute a9 * firmware in this CPU. They can also be configured to use an external CPU10 * handling the switch in a memory-mapped manner by connecting to that external11 * CPU's memory bus.12 *13 * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org>14 * Includes portions of code from the firmware uploader by:15 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>16 */17#include <linux/kernel.h>18#include <linux/module.h>19#include <linux/device.h>20#include <linux/iopoll.h>21#include <linux/of.h>22#include <linux/of_mdio.h>23#include <linux/bitops.h>24#include <linux/bitfield.h>25#include <linux/if_bridge.h>26#include <linux/if_vlan.h>27#include <linux/etherdevice.h>28#include <linux/gpio/consumer.h>29#include <linux/gpio/driver.h>30#include <linux/dsa/8021q.h>31#include <linux/random.h>32#include <net/dsa.h>33 34#include "vitesse-vsc73xx.h"35 36#define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */37#define VSC73XX_BLOCK_ANALYZER 0x2 /* Only subblock 0 */38#define VSC73XX_BLOCK_MII 0x3 /* Subblocks 0 and 1 */39#define VSC73XX_BLOCK_MEMINIT 0x3 /* Only subblock 2 */40#define VSC73XX_BLOCK_CAPTURE 0x4 /* Subblocks 0-4, 6, 7 */41#define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */42#define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */43 44/* MII Block subblock */45#define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */46#define VSC73XX_BLOCK_MII_EXTERNAL 0x1 /* External MDIO subblock */47 48#define CPU_PORT 6 /* CPU port */49#define VSC73XX_NUM_FDB_ROWS 204850#define VSC73XX_NUM_BUCKETS 451 52/* MAC Block registers */53#define VSC73XX_MAC_CFG 0x0054#define VSC73XX_MACHDXGAP 0x0255#define VSC73XX_FCCONF 0x0456#define VSC73XX_FCMACHI 0x0857#define VSC73XX_FCMACLO 0x0c58#define VSC73XX_MAXLEN 0x1059#define VSC73XX_ADVPORTM 0x1960#define VSC73XX_TXUPDCFG 0x2461#define VSC73XX_TXQ_SELECT_CFG 0x2862#define VSC73XX_RXOCT 0x5063#define VSC73XX_TXOCT 0x5164#define VSC73XX_C_RX0 0x5265#define VSC73XX_C_RX1 0x5366#define VSC73XX_C_RX2 0x5467#define VSC73XX_C_TX0 0x5568#define VSC73XX_C_TX1 0x5669#define VSC73XX_C_TX2 0x5770#define VSC73XX_C_CFG 0x5871#define VSC73XX_CAT_DROP 0x6e72#define VSC73XX_CAT_PR_MISC_L2 0x6f73#define VSC73XX_CAT_PR_USR_PRIO 0x7574#define VSC73XX_CAT_VLAN_MISC 0x7975#define VSC73XX_CAT_PORT_VLAN 0x7a76#define VSC73XX_Q_MISC_CONF 0xdf77 78/* MAC_CFG register bits */79#define VSC73XX_MAC_CFG_WEXC_DIS BIT(31)80#define VSC73XX_MAC_CFG_PORT_RST BIT(29)81#define VSC73XX_MAC_CFG_TX_EN BIT(28)82#define VSC73XX_MAC_CFG_SEED_LOAD BIT(27)83#define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19)84#define VSC73XX_MAC_CFG_SEED_OFFSET 1985#define VSC73XX_MAC_CFG_FDX BIT(18)86#define VSC73XX_MAC_CFG_GIGA_MODE BIT(17)87#define VSC73XX_MAC_CFG_RX_EN BIT(16)88#define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15)89#define VSC73XX_MAC_CFG_VLAN_AWR BIT(14)90#define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */91#define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6)92#define VSC73XX_MAC_CFG_TX_IPG_OFFSET 693#define VSC73XX_MAC_CFG_TX_IPG_1000M (6 << VSC73XX_MAC_CFG_TX_IPG_OFFSET)94#define VSC73XX_MAC_CFG_TX_IPG_100_10M (17 << VSC73XX_MAC_CFG_TX_IPG_OFFSET)95#define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5)96#define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4)97#define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0)98#define VSC73XX_MAC_CFG_CLK_SEL_OFFSET 099#define VSC73XX_MAC_CFG_CLK_SEL_1000M 1100#define VSC73XX_MAC_CFG_CLK_SEL_100M 2101#define VSC73XX_MAC_CFG_CLK_SEL_10M 3102#define VSC73XX_MAC_CFG_CLK_SEL_EXT 4103 104#define VSC73XX_MAC_CFG_1000M_F_PHY (VSC73XX_MAC_CFG_FDX | \105 VSC73XX_MAC_CFG_GIGA_MODE | \106 VSC73XX_MAC_CFG_TX_IPG_1000M | \107 VSC73XX_MAC_CFG_CLK_SEL_EXT)108#define VSC73XX_MAC_CFG_100_10M_F_PHY (VSC73XX_MAC_CFG_FDX | \109 VSC73XX_MAC_CFG_TX_IPG_100_10M | \110 VSC73XX_MAC_CFG_CLK_SEL_EXT)111#define VSC73XX_MAC_CFG_100_10M_H_PHY (VSC73XX_MAC_CFG_TX_IPG_100_10M | \112 VSC73XX_MAC_CFG_CLK_SEL_EXT)113#define VSC73XX_MAC_CFG_1000M_F_RGMII (VSC73XX_MAC_CFG_FDX | \114 VSC73XX_MAC_CFG_GIGA_MODE | \115 VSC73XX_MAC_CFG_TX_IPG_1000M | \116 VSC73XX_MAC_CFG_CLK_SEL_1000M)117#define VSC73XX_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \118 VSC73XX_MAC_CFG_MAC_RX_RST | \119 VSC73XX_MAC_CFG_MAC_TX_RST)120 121/* Flow control register bits */122#define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17)123#define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16)124#define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0)125 126/* ADVPORTM advanced port setup register bits */127#define VSC73XX_ADVPORTM_IFG_PPM BIT(7)128#define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6)129#define VSC73XX_ADVPORTM_EXT_PORT BIT(5)130#define VSC73XX_ADVPORTM_INV_GTX BIT(4)131#define VSC73XX_ADVPORTM_ENA_GTX BIT(3)132#define VSC73XX_ADVPORTM_DDR_MODE BIT(2)133#define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1)134#define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0)135 136/* TXUPDCFG transmit modify setup bits */137#define VSC73XX_TXUPDCFG_DSCP_REWR_MODE GENMASK(20, 19)138#define VSC73XX_TXUPDCFG_DSCP_REWR_ENA BIT(18)139#define VSC73XX_TXUPDCFG_TX_INT_TO_USRPRIO_ENA BIT(17)140#define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID GENMASK(15, 4)141#define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA BIT(3)142#define VSC73XX_TXUPDCFG_TX_UPDATE_CRC_CPU_ENA BIT(1)143#define VSC73XX_TXUPDCFG_TX_INSERT_TAG BIT(0)144 145#define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT 4146 147/* CAT_DROP categorizer frame dropping register bits */148#define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6)149#define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4)150#define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3)151#define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2)152#define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1)153#define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0)154 155#define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31)156#define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1)157#define VSC73XX_Q_MISC_CONF_EARLY_TX_512 (1 << 1)158#define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0)159 160/* CAT_VLAN_MISC categorizer VLAN miscellaneous bits */161#define VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA BIT(8)162#define VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA BIT(7)163 164/* CAT_PORT_VLAN categorizer port VLAN */165#define VSC73XX_CAT_PORT_VLAN_VLAN_CFI BIT(15)166#define VSC73XX_CAT_PORT_VLAN_VLAN_USR_PRIO GENMASK(14, 12)167#define VSC73XX_CAT_PORT_VLAN_VLAN_VID GENMASK(11, 0)168 169/* Frame analyzer block 2 registers */170#define VSC73XX_STORMLIMIT 0x02171#define VSC73XX_ADVLEARN 0x03172#define VSC73XX_IFLODMSK 0x04173#define VSC73XX_VLANMASK 0x05174#define VSC73XX_MACHDATA 0x06175#define VSC73XX_MACLDATA 0x07176#define VSC73XX_ANMOVED 0x08177#define VSC73XX_ANAGEFIL 0x09178#define VSC73XX_ANEVENTS 0x0a179#define VSC73XX_ANCNTMASK 0x0b180#define VSC73XX_ANCNTVAL 0x0c181#define VSC73XX_LEARNMASK 0x0d182#define VSC73XX_UFLODMASK 0x0e183#define VSC73XX_MFLODMASK 0x0f184#define VSC73XX_RECVMASK 0x10185#define VSC73XX_AGGRCTRL 0x20186#define VSC73XX_AGGRMSKS 0x30 /* Until 0x3f */187#define VSC73XX_DSTMASKS 0x40 /* Until 0x7f */188#define VSC73XX_SRCMASKS 0x80 /* Until 0x87 */189#define VSC73XX_CAPENAB 0xa0190#define VSC73XX_MACACCESS 0xb0191#define VSC73XX_IPMCACCESS 0xb1192#define VSC73XX_MACTINDX 0xc0193#define VSC73XX_VLANACCESS 0xd0194#define VSC73XX_VLANTIDX 0xe0195#define VSC73XX_AGENCTRL 0xf0196#define VSC73XX_CAPRST 0xff197 198#define VSC73XX_SRCMASKS_CPU_COPY BIT(27)199#define VSC73XX_SRCMASKS_MIRROR BIT(26)200#define VSC73XX_SRCMASKS_PORTS_MASK GENMASK(7, 0)201 202#define VSC73XX_MACHDATA_VID GENMASK(27, 16)203#define VSC73XX_MACHDATA_MAC0 GENMASK(15, 8)204#define VSC73XX_MACHDATA_MAC1 GENMASK(7, 0)205#define VSC73XX_MACLDATA_MAC2 GENMASK(31, 24)206#define VSC73XX_MACLDATA_MAC3 GENMASK(23, 16)207#define VSC73XX_MACLDATA_MAC4 GENMASK(15, 8)208#define VSC73XX_MACLDATA_MAC5 GENMASK(7, 0)209 210#define VSC73XX_HASH0_VID_FROM_MASK GENMASK(5, 0)211#define VSC73XX_HASH0_MAC0_FROM_MASK GENMASK(7, 4)212#define VSC73XX_HASH1_MAC0_FROM_MASK GENMASK(3, 0)213#define VSC73XX_HASH1_MAC1_FROM_MASK GENMASK(7, 1)214#define VSC73XX_HASH2_MAC1_FROM_MASK BIT(0)215#define VSC73XX_HASH2_MAC2_FROM_MASK GENMASK(7, 0)216#define VSC73XX_HASH2_MAC3_FROM_MASK GENMASK(7, 6)217#define VSC73XX_HASH3_MAC3_FROM_MASK GENMASK(5, 0)218#define VSC73XX_HASH3_MAC4_FROM_MASK GENMASK(7, 3)219#define VSC73XX_HASH4_MAC4_FROM_MASK GENMASK(2, 0)220 221#define VSC73XX_HASH0_VID_TO_MASK GENMASK(9, 4)222#define VSC73XX_HASH0_MAC0_TO_MASK GENMASK(3, 0)223#define VSC73XX_HASH1_MAC0_TO_MASK GENMASK(10, 7)224#define VSC73XX_HASH1_MAC1_TO_MASK GENMASK(6, 0)225#define VSC73XX_HASH2_MAC1_TO_MASK BIT(10)226#define VSC73XX_HASH2_MAC2_TO_MASK GENMASK(9, 2)227#define VSC73XX_HASH2_MAC3_TO_MASK GENMASK(1, 0)228#define VSC73XX_HASH3_MAC3_TO_MASK GENMASK(10, 5)229#define VSC73XX_HASH3_MAC4_TO_MASK GENMASK(4, 0)230#define VSC73XX_HASH4_MAC4_TO_MASK GENMASK(10, 8)231 232#define VSC73XX_MACTINDX_SHADOW BIT(13)233#define VSC73XX_MACTINDX_BUCKET_MSK GENMASK(12, 11)234#define VSC73XX_MACTINDX_INDEX_MSK GENMASK(10, 0)235 236#define VSC73XX_MACACCESS_CPU_COPY BIT(14)237#define VSC73XX_MACACCESS_FWD_KILL BIT(13)238#define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12)239#define VSC73XX_MACACCESS_AGED_FLAG BIT(11)240#define VSC73XX_MACACCESS_VALID BIT(10)241#define VSC73XX_MACACCESS_LOCKED BIT(9)242#define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3)243#define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0)244#define VSC73XX_MACACCESS_CMD_IDLE 0245#define VSC73XX_MACACCESS_CMD_LEARN 1246#define VSC73XX_MACACCESS_CMD_FORGET 2247#define VSC73XX_MACACCESS_CMD_AGE_TABLE 3248#define VSC73XX_MACACCESS_CMD_FLUSH_TABLE 4249#define VSC73XX_MACACCESS_CMD_CLEAR_TABLE 5250#define VSC73XX_MACACCESS_CMD_READ_ENTRY 6251#define VSC73XX_MACACCESS_CMD_WRITE_ENTRY 7252 253#define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30)254#define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29)255#define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28)256#define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2)257#define VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT 2258#define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(1, 0)259#define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE 0260#define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY 1261#define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY 2262#define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3263 264/* MII block 3 registers */265#define VSC73XX_MII_STAT 0x0266#define VSC73XX_MII_CMD 0x1267#define VSC73XX_MII_DATA 0x2268#define VSC73XX_MII_MPRES 0x3269 270#define VSC73XX_MII_STAT_BUSY BIT(3)271#define VSC73XX_MII_STAT_READ BIT(2)272#define VSC73XX_MII_STAT_WRITE BIT(1)273 274#define VSC73XX_MII_CMD_SCAN BIT(27)275#define VSC73XX_MII_CMD_OPERATION BIT(26)276#define VSC73XX_MII_CMD_PHY_ADDR GENMASK(25, 21)277#define VSC73XX_MII_CMD_PHY_REG GENMASK(20, 16)278#define VSC73XX_MII_CMD_WRITE_DATA GENMASK(15, 0)279 280#define VSC73XX_MII_DATA_FAILURE BIT(16)281#define VSC73XX_MII_DATA_READ_DATA GENMASK(15, 0)282 283#define VSC73XX_MII_MPRES_NOPREAMBLE BIT(6)284#define VSC73XX_MII_MPRES_PRESCALEVAL GENMASK(5, 0)285#define VSC73XX_MII_PRESCALEVAL_MIN 3 /* min allowed mdio clock prescaler */286 287#define VSC73XX_MII_STAT_BUSY BIT(3)288 289/* Arbiter block 5 registers */290#define VSC73XX_ARBEMPTY 0x0c291#define VSC73XX_ARBDISC 0x0e292#define VSC73XX_SBACKWDROP 0x12293#define VSC73XX_DBACKWDROP 0x13294#define VSC73XX_ARBBURSTPROB 0x15295 296/* System block 7 registers */297#define VSC73XX_ICPU_SIPAD 0x01298#define VSC73XX_GMIIDELAY 0x05299#define VSC73XX_ICPU_CTRL 0x10300#define VSC73XX_ICPU_ADDR 0x11301#define VSC73XX_ICPU_SRAM 0x12302#define VSC73XX_HWSEM 0x13303#define VSC73XX_GLORESET 0x14304#define VSC73XX_ICPU_MBOX_VAL 0x15305#define VSC73XX_ICPU_MBOX_SET 0x16306#define VSC73XX_ICPU_MBOX_CLR 0x17307#define VSC73XX_CHIPID 0x18308#define VSC73XX_GPIO 0x34309 310#define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE 0311#define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS 1312#define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS 2313#define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS 3314 315#define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE (0 << 4)316#define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS (1 << 4)317#define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS (2 << 4)318#define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS (3 << 4)319 320#define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31)321#define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8)322#define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7)323#define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6)324#define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3)325#define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2)326#define VSC73XX_ICPU_CTRL_CLK_EN BIT(1)327#define VSC73XX_ICPU_CTRL_SRST BIT(0)328 329#define VSC73XX_CHIPID_ID_SHIFT 12330#define VSC73XX_CHIPID_ID_MASK 0xffff331#define VSC73XX_CHIPID_REV_SHIFT 28332#define VSC73XX_CHIPID_REV_MASK 0xf333#define VSC73XX_CHIPID_ID_7385 0x7385334#define VSC73XX_CHIPID_ID_7388 0x7388335#define VSC73XX_CHIPID_ID_7395 0x7395336#define VSC73XX_CHIPID_ID_7398 0x7398337 338#define VSC73XX_GLORESET_STROBE BIT(4)339#define VSC73XX_GLORESET_ICPU_LOCK BIT(3)340#define VSC73XX_GLORESET_MEM_LOCK BIT(2)341#define VSC73XX_GLORESET_PHY_RESET BIT(1)342#define VSC73XX_GLORESET_MASTER_RESET BIT(0)343 344#define VSC7385_CLOCK_DELAY ((3 << 4) | 3)345#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3)346 347#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \348 VSC73XX_ICPU_CTRL_BOOT_EN | \349 VSC73XX_ICPU_CTRL_EXT_ACC_EN)350 351#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \352 VSC73XX_ICPU_CTRL_BOOT_EN | \353 VSC73XX_ICPU_CTRL_CLK_EN | \354 VSC73XX_ICPU_CTRL_SRST)355 356#define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385)357#define IS_7388(a) ((a)->chipid == VSC73XX_CHIPID_ID_7388)358#define IS_7395(a) ((a)->chipid == VSC73XX_CHIPID_ID_7395)359#define IS_7398(a) ((a)->chipid == VSC73XX_CHIPID_ID_7398)360#define IS_739X(a) (IS_7395(a) || IS_7398(a))361 362#define VSC73XX_POLL_SLEEP_US 1000363#define VSC73XX_MDIO_POLL_SLEEP_US 5364#define VSC73XX_POLL_TIMEOUT_US 10000365 366struct vsc73xx_counter {367 u8 counter;368 const char *name;369};370 371struct vsc73xx_fdb {372 u16 vid;373 u8 port;374 u8 mac[ETH_ALEN];375 bool valid;376};377 378/* Counters are named according to the MIB standards where applicable.379 * Some counters are custom, non-standard. The standard counters are380 * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex381 * 30A Counters.382 */383static const struct vsc73xx_counter vsc73xx_rx_counters[] = {384 { 0, "RxEtherStatsPkts" },385 { 1, "RxBroadcast+MulticastPkts" }, /* non-standard counter */386 { 2, "RxTotalErrorPackets" }, /* non-standard counter */387 { 3, "RxEtherStatsBroadcastPkts" },388 { 4, "RxEtherStatsMulticastPkts" },389 { 5, "RxEtherStatsPkts64Octets" },390 { 6, "RxEtherStatsPkts65to127Octets" },391 { 7, "RxEtherStatsPkts128to255Octets" },392 { 8, "RxEtherStatsPkts256to511Octets" },393 { 9, "RxEtherStatsPkts512to1023Octets" },394 { 10, "RxEtherStatsPkts1024to1518Octets" },395 { 11, "RxJumboFrames" }, /* non-standard counter */396 { 12, "RxaPauseMACControlFramesTransmitted" },397 { 13, "RxFIFODrops" }, /* non-standard counter */398 { 14, "RxBackwardDrops" }, /* non-standard counter */399 { 15, "RxClassifierDrops" }, /* non-standard counter */400 { 16, "RxEtherStatsCRCAlignErrors" },401 { 17, "RxEtherStatsUndersizePkts" },402 { 18, "RxEtherStatsOversizePkts" },403 { 19, "RxEtherStatsFragments" },404 { 20, "RxEtherStatsJabbers" },405 { 21, "RxaMACControlFramesReceived" },406 /* 22-24 are undefined */407 { 25, "RxaFramesReceivedOK" },408 { 26, "RxQoSClass0" }, /* non-standard counter */409 { 27, "RxQoSClass1" }, /* non-standard counter */410 { 28, "RxQoSClass2" }, /* non-standard counter */411 { 29, "RxQoSClass3" }, /* non-standard counter */412};413 414static const struct vsc73xx_counter vsc73xx_tx_counters[] = {415 { 0, "TxEtherStatsPkts" },416 { 1, "TxBroadcast+MulticastPkts" }, /* non-standard counter */417 { 2, "TxTotalErrorPackets" }, /* non-standard counter */418 { 3, "TxEtherStatsBroadcastPkts" },419 { 4, "TxEtherStatsMulticastPkts" },420 { 5, "TxEtherStatsPkts64Octets" },421 { 6, "TxEtherStatsPkts65to127Octets" },422 { 7, "TxEtherStatsPkts128to255Octets" },423 { 8, "TxEtherStatsPkts256to511Octets" },424 { 9, "TxEtherStatsPkts512to1023Octets" },425 { 10, "TxEtherStatsPkts1024to1518Octets" },426 { 11, "TxJumboFrames" }, /* non-standard counter */427 { 12, "TxaPauseMACControlFramesTransmitted" },428 { 13, "TxFIFODrops" }, /* non-standard counter */429 { 14, "TxDrops" }, /* non-standard counter */430 { 15, "TxEtherStatsCollisions" },431 { 16, "TxEtherStatsCRCAlignErrors" },432 { 17, "TxEtherStatsUndersizePkts" },433 { 18, "TxEtherStatsOversizePkts" },434 { 19, "TxEtherStatsFragments" },435 { 20, "TxEtherStatsJabbers" },436 /* 21-24 are undefined */437 { 25, "TxaFramesReceivedOK" },438 { 26, "TxQoSClass0" }, /* non-standard counter */439 { 27, "TxQoSClass1" }, /* non-standard counter */440 { 28, "TxQoSClass2" }, /* non-standard counter */441 { 29, "TxQoSClass3" }, /* non-standard counter */442};443 444struct vsc73xx_vlan_summary {445 size_t num_tagged;446 size_t num_untagged;447};448 449enum vsc73xx_port_vlan_conf {450 VSC73XX_VLAN_FILTER,451 VSC73XX_VLAN_FILTER_UNTAG_ALL,452 VSC73XX_VLAN_IGNORE,453};454 455int vsc73xx_is_addr_valid(u8 block, u8 subblock)456{457 switch (block) {458 case VSC73XX_BLOCK_MAC:459 switch (subblock) {460 case 0 ... 4:461 case 6:462 return 1;463 }464 break;465 466 case VSC73XX_BLOCK_ANALYZER:467 case VSC73XX_BLOCK_SYSTEM:468 switch (subblock) {469 case 0:470 return 1;471 }472 break;473 474 case VSC73XX_BLOCK_MII:475 case VSC73XX_BLOCK_ARBITER:476 switch (subblock) {477 case 0 ... 1:478 return 1;479 }480 break;481 case VSC73XX_BLOCK_CAPTURE:482 switch (subblock) {483 case 0 ... 4:484 case 6 ... 7:485 return 1;486 }487 break;488 }489 490 return 0;491}492EXPORT_SYMBOL(vsc73xx_is_addr_valid);493 494static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,495 u32 *val)496{497 return vsc->ops->read(vsc, block, subblock, reg, val);498}499 500static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,501 u32 val)502{503 return vsc->ops->write(vsc, block, subblock, reg, val);504}505 506static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock,507 u8 reg, u32 mask, u32 val)508{509 u32 tmp, orig;510 int ret;511 512 /* Same read-modify-write algorithm as e.g. regmap */513 ret = vsc73xx_read(vsc, block, subblock, reg, &orig);514 if (ret)515 return ret;516 tmp = orig & ~mask;517 tmp |= val & mask;518 return vsc73xx_write(vsc, block, subblock, reg, tmp);519}520 521static int vsc73xx_detect(struct vsc73xx *vsc)522{523 bool icpu_si_boot_en;524 bool icpu_pi_en;525 u32 val;526 u32 rev;527 int ret;528 u32 id;529 530 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,531 VSC73XX_ICPU_MBOX_VAL, &val);532 if (ret) {533 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret);534 return ret;535 }536 537 if (val == 0xffffffff) {538 dev_info(vsc->dev, "chip seems dead.\n");539 return -EAGAIN;540 }541 542 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,543 VSC73XX_CHIPID, &val);544 if (ret) {545 dev_err(vsc->dev, "unable to read chip id (%d)\n", ret);546 return ret;547 }548 549 id = (val >> VSC73XX_CHIPID_ID_SHIFT) &550 VSC73XX_CHIPID_ID_MASK;551 switch (id) {552 case VSC73XX_CHIPID_ID_7385:553 case VSC73XX_CHIPID_ID_7388:554 case VSC73XX_CHIPID_ID_7395:555 case VSC73XX_CHIPID_ID_7398:556 break;557 default:558 dev_err(vsc->dev, "unsupported chip, id=%04x\n", id);559 return -ENODEV;560 }561 562 vsc->chipid = id;563 rev = (val >> VSC73XX_CHIPID_REV_SHIFT) &564 VSC73XX_CHIPID_REV_MASK;565 dev_info(vsc->dev, "VSC%04X (rev: %d) switch found\n", id, rev);566 567 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,568 VSC73XX_ICPU_CTRL, &val);569 if (ret) {570 dev_err(vsc->dev, "unable to read iCPU control\n");571 return ret;572 }573 574 /* The iCPU can always be used but can boot in different ways.575 * If it is initially disabled and has no external memory,576 * we are in control and can do whatever we like, else we577 * are probably in trouble (we need some way to communicate578 * with the running firmware) so we bail out for now.579 */580 icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN);581 icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN);582 if (icpu_si_boot_en && icpu_pi_en) {583 dev_err(vsc->dev,584 "iCPU enabled boots from SI, has external memory\n");585 dev_err(vsc->dev, "no idea how to deal with this\n");586 return -ENODEV;587 }588 if (icpu_si_boot_en && !icpu_pi_en) {589 dev_err(vsc->dev,590 "iCPU enabled boots from PI/SI, no external memory\n");591 return -EAGAIN;592 }593 if (!icpu_si_boot_en && icpu_pi_en) {594 dev_err(vsc->dev,595 "iCPU enabled, boots from PI external memory\n");596 dev_err(vsc->dev, "no idea how to deal with this\n");597 return -ENODEV;598 }599 /* !icpu_si_boot_en && !cpu_pi_en */600 dev_info(vsc->dev, "iCPU disabled, no external memory\n");601 602 return 0;603}604 605static int vsc73xx_mdio_busy_check(struct vsc73xx *vsc)606{607 int ret, err;608 u32 val;609 610 ret = read_poll_timeout(vsc73xx_read, err,611 err < 0 || !(val & VSC73XX_MII_STAT_BUSY),612 VSC73XX_MDIO_POLL_SLEEP_US,613 VSC73XX_POLL_TIMEOUT_US, false, vsc,614 VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,615 VSC73XX_MII_STAT, &val);616 if (ret)617 return ret;618 return err;619}620 621static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum)622{623 struct vsc73xx *vsc = ds->priv;624 u32 cmd;625 u32 val;626 int ret;627 628 ret = vsc73xx_mdio_busy_check(vsc);629 if (ret)630 return ret;631 632 /* Setting bit 26 means "read" */633 cmd = VSC73XX_MII_CMD_OPERATION |634 FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) |635 FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum);636 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,637 VSC73XX_MII_CMD, cmd);638 if (ret)639 return ret;640 641 ret = vsc73xx_mdio_busy_check(vsc);642 if (ret)643 return ret;644 645 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,646 VSC73XX_MII_DATA, &val);647 if (ret)648 return ret;649 if (val & VSC73XX_MII_DATA_FAILURE) {650 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n",651 regnum, phy);652 return -EIO;653 }654 val &= VSC73XX_MII_DATA_READ_DATA;655 656 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n",657 regnum, phy, val);658 659 return val;660}661 662static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum,663 u16 val)664{665 struct vsc73xx *vsc = ds->priv;666 u32 cmd;667 int ret;668 669 ret = vsc73xx_mdio_busy_check(vsc);670 if (ret)671 return ret;672 673 cmd = FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) |674 FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum) |675 FIELD_PREP(VSC73XX_MII_CMD_WRITE_DATA, val);676 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,677 VSC73XX_MII_CMD, cmd);678 if (ret)679 return ret;680 681 dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n",682 val, regnum, phy);683 return 0;684}685 686static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds,687 int port,688 enum dsa_tag_protocol mp)689{690 /* The switch internally uses a 8 byte header with length,691 * source port, tag, LPA and priority. This is supposedly692 * only accessible when operating the switch using the internal693 * CPU or with an external CPU mapping the device in, but not694 * when operating the switch over SPI and putting frames in/out695 * on port 6 (the CPU port). So far we must assume that we696 * cannot access the tag. (See "Internal frame header" section697 * 3.9.1 in the manual.)698 */699 return DSA_TAG_PROTO_VSC73XX_8021Q;700}701 702static int vsc73xx_wait_for_vlan_table_cmd(struct vsc73xx *vsc)703{704 int ret, err;705 u32 val;706 707 ret = read_poll_timeout(vsc73xx_read, err,708 err < 0 ||709 ((val & VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK) ==710 VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE),711 VSC73XX_POLL_SLEEP_US, VSC73XX_POLL_TIMEOUT_US,712 false, vsc, VSC73XX_BLOCK_ANALYZER,713 0, VSC73XX_VLANACCESS, &val);714 if (ret)715 return ret;716 return err;717}718 719static int720vsc73xx_read_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 *portmap)721{722 u32 val;723 int ret;724 725 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid);726 727 ret = vsc73xx_wait_for_vlan_table_cmd(vsc);728 if (ret)729 return ret;730 731 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS,732 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK,733 VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY);734 735 ret = vsc73xx_wait_for_vlan_table_cmd(vsc);736 if (ret)737 return ret;738 739 vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, &val);740 *portmap = (val & VSC73XX_VLANACCESS_VLAN_PORT_MASK) >>741 VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT;742 743 return 0;744}745 746static int747vsc73xx_write_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 portmap)748{749 int ret;750 751 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid);752 753 ret = vsc73xx_wait_for_vlan_table_cmd(vsc);754 if (ret)755 return ret;756 757 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS,758 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK |759 VSC73XX_VLANACCESS_VLAN_SRC_CHECK |760 VSC73XX_VLANACCESS_VLAN_PORT_MASK,761 VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY |762 VSC73XX_VLANACCESS_VLAN_SRC_CHECK |763 (portmap << VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT));764 765 return vsc73xx_wait_for_vlan_table_cmd(vsc);766}767 768static int769vsc73xx_update_vlan_table(struct vsc73xx *vsc, int port, u16 vid, bool set)770{771 u8 portmap;772 int ret;773 774 ret = vsc73xx_read_vlan_table_entry(vsc, vid, &portmap);775 if (ret)776 return ret;777 778 if (set)779 portmap |= BIT(port);780 else781 portmap &= ~BIT(port);782 783 return vsc73xx_write_vlan_table_entry(vsc, vid, portmap);784}785 786static int vsc73xx_configure_rgmii_port_delay(struct dsa_switch *ds)787{788 /* Keep 2.0 ns delay for backward complatibility */789 u32 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS;790 u32 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS;791 struct dsa_port *dp = dsa_to_port(ds, CPU_PORT);792 struct device_node *port_dn = dp->dn;793 struct vsc73xx *vsc = ds->priv;794 u32 delay;795 796 if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay)) {797 switch (delay) {798 case 0:799 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE;800 break;801 case 1400:802 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS;803 break;804 case 1700:805 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS;806 break;807 case 2000:808 break;809 default:810 dev_err(vsc->dev,811 "Unsupported RGMII Transmit Clock Delay\n");812 return -EINVAL;813 }814 } else {815 dev_dbg(vsc->dev,816 "RGMII Transmit Clock Delay isn't configured, set to 2.0 ns\n");817 }818 819 if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay)) {820 switch (delay) {821 case 0:822 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE;823 break;824 case 1400:825 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS;826 break;827 case 1700:828 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS;829 break;830 case 2000:831 break;832 default:833 dev_err(vsc->dev,834 "Unsupported RGMII Receive Clock Delay value\n");835 return -EINVAL;836 }837 } else {838 dev_dbg(vsc->dev,839 "RGMII Receive Clock Delay isn't configured, set to 2.0 ns\n");840 }841 842 /* MII delay, set both GTX and RX delay */843 return vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GMIIDELAY,844 tx_delay | rx_delay);845}846 847static int vsc73xx_setup(struct dsa_switch *ds)848{849 struct vsc73xx *vsc = ds->priv;850 int i, ret, val;851 852 dev_info(vsc->dev, "set up the switch\n");853 854 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES;855 ds->fdb_isolation = true;856 857 /* Issue RESET */858 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET,859 VSC73XX_GLORESET_MASTER_RESET);860 usleep_range(125, 200);861 862 /* Initialize memory, initialize RAM bank 0..15 except 6 and 7863 * This sequence appears in the864 * VSC7385 SparX-G5 datasheet section 6.6.1865 * VSC7395 SparX-G5e datasheet section 6.6.1866 * "initialization sequence".867 * No explanation is given to the 0x1010400 magic number.868 */869 for (i = 0; i <= 15; i++) {870 if (i != 6 && i != 7) {871 vsc73xx_write(vsc, VSC73XX_BLOCK_MEMINIT,872 2,873 0, 0x1010400 + i);874 mdelay(1);875 }876 }877 mdelay(30);878 879 /* Clear MAC table */880 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0,881 VSC73XX_MACACCESS,882 VSC73XX_MACACCESS_CMD_CLEAR_TABLE);883 884 /* Set VLAN table to default values */885 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0,886 VSC73XX_VLANACCESS,887 VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE);888 889 msleep(40);890 891 /* Use 20KiB buffers on all ports on VSC7395892 * The VSC7385 has 16KiB buffers and that is the893 * default if we don't set this up explicitly.894 * Port "31" is "all ports".895 */896 if (IS_739X(vsc))897 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 0x1f,898 VSC73XX_Q_MISC_CONF,899 VSC73XX_Q_MISC_CONF_EXTENT_MEM);900 901 /* Put all ports into reset until enabled */902 for (i = 0; i < 7; i++) {903 if (i == 5)904 continue;905 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 4,906 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET);907 }908 909 /* Configure RGMII delay */910 ret = vsc73xx_configure_rgmii_port_delay(ds);911 if (ret)912 return ret;913 914 /* Ingess VLAN reception mask (table 145) */915 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANMASK,916 0xff);917 /* IP multicast flood mask (table 144) */918 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_IFLODMSK,919 0xff);920 921 mdelay(50);922 923 /* Disable preamble and use maximum allowed clock for the internal924 * mdio bus, used for communication with internal PHYs only.925 */926 val = VSC73XX_MII_MPRES_NOPREAMBLE |927 FIELD_PREP(VSC73XX_MII_MPRES_PRESCALEVAL,928 VSC73XX_MII_PRESCALEVAL_MIN);929 vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,930 VSC73XX_MII_MPRES, val);931 932 /* Release reset from the internal PHYs */933 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET,934 VSC73XX_GLORESET_PHY_RESET);935 936 udelay(4);937 938 /* Clear VLAN table */939 for (i = 0; i < VLAN_N_VID; i++)940 vsc73xx_write_vlan_table_entry(vsc, i, 0);941 942 INIT_LIST_HEAD(&vsc->vlans);943 944 rtnl_lock();945 ret = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));946 rtnl_unlock();947 948 return ret;949}950 951static void vsc73xx_teardown(struct dsa_switch *ds)952{953 rtnl_lock();954 dsa_tag_8021q_unregister(ds);955 rtnl_unlock();956}957 958static void vsc73xx_init_port(struct vsc73xx *vsc, int port)959{960 u32 val;961 962 /* MAC configure, first reset the port and then write defaults */963 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,964 port,965 VSC73XX_MAC_CFG,966 VSC73XX_MAC_CFG_RESET);967 968 /* Take up the port in 1Gbit mode by default, this will be969 * augmented after auto-negotiation on the PHY-facing970 * ports.971 */972 if (port == CPU_PORT)973 val = VSC73XX_MAC_CFG_1000M_F_RGMII;974 else975 val = VSC73XX_MAC_CFG_1000M_F_PHY;976 977 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,978 port,979 VSC73XX_MAC_CFG,980 val |981 VSC73XX_MAC_CFG_TX_EN |982 VSC73XX_MAC_CFG_RX_EN);983 984 /* Flow control for the CPU port:985 * Use a zero delay pause frame when pause condition is left986 * Obey pause control frames987 */988 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,989 port,990 VSC73XX_FCCONF,991 VSC73XX_FCCONF_ZERO_PAUSE_EN |992 VSC73XX_FCCONF_FLOW_CTRL_OBEY);993 994 /* Issue pause control frames on PHY facing ports.995 * Allow early initiation of MAC transmission if the amount996 * of egress data is below 512 bytes on CPU port.997 * FIXME: enable 20KiB buffers?998 */999 if (port == CPU_PORT)1000 val = VSC73XX_Q_MISC_CONF_EARLY_TX_512;1001 else1002 val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE;1003 val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM;1004 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,1005 port,1006 VSC73XX_Q_MISC_CONF,1007 val);1008 1009 /* Flow control MAC: a MAC address used in flow control frames */1010 val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]);1011 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,1012 port,1013 VSC73XX_FCMACHI,1014 val);1015 val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]);1016 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,1017 port,1018 VSC73XX_FCMACLO,1019 val);1020 1021 /* Tell the categorizer to forward pause frames, not control1022 * frame. Do not drop anything.1023 */1024 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,1025 port,1026 VSC73XX_CAT_DROP,1027 VSC73XX_CAT_DROP_FWD_PAUSE_ENA);1028 1029 /* Clear all counters */1030 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,1031 port, VSC73XX_C_RX0, 0);1032}1033 1034static void vsc73xx_reset_port(struct vsc73xx *vsc, int port, u32 initval)1035{1036 int ret, err;1037 u32 val;1038 1039 /* Disable RX on this port */1040 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,1041 VSC73XX_MAC_CFG,1042 VSC73XX_MAC_CFG_RX_EN, 0);1043 1044 /* Discard packets */1045 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,1046 VSC73XX_ARBDISC, BIT(port), BIT(port));1047 1048 /* Wait until queue is empty */1049 ret = read_poll_timeout(vsc73xx_read, err,1050 err < 0 || (val & BIT(port)),1051 VSC73XX_POLL_SLEEP_US,1052 VSC73XX_POLL_TIMEOUT_US, false,1053 vsc, VSC73XX_BLOCK_ARBITER, 0,1054 VSC73XX_ARBEMPTY, &val);1055 if (ret)1056 dev_err(vsc->dev,1057 "timeout waiting for block arbiter\n");1058 else if (err < 0)1059 dev_err(vsc->dev, "error reading arbiter\n");1060 1061 /* Put this port into reset */1062 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG,1063 VSC73XX_MAC_CFG_RESET | initval);1064}1065 1066static void vsc73xx_mac_config(struct phylink_config *config, unsigned int mode,1067 const struct phylink_link_state *state)1068{1069 struct dsa_port *dp = dsa_phylink_to_port(config);1070 struct vsc73xx *vsc = dp->ds->priv;1071 int port = dp->index;1072 1073 /* Special handling of the CPU-facing port */1074 if (port == CPU_PORT) {1075 /* Other ports are already initialized but not this one */1076 vsc73xx_init_port(vsc, CPU_PORT);1077 /* Select the external port for this interface (EXT_PORT)1078 * Enable the GMII GTX external clock1079 * Use double data rate (DDR mode)1080 */1081 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,1082 CPU_PORT,1083 VSC73XX_ADVPORTM,1084 VSC73XX_ADVPORTM_EXT_PORT |1085 VSC73XX_ADVPORTM_ENA_GTX |1086 VSC73XX_ADVPORTM_DDR_MODE);1087 }1088}1089 1090static void vsc73xx_mac_link_down(struct phylink_config *config,1091 unsigned int mode, phy_interface_t interface)1092{1093 struct dsa_port *dp = dsa_phylink_to_port(config);1094 struct vsc73xx *vsc = dp->ds->priv;1095 int port = dp->index;1096 1097 /* This routine is described in the datasheet (below ARBDISC register1098 * description)1099 */1100 vsc73xx_reset_port(vsc, port, 0);1101 1102 /* Allow backward dropping of frames from this port */1103 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,1104 VSC73XX_SBACKWDROP, BIT(port), BIT(port));1105}1106 1107static void vsc73xx_mac_link_up(struct phylink_config *config,1108 struct phy_device *phy, unsigned int mode,1109 phy_interface_t interface, int speed,1110 int duplex, bool tx_pause, bool rx_pause)1111{1112 struct dsa_port *dp = dsa_phylink_to_port(config);1113 struct vsc73xx *vsc = dp->ds->priv;1114 int port = dp->index;1115 u32 val;1116 u8 seed;1117 1118 if (speed == SPEED_1000)1119 val = VSC73XX_MAC_CFG_GIGA_MODE | VSC73XX_MAC_CFG_TX_IPG_1000M;1120 else1121 val = VSC73XX_MAC_CFG_TX_IPG_100_10M;1122 1123 if (phy_interface_mode_is_rgmii(interface))1124 val |= VSC73XX_MAC_CFG_CLK_SEL_1000M;1125 else1126 val |= VSC73XX_MAC_CFG_CLK_SEL_EXT;1127 1128 if (duplex == DUPLEX_FULL)1129 val |= VSC73XX_MAC_CFG_FDX;1130 else1131 /* In datasheet description ("Port Mode Procedure" in 5.6.2)1132 * this bit is configured only for half duplex.1133 */1134 val |= VSC73XX_MAC_CFG_WEXC_DIS;1135 1136 /* This routine is described in the datasheet (below ARBDISC register1137 * description)1138 */1139 vsc73xx_reset_port(vsc, port, val);1140 1141 /* Seed the port randomness with randomness */1142 get_random_bytes(&seed, 1);1143 val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET;1144 val |= VSC73XX_MAC_CFG_SEED_LOAD;1145 1146 /* Those bits are responsible for MTU only. Kernel takes care about MTU,1147 * let's enable +8 bytes frame length unconditionally.1148 */1149 val |= VSC73XX_MAC_CFG_VLAN_AWR | VSC73XX_MAC_CFG_VLAN_DBLAWR;1150 1151 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val);1152 1153 /* Flow control for the PHY facing ports:1154 * Use a zero delay pause frame when pause condition is left1155 * Obey pause control frames1156 * When generating pause frames, use 0xff as pause value1157 */1158 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF,1159 VSC73XX_FCCONF_ZERO_PAUSE_EN |1160 VSC73XX_FCCONF_FLOW_CTRL_OBEY |1161 0xff);1162 1163 /* Accept packets again */1164 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,1165 VSC73XX_ARBDISC, BIT(port), 0);1166 1167 /* Disallow backward dropping of frames from this port */1168 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,1169 VSC73XX_SBACKWDROP, BIT(port), 0);1170 1171 /* Enable TX, RX, deassert reset, stop loading seed */1172 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,1173 VSC73XX_MAC_CFG,1174 VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD |1175 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN,1176 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN);1177}1178 1179static bool vsc73xx_tag_8021q_active(struct dsa_port *dp)1180{1181 return !dsa_port_is_vlan_filtering(dp);1182}1183 1184static struct vsc73xx_bridge_vlan *1185vsc73xx_bridge_vlan_find(struct vsc73xx *vsc, u16 vid)1186{1187 struct vsc73xx_bridge_vlan *vlan;1188 1189 list_for_each_entry(vlan, &vsc->vlans, list)1190 if (vlan->vid == vid)1191 return vlan;1192 1193 return NULL;1194}1195 1196static void1197vsc73xx_bridge_vlan_remove_port(struct vsc73xx_bridge_vlan *vsc73xx_vlan,1198 int port)1199{1200 vsc73xx_vlan->portmask &= ~BIT(port);1201 1202 if (vsc73xx_vlan->portmask)1203 return;1204 1205 list_del(&vsc73xx_vlan->list);1206 kfree(vsc73xx_vlan);1207}1208 1209static void vsc73xx_bridge_vlan_summary(struct vsc73xx *vsc, int port,1210 struct vsc73xx_vlan_summary *summary,1211 u16 ignored_vid)1212{1213 size_t num_tagged = 0, num_untagged = 0;1214 struct vsc73xx_bridge_vlan *vlan;1215 1216 list_for_each_entry(vlan, &vsc->vlans, list) {1217 if (!(vlan->portmask & BIT(port)) || vlan->vid == ignored_vid)1218 continue;1219 1220 if (vlan->untagged & BIT(port))1221 num_untagged++;1222 else1223 num_tagged++;1224 }1225 1226 summary->num_untagged = num_untagged;1227 summary->num_tagged = num_tagged;1228}1229 1230static u16 vsc73xx_find_first_vlan_untagged(struct vsc73xx *vsc, int port)1231{1232 struct vsc73xx_bridge_vlan *vlan;1233 1234 list_for_each_entry(vlan, &vsc->vlans, list)1235 if ((vlan->portmask & BIT(port)) &&1236 (vlan->untagged & BIT(port)))1237 return vlan->vid;1238 1239 return VLAN_N_VID;1240}1241 1242static int vsc73xx_set_vlan_conf(struct vsc73xx *vsc, int port,1243 enum vsc73xx_port_vlan_conf port_vlan_conf)1244{1245 u32 val = 0;1246 int ret;1247 1248 if (port_vlan_conf == VSC73XX_VLAN_IGNORE)1249 val = VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA |1250 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA;1251 1252 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,1253 VSC73XX_CAT_VLAN_MISC,1254 VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA |1255 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA, val);1256 if (ret)1257 return ret;1258 1259 val = (port_vlan_conf == VSC73XX_VLAN_FILTER) ?1260 VSC73XX_TXUPDCFG_TX_INSERT_TAG : 0;1261 1262 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,1263 VSC73XX_TXUPDCFG,1264 VSC73XX_TXUPDCFG_TX_INSERT_TAG, val);1265}1266 1267/**1268 * vsc73xx_vlan_commit_conf - Update VLAN configuration of a port1269 * @vsc: Switch private data structure1270 * @port: Port index on which to operate1271 *1272 * Update the VLAN behavior of a port to make sure that when it is under1273 * a VLAN filtering bridge, the port is either filtering with tag1274 * preservation, or filtering with all VLANs egress-untagged. Otherwise,1275 * the port ignores VLAN tags from packets and applies the port-based1276 * VID.1277 *1278 * Must be called when changes are made to:1279 * - the bridge VLAN filtering state of the port1280 * - the number or attributes of VLANs from the bridge VLAN table,1281 * while the port is currently VLAN-aware1282 *1283 * Return: 0 on success, or negative errno on error.1284 */1285static int vsc73xx_vlan_commit_conf(struct vsc73xx *vsc, int port)1286{1287 enum vsc73xx_port_vlan_conf port_vlan_conf = VSC73XX_VLAN_IGNORE;1288 struct dsa_port *dp = dsa_to_port(vsc->ds, port);1289 1290 if (port == CPU_PORT) {1291 port_vlan_conf = VSC73XX_VLAN_FILTER;1292 } else if (dsa_port_is_vlan_filtering(dp)) {1293 struct vsc73xx_vlan_summary summary;1294 1295 port_vlan_conf = VSC73XX_VLAN_FILTER;1296 1297 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID);1298 if (summary.num_tagged == 0)1299 port_vlan_conf = VSC73XX_VLAN_FILTER_UNTAG_ALL;1300 }1301 1302 return vsc73xx_set_vlan_conf(vsc, port, port_vlan_conf);1303}1304 1305static int1306vsc73xx_vlan_change_untagged(struct vsc73xx *vsc, int port, u16 vid, bool set)1307{1308 u32 val = 0;1309 1310 if (set)1311 val = VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA |1312 ((vid << VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT) &1313 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID);1314 1315 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,1316 VSC73XX_TXUPDCFG,1317 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA |1318 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID, val);1319}1320 1321/**1322 * vsc73xx_vlan_commit_untagged - Update native VLAN of a port1323 * @vsc: Switch private data structure1324 * @port: Port index on which to operate1325 *1326 * Update the native VLAN of a port (the one VLAN which is transmitted1327 * as egress-tagged on a trunk port) when port is in VLAN filtering mode and1328 * only one untagged vid is configured.1329 * In other cases no need to configure it because switch can untag all vlans on1330 * the port.1331 *1332 * Return: 0 on success, or negative errno on error.1333 */1334static int vsc73xx_vlan_commit_untagged(struct vsc73xx *vsc, int port)1335{1336 struct dsa_port *dp = dsa_to_port(vsc->ds, port);1337 struct vsc73xx_vlan_summary summary;1338 u16 vid = 0;1339 bool valid;1340 1341 if (!dsa_port_is_vlan_filtering(dp))1342 /* Port is configured to untag all vlans in that case.1343 * No need to commit untagged config change.1344 */1345 return 0;1346 1347 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID);1348 1349 if (summary.num_untagged > 1)1350 /* Port must untag all vlans in that case.1351 * No need to commit untagged config change.1352 */1353 return 0;1354 1355 valid = (summary.num_untagged == 1);1356 if (valid)1357 vid = vsc73xx_find_first_vlan_untagged(vsc, port);1358 1359 return vsc73xx_vlan_change_untagged(vsc, port, vid, valid);1360}1361 1362static int1363vsc73xx_vlan_change_pvid(struct vsc73xx *vsc, int port, u16 vid, bool set)1364{1365 u32 val = 0;1366 int ret;1367 1368 val = set ? 0 : VSC73XX_CAT_DROP_UNTAGGED_ENA;1369 1370 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,1371 VSC73XX_CAT_DROP,1372 VSC73XX_CAT_DROP_UNTAGGED_ENA, val);1373 if (!set || ret)1374 return ret;1375 1376 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,1377 VSC73XX_CAT_PORT_VLAN,1378 VSC73XX_CAT_PORT_VLAN_VLAN_VID,1379 vid & VSC73XX_CAT_PORT_VLAN_VLAN_VID);1380}1381 1382/**1383 * vsc73xx_vlan_commit_pvid - Update port-based default VLAN of a port1384 * @vsc: Switch private data structure1385 * @port: Port index on which to operate1386 *1387 * Update the PVID of a port so that it follows either the bridge PVID1388 * configuration, when the bridge is currently VLAN-aware, or the PVID1389 * from tag_8021q, when the port is standalone or under a VLAN-unaware1390 * bridge. A port with no PVID drops all untagged and VID 0 tagged1391 * traffic.1392 *1393 * Must be called when changes are made to:1394 * - the bridge VLAN filtering state of the port1395 * - the number or attributes of VLANs from the bridge VLAN table,1396 * while the port is currently VLAN-aware1397 *1398 * Return: 0 on success, or negative errno on error.1399 */1400static int vsc73xx_vlan_commit_pvid(struct vsc73xx *vsc, int port)1401{1402 struct vsc73xx_portinfo *portinfo = &vsc->portinfo[port];1403 bool valid = portinfo->pvid_tag_8021q_configured;1404 struct dsa_port *dp = dsa_to_port(vsc->ds, port);1405 u16 vid = portinfo->pvid_tag_8021q;1406 1407 if (dsa_port_is_vlan_filtering(dp)) {1408 vid = portinfo->pvid_vlan_filtering;1409 valid = portinfo->pvid_vlan_filtering_configured;1410 }1411 1412 return vsc73xx_vlan_change_pvid(vsc, port, vid, valid);1413}1414 1415static int vsc73xx_vlan_commit_settings(struct vsc73xx *vsc, int port)1416{1417 int ret;1418 1419 ret = vsc73xx_vlan_commit_untagged(vsc, port);1420 if (ret)1421 return ret;1422 1423 ret = vsc73xx_vlan_commit_pvid(vsc, port);1424 if (ret)1425 return ret;1426 1427 return vsc73xx_vlan_commit_conf(vsc, port);1428}1429 1430static int vsc73xx_port_enable(struct dsa_switch *ds, int port,1431 struct phy_device *phy)1432{1433 struct vsc73xx *vsc = ds->priv;1434 1435 dev_info(vsc->dev, "enable port %d\n", port);1436 vsc73xx_init_port(vsc, port);1437 1438 return vsc73xx_vlan_commit_settings(vsc, port);1439}1440 1441static void vsc73xx_port_disable(struct dsa_switch *ds, int port)1442{1443 struct vsc73xx *vsc = ds->priv;1444 1445 /* Just put the port into reset */1446 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port,1447 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET);1448}1449 1450static const struct vsc73xx_counter *1451vsc73xx_find_counter(struct vsc73xx *vsc,1452 u8 counter,1453 bool tx)1454{1455 const struct vsc73xx_counter *cnts;1456 int num_cnts;1457 int i;1458 1459 if (tx) {1460 cnts = vsc73xx_tx_counters;1461 num_cnts = ARRAY_SIZE(vsc73xx_tx_counters);1462 } else {1463 cnts = vsc73xx_rx_counters;1464 num_cnts = ARRAY_SIZE(vsc73xx_rx_counters);1465 }1466 1467 for (i = 0; i < num_cnts; i++) {1468 const struct vsc73xx_counter *cnt;1469 1470 cnt = &cnts[i];1471 if (cnt->counter == counter)1472 return cnt;1473 }1474 1475 return NULL;1476}1477 1478static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset,1479 uint8_t *data)1480{1481 const struct vsc73xx_counter *cnt;1482 struct vsc73xx *vsc = ds->priv;1483 u8 indices[6];1484 u8 *buf = data;1485 int i;1486 u32 val;1487 int ret;1488 1489 if (stringset != ETH_SS_STATS)1490 return;1491 1492 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port,1493 VSC73XX_C_CFG, &val);1494 if (ret)1495 return;1496 1497 indices[0] = (val & 0x1f); /* RX counter 0 */1498 indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */1499 indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */1500 indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */1501 indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */1502 indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */1503 1504 /* The first counters is the RX octets */1505 ethtool_puts(&buf, "RxEtherStatsOctets");1506 1507 /* Each port supports recording 3 RX counters and 3 TX counters,1508 * figure out what counters we use in this set-up and return the1509 * names of them. The hardware default counters will be number of1510 * packets on RX/TX, combined broadcast+multicast packets RX/TX and1511 * total error packets RX/TX.1512 */1513 for (i = 0; i < 3; i++) {1514 cnt = vsc73xx_find_counter(vsc, indices[i], false);1515 ethtool_puts(&buf, cnt ? cnt->name : "");1516 }1517 1518 /* TX stats begins with the number of TX octets */1519 ethtool_puts(&buf, "TxEtherStatsOctets");1520 1521 for (i = 3; i < 6; i++) {1522 cnt = vsc73xx_find_counter(vsc, indices[i], true);1523 ethtool_puts(&buf, cnt ? cnt->name : "");1524 1525 }1526}1527 1528static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset)1529{1530 /* We only support SS_STATS */1531 if (sset != ETH_SS_STATS)1532 return 0;1533 /* RX and TX packets, then 3 RX counters, 3 TX counters */1534 return 8;1535}1536 1537static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port,1538 uint64_t *data)1539{1540 struct vsc73xx *vsc = ds->priv;1541 u8 regs[] = {1542 VSC73XX_RXOCT,1543 VSC73XX_C_RX0,1544 VSC73XX_C_RX1,1545 VSC73XX_C_RX2,1546 VSC73XX_TXOCT,1547 VSC73XX_C_TX0,1548 VSC73XX_C_TX1,1549 VSC73XX_C_TX2,1550 };1551 u32 val;1552 int ret;1553 int i;1554 1555 for (i = 0; i < ARRAY_SIZE(regs); i++) {1556 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port,1557 regs[i], &val);1558 if (ret) {1559 dev_err(vsc->dev, "error reading counter %d\n", i);1560 return;1561 }1562 data[i] = val;1563 }1564}1565 1566static int vsc73xx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)1567{1568 struct vsc73xx *vsc = ds->priv;1569 1570 return vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port,1571 VSC73XX_MAXLEN, new_mtu + ETH_HLEN + ETH_FCS_LEN);1572}1573 1574/* According to application not "VSC7398 Jumbo Frames" setting1575 * up the frame size to 9.6 KB does not affect the performance on standard1576 * frames. It is clear from the application note that1577 * "9.6 kilobytes" == 9600 bytes.1578 */1579static int vsc73xx_get_max_mtu(struct dsa_switch *ds, int port)1580{1581 return 9600 - ETH_HLEN - ETH_FCS_LEN;1582}1583 1584static void vsc73xx_phylink_get_caps(struct dsa_switch *dsa, int port,1585 struct phylink_config *config)1586{1587 unsigned long *interfaces = config->supported_interfaces;1588 1589 if (port == 5)1590 return;1591 1592 if (port == CPU_PORT) {1593 __set_bit(PHY_INTERFACE_MODE_MII, interfaces);1594 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);1595 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);1596 __set_bit(PHY_INTERFACE_MODE_RGMII, interfaces);1597 }1598 1599 if (port <= 4) {1600 /* Internal PHYs */1601 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces);1602 /* phylib default */1603 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces);1604 }1605 1606 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000;1607}1608 1609static int1610vsc73xx_port_vlan_filtering(struct dsa_switch *ds, int port,1611 bool vlan_filtering, struct netlink_ext_ack *extack)1612{1613 struct vsc73xx *vsc = ds->priv;1614 1615 /* The commit to hardware processed below is required because vsc73xx1616 * is using tag_8021q. When vlan_filtering is disabled, tag_8021q uses1617 * pvid/untagged vlans for port recognition. The values configured for1618 * vlans and pvid/untagged states are stored in portinfo structure.1619 * When vlan_filtering is enabled, we need to restore pvid/untagged from1620 * portinfo structure. Analogous routine is processed when1621 * vlan_filtering is disabled, but values used for tag_8021q are1622 * restored.1623 */1624 1625 return vsc73xx_vlan_commit_settings(vsc, port);1626}1627 1628static int vsc73xx_port_vlan_add(struct dsa_switch *ds, int port,1629 const struct switchdev_obj_port_vlan *vlan,1630 struct netlink_ext_ack *extack)1631{1632 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;1633 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;1634 struct dsa_port *dp = dsa_to_port(ds, port);1635 struct vsc73xx_bridge_vlan *vsc73xx_vlan;1636 struct vsc73xx_vlan_summary summary;1637 struct vsc73xx_portinfo *portinfo;1638 struct vsc73xx *vsc = ds->priv;1639 bool commit_to_hardware;1640 int ret = 0;1641 1642 /* Be sure to deny alterations to the configuration done by tag_8021q.1643 */1644 if (vid_is_dsa_8021q(vlan->vid)) {1645 NL_SET_ERR_MSG_MOD(extack,1646 "Range 3072-4095 reserved for dsa_8021q operation");1647 return -EBUSY;1648 }1649 1650 /* The processed vlan->vid is excluded from the search because the VLAN1651 * can be re-added with a different set of flags, so it's easiest to1652 * ignore its old flags from the VLAN database software copy.1653 */1654 vsc73xx_bridge_vlan_summary(vsc, port, &summary, vlan->vid);1655 1656 /* VSC73XX allows only three untagged states: none, one or all */1657 if ((untagged && summary.num_tagged > 0 && summary.num_untagged > 0) ||1658 (!untagged && summary.num_untagged > 1)) {1659 NL_SET_ERR_MSG_MOD(extack,1660 "Port can have only none, one or all untagged vlan");1661 return -EBUSY;1662 }1663 1664 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid);1665 1666 if (!vsc73xx_vlan) {1667 vsc73xx_vlan = kzalloc(sizeof(*vsc73xx_vlan), GFP_KERNEL);1668 if (!vsc73xx_vlan)1669 return -ENOMEM;1670 1671 vsc73xx_vlan->vid = vlan->vid;1672 1673 list_add_tail(&vsc73xx_vlan->list, &vsc->vlans);1674 }1675 1676 vsc73xx_vlan->portmask |= BIT(port);1677 1678 /* CPU port must be always tagged because source port identification is1679 * based on tag_8021q.1680 */1681 if (port == CPU_PORT)1682 goto update_vlan_table;1683 1684 if (untagged)1685 vsc73xx_vlan->untagged |= BIT(port);1686 else1687 vsc73xx_vlan->untagged &= ~BIT(port);1688 1689 portinfo = &vsc->portinfo[port];1690 1691 if (pvid) {1692 portinfo->pvid_vlan_filtering_configured = true;1693 portinfo->pvid_vlan_filtering = vlan->vid;1694 } else if (portinfo->pvid_vlan_filtering_configured &&1695 portinfo->pvid_vlan_filtering == vlan->vid) {1696 portinfo->pvid_vlan_filtering_configured = false;1697 }1698 1699 commit_to_hardware = !vsc73xx_tag_8021q_active(dp);1700 if (commit_to_hardware) {1701 ret = vsc73xx_vlan_commit_settings(vsc, port);1702 if (ret)1703 goto err;1704 }1705 1706update_vlan_table:1707 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, true);1708 if (!ret)1709 return 0;1710err:1711 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port);1712 return ret;1713}1714 1715static int vsc73xx_port_vlan_del(struct dsa_switch *ds, int port,1716 const struct switchdev_obj_port_vlan *vlan)1717{1718 struct vsc73xx_bridge_vlan *vsc73xx_vlan;1719 struct vsc73xx_portinfo *portinfo;1720 struct vsc73xx *vsc = ds->priv;1721 bool commit_to_hardware;1722 int ret;1723 1724 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, false);1725 if (ret)1726 return ret;1727 1728 portinfo = &vsc->portinfo[port];1729 1730 if (portinfo->pvid_vlan_filtering_configured &&1731 portinfo->pvid_vlan_filtering == vlan->vid)1732 portinfo->pvid_vlan_filtering_configured = false;1733 1734 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid);1735 1736 if (vsc73xx_vlan)1737 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port);1738 1739 commit_to_hardware = !vsc73xx_tag_8021q_active(dsa_to_port(ds, port));1740 1741 if (commit_to_hardware)1742 return vsc73xx_vlan_commit_settings(vsc, port);1743 1744 return 0;1745}1746 1747static int vsc73xx_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,1748 u16 flags)1749{1750 bool pvid = flags & BRIDGE_VLAN_INFO_PVID;1751 struct vsc73xx_portinfo *portinfo;1752 struct vsc73xx *vsc = ds->priv;1753 bool commit_to_hardware;1754 int ret;1755 1756 portinfo = &vsc->portinfo[port];1757 1758 if (pvid) {1759 portinfo->pvid_tag_8021q_configured = true;1760 portinfo->pvid_tag_8021q = vid;1761 }1762 1763 commit_to_hardware = vsc73xx_tag_8021q_active(dsa_to_port(ds, port));1764 if (commit_to_hardware) {1765 ret = vsc73xx_vlan_commit_settings(vsc, port);1766 if (ret)1767 return ret;1768 }1769 1770 return vsc73xx_update_vlan_table(vsc, port, vid, true);1771}1772 1773static int vsc73xx_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)1774{1775 struct vsc73xx_portinfo *portinfo;1776 struct vsc73xx *vsc = ds->priv;1777 1778 portinfo = &vsc->portinfo[port];1779 1780 if (portinfo->pvid_tag_8021q_configured &&1781 portinfo->pvid_tag_8021q == vid) {1782 struct dsa_port *dp = dsa_to_port(ds, port);1783 bool commit_to_hardware;1784 int err;1785 1786 portinfo->pvid_tag_8021q_configured = false;1787 1788 commit_to_hardware = vsc73xx_tag_8021q_active(dp);1789 if (commit_to_hardware) {1790 err = vsc73xx_vlan_commit_settings(vsc, port);1791 if (err)1792 return err;1793 }1794 }1795 1796 return vsc73xx_update_vlan_table(vsc, port, vid, false);1797}1798 1799static int vsc73xx_port_pre_bridge_flags(struct dsa_switch *ds, int port,1800 struct switchdev_brport_flags flags,1801 struct netlink_ext_ack *extack)1802{1803 if (flags.mask & ~BR_LEARNING)1804 return -EINVAL;1805 1806 return 0;1807}1808 1809static int vsc73xx_port_bridge_flags(struct dsa_switch *ds, int port,1810 struct switchdev_brport_flags flags,1811 struct netlink_ext_ack *extack)1812{1813 if (flags.mask & BR_LEARNING) {1814 u32 val = flags.val & BR_LEARNING ? BIT(port) : 0;1815 struct vsc73xx *vsc = ds->priv;1816 1817 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,1818 VSC73XX_LEARNMASK, BIT(port), val);1819 }1820 1821 return 0;1822}1823 1824static void vsc73xx_refresh_fwd_map(struct dsa_switch *ds, int port, u8 state)1825{1826 struct dsa_port *other_dp, *dp = dsa_to_port(ds, port);1827 struct vsc73xx *vsc = ds->priv;1828 u16 mask;1829 1830 if (state != BR_STATE_FORWARDING) {1831 /* Ports that aren't in the forwarding state must not1832 * forward packets anywhere.1833 */1834 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,1835 VSC73XX_SRCMASKS + port,1836 VSC73XX_SRCMASKS_PORTS_MASK, 0);1837 1838 dsa_switch_for_each_available_port(other_dp, ds) {1839 if (other_dp == dp)1840 continue;1841 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,1842 VSC73XX_SRCMASKS + other_dp->index,1843 BIT(port), 0);1844 }1845 1846 return;1847 }1848 1849 /* Forwarding ports must forward to the CPU and to other ports1850 * in the same bridge1851 */1852 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,1853 VSC73XX_SRCMASKS + CPU_PORT, BIT(port), BIT(port));1854 1855 mask = BIT(CPU_PORT);1856 1857 dsa_switch_for_each_user_port(other_dp, ds) {1858 int other_port = other_dp->index;1859 1860 if (port == other_port || !dsa_port_bridge_same(dp, other_dp) ||1861 other_dp->stp_state != BR_STATE_FORWARDING)1862 continue;1863 1864 mask |= BIT(other_port);1865 1866 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,1867 VSC73XX_SRCMASKS + other_port,1868 BIT(port), BIT(port));1869 }1870 1871 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,1872 VSC73XX_SRCMASKS + port,1873 VSC73XX_SRCMASKS_PORTS_MASK, mask);1874}1875 1876/* FIXME: STP frames aren't forwarded at this moment. BPDU frames are1877 * forwarded only from and to PI/SI interface. For more info see chapter1878 * 2.7.1 (CPU Forwarding) in datasheet.1879 * This function is required for tag_8021q operations.1880 */1881static void vsc73xx_port_stp_state_set(struct dsa_switch *ds, int port,1882 u8 state)1883{1884 struct dsa_port *dp = dsa_to_port(ds, port);1885 struct vsc73xx *vsc = ds->priv;1886 u32 val = 0;1887 1888 if (state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING)1889 val = dp->learning ? BIT(port) : 0;1890 1891 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,1892 VSC73XX_LEARNMASK, BIT(port), val);1893 1894 val = (state == BR_STATE_BLOCKING || state == BR_STATE_DISABLED) ?1895 0 : BIT(port);1896 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,1897 VSC73XX_RECVMASK, BIT(port), val);1898 1899 /* CPU Port should always forward packets when user ports are forwarding1900 * so let's configure it from other ports only.1901 */1902 if (port != CPU_PORT)1903 vsc73xx_refresh_fwd_map(ds, port, state);1904}1905 1906static u16 vsc73xx_calc_hash(const unsigned char *addr, u16 vid)1907{1908 /* VID 5-0, MAC 47-44 */1909 u16 hash = FIELD_PREP(VSC73XX_HASH0_VID_TO_MASK,1910 FIELD_GET(VSC73XX_HASH0_VID_FROM_MASK, vid)) |1911 FIELD_PREP(VSC73XX_HASH0_MAC0_TO_MASK,1912 FIELD_GET(VSC73XX_HASH0_MAC0_FROM_MASK, addr[0]));1913 /* MAC 43-33 */1914 hash ^= FIELD_PREP(VSC73XX_HASH1_MAC0_TO_MASK,1915 FIELD_GET(VSC73XX_HASH1_MAC0_FROM_MASK, addr[0])) |1916 FIELD_PREP(VSC73XX_HASH1_MAC1_TO_MASK,1917 FIELD_GET(VSC73XX_HASH1_MAC1_FROM_MASK, addr[1]));1918 /* MAC 32-22 */1919 hash ^= FIELD_PREP(VSC73XX_HASH2_MAC1_TO_MASK,1920 FIELD_GET(VSC73XX_HASH2_MAC1_FROM_MASK, addr[1])) |1921 FIELD_PREP(VSC73XX_HASH2_MAC2_TO_MASK,1922 FIELD_GET(VSC73XX_HASH2_MAC2_FROM_MASK, addr[2])) |1923 FIELD_PREP(VSC73XX_HASH2_MAC3_TO_MASK,1924 FIELD_GET(VSC73XX_HASH2_MAC3_FROM_MASK, addr[3]));1925 /* MAC 21-11 */1926 hash ^= FIELD_PREP(VSC73XX_HASH3_MAC3_TO_MASK,1927 FIELD_GET(VSC73XX_HASH3_MAC3_FROM_MASK, addr[3])) |1928 FIELD_PREP(VSC73XX_HASH3_MAC4_TO_MASK,1929 FIELD_GET(VSC73XX_HASH3_MAC4_FROM_MASK, addr[4]));1930 /* MAC 10-0 */1931 hash ^= FIELD_PREP(VSC73XX_HASH4_MAC4_TO_MASK,1932 FIELD_GET(VSC73XX_HASH4_MAC4_FROM_MASK, addr[4])) |1933 addr[5];1934 1935 return hash;1936}1937 1938static int1939vsc73xx_port_wait_for_mac_table_cmd(struct vsc73xx *vsc)1940{1941 int ret, err;1942 u32 val;1943 1944 ret = read_poll_timeout(vsc73xx_read, err,1945 err < 0 ||1946 ((val & VSC73XX_MACACCESS_CMD_MASK) ==1947 VSC73XX_MACACCESS_CMD_IDLE),1948 VSC73XX_POLL_SLEEP_US, VSC73XX_POLL_TIMEOUT_US,1949 false, vsc, VSC73XX_BLOCK_ANALYZER,1950 0, VSC73XX_MACACCESS, &val);1951 if (ret)1952 return ret;1953 return err;1954}1955 1956static int vsc73xx_port_read_mac_table_row(struct vsc73xx *vsc, u16 index,1957 struct vsc73xx_fdb *fdb)1958{1959 int ret, i;1960 u32 val;1961 1962 if (!fdb)1963 return -EINVAL;1964 if (index >= VSC73XX_NUM_FDB_ROWS)1965 return -EINVAL;1966 1967 for (i = 0; i < VSC73XX_NUM_BUCKETS; i++) {1968 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0,1969 VSC73XX_MACTINDX,1970 (i ? 0 : VSC73XX_MACTINDX_SHADOW) |1971 FIELD_PREP(VSC73XX_MACTINDX_BUCKET_MSK, i) |1972 index);1973 if (ret)1974 return ret;1975 1976 ret = vsc73xx_port_wait_for_mac_table_cmd(vsc);1977 if (ret)1978 return ret;1979 1980 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,1981 VSC73XX_MACACCESS,1982 VSC73XX_MACACCESS_CMD_MASK,1983 VSC73XX_MACACCESS_CMD_READ_ENTRY);1984 if (ret)1985 return ret;1986 1987 ret = vsc73xx_port_wait_for_mac_table_cmd(vsc);1988 if (ret)1989 return ret;1990 1991 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0,1992 VSC73XX_MACACCESS, &val);1993 if (ret)1994 return ret;1995 1996 fdb[i].valid = FIELD_GET(VSC73XX_MACACCESS_VALID, val);1997 if (!fdb[i].valid)1998 continue;1999 2000 fdb[i].port = FIELD_GET(VSC73XX_MACACCESS_DEST_IDX_MASK, val);2001 2002 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0,2003 VSC73XX_MACHDATA, &val);2004 if (ret)2005 return ret;2006 2007 fdb[i].vid = FIELD_GET(VSC73XX_MACHDATA_VID, val);2008 fdb[i].mac[0] = FIELD_GET(VSC73XX_MACHDATA_MAC0, val);2009 fdb[i].mac[1] = FIELD_GET(VSC73XX_MACHDATA_MAC1, val);2010 2011 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0,2012 VSC73XX_MACLDATA, &val);2013 if (ret)2014 return ret;2015 2016 fdb[i].mac[2] = FIELD_GET(VSC73XX_MACLDATA_MAC2, val);2017 fdb[i].mac[3] = FIELD_GET(VSC73XX_MACLDATA_MAC3, val);2018 fdb[i].mac[4] = FIELD_GET(VSC73XX_MACLDATA_MAC4, val);2019 fdb[i].mac[5] = FIELD_GET(VSC73XX_MACLDATA_MAC5, val);2020 }2021 2022 return ret;2023}2024 2025static int2026vsc73xx_fdb_operation(struct vsc73xx *vsc, const unsigned char *addr, u16 vid,2027 u16 hash, u16 cmd_mask, u16 cmd_val)2028{2029 int ret;2030 u32 val;2031 2032 val = FIELD_PREP(VSC73XX_MACHDATA_VID, vid) |2033 FIELD_PREP(VSC73XX_MACHDATA_MAC0, addr[0]) |2034 FIELD_PREP(VSC73XX_MACHDATA_MAC1, addr[1]);2035 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_MACHDATA,2036 val);2037 if (ret)2038 return ret;2039 2040 val = FIELD_PREP(VSC73XX_MACLDATA_MAC2, addr[2]) |2041 FIELD_PREP(VSC73XX_MACLDATA_MAC3, addr[3]) |2042 FIELD_PREP(VSC73XX_MACLDATA_MAC4, addr[4]) |2043 FIELD_PREP(VSC73XX_MACLDATA_MAC5, addr[5]);2044 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_MACLDATA,2045 val);2046 if (ret)2047 return ret;2048 2049 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_MACTINDX,2050 hash);2051 if (ret)2052 return ret;2053 2054 ret = vsc73xx_port_wait_for_mac_table_cmd(vsc);2055 if (ret)2056 return ret;2057 2058 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,2059 VSC73XX_MACACCESS, cmd_mask, cmd_val);2060 if (ret)2061 return ret;2062 2063 return vsc73xx_port_wait_for_mac_table_cmd(vsc);2064}2065 2066static int vsc73xx_fdb_del_entry(struct vsc73xx *vsc, int port,2067 const unsigned char *addr, u16 vid)2068{2069 struct vsc73xx_fdb fdb[VSC73XX_NUM_BUCKETS];2070 u16 hash = vsc73xx_calc_hash(addr, vid);2071 int bucket, ret;2072 2073 mutex_lock(&vsc->fdb_lock);2074 2075 ret = vsc73xx_port_read_mac_table_row(vsc, hash, fdb);2076 if (ret)2077 goto err;2078 2079 for (bucket = 0; bucket < VSC73XX_NUM_BUCKETS; bucket++) {2080 if (fdb[bucket].valid && fdb[bucket].port == port &&2081 ether_addr_equal(addr, fdb[bucket].mac))2082 break;2083 }2084 2085 if (bucket == VSC73XX_NUM_BUCKETS) {2086 /* Can't find MAC in MAC table */2087 ret = -ENODATA;2088 goto err;2089 }2090 2091 ret = vsc73xx_fdb_operation(vsc, addr, vid, hash,2092 VSC73XX_MACACCESS_CMD_MASK,2093 VSC73XX_MACACCESS_CMD_FORGET);2094err:2095 mutex_unlock(&vsc->fdb_lock);2096 return ret;2097}2098 2099static int vsc73xx_fdb_add_entry(struct vsc73xx *vsc, int port,2100 const unsigned char *addr, u16 vid)2101{2102 struct vsc73xx_fdb fdb[VSC73XX_NUM_BUCKETS];2103 u16 hash = vsc73xx_calc_hash(addr, vid);2104 int bucket, ret;2105 u32 val;2106 2107 mutex_lock(&vsc->fdb_lock);2108 2109 ret = vsc73xx_port_read_mac_table_row(vsc, hash, fdb);2110 if (ret)2111 goto err;2112 2113 for (bucket = 0; bucket < VSC73XX_NUM_BUCKETS; bucket++) {2114 if (!fdb[bucket].valid)2115 break;2116 }2117 2118 if (bucket == VSC73XX_NUM_BUCKETS) {2119 /* Bucket is full */2120 ret = -EOVERFLOW;2121 goto err;2122 }2123 2124 val = VSC73XX_MACACCESS_VALID | VSC73XX_MACACCESS_LOCKED |2125 FIELD_PREP(VSC73XX_MACACCESS_DEST_IDX_MASK, port) |2126 VSC73XX_MACACCESS_CMD_LEARN;2127 ret = vsc73xx_fdb_operation(vsc, addr, vid, hash,2128 VSC73XX_MACACCESS_VALID |2129 VSC73XX_MACACCESS_LOCKED |2130 VSC73XX_MACACCESS_DEST_IDX_MASK |2131 VSC73XX_MACACCESS_CMD_MASK, val);2132err:2133 mutex_unlock(&vsc->fdb_lock);2134 return ret;2135}2136 2137static int vsc73xx_fdb_add(struct dsa_switch *ds, int port,2138 const unsigned char *addr, u16 vid, struct dsa_db db)2139{2140 struct vsc73xx *vsc = ds->priv;2141 2142 if (!vid) {2143 switch (db.type) {2144 case DSA_DB_PORT:2145 vid = dsa_tag_8021q_standalone_vid(db.dp);2146 break;2147 case DSA_DB_BRIDGE:2148 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);2149 break;2150 default:2151 return -EOPNOTSUPP;2152 }2153 }2154 2155 return vsc73xx_fdb_add_entry(vsc, port, addr, vid);2156}2157 2158static int vsc73xx_fdb_del(struct dsa_switch *ds, int port,2159 const unsigned char *addr, u16 vid, struct dsa_db db)2160{2161 struct vsc73xx *vsc = ds->priv;2162 2163 if (!vid) {2164 switch (db.type) {2165 case DSA_DB_PORT:2166 vid = dsa_tag_8021q_standalone_vid(db.dp);2167 break;2168 case DSA_DB_BRIDGE:2169 vid = dsa_tag_8021q_bridge_vid(db.bridge.num);2170 break;2171 default:2172 return -EOPNOTSUPP;2173 }2174 }2175 2176 return vsc73xx_fdb_del_entry(vsc, port, addr, vid);2177}2178 2179static int vsc73xx_port_fdb_dump(struct dsa_switch *ds,2180 int port, dsa_fdb_dump_cb_t *cb, void *data)2181{2182 struct vsc73xx_fdb fdb[VSC73XX_NUM_BUCKETS];2183 struct vsc73xx *vsc = ds->priv;2184 u16 i, bucket;2185 int err = 0;2186 2187 mutex_lock(&vsc->fdb_lock);2188 2189 for (i = 0; i < VSC73XX_NUM_FDB_ROWS; i++) {2190 err = vsc73xx_port_read_mac_table_row(vsc, i, fdb);2191 if (err)2192 goto unlock;2193 2194 for (bucket = 0; bucket < VSC73XX_NUM_BUCKETS; bucket++) {2195 if (!fdb[bucket].valid || fdb[bucket].port != port)2196 continue;2197 2198 /* We need to hide dsa_8021q VLANs from the user */2199 if (vid_is_dsa_8021q(fdb[bucket].vid))2200 fdb[bucket].vid = 0;2201 2202 err = cb(fdb[bucket].mac, fdb[bucket].vid, false, data);2203 if (err)2204 goto unlock;2205 }2206 }2207unlock:2208 mutex_unlock(&vsc->fdb_lock);2209 return err;2210}2211 2212static const struct phylink_mac_ops vsc73xx_phylink_mac_ops = {2213 .mac_config = vsc73xx_mac_config,2214 .mac_link_down = vsc73xx_mac_link_down,2215 .mac_link_up = vsc73xx_mac_link_up,2216};2217 2218static const struct dsa_switch_ops vsc73xx_ds_ops = {2219 .get_tag_protocol = vsc73xx_get_tag_protocol,2220 .setup = vsc73xx_setup,2221 .teardown = vsc73xx_teardown,2222 .phy_read = vsc73xx_phy_read,2223 .phy_write = vsc73xx_phy_write,2224 .get_strings = vsc73xx_get_strings,2225 .get_ethtool_stats = vsc73xx_get_ethtool_stats,2226 .get_sset_count = vsc73xx_get_sset_count,2227 .port_enable = vsc73xx_port_enable,2228 .port_disable = vsc73xx_port_disable,2229 .port_pre_bridge_flags = vsc73xx_port_pre_bridge_flags,2230 .port_bridge_flags = vsc73xx_port_bridge_flags,2231 .port_bridge_join = dsa_tag_8021q_bridge_join,2232 .port_bridge_leave = dsa_tag_8021q_bridge_leave,2233 .port_change_mtu = vsc73xx_change_mtu,2234 .port_fdb_add = vsc73xx_fdb_add,2235 .port_fdb_del = vsc73xx_fdb_del,2236 .port_fdb_dump = vsc73xx_port_fdb_dump,2237 .port_max_mtu = vsc73xx_get_max_mtu,2238 .port_stp_state_set = vsc73xx_port_stp_state_set,2239 .port_vlan_filtering = vsc73xx_port_vlan_filtering,2240 .port_vlan_add = vsc73xx_port_vlan_add,2241 .port_vlan_del = vsc73xx_port_vlan_del,2242 .phylink_get_caps = vsc73xx_phylink_get_caps,2243 .tag_8021q_vlan_add = vsc73xx_tag_8021q_vlan_add,2244 .tag_8021q_vlan_del = vsc73xx_tag_8021q_vlan_del,2245};2246 2247static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset)2248{2249 struct vsc73xx *vsc = gpiochip_get_data(chip);2250 u32 val;2251 int ret;2252 2253 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,2254 VSC73XX_GPIO, &val);2255 if (ret)2256 return ret;2257 2258 return !!(val & BIT(offset));2259}2260 2261static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset,2262 int val)2263{2264 struct vsc73xx *vsc = gpiochip_get_data(chip);2265 u32 tmp = val ? BIT(offset) : 0;2266 2267 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0,2268 VSC73XX_GPIO, BIT(offset), tmp);2269}2270 2271static int vsc73xx_gpio_direction_output(struct gpio_chip *chip,2272 unsigned int offset, int val)2273{2274 struct vsc73xx *vsc = gpiochip_get_data(chip);2275 u32 tmp = val ? BIT(offset) : 0;2276 2277 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0,2278 VSC73XX_GPIO, BIT(offset + 4) | BIT(offset),2279 BIT(offset + 4) | tmp);2280}2281 2282static int vsc73xx_gpio_direction_input(struct gpio_chip *chip,2283 unsigned int offset)2284{2285 struct vsc73xx *vsc = gpiochip_get_data(chip);2286 2287 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0,2288 VSC73XX_GPIO, BIT(offset + 4),2289 0);2290}2291 2292static int vsc73xx_gpio_get_direction(struct gpio_chip *chip,2293 unsigned int offset)2294{2295 struct vsc73xx *vsc = gpiochip_get_data(chip);2296 u32 val;2297 int ret;2298 2299 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,2300 VSC73XX_GPIO, &val);2301 if (ret)2302 return ret;2303 2304 return !(val & BIT(offset + 4));2305}2306 2307static int vsc73xx_gpio_probe(struct vsc73xx *vsc)2308{2309 int ret;2310 2311 vsc->gc.label = devm_kasprintf(vsc->dev, GFP_KERNEL, "VSC%04x",2312 vsc->chipid);2313 if (!vsc->gc.label)2314 return -ENOMEM;2315 vsc->gc.ngpio = 4;2316 vsc->gc.owner = THIS_MODULE;2317 vsc->gc.parent = vsc->dev;2318 vsc->gc.base = -1;2319 vsc->gc.get = vsc73xx_gpio_get;2320 vsc->gc.set = vsc73xx_gpio_set;2321 vsc->gc.direction_input = vsc73xx_gpio_direction_input;2322 vsc->gc.direction_output = vsc73xx_gpio_direction_output;2323 vsc->gc.get_direction = vsc73xx_gpio_get_direction;2324 vsc->gc.can_sleep = true;2325 ret = devm_gpiochip_add_data(vsc->dev, &vsc->gc, vsc);2326 if (ret) {2327 dev_err(vsc->dev, "unable to register GPIO chip\n");2328 return ret;2329 }2330 return 0;2331}2332 2333int vsc73xx_probe(struct vsc73xx *vsc)2334{2335 struct device *dev = vsc->dev;2336 int ret;2337 2338 /* Release reset, if any */2339 vsc->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);2340 if (IS_ERR(vsc->reset)) {2341 dev_err(dev, "failed to get RESET GPIO\n");2342 return PTR_ERR(vsc->reset);2343 }2344 if (vsc->reset)2345 /* Wait 20ms according to datasheet table 245 */2346 msleep(20);2347 2348 ret = vsc73xx_detect(vsc);2349 if (ret == -EAGAIN) {2350 dev_err(vsc->dev,2351 "Chip seems to be out of control. Assert reset and try again.\n");2352 gpiod_set_value_cansleep(vsc->reset, 1);2353 /* Reset pulse should be 20ns minimum, according to datasheet2354 * table 245, so 10us should be fine2355 */2356 usleep_range(10, 100);2357 gpiod_set_value_cansleep(vsc->reset, 0);2358 /* Wait 20ms according to datasheet table 245 */2359 msleep(20);2360 ret = vsc73xx_detect(vsc);2361 }2362 if (ret) {2363 dev_err(dev, "no chip found (%d)\n", ret);2364 return -ENODEV;2365 }2366 2367 mutex_init(&vsc->fdb_lock);2368 2369 eth_random_addr(vsc->addr);2370 dev_info(vsc->dev,2371 "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n",2372 vsc->addr[0], vsc->addr[1], vsc->addr[2],2373 vsc->addr[3], vsc->addr[4], vsc->addr[5]);2374 2375 vsc->ds = devm_kzalloc(dev, sizeof(*vsc->ds), GFP_KERNEL);2376 if (!vsc->ds)2377 return -ENOMEM;2378 2379 vsc->ds->dev = dev;2380 vsc->ds->num_ports = VSC73XX_MAX_NUM_PORTS;2381 vsc->ds->priv = vsc;2382 2383 vsc->ds->ops = &vsc73xx_ds_ops;2384 vsc->ds->phylink_mac_ops = &vsc73xx_phylink_mac_ops;2385 ret = dsa_register_switch(vsc->ds);2386 if (ret) {2387 dev_err(dev, "unable to register switch (%d)\n", ret);2388 return ret;2389 }2390 2391 ret = vsc73xx_gpio_probe(vsc);2392 if (ret) {2393 dsa_unregister_switch(vsc->ds);2394 return ret;2395 }2396 2397 return 0;2398}2399EXPORT_SYMBOL(vsc73xx_probe);2400 2401void vsc73xx_remove(struct vsc73xx *vsc)2402{2403 dsa_unregister_switch(vsc->ds);2404 gpiod_set_value(vsc->reset, 1);2405}2406EXPORT_SYMBOL(vsc73xx_remove);2407 2408void vsc73xx_shutdown(struct vsc73xx *vsc)2409{2410 dsa_switch_shutdown(vsc->ds);2411}2412EXPORT_SYMBOL(vsc73xx_shutdown);2413 2414MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");2415MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver");2416MODULE_LICENSE("GPL v2");2417