281 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Actions Semi Owl SoCs Ethernet MAC driver4 *5 * Copyright (c) 2012 Actions Semi Inc.6 * Copyright (c) 2021 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>7 */8 9#ifndef __OWL_EMAC_H__10#define __OWL_EMAC_H__11 12#define OWL_EMAC_DRVNAME "owl-emac"13 14#define OWL_EMAC_POLL_DELAY_USEC 515#define OWL_EMAC_MDIO_POLL_TIMEOUT_USEC 100016#define OWL_EMAC_RESET_POLL_TIMEOUT_USEC 200017#define OWL_EMAC_TX_TIMEOUT (2 * HZ)18 19#define OWL_EMAC_MTU_MIN ETH_MIN_MTU20#define OWL_EMAC_MTU_MAX ETH_DATA_LEN21#define OWL_EMAC_RX_FRAME_MAX_LEN (ETH_FRAME_LEN + ETH_FCS_LEN)22#define OWL_EMAC_SKB_ALIGN 423#define OWL_EMAC_SKB_RESERVE 1824 25#define OWL_EMAC_MAX_MULTICAST_ADDRS 1426#define OWL_EMAC_SETUP_FRAME_LEN 19227 28#define OWL_EMAC_RX_RING_SIZE 6429#define OWL_EMAC_TX_RING_SIZE 3230 31/* Bus mode register */32#define OWL_EMAC_REG_MAC_CSR0 0x000033#define OWL_EMAC_BIT_MAC_CSR0_SWR BIT(0) /* Software reset */34 35/* Transmit/receive poll demand registers */36#define OWL_EMAC_REG_MAC_CSR1 0x000837#define OWL_EMAC_VAL_MAC_CSR1_TPD 0x0138#define OWL_EMAC_REG_MAC_CSR2 0x001039#define OWL_EMAC_VAL_MAC_CSR2_RPD 0x0140 41/* Receive/transmit descriptor list base address registers */42#define OWL_EMAC_REG_MAC_CSR3 0x001843#define OWL_EMAC_REG_MAC_CSR4 0x002044 45/* Status register */46#define OWL_EMAC_REG_MAC_CSR5 0x002847#define OWL_EMAC_MSK_MAC_CSR5_TS GENMASK(22, 20) /* Transmit process state */48#define OWL_EMAC_OFF_MAC_CSR5_TS 2049#define OWL_EMAC_VAL_MAC_CSR5_TS_DATA 0x03 /* Transferring data HOST -> FIFO */50#define OWL_EMAC_VAL_MAC_CSR5_TS_CDES 0x07 /* Closing transmit descriptor */51#define OWL_EMAC_MSK_MAC_CSR5_RS GENMASK(19, 17) /* Receive process state */52#define OWL_EMAC_OFF_MAC_CSR5_RS 1753#define OWL_EMAC_VAL_MAC_CSR5_RS_FDES 0x01 /* Fetching receive descriptor */54#define OWL_EMAC_VAL_MAC_CSR5_RS_CDES 0x05 /* Closing receive descriptor */55#define OWL_EMAC_VAL_MAC_CSR5_RS_DATA 0x07 /* Transferring data FIFO -> HOST */56#define OWL_EMAC_BIT_MAC_CSR5_NIS BIT(16) /* Normal interrupt summary */57#define OWL_EMAC_BIT_MAC_CSR5_AIS BIT(15) /* Abnormal interrupt summary */58#define OWL_EMAC_BIT_MAC_CSR5_ERI BIT(14) /* Early receive interrupt */59#define OWL_EMAC_BIT_MAC_CSR5_GTE BIT(11) /* General-purpose timer expiration */60#define OWL_EMAC_BIT_MAC_CSR5_ETI BIT(10) /* Early transmit interrupt */61#define OWL_EMAC_BIT_MAC_CSR5_RPS BIT(8) /* Receive process stopped */62#define OWL_EMAC_BIT_MAC_CSR5_RU BIT(7) /* Receive buffer unavailable */63#define OWL_EMAC_BIT_MAC_CSR5_RI BIT(6) /* Receive interrupt */64#define OWL_EMAC_BIT_MAC_CSR5_UNF BIT(5) /* Transmit underflow */65#define OWL_EMAC_BIT_MAC_CSR5_LCIS BIT(4) /* Link change status */66#define OWL_EMAC_BIT_MAC_CSR5_LCIQ BIT(3) /* Link change interrupt */67#define OWL_EMAC_BIT_MAC_CSR5_TU BIT(2) /* Transmit buffer unavailable */68#define OWL_EMAC_BIT_MAC_CSR5_TPS BIT(1) /* Transmit process stopped */69#define OWL_EMAC_BIT_MAC_CSR5_TI BIT(0) /* Transmit interrupt */70 71/* Operation mode register */72#define OWL_EMAC_REG_MAC_CSR6 0x003073#define OWL_EMAC_BIT_MAC_CSR6_RA BIT(30) /* Receive all */74#define OWL_EMAC_BIT_MAC_CSR6_TTM BIT(22) /* Transmit threshold mode */75#define OWL_EMAC_BIT_MAC_CSR6_SF BIT(21) /* Store and forward */76#define OWL_EMAC_MSK_MAC_CSR6_SPEED GENMASK(17, 16) /* Eth speed selection */77#define OWL_EMAC_OFF_MAC_CSR6_SPEED 1678#define OWL_EMAC_VAL_MAC_CSR6_SPEED_100M 0x0079#define OWL_EMAC_VAL_MAC_CSR6_SPEED_10M 0x0280#define OWL_EMAC_BIT_MAC_CSR6_ST BIT(13) /* Start/stop transmit command */81#define OWL_EMAC_BIT_MAC_CSR6_LP BIT(10) /* Loopback mode */82#define OWL_EMAC_BIT_MAC_CSR6_FD BIT(9) /* Full duplex mode */83#define OWL_EMAC_BIT_MAC_CSR6_PM BIT(7) /* Pass all multicast */84#define OWL_EMAC_BIT_MAC_CSR6_PR BIT(6) /* Promiscuous mode */85#define OWL_EMAC_BIT_MAC_CSR6_IF BIT(4) /* Inverse filtering */86#define OWL_EMAC_BIT_MAC_CSR6_PB BIT(3) /* Pass bad frames */87#define OWL_EMAC_BIT_MAC_CSR6_HO BIT(2) /* Hash only filtering mode */88#define OWL_EMAC_BIT_MAC_CSR6_SR BIT(1) /* Start/stop receive command */89#define OWL_EMAC_BIT_MAC_CSR6_HP BIT(0) /* Hash/perfect receive filtering mode */90#define OWL_EMAC_MSK_MAC_CSR6_STSR (OWL_EMAC_BIT_MAC_CSR6_ST | \91 OWL_EMAC_BIT_MAC_CSR6_SR)92 93/* Interrupt enable register */94#define OWL_EMAC_REG_MAC_CSR7 0x003895#define OWL_EMAC_BIT_MAC_CSR7_NIE BIT(16) /* Normal interrupt summary enable */96#define OWL_EMAC_BIT_MAC_CSR7_AIE BIT(15) /* Abnormal interrupt summary enable */97#define OWL_EMAC_BIT_MAC_CSR7_ERE BIT(14) /* Early receive interrupt enable */98#define OWL_EMAC_BIT_MAC_CSR7_GTE BIT(11) /* General-purpose timer overflow */99#define OWL_EMAC_BIT_MAC_CSR7_ETE BIT(10) /* Early transmit interrupt enable */100#define OWL_EMAC_BIT_MAC_CSR7_RSE BIT(8) /* Receive stopped enable */101#define OWL_EMAC_BIT_MAC_CSR7_RUE BIT(7) /* Receive buffer unavailable enable */102#define OWL_EMAC_BIT_MAC_CSR7_RIE BIT(6) /* Receive interrupt enable */103#define OWL_EMAC_BIT_MAC_CSR7_UNE BIT(5) /* Underflow interrupt enable */104#define OWL_EMAC_BIT_MAC_CSR7_TUE BIT(2) /* Transmit buffer unavailable enable */105#define OWL_EMAC_BIT_MAC_CSR7_TSE BIT(1) /* Transmit stopped enable */106#define OWL_EMAC_BIT_MAC_CSR7_TIE BIT(0) /* Transmit interrupt enable */107#define OWL_EMAC_BIT_MAC_CSR7_ALL_NOT_TUE (OWL_EMAC_BIT_MAC_CSR7_ERE | \108 OWL_EMAC_BIT_MAC_CSR7_GTE | \109 OWL_EMAC_BIT_MAC_CSR7_ETE | \110 OWL_EMAC_BIT_MAC_CSR7_RSE | \111 OWL_EMAC_BIT_MAC_CSR7_RUE | \112 OWL_EMAC_BIT_MAC_CSR7_RIE | \113 OWL_EMAC_BIT_MAC_CSR7_UNE | \114 OWL_EMAC_BIT_MAC_CSR7_TSE | \115 OWL_EMAC_BIT_MAC_CSR7_TIE)116 117/* Missed frames and overflow counter register */118#define OWL_EMAC_REG_MAC_CSR8 0x0040119/* MII management and serial ROM register */120#define OWL_EMAC_REG_MAC_CSR9 0x0048121 122/* MII serial management register */123#define OWL_EMAC_REG_MAC_CSR10 0x0050124#define OWL_EMAC_BIT_MAC_CSR10_SB BIT(31) /* Start transfer or busy */125#define OWL_EMAC_MSK_MAC_CSR10_CLKDIV GENMASK(30, 28) /* Clock divider */126#define OWL_EMAC_OFF_MAC_CSR10_CLKDIV 28127#define OWL_EMAC_VAL_MAC_CSR10_CLKDIV_128 0x04128#define OWL_EMAC_VAL_MAC_CSR10_OPCODE_WR 0x01 /* Register write command */129#define OWL_EMAC_OFF_MAC_CSR10_OPCODE 26 /* Operation mode */130#define OWL_EMAC_VAL_MAC_CSR10_OPCODE_DCG 0x00 /* Disable clock generation */131#define OWL_EMAC_VAL_MAC_CSR10_OPCODE_WR 0x01 /* Register write command */132#define OWL_EMAC_VAL_MAC_CSR10_OPCODE_RD 0x02 /* Register read command */133#define OWL_EMAC_VAL_MAC_CSR10_OPCODE_CDS 0x03 /* Clock divider set */134#define OWL_EMAC_MSK_MAC_CSR10_PHYADD GENMASK(25, 21) /* Physical layer address */135#define OWL_EMAC_OFF_MAC_CSR10_PHYADD 21136#define OWL_EMAC_MSK_MAC_CSR10_REGADD GENMASK(20, 16) /* Register address */137#define OWL_EMAC_OFF_MAC_CSR10_REGADD 16138#define OWL_EMAC_MSK_MAC_CSR10_DATA GENMASK(15, 0) /* Register data */139 140/* General-purpose timer and interrupt mitigation control register */141#define OWL_EMAC_REG_MAC_CSR11 0x0058142#define OWL_EMAC_OFF_MAC_CSR11_TT 27 /* Transmit timer */143#define OWL_EMAC_OFF_MAC_CSR11_NTP 24 /* No. of transmit packets */144#define OWL_EMAC_OFF_MAC_CSR11_RT 20 /* Receive timer */145#define OWL_EMAC_OFF_MAC_CSR11_NRP 17 /* No. of receive packets */146 147/* MAC address low/high registers */148#define OWL_EMAC_REG_MAC_CSR16 0x0080149#define OWL_EMAC_REG_MAC_CSR17 0x0088150 151/* Pause time & cache thresholds register */152#define OWL_EMAC_REG_MAC_CSR18 0x0090153#define OWL_EMAC_OFF_MAC_CSR18_CPTL 24 /* Cache pause threshold level */154#define OWL_EMAC_OFF_MAC_CSR18_CRTL 16 /* Cache restart threshold level */155#define OWL_EMAC_OFF_MAC_CSR18_PQT 0 /* Flow control pause quanta time */156 157/* FIFO pause & restart threshold register */158#define OWL_EMAC_REG_MAC_CSR19 0x0098159#define OWL_EMAC_OFF_MAC_CSR19_FPTL 16 /* FIFO pause threshold level */160#define OWL_EMAC_OFF_MAC_CSR19_FRTL 0 /* FIFO restart threshold level */161 162/* Flow control setup & status register */163#define OWL_EMAC_REG_MAC_CSR20 0x00A0164#define OWL_EMAC_BIT_MAC_CSR20_FCE BIT(31) /* Flow Control Enable */165#define OWL_EMAC_BIT_MAC_CSR20_TUE BIT(30) /* Transmit Un-pause frames Enable */166#define OWL_EMAC_BIT_MAC_CSR20_TPE BIT(29) /* Transmit Pause frames Enable */167#define OWL_EMAC_BIT_MAC_CSR20_RPE BIT(28) /* Receive Pause frames Enable */168#define OWL_EMAC_BIT_MAC_CSR20_BPE BIT(27) /* Back pressure (half-duplex) Enable */169 170/* MII control register */171#define OWL_EMAC_REG_MAC_CTRL 0x00B0172#define OWL_EMAC_BIT_MAC_CTRL_RRSB BIT(8) /* RMII_REFCLK select bit */173#define OWL_EMAC_OFF_MAC_CTRL_SSDC 4 /* SMII SYNC delay cycle */174#define OWL_EMAC_BIT_MAC_CTRL_RCPS BIT(1) /* REF_CLK phase select */175#define OWL_EMAC_BIT_MAC_CTRL_RSIS BIT(0) /* RMII/SMII interface select */176 177/* Receive descriptor status field */178#define OWL_EMAC_BIT_RDES0_OWN BIT(31) /* Ownership bit */179#define OWL_EMAC_BIT_RDES0_FF BIT(30) /* Filtering fail */180#define OWL_EMAC_MSK_RDES0_FL GENMASK(29, 16) /* Frame length */181#define OWL_EMAC_OFF_RDES0_FL 16182#define OWL_EMAC_BIT_RDES0_ES BIT(15) /* Error summary */183#define OWL_EMAC_BIT_RDES0_DE BIT(14) /* Descriptor error */184#define OWL_EMAC_BIT_RDES0_RF BIT(11) /* Runt frame */185#define OWL_EMAC_BIT_RDES0_MF BIT(10) /* Multicast frame */186#define OWL_EMAC_BIT_RDES0_FS BIT(9) /* First descriptor */187#define OWL_EMAC_BIT_RDES0_LS BIT(8) /* Last descriptor */188#define OWL_EMAC_BIT_RDES0_TL BIT(7) /* Frame too long */189#define OWL_EMAC_BIT_RDES0_CS BIT(6) /* Collision seen */190#define OWL_EMAC_BIT_RDES0_FT BIT(5) /* Frame type */191#define OWL_EMAC_BIT_RDES0_RE BIT(3) /* Report on MII error */192#define OWL_EMAC_BIT_RDES0_DB BIT(2) /* Dribbling bit */193#define OWL_EMAC_BIT_RDES0_CE BIT(1) /* CRC error */194#define OWL_EMAC_BIT_RDES0_ZERO BIT(0) /* Legal frame length indicator */195 196/* Receive descriptor control and count field */197#define OWL_EMAC_BIT_RDES1_RER BIT(25) /* Receive end of ring */198#define OWL_EMAC_MSK_RDES1_RBS1 GENMASK(10, 0) /* Buffer 1 size */199 200/* Transmit descriptor status field */201#define OWL_EMAC_BIT_TDES0_OWN BIT(31) /* Ownership bit */202#define OWL_EMAC_BIT_TDES0_ES BIT(15) /* Error summary */203#define OWL_EMAC_BIT_TDES0_LO BIT(11) /* Loss of carrier */204#define OWL_EMAC_BIT_TDES0_NC BIT(10) /* No carrier */205#define OWL_EMAC_BIT_TDES0_LC BIT(9) /* Late collision */206#define OWL_EMAC_BIT_TDES0_EC BIT(8) /* Excessive collisions */207#define OWL_EMAC_MSK_TDES0_CC GENMASK(6, 3) /* Collision count */208#define OWL_EMAC_BIT_TDES0_UF BIT(1) /* Underflow error */209#define OWL_EMAC_BIT_TDES0_DE BIT(0) /* Deferred */210 211/* Transmit descriptor control and count field */212#define OWL_EMAC_BIT_TDES1_IC BIT(31) /* Interrupt on completion */213#define OWL_EMAC_BIT_TDES1_LS BIT(30) /* Last descriptor */214#define OWL_EMAC_BIT_TDES1_FS BIT(29) /* First descriptor */215#define OWL_EMAC_BIT_TDES1_FT1 BIT(28) /* Filtering type */216#define OWL_EMAC_BIT_TDES1_SET BIT(27) /* Setup packet */217#define OWL_EMAC_BIT_TDES1_AC BIT(26) /* Add CRC disable */218#define OWL_EMAC_BIT_TDES1_TER BIT(25) /* Transmit end of ring */219#define OWL_EMAC_BIT_TDES1_DPD BIT(23) /* Disabled padding */220#define OWL_EMAC_BIT_TDES1_FT0 BIT(22) /* Filtering type */221#define OWL_EMAC_MSK_TDES1_TBS1 GENMASK(10, 0) /* Buffer 1 size */222 223static const char *const owl_emac_clk_names[] = { "eth", "rmii" };224#define OWL_EMAC_NCLKS ARRAY_SIZE(owl_emac_clk_names)225 226enum owl_emac_clk_map {227 OWL_EMAC_CLK_ETH = 0,228 OWL_EMAC_CLK_RMII229};230 231struct owl_emac_addr_list {232 u8 addrs[OWL_EMAC_MAX_MULTICAST_ADDRS][ETH_ALEN];233 int count;234};235 236/* TX/RX descriptors */237struct owl_emac_ring_desc {238 u32 status;239 u32 control;240 u32 buf_addr;241 u32 reserved; /* 2nd buffer address is not used */242};243 244struct owl_emac_ring {245 struct owl_emac_ring_desc *descs;246 dma_addr_t descs_dma;247 struct sk_buff **skbs;248 dma_addr_t *skbs_dma;249 unsigned int size;250 unsigned int head;251 unsigned int tail;252};253 254struct owl_emac_priv {255 struct net_device *netdev;256 void __iomem *base;257 258 struct clk_bulk_data clks[OWL_EMAC_NCLKS];259 struct reset_control *reset;260 261 struct owl_emac_ring rx_ring;262 struct owl_emac_ring tx_ring;263 264 struct mii_bus *mii;265 struct napi_struct napi;266 267 phy_interface_t phy_mode;268 unsigned int link;269 int speed;270 int duplex;271 int pause;272 struct owl_emac_addr_list mcaddr_list;273 274 struct work_struct mac_reset_task;275 276 u32 msg_enable; /* Debug message level */277 spinlock_t lock; /* Sync concurrent ring access */278};279 280#endif /* __OWL_EMAC_H__ */281