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1/* SPDX-License-Identifier: GPL-2.0 */2 3#ifndef _SLIC_H4#define _SLIC_H5 6#include <linux/types.h>7#include <linux/netdevice.h>8#include <linux/spinlock_types.h>9#include <linux/dma-mapping.h>10#include <linux/pci.h>11#include <linux/list.h>12#include <linux/u64_stats_sync.h>13 14#define SLIC_VGBSTAT_XPERR 0x4000000015#define SLIC_VGBSTAT_XERRSHFT 2516#define SLIC_VGBSTAT_XCSERR 0x2317#define SLIC_VGBSTAT_XUFLOW 0x2218#define SLIC_VGBSTAT_XHLEN 0x2019#define SLIC_VGBSTAT_NETERR 0x0100000020#define SLIC_VGBSTAT_NERRSHFT 1621#define SLIC_VGBSTAT_NERRMSK 0x1ff22#define SLIC_VGBSTAT_NCSERR 0x10323#define SLIC_VGBSTAT_NUFLOW 0x10224#define SLIC_VGBSTAT_NHLEN 0x10025#define SLIC_VGBSTAT_LNKERR 0x0000008026#define SLIC_VGBSTAT_LERRMSK 0xff27#define SLIC_VGBSTAT_LDEARLY 0x8628#define SLIC_VGBSTAT_LBOFLO 0x8529#define SLIC_VGBSTAT_LCODERR 0x8430#define SLIC_VGBSTAT_LDBLNBL 0x8331#define SLIC_VGBSTAT_LCRCERR 0x8232#define SLIC_VGBSTAT_LOFLO 0x8133#define SLIC_VGBSTAT_LUFLO 0x8034 35#define SLIC_IRHDDR_FLEN_MSK 0x0000ffff36#define SLIC_IRHDDR_SVALID 0x8000000037#define SLIC_IRHDDR_ERR 0x1000000038 39#define SLIC_VRHSTAT_802OE 0x8000000040#define SLIC_VRHSTAT_TPOFLO 0x1000000041#define SLIC_VRHSTATB_802UE 0x8000000042#define SLIC_VRHSTATB_RCVE 0x4000000043#define SLIC_VRHSTATB_BUFF 0x2000000044#define SLIC_VRHSTATB_CARRE 0x0800000045#define SLIC_VRHSTATB_LONGE 0x0200000046#define SLIC_VRHSTATB_PREA 0x0100000047#define SLIC_VRHSTATB_CRC 0x0080000048#define SLIC_VRHSTATB_DRBL 0x0040000049#define SLIC_VRHSTATB_CODE 0x0020000050#define SLIC_VRHSTATB_TPCSUM 0x0010000051#define SLIC_VRHSTATB_TPHLEN 0x0008000052#define SLIC_VRHSTATB_IPCSUM 0x0004000053#define SLIC_VRHSTATB_IPLERR 0x0002000054#define SLIC_VRHSTATB_IPHERR 0x0001000055 56#define SLIC_CMD_XMT_REQ 0x0157#define SLIC_CMD_TYPE_DUMB 358 59#define SLIC_RESET_MAGIC 0xDEAD60#define SLIC_ICR_INT_OFF 061#define SLIC_ICR_INT_ON 162#define SLIC_ICR_INT_MASK 263 64#define SLIC_ISR_ERR 0x8000000065#define SLIC_ISR_RCV 0x4000000066#define SLIC_ISR_CMD 0x2000000067#define SLIC_ISR_IO 0x6000000068#define SLIC_ISR_UPC 0x1000000069#define SLIC_ISR_LEVENT 0x0800000070#define SLIC_ISR_RMISS 0x0200000071#define SLIC_ISR_UPCERR 0x0100000072#define SLIC_ISR_XDROP 0x0080000073#define SLIC_ISR_UPCBSY 0x0002000074 75#define SLIC_ISR_PING_MASK 0x0070000076#define SLIC_ISR_UPCERR_MASK (SLIC_ISR_UPCERR | SLIC_ISR_UPCBSY)77#define SLIC_ISR_UPC_MASK (SLIC_ISR_UPC | SLIC_ISR_UPCERR_MASK)78#define SLIC_WCS_START 0x8000000079#define SLIC_WCS_COMPARE 0x4000000080#define SLIC_RCVWCS_BEGIN 0x4000000081#define SLIC_RCVWCS_FINISH 0x8000000082 83#define SLIC_MIICR_REG_16 0x0010000084#define SLIC_MRV_REG16_XOVERON 0x006885 86#define SLIC_GIG_LINKUP 0x000187#define SLIC_GIG_FULLDUPLEX 0x000288#define SLIC_GIG_SPEED_MASK 0x000C89#define SLIC_GIG_SPEED_1000 0x000890#define SLIC_GIG_SPEED_100 0x000491#define SLIC_GIG_SPEED_10 0x000092 93#define SLIC_GMCR_RESET 0x8000000094#define SLIC_GMCR_GBIT 0x2000000095#define SLIC_GMCR_FULLD 0x1000000096#define SLIC_GMCR_GAPBB_SHIFT 1497#define SLIC_GMCR_GAPR1_SHIFT 798#define SLIC_GMCR_GAPR2_SHIFT 099#define SLIC_GMCR_GAPBB_1000 0x60100#define SLIC_GMCR_GAPR1_1000 0x2C101#define SLIC_GMCR_GAPR2_1000 0x40102#define SLIC_GMCR_GAPBB_100 0x70103#define SLIC_GMCR_GAPR1_100 0x2C104#define SLIC_GMCR_GAPR2_100 0x40105 106#define SLIC_XCR_RESET 0x80000000107#define SLIC_XCR_XMTEN 0x40000000108#define SLIC_XCR_PAUSEEN 0x20000000109#define SLIC_XCR_LOADRNG 0x10000000110 111#define SLIC_GXCR_RESET 0x80000000112#define SLIC_GXCR_XMTEN 0x40000000113#define SLIC_GXCR_PAUSEEN 0x20000000114 115#define SLIC_GRCR_RESET 0x80000000116#define SLIC_GRCR_RCVEN 0x40000000117#define SLIC_GRCR_RCVALL 0x20000000118#define SLIC_GRCR_RCVBAD 0x10000000119#define SLIC_GRCR_CTLEN 0x08000000120#define SLIC_GRCR_ADDRAEN 0x02000000121#define SLIC_GRCR_HASHSIZE_SHIFT 17122#define SLIC_GRCR_HASHSIZE 14123 124/* Reset Register */125#define SLIC_REG_RESET 0x0000126/* Interrupt Control Register */127#define SLIC_REG_ICR 0x0008128/* Interrupt status pointer */129#define SLIC_REG_ISP 0x0010130/* Interrupt status */131#define SLIC_REG_ISR 0x0018132/* Header buffer address reg133 * 31-8 - phy addr of set of contiguous hdr buffers134 * 7-0 - number of buffers passed135 * Buffers are 256 bytes long on 256-byte boundaries.136 */137#define SLIC_REG_HBAR 0x0020138/* Data buffer handle & address reg139 * 4 sets of registers; Buffers are 2K bytes long 2 per 4K page.140 */141#define SLIC_REG_DBAR 0x0028142/* Xmt Cmd buf addr regs.143 * 1 per XMT interface144 * 31-5 - phy addr of host command buffer145 * 4-0 - length of cmd in multiples of 32 bytes146 * Buffers are 32 bytes up to 512 bytes long147 */148#define SLIC_REG_CBAR 0x0030149/* Write control store */150#define SLIC_REG_WCS 0x0034151/*Response buffer address reg.152 * 31-8 - phy addr of set of contiguous response buffers153 * 7-0 - number of buffers passed154 * Buffers are 32 bytes long on 32-byte boundaries.155 */156#define SLIC_REG_RBAR 0x0038157/* Read statistics (UPR) */158#define SLIC_REG_RSTAT 0x0040159/* Read link status */160#define SLIC_REG_LSTAT 0x0048161/* Write Mac Config */162#define SLIC_REG_WMCFG 0x0050163/* Write phy register */164#define SLIC_REG_WPHY 0x0058165/* Rcv Cmd buf addr reg */166#define SLIC_REG_RCBAR 0x0060167/* Read SLIC Config*/168#define SLIC_REG_RCONFIG 0x0068169/* Interrupt aggregation time */170#define SLIC_REG_INTAGG 0x0070171/* Write XMIT config reg */172#define SLIC_REG_WXCFG 0x0078173/* Write RCV config reg */174#define SLIC_REG_WRCFG 0x0080175/* Write rcv addr a low */176#define SLIC_REG_WRADDRAL 0x0088177/* Write rcv addr a high */178#define SLIC_REG_WRADDRAH 0x0090179/* Write rcv addr b low */180#define SLIC_REG_WRADDRBL 0x0098181/* Write rcv addr b high */182#define SLIC_REG_WRADDRBH 0x00a0183/* Low bits of mcast mask */184#define SLIC_REG_MCASTLOW 0x00a8185/* High bits of mcast mask */186#define SLIC_REG_MCASTHIGH 0x00b0187/* Ping the card */188#define SLIC_REG_PING 0x00b8189/* Dump command */190#define SLIC_REG_DUMP_CMD 0x00c0191/* Dump data pointer */192#define SLIC_REG_DUMP_DATA 0x00c8193/* Read card's pci_status register */194#define SLIC_REG_PCISTATUS 0x00d0195/* Write hostid field */196#define SLIC_REG_WRHOSTID 0x00d8197/* Put card in a low power state */198#define SLIC_REG_LOW_POWER 0x00e0199/* Force slic into quiescent state before soft reset */200#define SLIC_REG_QUIESCE 0x00e8201/* Reset interface queues */202#define SLIC_REG_RESET_IFACE 0x00f0203/* Register is only written when it has changed.204 * Bits 63-32 for host i/f addrs.205 */206#define SLIC_REG_ADDR_UPPER 0x00f8207/* 64 bit Header buffer address reg */208#define SLIC_REG_HBAR64 0x0100209/* 64 bit Data buffer handle & address reg */210#define SLIC_REG_DBAR64 0x0108211/* 64 bit Xmt Cmd buf addr regs. */212#define SLIC_REG_CBAR64 0x0110213/* 64 bit Response buffer address reg.*/214#define SLIC_REG_RBAR64 0x0118215/* 64 bit Rcv Cmd buf addr reg*/216#define SLIC_REG_RCBAR64 0x0120217/* Read statistics (64 bit UPR) */218#define SLIC_REG_RSTAT64 0x0128219/* Download Gigabit RCV sequencer ucode */220#define SLIC_REG_RCV_WCS 0x0130221/* Write VlanId field */222#define SLIC_REG_WRVLANID 0x0138223/* Read Transformer info */224#define SLIC_REG_READ_XF_INFO 0x0140225/* Write Transformer info */226#define SLIC_REG_WRITE_XF_INFO 0x0148227/* Write card ticks per second */228#define SLIC_REG_TICKS_PER_SEC 0x0170229#define SLIC_REG_HOSTID 0x1554230 231#define PCI_VENDOR_ID_ALACRITECH 0x139A232#define PCI_DEVICE_ID_ALACRITECH_MOJAVE 0x0005233#define PCI_SUBDEVICE_ID_ALACRITECH_1000X1 0x0005234#define PCI_SUBDEVICE_ID_ALACRITECH_1000X1_2 0x0006235#define PCI_SUBDEVICE_ID_ALACRITECH_1000X1F 0x0007236#define PCI_SUBDEVICE_ID_ALACRITECH_CICADA 0x0008237#define PCI_SUBDEVICE_ID_ALACRITECH_SES1001T 0x2006238#define PCI_SUBDEVICE_ID_ALACRITECH_SES1001F 0x2007239#define PCI_DEVICE_ID_ALACRITECH_OASIS 0x0007240#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XT 0x000B241#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XF 0x000C242#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XT 0x000D243#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XF 0x000E244#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2104EF 0x000F245#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2104ET 0x0010246#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2102EF 0x0011247#define PCI_SUBDEVICE_ID_ALACRITECH_SEN2102ET 0x0012248 249/* Note: power of two required for number descriptors */250#define SLIC_NUM_RX_LES 256251#define SLIC_RX_BUFF_SIZE 2048252#define SLIC_RX_BUFF_ALIGN 256253#define SLIC_RX_BUFF_HDR_SIZE 34254#define SLIC_MAX_REQ_RX_DESCS 1255 256#define SLIC_NUM_TX_DESCS 256257#define SLIC_TX_DESC_ALIGN 32258#define SLIC_MIN_TX_WAKEUP_DESCS 10259#define SLIC_MAX_REQ_TX_DESCS 1260#define SLIC_MAX_TX_COMPLETIONS 100261 262#define SLIC_NUM_STAT_DESCS 128263#define SLIC_STATS_DESC_ALIGN 256264 265#define SLIC_NUM_STAT_DESC_ARRAYS 4266#define SLIC_INVALID_STAT_DESC_IDX 0xffffffff267 268#define SLIC_UPR_LSTAT 0269#define SLIC_UPR_CONFIG 1270 271#define SLIC_EEPROM_SIZE 128272#define SLIC_EEPROM_MAGIC 0xa5a5273 274#define SLIC_FIRMWARE_MOJAVE "slicoss/gbdownload.sys"275#define SLIC_FIRMWARE_OASIS "slicoss/oasisdownload.sys"276#define SLIC_RCV_FIRMWARE_MOJAVE "slicoss/gbrcvucode.sys"277#define SLIC_RCV_FIRMWARE_OASIS "slicoss/oasisrcvucode.sys"278#define SLIC_FIRMWARE_MIN_SIZE 64279#define SLIC_FIRMWARE_MAX_SECTIONS 3280 281#define SLIC_MODEL_MOJAVE 0282#define SLIC_MODEL_OASIS 1283 284#define SLIC_INC_STATS_COUNTER(st, counter) \285do { \286 u64_stats_update_begin(&(st)->syncp); \287 (st)->counter++; \288 u64_stats_update_end(&(st)->syncp); \289} while (0)290 291#define SLIC_GET_STATS_COUNTER(newst, st, counter) \292{ \293 unsigned int start; \294 do { \295 start = u64_stats_fetch_begin(&(st)->syncp); \296 newst = (st)->counter; \297 } while (u64_stats_fetch_retry(&(st)->syncp, start)); \298}299 300struct slic_upr {301 dma_addr_t paddr;302 unsigned int type;303 struct list_head list;304};305 306struct slic_upr_list {307 bool pending;308 struct list_head list;309 /* upr list lock */310 spinlock_t lock;311};312 313/* SLIC EEPROM structure for Mojave */314struct slic_mojave_eeprom {315 __le16 id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/316 __le16 eeprom_code_size;/* 01 Size of EEPROM Codes (bytes * 4)*/317 __le16 flash_size; /* 02 Flash size */318 __le16 eeprom_size; /* 03 EEPROM Size */319 __le16 vendor_id; /* 04 Vendor ID */320 __le16 dev_id; /* 05 Device ID */321 u8 rev_id; /* 06 Revision ID */322 u8 class_code[3]; /* 07 Class Code */323 u8 irqpin_dbg; /* 08 Debug Interrupt pin */324 u8 irqpin; /* Network Interrupt Pin */325 u8 min_grant; /* 09 Minimum grant */326 u8 max_lat; /* Maximum Latency */327 __le16 pci_stat; /* 10 PCI Status */328 __le16 sub_vendor_id; /* 11 Subsystem Vendor Id */329 __le16 sub_id; /* 12 Subsystem ID */330 __le16 dev_id_dbg; /* 13 Debug Device Id */331 __le16 ramrom; /* 14 Dram/Rom function */332 __le16 dram_size2pci; /* 15 DRAM size to PCI (bytes * 64K) */333 __le16 rom_size2pci; /* 16 ROM extension size to PCI (bytes * 4k) */334 u8 pad[2]; /* 17 Padding */335 u8 freetime; /* 18 FreeTime setting */336 u8 ifctrl; /* 10-bit interface control (Mojave only) */337 __le16 dram_size; /* 19 DRAM size (bytes * 64k) */338 u8 mac[ETH_ALEN]; /* 20 MAC addresses */339 u8 mac2[ETH_ALEN];340 u8 pad2[6];341 u16 dev_id2; /* Device ID for 2nd PCI function */342 u8 irqpin2; /* Interrupt pin for 2nd PCI function */343 u8 class_code2[3]; /* Class Code for 2nd PCI function */344 u16 cfg_byte6; /* Config Byte 6 */345 u16 pme_cap; /* Power Mgment capabilities */346 u16 nwclk_ctrl; /* NetworkClockControls */347 u8 fru_format; /* Alacritech FRU format type */348 u8 fru_assembly[6]; /* Alacritech FRU information */349 u8 fru_rev[2];350 u8 fru_serial[14];351 u8 fru_pad[3];352 u8 oem_fru[28]; /* optional OEM FRU format type */353 u8 pad3[4]; /* Pad to 128 bytes - includes 2 cksum bytes354 * (if OEM FRU info exists) and two unusable355 * bytes at the end356 */357};358 359/* SLIC EEPROM structure for Oasis */360struct slic_oasis_eeprom {361 __le16 id; /* 00 EEPROM/FLASH Magic code 'A5A5' */362 __le16 eeprom_code_size;/* 01 Size of EEPROM Codes (bytes * 4)*/363 __le16 spidev0_cfg; /* 02 Flash Config for SPI device 0 */364 __le16 spidev1_cfg; /* 03 Flash Config for SPI device 1 */365 __le16 vendor_id; /* 04 Vendor ID */366 __le16 dev_id; /* 05 Device ID (function 0) */367 u8 rev_id; /* 06 Revision ID */368 u8 class_code0[3]; /* 07 Class Code for PCI function 0 */369 u8 irqpin1; /* 08 Interrupt pin for PCI function 1*/370 u8 class_code1[3]; /* 09 Class Code for PCI function 1 */371 u8 irqpin2; /* 10 Interrupt pin for PCI function 2*/372 u8 irqpin0; /* Interrupt pin for PCI function 0*/373 u8 min_grant; /* 11 Minimum grant */374 u8 max_lat; /* Maximum Latency */375 __le16 sub_vendor_id; /* 12 Subsystem Vendor Id */376 __le16 sub_id; /* 13 Subsystem ID */377 __le16 flash_size; /* 14 Flash size (bytes / 4K) */378 __le16 dram_size2pci; /* 15 DRAM size to PCI (bytes / 64K) */379 __le16 rom_size2pci; /* 16 Flash (ROM extension) size to PCI380 * (bytes / 4K)381 */382 __le16 dev_id1; /* 17 Device Id (function 1) */383 __le16 dev_id2; /* 18 Device Id (function 2) */384 __le16 dev_stat_cfg; /* 19 Device Status Config Bytes 6-7 */385 __le16 pme_cap; /* 20 Power Mgment capabilities */386 u8 msi_cap; /* 21 MSI capabilities */387 u8 clock_div; /* Clock divider */388 __le16 pci_stat_lo; /* 22 PCI Status bits 15:0 */389 __le16 pci_stat_hi; /* 23 PCI Status bits 31:16 */390 __le16 dram_cfg_lo; /* 24 DRAM Configuration bits 15:0 */391 __le16 dram_cfg_hi; /* 25 DRAM Configuration bits 31:16 */392 __le16 dram_size; /* 26 DRAM size (bytes / 64K) */393 __le16 gpio_tbi_ctrl; /* 27 GPIO/TBI controls for functions 1/0 */394 __le16 eeprom_size; /* 28 EEPROM Size */395 u8 mac[ETH_ALEN]; /* 29 MAC addresses (2 ports) */396 u8 mac2[ETH_ALEN];397 u8 fru_format; /* 35 Alacritech FRU format type */398 u8 fru_assembly[6]; /* Alacritech FRU information */399 u8 fru_rev[2];400 u8 fru_serial[14];401 u8 fru_pad[3];402 u8 oem_fru[28]; /* optional OEM FRU information */403 u8 pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes404 * (if OEM FRU info exists) and two unusable405 * bytes at the end406 */407};408 409struct slic_stats {410 u64 rx_packets;411 u64 rx_bytes;412 u64 rx_mcasts;413 u64 rx_errors;414 u64 tx_packets;415 u64 tx_bytes;416 /* HW STATS */417 u64 rx_buff_miss;418 u64 tx_dropped;419 u64 irq_errs;420 /* transport layer */421 u64 rx_tpcsum;422 u64 rx_tpoflow;423 u64 rx_tphlen;424 /* ip layer */425 u64 rx_ipcsum;426 u64 rx_iplen;427 u64 rx_iphlen;428 /* link layer */429 u64 rx_early;430 u64 rx_buffoflow;431 u64 rx_lcode;432 u64 rx_drbl;433 u64 rx_crc;434 u64 rx_oflow802;435 u64 rx_uflow802;436 /* oasis only */437 u64 tx_carrier;438 struct u64_stats_sync syncp;439};440 441struct slic_shmem_data {442 __le32 isr;443 __le32 link;444};445 446struct slic_shmem {447 dma_addr_t isr_paddr;448 dma_addr_t link_paddr;449 struct slic_shmem_data *shmem_data;450};451 452struct slic_rx_info_oasis {453 __le32 frame_status;454 __le32 frame_status_b;455 __le32 time_stamp;456 __le32 checksum;457};458 459struct slic_rx_info_mojave {460 __le32 frame_status;461 __le16 byte_cnt;462 __le16 tp_chksum;463 __le16 ctx_hash;464 __le16 mac_hash;465 __le16 buff_lnk;466};467 468struct slic_stat_desc {469 __le32 hnd;470 __u8 pad[8];471 __le32 status;472 __u8 pad2[16];473};474 475struct slic_stat_queue {476 struct slic_stat_desc *descs[SLIC_NUM_STAT_DESC_ARRAYS];477 dma_addr_t paddr[SLIC_NUM_STAT_DESC_ARRAYS];478 unsigned int addr_offset[SLIC_NUM_STAT_DESC_ARRAYS];479 unsigned int active_array;480 unsigned int len;481 unsigned int done_idx;482 size_t mem_size;483};484 485struct slic_tx_desc {486 __le32 hnd;487 __le32 rsvd;488 u8 cmd;489 u8 flags;490 __le16 rsvd2;491 __le32 totlen;492 __le32 paddrl;493 __le32 paddrh;494 __le32 len;495 __le32 type;496};497 498struct slic_tx_buffer {499 struct sk_buff *skb;500 DEFINE_DMA_UNMAP_ADDR(map_addr);501 DEFINE_DMA_UNMAP_LEN(map_len);502 struct slic_tx_desc *desc;503 dma_addr_t desc_paddr;504};505 506struct slic_tx_queue {507 struct dma_pool *dma_pool;508 struct slic_tx_buffer *txbuffs;509 unsigned int len;510 unsigned int put_idx;511 unsigned int done_idx;512};513 514struct slic_rx_desc {515 u8 pad[16];516 __le32 buffer;517 __le32 length;518 __le32 status;519};520 521struct slic_rx_buffer {522 struct sk_buff *skb;523 DEFINE_DMA_UNMAP_ADDR(map_addr);524 DEFINE_DMA_UNMAP_LEN(map_len);525 unsigned int addr_offset;526};527 528struct slic_rx_queue {529 struct slic_rx_buffer *rxbuffs;530 unsigned int len;531 unsigned int done_idx;532 unsigned int put_idx;533};534 535struct slic_device {536 struct pci_dev *pdev;537 struct net_device *netdev;538 void __iomem *regs;539 /* upper address setting lock */540 spinlock_t upper_lock;541 struct slic_shmem shmem;542 struct napi_struct napi;543 struct slic_rx_queue rxq;544 struct slic_tx_queue txq;545 struct slic_stat_queue stq;546 struct slic_stats stats;547 struct slic_upr_list upr_list;548 /* link configuration lock */549 spinlock_t link_lock;550 bool promisc;551 int speed;552 unsigned int duplex;553 bool is_fiber;554 unsigned char model;555};556 557static inline u32 slic_read(struct slic_device *sdev, unsigned int reg)558{559 return ioread32(sdev->regs + reg);560}561 562static inline void slic_write(struct slic_device *sdev, unsigned int reg,563 u32 val)564{565 iowrite32(val, sdev->regs + reg);566}567 568static inline void slic_flush_write(struct slic_device *sdev)569{570 (void)ioread32(sdev->regs + SLIC_REG_HOSTID);571}572 573#endif /* _SLIC_H */574