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1/* SPDX-License-Identifier: GPL-2.0-only */2/* Altera TSE SGDMA and MSGDMA Linux driver3 * Copyright (C) 2014 Altera Corporation. All rights reserved4 */5 6#ifndef __ALTERA_MSGDMAHW_H__7#define __ALTERA_MSGDMAHW_H__8 9/* mSGDMA extended descriptor format10 */11struct msgdma_extended_desc {12 u32 read_addr_lo; /* data buffer source address low bits */13 u32 write_addr_lo; /* data buffer destination address low bits */14 u32 len; /* the number of bytes to transfer15 * per descriptor16 */17 u32 burst_seq_num; /* bit 31:24 write burst18 * bit 23:16 read burst19 * bit 15:0 sequence number20 */21 u32 stride; /* bit 31:16 write stride22 * bit 15:0 read stride23 */24 u32 read_addr_hi; /* data buffer source address high bits */25 u32 write_addr_hi; /* data buffer destination address high bits */26 u32 control; /* characteristics of the transfer */27};28 29/* mSGDMA descriptor control field bit definitions30 */31#define MSGDMA_DESC_CTL_SET_CH(x) ((x) & 0xff)32#define MSGDMA_DESC_CTL_GEN_SOP BIT(8)33#define MSGDMA_DESC_CTL_GEN_EOP BIT(9)34#define MSGDMA_DESC_CTL_PARK_READS BIT(10)35#define MSGDMA_DESC_CTL_PARK_WRITES BIT(11)36#define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)37#define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)38#define MSGDMA_DESC_CTL_TR_COMP_IRQ BIT(14)39#define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15)40#define MSGDMA_DESC_CTL_TR_ERR_IRQ (0xff << 16)41#define MSGDMA_DESC_CTL_EARLY_DONE BIT(24)42/* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the43 * descriptor FIFO(s)44 */45#define MSGDMA_DESC_CTL_GO BIT(31)46 47/* Tx buffer control flags48 */49#define MSGDMA_DESC_CTL_TX_FIRST (MSGDMA_DESC_CTL_GEN_SOP | \50 MSGDMA_DESC_CTL_GO)51 52#define MSGDMA_DESC_CTL_TX_MIDDLE (MSGDMA_DESC_CTL_GO)53 54#define MSGDMA_DESC_CTL_TX_LAST (MSGDMA_DESC_CTL_GEN_EOP | \55 MSGDMA_DESC_CTL_TR_COMP_IRQ | \56 MSGDMA_DESC_CTL_GO)57 58#define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \59 MSGDMA_DESC_CTL_GEN_EOP | \60 MSGDMA_DESC_CTL_TR_COMP_IRQ | \61 MSGDMA_DESC_CTL_GO)62 63#define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \64 MSGDMA_DESC_CTL_END_ON_LEN | \65 MSGDMA_DESC_CTL_TR_COMP_IRQ | \66 MSGDMA_DESC_CTL_EARLY_IRQ | \67 MSGDMA_DESC_CTL_TR_ERR_IRQ | \68 MSGDMA_DESC_CTL_GO)69 70/* mSGDMA extended descriptor stride definitions71 */72#define MSGDMA_DESC_TX_STRIDE (0x00010001)73#define MSGDMA_DESC_RX_STRIDE (0x00010001)74 75/* mSGDMA dispatcher control and status register map76 */77struct msgdma_csr {78 u32 status; /* Read/Clear */79 u32 control; /* Read/Write */80 u32 rw_fill_level; /* bit 31:16 - write fill level81 * bit 15:0 - read fill level82 */83 u32 resp_fill_level; /* bit 15:0 */84 u32 rw_seq_num; /* bit 31:16 - write sequence number85 * bit 15:0 - read sequence number86 */87 u32 pad[3]; /* reserved */88};89 90/* mSGDMA CSR status register bit definitions91 */92#define MSGDMA_CSR_STAT_BUSY BIT(0)93#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY BIT(1)94#define MSGDMA_CSR_STAT_DESC_BUF_FULL BIT(2)95#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY BIT(3)96#define MSGDMA_CSR_STAT_RESP_BUF_FULL BIT(4)97#define MSGDMA_CSR_STAT_STOPPED BIT(5)98#define MSGDMA_CSR_STAT_RESETTING BIT(6)99#define MSGDMA_CSR_STAT_STOPPED_ON_ERR BIT(7)100#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY BIT(8)101#define MSGDMA_CSR_STAT_IRQ BIT(9)102#define MSGDMA_CSR_STAT_MASK 0x3FF103#define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ 0x1FF104 105#define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0)106#define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 1)107#define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v) GET_BIT_VALUE(v, 2)108#define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 3)109#define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v) GET_BIT_VALUE(v, 4)110#define MSGDMA_CSR_STAT_STOPPED_GET(v) GET_BIT_VALUE(v, 5)111#define MSGDMA_CSR_STAT_RESETTING_GET(v) GET_BIT_VALUE(v, 6)112#define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v) GET_BIT_VALUE(v, 7)113#define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v) GET_BIT_VALUE(v, 8)114#define MSGDMA_CSR_STAT_IRQ_GET(v) GET_BIT_VALUE(v, 9)115 116/* mSGDMA CSR control register bit definitions117 */118#define MSGDMA_CSR_CTL_STOP BIT(0)119#define MSGDMA_CSR_CTL_RESET BIT(1)120#define MSGDMA_CSR_CTL_STOP_ON_ERR BIT(2)121#define MSGDMA_CSR_CTL_STOP_ON_EARLY BIT(3)122#define MSGDMA_CSR_CTL_GLOBAL_INTR BIT(4)123#define MSGDMA_CSR_CTL_STOP_DESCS BIT(5)124 125/* mSGDMA CSR fill level bits126 */127#define MSGDMA_CSR_WR_FILL_LEVEL_GET(v) (((v) & 0xffff0000) >> 16)128#define MSGDMA_CSR_RD_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)129#define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v) ((v) & 0x0000ffff)130 131/* mSGDMA response register map132 */133struct msgdma_response {134 u32 bytes_transferred;135 u32 status;136};137 138#define msgdma_respoffs(a) (offsetof(struct msgdma_response, a))139#define msgdma_csroffs(a) (offsetof(struct msgdma_csr, a))140#define msgdma_descroffs(a) (offsetof(struct msgdma_extended_desc, a))141 142/* mSGDMA response register bit definitions143 */144#define MSGDMA_RESP_EARLY_TERM BIT(8)145#define MSGDMA_RESP_ERR_MASK 0xFF146 147#endif /* __ALTERA_MSGDMA_H__*/148