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1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */2/*3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.4 */5#ifndef _ENA_ADMIN_H_6#define _ENA_ADMIN_H_7 8#define ENA_ADMIN_RSS_KEY_PARTS 109 10#define ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK 0x3F11#define ENA_ADMIN_CUSTOMER_METRICS_MIN_SUPPORT_MASK 0x1F12 13 /* customer metrics - in correlation with14 * ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK15 */16enum ena_admin_customer_metrics_id {17 ENA_ADMIN_BW_IN_ALLOWANCE_EXCEEDED = 0,18 ENA_ADMIN_BW_OUT_ALLOWANCE_EXCEEDED = 1,19 ENA_ADMIN_PPS_ALLOWANCE_EXCEEDED = 2,20 ENA_ADMIN_CONNTRACK_ALLOWANCE_EXCEEDED = 3,21 ENA_ADMIN_LINKLOCAL_ALLOWANCE_EXCEEDED = 4,22 ENA_ADMIN_CONNTRACK_ALLOWANCE_AVAILABLE = 5,23};24 25enum ena_admin_aq_opcode {26 ENA_ADMIN_CREATE_SQ = 1,27 ENA_ADMIN_DESTROY_SQ = 2,28 ENA_ADMIN_CREATE_CQ = 3,29 ENA_ADMIN_DESTROY_CQ = 4,30 ENA_ADMIN_GET_FEATURE = 8,31 ENA_ADMIN_SET_FEATURE = 9,32 ENA_ADMIN_GET_STATS = 11,33};34 35enum ena_admin_aq_completion_status {36 ENA_ADMIN_SUCCESS = 0,37 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,38 ENA_ADMIN_BAD_OPCODE = 2,39 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,40 ENA_ADMIN_MALFORMED_REQUEST = 4,41 /* Additional status is provided in ACQ entry extended_status */42 ENA_ADMIN_ILLEGAL_PARAMETER = 5,43 ENA_ADMIN_UNKNOWN_ERROR = 6,44 ENA_ADMIN_RESOURCE_BUSY = 7,45};46 47/* subcommands for the set/get feature admin commands */48enum ena_admin_aq_feature_id {49 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,50 ENA_ADMIN_MAX_QUEUES_NUM = 2,51 ENA_ADMIN_HW_HINTS = 3,52 ENA_ADMIN_LLQ = 4,53 ENA_ADMIN_MAX_QUEUES_EXT = 7,54 ENA_ADMIN_RSS_HASH_FUNCTION = 10,55 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,56 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12,57 ENA_ADMIN_MTU = 14,58 ENA_ADMIN_RSS_HASH_INPUT = 18,59 ENA_ADMIN_INTERRUPT_MODERATION = 20,60 ENA_ADMIN_AENQ_CONFIG = 26,61 ENA_ADMIN_LINK_CONFIG = 27,62 ENA_ADMIN_HOST_ATTR_CONFIG = 28,63 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,64};65 66/* device capabilities */67enum ena_admin_aq_caps_id {68 ENA_ADMIN_ENI_STATS = 0,69 /* ENA SRD customer metrics */70 ENA_ADMIN_ENA_SRD_INFO = 1,71 ENA_ADMIN_CUSTOMER_METRICS = 2,72};73 74enum ena_admin_placement_policy_type {75 /* descriptors and headers are in host memory */76 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,77 /* descriptors and headers are in device memory (a.k.a Low Latency78 * Queue)79 */80 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,81};82 83enum ena_admin_link_types {84 ENA_ADMIN_LINK_SPEED_1G = 0x1,85 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,86 ENA_ADMIN_LINK_SPEED_5G = 0x4,87 ENA_ADMIN_LINK_SPEED_10G = 0x8,88 ENA_ADMIN_LINK_SPEED_25G = 0x10,89 ENA_ADMIN_LINK_SPEED_40G = 0x20,90 ENA_ADMIN_LINK_SPEED_50G = 0x40,91 ENA_ADMIN_LINK_SPEED_100G = 0x80,92 ENA_ADMIN_LINK_SPEED_200G = 0x100,93 ENA_ADMIN_LINK_SPEED_400G = 0x200,94};95 96enum ena_admin_completion_policy_type {97 /* completion queue entry for each sq descriptor */98 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,99 /* completion queue entry upon request in sq descriptor */100 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,101 /* current queue head pointer is updated in OS memory upon sq102 * descriptor request103 */104 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,105 /* current queue head pointer is updated in OS memory for each sq106 * descriptor107 */108 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,109};110 111/* basic stats return ena_admin_basic_stats while extanded stats return a112 * buffer (string format) with additional statistics per queue and per113 * device id114 */115enum ena_admin_get_stats_type {116 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,117 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,118 /* extra HW stats for specific network interface */119 ENA_ADMIN_GET_STATS_TYPE_ENI = 2,120 /* extra HW stats for ENA SRD */121 ENA_ADMIN_GET_STATS_TYPE_ENA_SRD = 3,122 ENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS = 4,123};124 125enum ena_admin_get_stats_scope {126 ENA_ADMIN_SPECIFIC_QUEUE = 0,127 ENA_ADMIN_ETH_TRAFFIC = 1,128};129 130/* ENA SRD configuration for ENI */131enum ena_admin_ena_srd_flags {132 /* Feature enabled */133 ENA_ADMIN_ENA_SRD_ENABLED = BIT(0),134 /* UDP support enabled */135 ENA_ADMIN_ENA_SRD_UDP_ENABLED = BIT(1),136 /* Bypass Rx UDP ordering */137 ENA_ADMIN_ENA_SRD_UDP_ORDERING_BYPASS_ENABLED = BIT(2),138};139 140struct ena_admin_aq_common_desc {141 /* 11:0 : command_id142 * 15:12 : reserved12143 */144 u16 command_id;145 146 /* as appears in ena_admin_aq_opcode */147 u8 opcode;148 149 /* 0 : phase150 * 1 : ctrl_data - control buffer address valid151 * 2 : ctrl_data_indirect - control buffer address152 * points to list of pages with addresses of control153 * buffers154 * 7:3 : reserved3155 */156 u8 flags;157};158 159/* used in ena_admin_aq_entry. Can point directly to control data, or to a160 * page list chunk. Used also at the end of indirect mode page list chunks,161 * for chaining.162 */163struct ena_admin_ctrl_buff_info {164 u32 length;165 166 struct ena_common_mem_addr address;167};168 169struct ena_admin_sq {170 u16 sq_idx;171 172 /* 4:0 : reserved173 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx174 */175 u8 sq_identity;176 177 u8 reserved1;178};179 180struct ena_admin_aq_entry {181 struct ena_admin_aq_common_desc aq_common_descriptor;182 183 union {184 u32 inline_data_w1[3];185 186 struct ena_admin_ctrl_buff_info control_buffer;187 } u;188 189 u32 inline_data_w4[12];190};191 192struct ena_admin_acq_common_desc {193 /* command identifier to associate it with the aq descriptor194 * 11:0 : command_id195 * 15:12 : reserved12196 */197 u16 command;198 199 u8 status;200 201 /* 0 : phase202 * 7:1 : reserved1203 */204 u8 flags;205 206 u16 extended_status;207 208 /* indicates to the driver which AQ entry has been consumed by the209 * device and could be reused210 */211 u16 sq_head_indx;212};213 214struct ena_admin_acq_entry {215 struct ena_admin_acq_common_desc acq_common_descriptor;216 217 u32 response_specific_data[14];218};219 220struct ena_admin_aq_create_sq_cmd {221 struct ena_admin_aq_common_desc aq_common_descriptor;222 223 /* 4:0 : reserved0_w1224 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx225 */226 u8 sq_identity;227 228 u8 reserved8_w1;229 230 /* 3:0 : placement_policy - Describing where the SQ231 * descriptor ring and the SQ packet headers reside:232 * 0x1 - descriptors and headers are in OS memory,233 * 0x3 - descriptors and headers in device memory234 * (a.k.a Low Latency Queue)235 * 6:4 : completion_policy - Describing what policy236 * to use for generation completion entry (cqe) in237 * the CQ associated with this SQ: 0x0 - cqe for each238 * sq descriptor, 0x1 - cqe upon request in sq239 * descriptor, 0x2 - current queue head pointer is240 * updated in OS memory upon sq descriptor request241 * 0x3 - current queue head pointer is updated in OS242 * memory for each sq descriptor243 * 7 : reserved15_w1244 */245 u8 sq_caps_2;246 247 /* 0 : is_physically_contiguous - Described if the248 * queue ring memory is allocated in physical249 * contiguous pages or split.250 * 7:1 : reserved17_w1251 */252 u8 sq_caps_3;253 254 /* associated completion queue id. This CQ must be created prior to SQ255 * creation256 */257 u16 cq_idx;258 259 /* submission queue depth in entries */260 u16 sq_depth;261 262 /* SQ physical base address in OS memory. This field should not be263 * used for Low Latency queues. Has to be page aligned.264 */265 struct ena_common_mem_addr sq_ba;266 267 /* specifies queue head writeback location in OS memory. Valid if268 * completion_policy is set to completion_policy_head_on_demand or269 * completion_policy_head. Has to be cache aligned270 */271 struct ena_common_mem_addr sq_head_writeback;272 273 u32 reserved0_w7;274 275 u32 reserved0_w8;276};277 278enum ena_admin_sq_direction {279 ENA_ADMIN_SQ_DIRECTION_TX = 1,280 ENA_ADMIN_SQ_DIRECTION_RX = 2,281};282 283struct ena_admin_acq_create_sq_resp_desc {284 struct ena_admin_acq_common_desc acq_common_desc;285 286 u16 sq_idx;287 288 u16 reserved;289 290 /* queue doorbell address as an offset to PCIe MMIO REG BAR */291 u32 sq_doorbell_offset;292 293 /* low latency queue ring base address as an offset to PCIe MMIO294 * LLQ_MEM BAR295 */296 u32 llq_descriptors_offset;297 298 /* low latency queue headers' memory as an offset to PCIe MMIO299 * LLQ_MEM BAR300 */301 u32 llq_headers_offset;302};303 304struct ena_admin_aq_destroy_sq_cmd {305 struct ena_admin_aq_common_desc aq_common_descriptor;306 307 struct ena_admin_sq sq;308};309 310struct ena_admin_acq_destroy_sq_resp_desc {311 struct ena_admin_acq_common_desc acq_common_desc;312};313 314struct ena_admin_aq_create_cq_cmd {315 struct ena_admin_aq_common_desc aq_common_descriptor;316 317 /* 4:0 : reserved5318 * 5 : interrupt_mode_enabled - if set, cq operates319 * in interrupt mode, otherwise - polling320 * 7:6 : reserved6321 */322 u8 cq_caps_1;323 324 /* 4:0 : cq_entry_size_words - size of CQ entry in325 * 32-bit words, valid values: 4, 8.326 * 7:5 : reserved7327 */328 u8 cq_caps_2;329 330 /* completion queue depth in # of entries. must be power of 2 */331 u16 cq_depth;332 333 /* msix vector assigned to this cq */334 u32 msix_vector;335 336 /* cq physical base address in OS memory. CQ must be physically337 * contiguous338 */339 struct ena_common_mem_addr cq_ba;340};341 342struct ena_admin_acq_create_cq_resp_desc {343 struct ena_admin_acq_common_desc acq_common_desc;344 345 u16 cq_idx;346 347 /* actual cq depth in number of entries */348 u16 cq_actual_depth;349 350 u32 numa_node_register_offset;351 352 u32 cq_head_db_register_offset;353 354 u32 cq_interrupt_unmask_register_offset;355};356 357struct ena_admin_aq_destroy_cq_cmd {358 struct ena_admin_aq_common_desc aq_common_descriptor;359 360 u16 cq_idx;361 362 u16 reserved1;363};364 365struct ena_admin_acq_destroy_cq_resp_desc {366 struct ena_admin_acq_common_desc acq_common_desc;367};368 369/* ENA AQ Get Statistics command. Extended statistics are placed in control370 * buffer pointed by AQ entry371 */372struct ena_admin_aq_get_stats_cmd {373 struct ena_admin_aq_common_desc aq_common_descriptor;374 375 union {376 /* command specific inline data */377 u32 inline_data_w1[3];378 379 struct ena_admin_ctrl_buff_info control_buffer;380 } u;381 382 /* stats type as defined in enum ena_admin_get_stats_type */383 u8 type;384 385 /* stats scope defined in enum ena_admin_get_stats_scope */386 u8 scope;387 388 u16 reserved3;389 390 /* queue id. used when scope is specific_queue */391 u16 queue_idx;392 393 /* device id, value 0xFFFF means mine. only privileged device can get394 * stats of other device395 */396 u16 device_id;397 398 /* a bitmap representing the requested metric values */399 u64 requested_metrics;400};401 402/* Basic Statistics Command. */403struct ena_admin_basic_stats {404 u32 tx_bytes_low;405 406 u32 tx_bytes_high;407 408 u32 tx_pkts_low;409 410 u32 tx_pkts_high;411 412 u32 rx_bytes_low;413 414 u32 rx_bytes_high;415 416 u32 rx_pkts_low;417 418 u32 rx_pkts_high;419 420 u32 rx_drops_low;421 422 u32 rx_drops_high;423 424 u32 tx_drops_low;425 426 u32 tx_drops_high;427};428 429/* ENI Statistics Command. */430struct ena_admin_eni_stats {431 /* The number of packets shaped due to inbound aggregate BW432 * allowance being exceeded433 */434 u64 bw_in_allowance_exceeded;435 436 /* The number of packets shaped due to outbound aggregate BW437 * allowance being exceeded438 */439 u64 bw_out_allowance_exceeded;440 441 /* The number of packets shaped due to PPS allowance being exceeded */442 u64 pps_allowance_exceeded;443 444 /* The number of packets shaped due to connection tracking445 * allowance being exceeded and leading to failure in establishment446 * of new connections447 */448 u64 conntrack_allowance_exceeded;449 450 /* The number of packets shaped due to linklocal packet rate451 * allowance being exceeded452 */453 u64 linklocal_allowance_exceeded;454};455 456struct ena_admin_ena_srd_stats {457 /* Number of packets transmitted over ENA SRD */458 u64 ena_srd_tx_pkts;459 460 /* Number of packets transmitted or could have been461 * transmitted over ENA SRD462 */463 u64 ena_srd_eligible_tx_pkts;464 465 /* Number of packets received over ENA SRD */466 u64 ena_srd_rx_pkts;467 468 /* Percentage of the ENA SRD resources that is in use */469 u64 ena_srd_resource_utilization;470};471 472/* ENA SRD Statistics Command */473struct ena_admin_ena_srd_info {474 /* ENA SRD configuration bitmap. See ena_admin_ena_srd_flags for475 * details476 */477 u64 flags;478 479 struct ena_admin_ena_srd_stats ena_srd_stats;480};481 482/* Customer Metrics Command. */483struct ena_admin_customer_metrics {484 /* A bitmap representing the reported customer metrics according to485 * the order they are reported486 */487 u64 reported_metrics;488};489 490struct ena_admin_acq_get_stats_resp {491 struct ena_admin_acq_common_desc acq_common_desc;492 493 union {494 u64 raw[7];495 496 struct ena_admin_basic_stats basic_stats;497 498 struct ena_admin_eni_stats eni_stats;499 500 struct ena_admin_ena_srd_info ena_srd_info;501 502 struct ena_admin_customer_metrics customer_metrics;503 } u;504};505 506struct ena_admin_get_set_feature_common_desc {507 /* 1:0 : select - 0x1 - current value; 0x3 - default508 * value509 * 7:3 : reserved3510 */511 u8 flags;512 513 /* as appears in ena_admin_aq_feature_id */514 u8 feature_id;515 516 /* The driver specifies the max feature version it supports and the517 * device responds with the currently supported feature version. The518 * field is zero based519 */520 u8 feature_version;521 522 u8 reserved8;523};524 525struct ena_admin_device_attr_feature_desc {526 u32 impl_id;527 528 u32 device_version;529 530 /* bitmap of ena_admin_aq_feature_id, which represents supported531 * subcommands for the set/get feature admin commands.532 */533 u32 supported_features;534 535 /* bitmap of ena_admin_aq_caps_id, which represents device536 * capabilities.537 */538 u32 capabilities;539 540 /* Indicates how many bits are used physical address access. */541 u32 phys_addr_width;542 543 /* Indicates how many bits are used virtual address access. */544 u32 virt_addr_width;545 546 /* unicast MAC address (in Network byte order) */547 u8 mac_addr[6];548 549 u8 reserved7[2];550 551 u32 max_mtu;552};553 554enum ena_admin_llq_header_location {555 /* header is in descriptor list */556 ENA_ADMIN_INLINE_HEADER = 1,557 /* header in a separate ring, implies 16B descriptor list entry */558 ENA_ADMIN_HEADER_RING = 2,559};560 561enum ena_admin_llq_ring_entry_size {562 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,563 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,564 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,565};566 567enum ena_admin_llq_num_descs_before_header {568 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,569 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,570 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,571 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,572 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,573};574 575/* packet descriptor list entry always starts with one or more descriptors,576 * followed by a header. The rest of the descriptors are located in the577 * beginning of the subsequent entry. Stride refers to how the rest of the578 * descriptors are placed. This field is relevant only for inline header579 * mode580 */581enum ena_admin_llq_stride_ctrl {582 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,583 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,584};585 586enum ena_admin_accel_mode_feat {587 ENA_ADMIN_DISABLE_META_CACHING = 0,588 ENA_ADMIN_LIMIT_TX_BURST = 1,589};590 591struct ena_admin_accel_mode_get {592 /* bit field of enum ena_admin_accel_mode_feat */593 u16 supported_flags;594 595 /* maximum burst size between two doorbells. The size is in bytes */596 u16 max_tx_burst_size;597};598 599struct ena_admin_accel_mode_set {600 /* bit field of enum ena_admin_accel_mode_feat */601 u16 enabled_flags;602 603 u16 reserved;604};605 606struct ena_admin_accel_mode_req {607 union {608 u32 raw[2];609 610 struct ena_admin_accel_mode_get get;611 612 struct ena_admin_accel_mode_set set;613 } u;614};615 616struct ena_admin_feature_llq_desc {617 u32 max_llq_num;618 619 u32 max_llq_depth;620 621 /* specify the header locations the device supports. bitfield of enum622 * ena_admin_llq_header_location.623 */624 u16 header_location_ctrl_supported;625 626 /* the header location the driver selected to use. */627 u16 header_location_ctrl_enabled;628 629 /* if inline header is specified - this is the size of descriptor list630 * entry. If header in a separate ring is specified - this is the size631 * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size.632 * specify the entry sizes the device supports633 */634 u16 entry_size_ctrl_supported;635 636 /* the entry size the driver selected to use. */637 u16 entry_size_ctrl_enabled;638 639 /* valid only if inline header is specified. First entry associated with640 * the packet includes descriptors and header. Rest of the entries641 * occupied by descriptors. This parameter defines the max number of642 * descriptors precedding the header in the first entry. The field is643 * bitfield of enum ena_admin_llq_num_descs_before_header and specify644 * the values the device supports645 */646 u16 desc_num_before_header_supported;647 648 /* the desire field the driver selected to use */649 u16 desc_num_before_header_enabled;650 651 /* valid only if inline was chosen. bitfield of enum652 * ena_admin_llq_stride_ctrl653 */654 u16 descriptors_stride_ctrl_supported;655 656 /* the stride control the driver selected to use */657 u16 descriptors_stride_ctrl_enabled;658 659 /* reserved */660 u32 reserved1;661 662 /* accelerated low latency queues requirement. driver needs to663 * support those requirements in order to use accelerated llq664 */665 struct ena_admin_accel_mode_req accel_mode;666};667 668struct ena_admin_queue_ext_feature_fields {669 u32 max_tx_sq_num;670 671 u32 max_tx_cq_num;672 673 u32 max_rx_sq_num;674 675 u32 max_rx_cq_num;676 677 u32 max_tx_sq_depth;678 679 u32 max_tx_cq_depth;680 681 u32 max_rx_sq_depth;682 683 u32 max_rx_cq_depth;684 685 u32 max_tx_header_size;686 687 /* Maximum Descriptors number, including meta descriptor, allowed for a688 * single Tx packet689 */690 u16 max_per_packet_tx_descs;691 692 /* Maximum Descriptors number allowed for a single Rx packet */693 u16 max_per_packet_rx_descs;694};695 696struct ena_admin_queue_feature_desc {697 u32 max_sq_num;698 699 u32 max_sq_depth;700 701 u32 max_cq_num;702 703 u32 max_cq_depth;704 705 u32 max_legacy_llq_num;706 707 u32 max_legacy_llq_depth;708 709 u32 max_header_size;710 711 /* Maximum Descriptors number, including meta descriptor, allowed for a712 * single Tx packet713 */714 u16 max_packet_tx_descs;715 716 /* Maximum Descriptors number allowed for a single Rx packet */717 u16 max_packet_rx_descs;718};719 720struct ena_admin_set_feature_mtu_desc {721 /* exclude L2 */722 u32 mtu;723};724 725struct ena_admin_set_feature_host_attr_desc {726 /* host OS info base address in OS memory. host info is 4KB of727 * physically contiguous728 */729 struct ena_common_mem_addr os_info_ba;730 731 /* host debug area base address in OS memory. debug area must be732 * physically contiguous733 */734 struct ena_common_mem_addr debug_ba;735 736 /* debug area size */737 u32 debug_area_size;738};739 740struct ena_admin_feature_intr_moder_desc {741 /* interrupt delay granularity in usec */742 u16 intr_delay_resolution;743 744 u16 reserved;745};746 747struct ena_admin_get_feature_link_desc {748 /* Link speed in Mb */749 u32 speed;750 751 /* bit field of enum ena_admin_link types */752 u32 supported;753 754 /* 0 : autoneg755 * 1 : duplex - Full Duplex756 * 31:2 : reserved2757 */758 u32 flags;759};760 761struct ena_admin_feature_aenq_desc {762 /* bitmask for AENQ groups the device can report */763 u32 supported_groups;764 765 /* bitmask for AENQ groups to report */766 u32 enabled_groups;767};768 769struct ena_admin_feature_offload_desc {770 /* 0 : TX_L3_csum_ipv4771 * 1 : TX_L4_ipv4_csum_part - The checksum field772 * should be initialized with pseudo header checksum773 * 2 : TX_L4_ipv4_csum_full774 * 3 : TX_L4_ipv6_csum_part - The checksum field775 * should be initialized with pseudo header checksum776 * 4 : TX_L4_ipv6_csum_full777 * 5 : tso_ipv4778 * 6 : tso_ipv6779 * 7 : tso_ecn780 */781 u32 tx;782 783 /* Receive side supported stateless offload784 * 0 : RX_L3_csum_ipv4 - IPv4 checksum785 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum786 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum787 * 3 : RX_hash - Hash calculation788 */789 u32 rx_supported;790 791 u32 rx_enabled;792};793 794enum ena_admin_hash_functions {795 ENA_ADMIN_TOEPLITZ = 1,796 ENA_ADMIN_CRC32 = 2,797};798 799struct ena_admin_feature_rss_flow_hash_control {800 u32 key_parts;801 802 u32 reserved;803 804 u32 key[ENA_ADMIN_RSS_KEY_PARTS];805};806 807struct ena_admin_feature_rss_flow_hash_function {808 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */809 u32 supported_func;810 811 /* 7:0 : selected_func - bitmask of812 * ena_admin_hash_functions813 */814 u32 selected_func;815 816 /* initial value */817 u32 init_val;818};819 820/* RSS flow hash protocols */821enum ena_admin_flow_hash_proto {822 ENA_ADMIN_RSS_TCP4 = 0,823 ENA_ADMIN_RSS_UDP4 = 1,824 ENA_ADMIN_RSS_TCP6 = 2,825 ENA_ADMIN_RSS_UDP6 = 3,826 ENA_ADMIN_RSS_IP4 = 4,827 ENA_ADMIN_RSS_IP6 = 5,828 ENA_ADMIN_RSS_IP4_FRAG = 6,829 ENA_ADMIN_RSS_NOT_IP = 7,830 /* TCPv6 with extension header */831 ENA_ADMIN_RSS_TCP6_EX = 8,832 /* IPv6 with extension header */833 ENA_ADMIN_RSS_IP6_EX = 9,834 ENA_ADMIN_RSS_PROTO_NUM = 16,835};836 837/* RSS flow hash fields */838enum ena_admin_flow_hash_fields {839 /* Ethernet Dest Addr */840 ENA_ADMIN_RSS_L2_DA = BIT(0),841 /* Ethernet Src Addr */842 ENA_ADMIN_RSS_L2_SA = BIT(1),843 /* ipv4/6 Dest Addr */844 ENA_ADMIN_RSS_L3_DA = BIT(2),845 /* ipv4/6 Src Addr */846 ENA_ADMIN_RSS_L3_SA = BIT(3),847 /* tcp/udp Dest Port */848 ENA_ADMIN_RSS_L4_DP = BIT(4),849 /* tcp/udp Src Port */850 ENA_ADMIN_RSS_L4_SP = BIT(5),851};852 853struct ena_admin_proto_input {854 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */855 u16 fields;856 857 u16 reserved2;858};859 860struct ena_admin_feature_rss_hash_control {861 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];862 863 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];864 865 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];866 867 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];868};869 870struct ena_admin_feature_rss_flow_hash_input {871 /* supported hash input sorting872 * 1 : L3_sort - support swap L3 addresses if DA is873 * smaller than SA874 * 2 : L4_sort - support swap L4 ports if DP smaller875 * SP876 */877 u16 supported_input_sort;878 879 /* enabled hash input sorting880 * 1 : enable_L3_sort - enable swap L3 addresses if881 * DA smaller than SA882 * 2 : enable_L4_sort - enable swap L4 ports if DP883 * smaller than SP884 */885 u16 enabled_input_sort;886};887 888enum ena_admin_os_type {889 ENA_ADMIN_OS_LINUX = 1,890 ENA_ADMIN_OS_WIN = 2,891 ENA_ADMIN_OS_DPDK = 3,892 ENA_ADMIN_OS_FREEBSD = 4,893 ENA_ADMIN_OS_IPXE = 5,894 ENA_ADMIN_OS_ESXI = 6,895 ENA_ADMIN_OS_GROUPS_NUM = 6,896};897 898struct ena_admin_host_info {899 /* defined in enum ena_admin_os_type */900 u32 os_type;901 902 /* os distribution string format */903 u8 os_dist_str[128];904 905 /* OS distribution numeric format */906 u32 os_dist;907 908 /* kernel version string format */909 u8 kernel_ver_str[32];910 911 /* Kernel version numeric format */912 u32 kernel_ver;913 914 /* 7:0 : major915 * 15:8 : minor916 * 23:16 : sub_minor917 * 31:24 : module_type918 */919 u32 driver_version;920 921 /* features bitmap */922 u32 supported_network_features[2];923 924 /* ENA spec version of driver */925 u16 ena_spec_version;926 927 /* ENA device's Bus, Device and Function928 * 2:0 : function929 * 7:3 : device930 * 15:8 : bus931 */932 u16 bdf;933 934 /* Number of CPUs */935 u16 num_cpus;936 937 u16 reserved;938 939 /* 0 : reserved940 * 1 : rx_offset941 * 2 : interrupt_moderation942 * 3 : rx_buf_mirroring943 * 4 : rss_configurable_function_key944 * 5 : reserved945 * 6 : rx_page_reuse946 * 31:7 : reserved947 */948 u32 driver_supported_features;949};950 951struct ena_admin_rss_ind_table_entry {952 u16 cq_idx;953 954 u16 reserved;955};956 957struct ena_admin_feature_rss_ind_table {958 /* min supported table size (2^min_size) */959 u16 min_size;960 961 /* max supported table size (2^max_size) */962 u16 max_size;963 964 /* table size (2^size) */965 u16 size;966 967 u16 reserved;968 969 /* index of the inline entry. 0xFFFFFFFF means invalid */970 u32 inline_index;971 972 /* used for updating single entry, ignored when setting the entire973 * table through the control buffer.974 */975 struct ena_admin_rss_ind_table_entry inline_entry;976};977 978/* When hint value is 0, driver should use it's own predefined value */979struct ena_admin_ena_hw_hints {980 /* value in ms */981 u16 mmio_read_timeout;982 983 /* value in ms */984 u16 driver_watchdog_timeout;985 986 /* Per packet tx completion timeout. value in ms */987 u16 missing_tx_completion_timeout;988 989 u16 missed_tx_completion_count_threshold_to_reset;990 991 /* value in ms */992 u16 admin_completion_tx_timeout;993 994 u16 netdev_wd_timeout;995 996 u16 max_tx_sgl_size;997 998 u16 max_rx_sgl_size;999 1000 u16 reserved[8];1001};1002 1003struct ena_admin_get_feat_cmd {1004 struct ena_admin_aq_common_desc aq_common_descriptor;1005 1006 struct ena_admin_ctrl_buff_info control_buffer;1007 1008 struct ena_admin_get_set_feature_common_desc feat_common;1009 1010 u32 raw[11];1011};1012 1013struct ena_admin_queue_ext_feature_desc {1014 /* version */1015 u8 version;1016 1017 u8 reserved1[3];1018 1019 union {1020 struct ena_admin_queue_ext_feature_fields max_queue_ext;1021 1022 u32 raw[10];1023 };1024};1025 1026struct ena_admin_get_feat_resp {1027 struct ena_admin_acq_common_desc acq_common_desc;1028 1029 union {1030 u32 raw[14];1031 1032 struct ena_admin_device_attr_feature_desc dev_attr;1033 1034 struct ena_admin_feature_llq_desc llq;1035 1036 struct ena_admin_queue_feature_desc max_queue;1037 1038 struct ena_admin_queue_ext_feature_desc max_queue_ext;1039 1040 struct ena_admin_feature_aenq_desc aenq;1041 1042 struct ena_admin_get_feature_link_desc link;1043 1044 struct ena_admin_feature_offload_desc offload;1045 1046 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;1047 1048 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;1049 1050 struct ena_admin_feature_rss_ind_table ind_table;1051 1052 struct ena_admin_feature_intr_moder_desc intr_moderation;1053 1054 struct ena_admin_ena_hw_hints hw_hints;1055 } u;1056};1057 1058struct ena_admin_set_feat_cmd {1059 struct ena_admin_aq_common_desc aq_common_descriptor;1060 1061 struct ena_admin_ctrl_buff_info control_buffer;1062 1063 struct ena_admin_get_set_feature_common_desc feat_common;1064 1065 union {1066 u32 raw[11];1067 1068 /* mtu size */1069 struct ena_admin_set_feature_mtu_desc mtu;1070 1071 /* host attributes */1072 struct ena_admin_set_feature_host_attr_desc host_attr;1073 1074 /* AENQ configuration */1075 struct ena_admin_feature_aenq_desc aenq;1076 1077 /* rss flow hash function */1078 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;1079 1080 /* rss flow hash input */1081 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;1082 1083 /* rss indirection table */1084 struct ena_admin_feature_rss_ind_table ind_table;1085 1086 /* LLQ configuration */1087 struct ena_admin_feature_llq_desc llq;1088 } u;1089};1090 1091struct ena_admin_set_feat_resp {1092 struct ena_admin_acq_common_desc acq_common_desc;1093 1094 union {1095 u32 raw[14];1096 } u;1097};1098 1099struct ena_admin_aenq_common_desc {1100 u16 group;1101 1102 u16 syndrome;1103 1104 /* 0 : phase1105 * 7:1 : reserved - MBZ1106 */1107 u8 flags;1108 1109 u8 reserved1[3];1110 1111 u32 timestamp_low;1112 1113 u32 timestamp_high;1114};1115 1116/* asynchronous event notification groups */1117enum ena_admin_aenq_group {1118 ENA_ADMIN_LINK_CHANGE = 0,1119 ENA_ADMIN_FATAL_ERROR = 1,1120 ENA_ADMIN_WARNING = 2,1121 ENA_ADMIN_NOTIFICATION = 3,1122 ENA_ADMIN_KEEP_ALIVE = 4,1123 ENA_ADMIN_AENQ_GROUPS_NUM = 5,1124};1125 1126enum ena_admin_aenq_notification_syndrome {1127 ENA_ADMIN_UPDATE_HINTS = 2,1128};1129 1130struct ena_admin_aenq_entry {1131 struct ena_admin_aenq_common_desc aenq_common_desc;1132 1133 /* command specific inline data */1134 u32 inline_data_w4[12];1135};1136 1137struct ena_admin_aenq_link_change_desc {1138 struct ena_admin_aenq_common_desc aenq_common_desc;1139 1140 /* 0 : link_status */1141 u32 flags;1142};1143 1144struct ena_admin_aenq_keep_alive_desc {1145 struct ena_admin_aenq_common_desc aenq_common_desc;1146 1147 u32 rx_drops_low;1148 1149 u32 rx_drops_high;1150 1151 u32 tx_drops_low;1152 1153 u32 tx_drops_high;1154};1155 1156struct ena_admin_ena_mmio_req_read_less_resp {1157 u16 req_id;1158 1159 u16 reg_off;1160 1161 /* value is valid when poll is cleared */1162 u32 reg_val;1163};1164 1165/* aq_common_desc */1166#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)1167#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)1168#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 11169#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)1170#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 21171#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)1172 1173/* sq */1174#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 51175#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)1176 1177/* acq_common_desc */1178#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)1179#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)1180 1181/* aq_create_sq_cmd */1182#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 51183#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)1184#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)1185#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 41186#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)1187#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)1188 1189/* aq_create_cq_cmd */1190#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 51191#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)1192#define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)1193 1194/* get_set_feature_common_desc */1195#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)1196 1197/* get_feature_link_desc */1198#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)1199#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 11200#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)1201 1202/* feature_offload_desc */1203#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)1204#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 11205#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)1206#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 21207#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)1208#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 31209#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)1210#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 41211#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)1212#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 51213#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)1214#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 61215#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)1216#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 71217#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)1218#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)1219#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 11220#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)1221#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 21222#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)1223#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 31224#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)1225 1226/* feature_rss_flow_hash_function */1227#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)1228#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)1229 1230/* feature_rss_flow_hash_input */1231#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 11232#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)1233#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 21234#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)1235#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 11236#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)1237#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 21238#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)1239 1240/* host_info */1241#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)1242#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 81243#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)1244#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 161245#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)1246#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 241247#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)1248#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)1249#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 31250#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)1251#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 81252#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)1253#define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 11254#define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1)1255#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 21256#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)1257#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 31258#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3)1259#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 41260#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)1261#define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT 61262#define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6)1263 1264/* aenq_common_desc */1265#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)1266 1267/* aenq_link_change_desc */1268#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)1269 1270#endif /* _ENA_ADMIN_H_ */1271