133 lines · c
1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */2/*3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.4 */5#ifndef _ENA_REGS_H_6#define _ENA_REGS_H_7 8enum ena_regs_reset_reason_types {9 ENA_REGS_RESET_NORMAL = 0,10 ENA_REGS_RESET_KEEP_ALIVE_TO = 1,11 ENA_REGS_RESET_ADMIN_TO = 2,12 ENA_REGS_RESET_MISS_TX_CMPL = 3,13 ENA_REGS_RESET_INV_RX_REQ_ID = 4,14 ENA_REGS_RESET_INV_TX_REQ_ID = 5,15 ENA_REGS_RESET_TOO_MANY_RX_DESCS = 6,16 ENA_REGS_RESET_INIT_ERR = 7,17 ENA_REGS_RESET_DRIVER_INVALID_STATE = 8,18 ENA_REGS_RESET_OS_TRIGGER = 9,19 ENA_REGS_RESET_OS_NETDEV_WD = 10,20 ENA_REGS_RESET_SHUTDOWN = 11,21 ENA_REGS_RESET_USER_TRIGGER = 12,22 ENA_REGS_RESET_GENERIC = 13,23 ENA_REGS_RESET_MISS_INTERRUPT = 14,24 ENA_REGS_RESET_SUSPECTED_POLL_STARVATION = 15,25 ENA_REGS_RESET_RX_DESCRIPTOR_MALFORMED = 16,26};27 28/* ena_registers offsets */29 30/* 0 base */31#define ENA_REGS_VERSION_OFF 0x032#define ENA_REGS_CONTROLLER_VERSION_OFF 0x433#define ENA_REGS_CAPS_OFF 0x834#define ENA_REGS_CAPS_EXT_OFF 0xc35#define ENA_REGS_AQ_BASE_LO_OFF 0x1036#define ENA_REGS_AQ_BASE_HI_OFF 0x1437#define ENA_REGS_AQ_CAPS_OFF 0x1838#define ENA_REGS_ACQ_BASE_LO_OFF 0x2039#define ENA_REGS_ACQ_BASE_HI_OFF 0x2440#define ENA_REGS_ACQ_CAPS_OFF 0x2841#define ENA_REGS_AQ_DB_OFF 0x2c42#define ENA_REGS_ACQ_TAIL_OFF 0x3043#define ENA_REGS_AENQ_CAPS_OFF 0x3444#define ENA_REGS_AENQ_BASE_LO_OFF 0x3845#define ENA_REGS_AENQ_BASE_HI_OFF 0x3c46#define ENA_REGS_AENQ_HEAD_DB_OFF 0x4047#define ENA_REGS_AENQ_TAIL_OFF 0x4448#define ENA_REGS_INTR_MASK_OFF 0x4c49#define ENA_REGS_DEV_CTL_OFF 0x5450#define ENA_REGS_DEV_STS_OFF 0x5851#define ENA_REGS_MMIO_REG_READ_OFF 0x5c52#define ENA_REGS_MMIO_RESP_LO_OFF 0x6053#define ENA_REGS_MMIO_RESP_HI_OFF 0x6454#define ENA_REGS_RSS_IND_ENTRY_UPDATE_OFF 0x6855 56/* version register */57#define ENA_REGS_VERSION_MINOR_VERSION_MASK 0xff58#define ENA_REGS_VERSION_MAJOR_VERSION_SHIFT 859#define ENA_REGS_VERSION_MAJOR_VERSION_MASK 0xff0060 61/* controller_version register */62#define ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff63#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT 864#define ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff0065#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT 1666#define ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff000067#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT 2468#define ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff00000069 70/* caps register */71#define ENA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x172#define ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT 173#define ENA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e74#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT 875#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff0076#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT 1677#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf000078 79/* aq_caps register */80#define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff81#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT 1682#define ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff000083 84/* acq_caps register */85#define ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff86#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT 1687#define ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xffff000088 89/* aenq_caps register */90#define ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff91#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT 1692#define ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xffff000093 94/* dev_ctl register */95#define ENA_REGS_DEV_CTL_DEV_RESET_MASK 0x196#define ENA_REGS_DEV_CTL_AQ_RESTART_SHIFT 197#define ENA_REGS_DEV_CTL_AQ_RESTART_MASK 0x298#define ENA_REGS_DEV_CTL_QUIESCENT_SHIFT 299#define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4100#define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT 3101#define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8102#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT 28103#define ENA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000104 105/* dev_sts register */106#define ENA_REGS_DEV_STS_READY_MASK 0x1107#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1108#define ENA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2109#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2110#define ENA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4111#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_SHIFT 3112#define ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8113#define ENA_REGS_DEV_STS_RESET_FINISHED_SHIFT 4114#define ENA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10115#define ENA_REGS_DEV_STS_FATAL_ERROR_SHIFT 5116#define ENA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20117#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT 6118#define ENA_REGS_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40119#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT 7120#define ENA_REGS_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80121 122/* mmio_reg_read register */123#define ENA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff124#define ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT 16125#define ENA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000126 127/* rss_ind_entry_update register */128#define ENA_REGS_RSS_IND_ENTRY_UPDATE_INDEX_MASK 0xffff129#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_SHIFT 16130#define ENA_REGS_RSS_IND_ENTRY_UPDATE_CQ_IDX_MASK 0xffff0000131 132#endif /* _ENA_REGS_H_ */133