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1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */2/*3 * Copyright 1996-1999 Thomas Bogendoerfer4 *5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.6 *7 * Copyright 1993 United States Government as represented by the8 * Director, National Security Agency.9 *10 * This software may be used and distributed according to the terms11 * of the GNU General Public License, incorporated herein by reference.12 *13 * This driver is for PCnet32 and PCnetPCI based ethercards14 */15/**************************************************************************16 * 23 Oct, 2000.17 * Fixed a few bugs, related to running the controller in 32bit mode.18 *19 * Carsten Langgaard, carstenl@mips.com20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.21 *22 *************************************************************************/23 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt25 26#define DRV_NAME "pcnet32"27#define DRV_RELDATE "21.Apr.2008"28#define PFX DRV_NAME ": "29 30#include <linux/module.h>31#include <linux/kernel.h>32#include <linux/sched.h>33#include <linux/string.h>34#include <linux/errno.h>35#include <linux/ioport.h>36#include <linux/slab.h>37#include <linux/interrupt.h>38#include <linux/pci.h>39#include <linux/delay.h>40#include <linux/init.h>41#include <linux/ethtool.h>42#include <linux/mii.h>43#include <linux/crc32.h>44#include <linux/netdevice.h>45#include <linux/etherdevice.h>46#include <linux/if_ether.h>47#include <linux/skbuff.h>48#include <linux/spinlock.h>49#include <linux/moduleparam.h>50#include <linux/bitops.h>51#include <linux/io.h>52#include <linux/uaccess.h>53 54#include <asm/dma.h>55#include <asm/irq.h>56 57/*58 * PCI device identifiers for "new style" Linux PCI Device Drivers59 */60static const struct pci_device_id pcnet32_pci_tbl[] = {61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },63 64 /*65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have66 * the incorrect vendor id.67 */68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },70 71 { } /* terminate list */72};73 74MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);75 76static int cards_found;77 78/*79 * VLB I/O addresses80 */81static unsigned int pcnet32_portlist[] =82 { 0x300, 0x320, 0x340, 0x360, 0 };83 84static int pcnet32_debug;85static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */86static int pcnet32vlb; /* check for VLB cards ? */87 88static struct net_device *pcnet32_dev;89 90static int max_interrupt_work = 2;91static int rx_copybreak = 200;92 93#define PCNET32_PORT_AUI 0x0094#define PCNET32_PORT_10BT 0x0195#define PCNET32_PORT_GPSI 0x0296#define PCNET32_PORT_MII 0x0397 98#define PCNET32_PORT_PORTSEL 0x0399#define PCNET32_PORT_ASEL 0x04100#define PCNET32_PORT_100 0x40101#define PCNET32_PORT_FD 0x80102 103#define PCNET32_DMA_MASK 0xffffffff104 105#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))106#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))107 108/*109 * table to translate option values from tulip110 * to internal options111 */112static const unsigned char options_mapping[] = {113 PCNET32_PORT_ASEL, /* 0 Auto-select */114 PCNET32_PORT_AUI, /* 1 BNC/AUI */115 PCNET32_PORT_AUI, /* 2 AUI/BNC */116 PCNET32_PORT_ASEL, /* 3 not supported */117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */118 PCNET32_PORT_ASEL, /* 5 not supported */119 PCNET32_PORT_ASEL, /* 6 not supported */120 PCNET32_PORT_ASEL, /* 7 not supported */121 PCNET32_PORT_ASEL, /* 8 not supported */122 PCNET32_PORT_MII, /* 9 MII 10baseT */123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */124 PCNET32_PORT_MII, /* 11 MII (autosel) */125 PCNET32_PORT_10BT, /* 12 10BaseT */126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */127 /* 14 MII 100BaseTx-FD */128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,129 PCNET32_PORT_ASEL /* 15 not supported */130};131 132static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {133 "Loopback test (offline)"134};135 136#define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)137 138#define PCNET32_NUM_REGS 136139 140#define MAX_UNITS 8 /* More are supported, limit only on options */141static int options[MAX_UNITS];142static int full_duplex[MAX_UNITS];143static int homepna[MAX_UNITS];144 145/*146 * Theory of Operation147 *148 * This driver uses the same software structure as the normal lance149 * driver. So look for a verbose description in lance.c. The differences150 * to the normal lance driver is the use of the 32bit mode of PCnet32151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no152 * 16MB limitation and we don't need bounce buffers.153 */154 155/*156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).159 */160#ifndef PCNET32_LOG_TX_BUFFERS161#define PCNET32_LOG_TX_BUFFERS 4162#define PCNET32_LOG_RX_BUFFERS 5163#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */164#define PCNET32_LOG_MAX_RX_BUFFERS 9165#endif166 167#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))168#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))169 170#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))171#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))172 173#define PKT_BUF_SKB 1544174/* actual buffer length after being aligned */175#define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)176/* chip wants twos complement of the (aligned) buffer length */177#define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)178 179/* Offsets from base I/O address. */180#define PCNET32_WIO_RDP 0x10181#define PCNET32_WIO_RAP 0x12182#define PCNET32_WIO_RESET 0x14183#define PCNET32_WIO_BDP 0x16184 185#define PCNET32_DWIO_RDP 0x10186#define PCNET32_DWIO_RAP 0x14187#define PCNET32_DWIO_RESET 0x18188#define PCNET32_DWIO_BDP 0x1C189 190#define PCNET32_TOTAL_SIZE 0x20191 192#define CSR0 0193#define CSR0_INIT 0x1194#define CSR0_START 0x2195#define CSR0_STOP 0x4196#define CSR0_TXPOLL 0x8197#define CSR0_INTEN 0x40198#define CSR0_IDON 0x0100199#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)200#define PCNET32_INIT_LOW 1201#define PCNET32_INIT_HIGH 2202#define CSR3 3203#define CSR4 4204#define CSR5 5205#define CSR5_SUSPEND 0x0001206#define CSR15 15207#define PCNET32_MC_FILTER 8208 209#define PCNET32_79C970A 0x2621210 211/* The PCNET32 Rx and Tx ring descriptors. */212struct pcnet32_rx_head {213 __le32 base;214 __le16 buf_length; /* two`s complement of length */215 __le16 status;216 __le32 msg_length;217 __le32 reserved;218};219 220struct pcnet32_tx_head {221 __le32 base;222 __le16 length; /* two`s complement of length */223 __le16 status;224 __le32 misc;225 __le32 reserved;226};227 228/* The PCNET32 32-Bit initialization block, described in databook. */229struct pcnet32_init_block {230 __le16 mode;231 __le16 tlen_rlen;232 u8 phys_addr[6];233 __le16 reserved;234 __le32 filter[2];235 /* Receive and transmit ring base, along with extra bits. */236 __le32 rx_ring;237 __le32 tx_ring;238};239 240/* PCnet32 access functions */241struct pcnet32_access {242 u16 (*read_csr) (unsigned long, int);243 void (*write_csr) (unsigned long, int, u16);244 u16 (*read_bcr) (unsigned long, int);245 void (*write_bcr) (unsigned long, int, u16);246 u16 (*read_rap) (unsigned long);247 void (*write_rap) (unsigned long, u16);248 void (*reset) (unsigned long);249};250 251/*252 * The first field of pcnet32_private is read by the ethernet device253 * so the structure should be allocated using dma_alloc_coherent().254 */255struct pcnet32_private {256 struct pcnet32_init_block *init_block;257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */258 struct pcnet32_rx_head *rx_ring;259 struct pcnet32_tx_head *tx_ring;260 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,261 returned by dma_alloc_coherent */262 struct pci_dev *pci_dev;263 const char *name;264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */265 struct sk_buff **tx_skbuff;266 struct sk_buff **rx_skbuff;267 dma_addr_t *tx_dma_addr;268 dma_addr_t *rx_dma_addr;269 const struct pcnet32_access *a;270 spinlock_t lock; /* Guard lock */271 unsigned int cur_rx, cur_tx; /* The next free ring entry */272 unsigned int rx_ring_size; /* current rx ring size */273 unsigned int tx_ring_size; /* current tx ring size */274 unsigned int rx_mod_mask; /* rx ring modular mask */275 unsigned int tx_mod_mask; /* tx ring modular mask */276 unsigned short rx_len_bits;277 unsigned short tx_len_bits;278 dma_addr_t rx_ring_dma_addr;279 dma_addr_t tx_ring_dma_addr;280 unsigned int dirty_rx, /* ring entries to be freed. */281 dirty_tx;282 283 struct net_device *dev;284 struct napi_struct napi;285 char tx_full;286 char phycount; /* number of phys found */287 int options;288 unsigned int shared_irq:1, /* shared irq possible */289 dxsuflo:1, /* disable transmit stop on uflo */290 mii:1, /* mii port available */291 autoneg:1, /* autoneg enabled */292 port_tp:1, /* port set to TP */293 fdx:1; /* full duplex enabled */294 struct net_device *next;295 struct mii_if_info mii_if;296 struct timer_list watchdog_timer;297 u32 msg_enable; /* debug message level */298 299 /* each bit indicates an available PHY */300 u32 phymask;301 unsigned short chip_version; /* which variant this is */302 303 /* saved registers during ethtool blink */304 u16 save_regs[4];305};306 307static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);308static int pcnet32_probe1(unsigned long, int, struct pci_dev *);309static int pcnet32_open(struct net_device *);310static int pcnet32_init_ring(struct net_device *);311static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,312 struct net_device *);313static void pcnet32_tx_timeout(struct net_device *dev, unsigned int txqueue);314static irqreturn_t pcnet32_interrupt(int, void *);315static int pcnet32_close(struct net_device *);316static struct net_device_stats *pcnet32_get_stats(struct net_device *);317static void pcnet32_load_multicast(struct net_device *dev);318static void pcnet32_set_multicast_list(struct net_device *);319static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);320static void pcnet32_watchdog(struct timer_list *);321static int mdio_read(struct net_device *dev, int phy_id, int reg_num);322static void mdio_write(struct net_device *dev, int phy_id, int reg_num,323 int val);324static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);325static void pcnet32_ethtool_test(struct net_device *dev,326 struct ethtool_test *eth_test, u64 * data);327static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);328static int pcnet32_get_regs_len(struct net_device *dev);329static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,330 void *ptr);331static void pcnet32_purge_tx_ring(struct net_device *dev);332static int pcnet32_alloc_ring(struct net_device *dev, const char *name);333static void pcnet32_free_ring(struct net_device *dev);334static void pcnet32_check_media(struct net_device *dev, int verbose);335 336static u16 pcnet32_wio_read_csr(unsigned long addr, int index)337{338 outw(index, addr + PCNET32_WIO_RAP);339 return inw(addr + PCNET32_WIO_RDP);340}341 342static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)343{344 outw(index, addr + PCNET32_WIO_RAP);345 outw(val, addr + PCNET32_WIO_RDP);346}347 348static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)349{350 outw(index, addr + PCNET32_WIO_RAP);351 return inw(addr + PCNET32_WIO_BDP);352}353 354static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)355{356 outw(index, addr + PCNET32_WIO_RAP);357 outw(val, addr + PCNET32_WIO_BDP);358}359 360static u16 pcnet32_wio_read_rap(unsigned long addr)361{362 return inw(addr + PCNET32_WIO_RAP);363}364 365static void pcnet32_wio_write_rap(unsigned long addr, u16 val)366{367 outw(val, addr + PCNET32_WIO_RAP);368}369 370static void pcnet32_wio_reset(unsigned long addr)371{372 inw(addr + PCNET32_WIO_RESET);373}374 375static int pcnet32_wio_check(unsigned long addr)376{377 outw(88, addr + PCNET32_WIO_RAP);378 return inw(addr + PCNET32_WIO_RAP) == 88;379}380 381static const struct pcnet32_access pcnet32_wio = {382 .read_csr = pcnet32_wio_read_csr,383 .write_csr = pcnet32_wio_write_csr,384 .read_bcr = pcnet32_wio_read_bcr,385 .write_bcr = pcnet32_wio_write_bcr,386 .read_rap = pcnet32_wio_read_rap,387 .write_rap = pcnet32_wio_write_rap,388 .reset = pcnet32_wio_reset389};390 391static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)392{393 outl(index, addr + PCNET32_DWIO_RAP);394 return inl(addr + PCNET32_DWIO_RDP) & 0xffff;395}396 397static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)398{399 outl(index, addr + PCNET32_DWIO_RAP);400 outl(val, addr + PCNET32_DWIO_RDP);401}402 403static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)404{405 outl(index, addr + PCNET32_DWIO_RAP);406 return inl(addr + PCNET32_DWIO_BDP) & 0xffff;407}408 409static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)410{411 outl(index, addr + PCNET32_DWIO_RAP);412 outl(val, addr + PCNET32_DWIO_BDP);413}414 415static u16 pcnet32_dwio_read_rap(unsigned long addr)416{417 return inl(addr + PCNET32_DWIO_RAP) & 0xffff;418}419 420static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)421{422 outl(val, addr + PCNET32_DWIO_RAP);423}424 425static void pcnet32_dwio_reset(unsigned long addr)426{427 inl(addr + PCNET32_DWIO_RESET);428}429 430static int pcnet32_dwio_check(unsigned long addr)431{432 outl(88, addr + PCNET32_DWIO_RAP);433 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88;434}435 436static const struct pcnet32_access pcnet32_dwio = {437 .read_csr = pcnet32_dwio_read_csr,438 .write_csr = pcnet32_dwio_write_csr,439 .read_bcr = pcnet32_dwio_read_bcr,440 .write_bcr = pcnet32_dwio_write_bcr,441 .read_rap = pcnet32_dwio_read_rap,442 .write_rap = pcnet32_dwio_write_rap,443 .reset = pcnet32_dwio_reset444};445 446static void pcnet32_netif_stop(struct net_device *dev)447{448 struct pcnet32_private *lp = netdev_priv(dev);449 450 netif_trans_update(dev); /* prevent tx timeout */451 napi_disable(&lp->napi);452 netif_tx_disable(dev);453}454 455static void pcnet32_netif_start(struct net_device *dev)456{457 struct pcnet32_private *lp = netdev_priv(dev);458 ulong ioaddr = dev->base_addr;459 u16 val;460 461 netif_wake_queue(dev);462 val = lp->a->read_csr(ioaddr, CSR3);463 val &= 0x00ff;464 lp->a->write_csr(ioaddr, CSR3, val);465 napi_enable(&lp->napi);466}467 468/*469 * Allocate space for the new sized tx ring.470 * Free old resources471 * Save new resources.472 * Any failure keeps old resources.473 * Must be called with lp->lock held.474 */475static void pcnet32_realloc_tx_ring(struct net_device *dev,476 struct pcnet32_private *lp,477 unsigned int size)478{479 dma_addr_t new_ring_dma_addr;480 dma_addr_t *new_dma_addr_list;481 struct pcnet32_tx_head *new_tx_ring;482 struct sk_buff **new_skb_list;483 unsigned int entries = BIT(size);484 485 pcnet32_purge_tx_ring(dev);486 487 new_tx_ring =488 dma_alloc_coherent(&lp->pci_dev->dev,489 sizeof(struct pcnet32_tx_head) * entries,490 &new_ring_dma_addr, GFP_ATOMIC);491 if (!new_tx_ring)492 return;493 494 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);495 if (!new_dma_addr_list)496 goto free_new_tx_ring;497 498 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);499 if (!new_skb_list)500 goto free_new_lists;501 502 kfree(lp->tx_skbuff);503 kfree(lp->tx_dma_addr);504 dma_free_coherent(&lp->pci_dev->dev,505 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,506 lp->tx_ring, lp->tx_ring_dma_addr);507 508 lp->tx_ring_size = entries;509 lp->tx_mod_mask = lp->tx_ring_size - 1;510 lp->tx_len_bits = (size << 12);511 lp->tx_ring = new_tx_ring;512 lp->tx_ring_dma_addr = new_ring_dma_addr;513 lp->tx_dma_addr = new_dma_addr_list;514 lp->tx_skbuff = new_skb_list;515 return;516 517free_new_lists:518 kfree(new_dma_addr_list);519free_new_tx_ring:520 dma_free_coherent(&lp->pci_dev->dev,521 sizeof(struct pcnet32_tx_head) * entries,522 new_tx_ring, new_ring_dma_addr);523}524 525/*526 * Allocate space for the new sized rx ring.527 * Re-use old receive buffers.528 * alloc extra buffers529 * free unneeded buffers530 * free unneeded buffers531 * Save new resources.532 * Any failure keeps old resources.533 * Must be called with lp->lock held.534 */535static void pcnet32_realloc_rx_ring(struct net_device *dev,536 struct pcnet32_private *lp,537 unsigned int size)538{539 dma_addr_t new_ring_dma_addr;540 dma_addr_t *new_dma_addr_list;541 struct pcnet32_rx_head *new_rx_ring;542 struct sk_buff **new_skb_list;543 int new, overlap;544 unsigned int entries = BIT(size);545 546 new_rx_ring =547 dma_alloc_coherent(&lp->pci_dev->dev,548 sizeof(struct pcnet32_rx_head) * entries,549 &new_ring_dma_addr, GFP_ATOMIC);550 if (!new_rx_ring)551 return;552 553 new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);554 if (!new_dma_addr_list)555 goto free_new_rx_ring;556 557 new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);558 if (!new_skb_list)559 goto free_new_lists;560 561 /* first copy the current receive buffers */562 overlap = min(entries, lp->rx_ring_size);563 for (new = 0; new < overlap; new++) {564 new_rx_ring[new] = lp->rx_ring[new];565 new_dma_addr_list[new] = lp->rx_dma_addr[new];566 new_skb_list[new] = lp->rx_skbuff[new];567 }568 /* now allocate any new buffers needed */569 for (; new < entries; new++) {570 struct sk_buff *rx_skbuff;571 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB);572 rx_skbuff = new_skb_list[new];573 if (!rx_skbuff) {574 /* keep the original lists and buffers */575 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",576 __func__);577 goto free_all_new;578 }579 skb_reserve(rx_skbuff, NET_IP_ALIGN);580 581 new_dma_addr_list[new] =582 dma_map_single(&lp->pci_dev->dev, rx_skbuff->data,583 PKT_BUF_SIZE, DMA_FROM_DEVICE);584 if (dma_mapping_error(&lp->pci_dev->dev, new_dma_addr_list[new])) {585 netif_err(lp, drv, dev, "%s dma mapping failed\n",586 __func__);587 dev_kfree_skb(new_skb_list[new]);588 goto free_all_new;589 }590 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);591 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);592 new_rx_ring[new].status = cpu_to_le16(0x8000);593 }594 /* and free any unneeded buffers */595 for (; new < lp->rx_ring_size; new++) {596 if (lp->rx_skbuff[new]) {597 if (!dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[new]))598 dma_unmap_single(&lp->pci_dev->dev,599 lp->rx_dma_addr[new],600 PKT_BUF_SIZE,601 DMA_FROM_DEVICE);602 dev_kfree_skb(lp->rx_skbuff[new]);603 }604 }605 606 kfree(lp->rx_skbuff);607 kfree(lp->rx_dma_addr);608 dma_free_coherent(&lp->pci_dev->dev,609 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,610 lp->rx_ring, lp->rx_ring_dma_addr);611 612 lp->rx_ring_size = entries;613 lp->rx_mod_mask = lp->rx_ring_size - 1;614 lp->rx_len_bits = (size << 4);615 lp->rx_ring = new_rx_ring;616 lp->rx_ring_dma_addr = new_ring_dma_addr;617 lp->rx_dma_addr = new_dma_addr_list;618 lp->rx_skbuff = new_skb_list;619 return;620 621free_all_new:622 while (--new >= lp->rx_ring_size) {623 if (new_skb_list[new]) {624 if (!dma_mapping_error(&lp->pci_dev->dev, new_dma_addr_list[new]))625 dma_unmap_single(&lp->pci_dev->dev,626 new_dma_addr_list[new],627 PKT_BUF_SIZE,628 DMA_FROM_DEVICE);629 dev_kfree_skb(new_skb_list[new]);630 }631 }632 kfree(new_skb_list);633free_new_lists:634 kfree(new_dma_addr_list);635free_new_rx_ring:636 dma_free_coherent(&lp->pci_dev->dev,637 sizeof(struct pcnet32_rx_head) * entries,638 new_rx_ring, new_ring_dma_addr);639}640 641static void pcnet32_purge_rx_ring(struct net_device *dev)642{643 struct pcnet32_private *lp = netdev_priv(dev);644 int i;645 646 /* free all allocated skbuffs */647 for (i = 0; i < lp->rx_ring_size; i++) {648 lp->rx_ring[i].status = 0; /* CPU owns buffer */649 wmb(); /* Make sure adapter sees owner change */650 if (lp->rx_skbuff[i]) {651 if (!dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[i]))652 dma_unmap_single(&lp->pci_dev->dev,653 lp->rx_dma_addr[i],654 PKT_BUF_SIZE,655 DMA_FROM_DEVICE);656 dev_kfree_skb_any(lp->rx_skbuff[i]);657 }658 lp->rx_skbuff[i] = NULL;659 lp->rx_dma_addr[i] = 0;660 }661}662 663#ifdef CONFIG_NET_POLL_CONTROLLER664static void pcnet32_poll_controller(struct net_device *dev)665{666 disable_irq(dev->irq);667 pcnet32_interrupt(0, dev);668 enable_irq(dev->irq);669}670#endif671 672/*673 * lp->lock must be held.674 */675static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,676 int can_sleep)677{678 int csr5;679 struct pcnet32_private *lp = netdev_priv(dev);680 const struct pcnet32_access *a = lp->a;681 ulong ioaddr = dev->base_addr;682 int ticks;683 684 /* really old chips have to be stopped. */685 if (lp->chip_version < PCNET32_79C970A)686 return 0;687 688 /* set SUSPEND (SPND) - CSR5 bit 0 */689 csr5 = a->read_csr(ioaddr, CSR5);690 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);691 692 /* poll waiting for bit to be set */693 ticks = 0;694 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {695 spin_unlock_irqrestore(&lp->lock, *flags);696 if (can_sleep)697 msleep(1);698 else699 mdelay(1);700 spin_lock_irqsave(&lp->lock, *flags);701 ticks++;702 if (ticks > 200) {703 netif_printk(lp, hw, KERN_DEBUG, dev,704 "Error getting into suspend!\n");705 return 0;706 }707 }708 return 1;709}710 711static void pcnet32_clr_suspend(struct pcnet32_private *lp, ulong ioaddr)712{713 int csr5 = lp->a->read_csr(ioaddr, CSR5);714 /* clear SUSPEND (SPND) - CSR5 bit 0 */715 lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND);716}717 718static int pcnet32_get_link_ksettings(struct net_device *dev,719 struct ethtool_link_ksettings *cmd)720{721 struct pcnet32_private *lp = netdev_priv(dev);722 unsigned long flags;723 724 spin_lock_irqsave(&lp->lock, flags);725 if (lp->mii) {726 mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);727 } else if (lp->chip_version == PCNET32_79C970A) {728 if (lp->autoneg) {729 cmd->base.autoneg = AUTONEG_ENABLE;730 if (lp->a->read_bcr(dev->base_addr, 4) == 0xc0)731 cmd->base.port = PORT_AUI;732 else733 cmd->base.port = PORT_TP;734 } else {735 cmd->base.autoneg = AUTONEG_DISABLE;736 cmd->base.port = lp->port_tp ? PORT_TP : PORT_AUI;737 }738 cmd->base.duplex = lp->fdx ? DUPLEX_FULL : DUPLEX_HALF;739 cmd->base.speed = SPEED_10;740 ethtool_convert_legacy_u32_to_link_mode(741 cmd->link_modes.supported,742 SUPPORTED_TP | SUPPORTED_AUI);743 }744 spin_unlock_irqrestore(&lp->lock, flags);745 return 0;746}747 748static int pcnet32_set_link_ksettings(struct net_device *dev,749 const struct ethtool_link_ksettings *cmd)750{751 struct pcnet32_private *lp = netdev_priv(dev);752 ulong ioaddr = dev->base_addr;753 unsigned long flags;754 int r = -EOPNOTSUPP;755 int suspended, bcr2, bcr9, csr15;756 757 spin_lock_irqsave(&lp->lock, flags);758 if (lp->mii) {759 r = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);760 } else if (lp->chip_version == PCNET32_79C970A) {761 suspended = pcnet32_suspend(dev, &flags, 0);762 if (!suspended)763 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);764 765 lp->autoneg = cmd->base.autoneg == AUTONEG_ENABLE;766 bcr2 = lp->a->read_bcr(ioaddr, 2);767 if (cmd->base.autoneg == AUTONEG_ENABLE) {768 lp->a->write_bcr(ioaddr, 2, bcr2 | 0x0002);769 } else {770 lp->a->write_bcr(ioaddr, 2, bcr2 & ~0x0002);771 772 lp->port_tp = cmd->base.port == PORT_TP;773 csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180;774 if (cmd->base.port == PORT_TP)775 csr15 |= 0x0080;776 lp->a->write_csr(ioaddr, CSR15, csr15);777 lp->init_block->mode = cpu_to_le16(csr15);778 779 lp->fdx = cmd->base.duplex == DUPLEX_FULL;780 bcr9 = lp->a->read_bcr(ioaddr, 9) & ~0x0003;781 if (cmd->base.duplex == DUPLEX_FULL)782 bcr9 |= 0x0003;783 lp->a->write_bcr(ioaddr, 9, bcr9);784 }785 if (suspended)786 pcnet32_clr_suspend(lp, ioaddr);787 else if (netif_running(dev))788 pcnet32_restart(dev, CSR0_NORMAL);789 r = 0;790 }791 spin_unlock_irqrestore(&lp->lock, flags);792 return r;793}794 795static void pcnet32_get_drvinfo(struct net_device *dev,796 struct ethtool_drvinfo *info)797{798 struct pcnet32_private *lp = netdev_priv(dev);799 800 strscpy(info->driver, DRV_NAME, sizeof(info->driver));801 if (lp->pci_dev)802 strscpy(info->bus_info, pci_name(lp->pci_dev),803 sizeof(info->bus_info));804 else805 snprintf(info->bus_info, sizeof(info->bus_info),806 "VLB 0x%lx", dev->base_addr);807}808 809static u32 pcnet32_get_link(struct net_device *dev)810{811 struct pcnet32_private *lp = netdev_priv(dev);812 unsigned long flags;813 int r;814 815 spin_lock_irqsave(&lp->lock, flags);816 if (lp->mii) {817 r = mii_link_ok(&lp->mii_if);818 } else if (lp->chip_version == PCNET32_79C970A) {819 ulong ioaddr = dev->base_addr; /* card base I/O address */820 /* only read link if port is set to TP */821 if (!lp->autoneg && lp->port_tp)822 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);823 else /* link always up for AUI port or port auto select */824 r = 1;825 } else if (lp->chip_version > PCNET32_79C970A) {826 ulong ioaddr = dev->base_addr; /* card base I/O address */827 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);828 } else { /* can not detect link on really old chips */829 r = 1;830 }831 spin_unlock_irqrestore(&lp->lock, flags);832 833 return r;834}835 836static u32 pcnet32_get_msglevel(struct net_device *dev)837{838 struct pcnet32_private *lp = netdev_priv(dev);839 return lp->msg_enable;840}841 842static void pcnet32_set_msglevel(struct net_device *dev, u32 value)843{844 struct pcnet32_private *lp = netdev_priv(dev);845 lp->msg_enable = value;846}847 848static int pcnet32_nway_reset(struct net_device *dev)849{850 struct pcnet32_private *lp = netdev_priv(dev);851 unsigned long flags;852 int r = -EOPNOTSUPP;853 854 if (lp->mii) {855 spin_lock_irqsave(&lp->lock, flags);856 r = mii_nway_restart(&lp->mii_if);857 spin_unlock_irqrestore(&lp->lock, flags);858 }859 return r;860}861 862static void pcnet32_get_ringparam(struct net_device *dev,863 struct ethtool_ringparam *ering,864 struct kernel_ethtool_ringparam *kernel_ering,865 struct netlink_ext_ack *extack)866{867 struct pcnet32_private *lp = netdev_priv(dev);868 869 ering->tx_max_pending = TX_MAX_RING_SIZE;870 ering->tx_pending = lp->tx_ring_size;871 ering->rx_max_pending = RX_MAX_RING_SIZE;872 ering->rx_pending = lp->rx_ring_size;873}874 875static int pcnet32_set_ringparam(struct net_device *dev,876 struct ethtool_ringparam *ering,877 struct kernel_ethtool_ringparam *kernel_ering,878 struct netlink_ext_ack *extack)879{880 struct pcnet32_private *lp = netdev_priv(dev);881 unsigned long flags;882 unsigned int size;883 ulong ioaddr = dev->base_addr;884 int i;885 886 if (ering->rx_mini_pending || ering->rx_jumbo_pending)887 return -EINVAL;888 889 if (netif_running(dev))890 pcnet32_netif_stop(dev);891 892 spin_lock_irqsave(&lp->lock, flags);893 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */894 895 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);896 897 /* set the minimum ring size to 4, to allow the loopback test to work898 * unchanged.899 */900 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {901 if (size <= (1 << i))902 break;903 }904 if ((1 << i) != lp->tx_ring_size)905 pcnet32_realloc_tx_ring(dev, lp, i);906 907 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);908 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {909 if (size <= (1 << i))910 break;911 }912 if ((1 << i) != lp->rx_ring_size)913 pcnet32_realloc_rx_ring(dev, lp, i);914 915 lp->napi.weight = lp->rx_ring_size / 2;916 917 if (netif_running(dev)) {918 pcnet32_netif_start(dev);919 pcnet32_restart(dev, CSR0_NORMAL);920 }921 922 spin_unlock_irqrestore(&lp->lock, flags);923 924 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",925 lp->rx_ring_size, lp->tx_ring_size);926 927 return 0;928}929 930static void pcnet32_get_strings(struct net_device *dev, u32 stringset,931 u8 *data)932{933 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));934}935 936static int pcnet32_get_sset_count(struct net_device *dev, int sset)937{938 switch (sset) {939 case ETH_SS_TEST:940 return PCNET32_TEST_LEN;941 default:942 return -EOPNOTSUPP;943 }944}945 946static void pcnet32_ethtool_test(struct net_device *dev,947 struct ethtool_test *test, u64 * data)948{949 struct pcnet32_private *lp = netdev_priv(dev);950 int rc;951 952 if (test->flags == ETH_TEST_FL_OFFLINE) {953 rc = pcnet32_loopback_test(dev, data);954 if (rc) {955 netif_printk(lp, hw, KERN_DEBUG, dev,956 "Loopback test failed\n");957 test->flags |= ETH_TEST_FL_FAILED;958 } else959 netif_printk(lp, hw, KERN_DEBUG, dev,960 "Loopback test passed\n");961 } else962 netif_printk(lp, hw, KERN_DEBUG, dev,963 "No tests to run (specify 'Offline' on ethtool)\n");964} /* end pcnet32_ethtool_test */965 966static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)967{968 struct pcnet32_private *lp = netdev_priv(dev);969 const struct pcnet32_access *a = lp->a; /* access to registers */970 ulong ioaddr = dev->base_addr; /* card base I/O address */971 struct sk_buff *skb; /* sk buff */972 int x, i; /* counters */973 int numbuffs = 4; /* number of TX/RX buffers and descs */974 u16 status = 0x8300; /* TX ring status */975 __le16 teststatus; /* test of ring status */976 int rc; /* return code */977 int size; /* size of packets */978 unsigned char *packet; /* source packet data */979 static const int data_len = 60; /* length of source packets */980 unsigned long flags;981 unsigned long ticks;982 983 rc = 1; /* default to fail */984 985 if (netif_running(dev))986 pcnet32_netif_stop(dev);987 988 spin_lock_irqsave(&lp->lock, flags);989 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */990 991 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));992 993 /* Reset the PCNET32 */994 lp->a->reset(ioaddr);995 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */996 997 /* switch pcnet32 to 32bit mode */998 lp->a->write_bcr(ioaddr, 20, 2);999 1000 /* purge & init rings but don't actually restart */1001 pcnet32_restart(dev, 0x0000);1002 1003 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */1004 1005 /* Initialize Transmit buffers. */1006 size = data_len + 15;1007 for (x = 0; x < numbuffs; x++) {1008 skb = netdev_alloc_skb(dev, size);1009 if (!skb) {1010 netif_printk(lp, hw, KERN_DEBUG, dev,1011 "Cannot allocate skb at line: %d!\n",1012 __LINE__);1013 goto clean_up;1014 }1015 packet = skb->data;1016 skb_put(skb, size); /* create space for data */1017 lp->tx_skbuff[x] = skb;1018 lp->tx_ring[x].length = cpu_to_le16(-skb->len);1019 lp->tx_ring[x].misc = 0;1020 1021 /* put DA and SA into the skb */1022 for (i = 0; i < 6; i++)1023 *packet++ = dev->dev_addr[i];1024 for (i = 0; i < 6; i++)1025 *packet++ = dev->dev_addr[i];1026 /* type */1027 *packet++ = 0x08;1028 *packet++ = 0x06;1029 /* packet number */1030 *packet++ = x;1031 /* fill packet with data */1032 for (i = 0; i < data_len; i++)1033 *packet++ = i;1034 1035 lp->tx_dma_addr[x] =1036 dma_map_single(&lp->pci_dev->dev, skb->data, skb->len,1037 DMA_TO_DEVICE);1038 if (dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[x])) {1039 netif_printk(lp, hw, KERN_DEBUG, dev,1040 "DMA mapping error at line: %d!\n",1041 __LINE__);1042 goto clean_up;1043 }1044 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);1045 wmb(); /* Make sure owner changes after all others are visible */1046 lp->tx_ring[x].status = cpu_to_le16(status);1047 }1048 1049 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */1050 a->write_bcr(ioaddr, 32, x | 0x0002);1051 1052 /* set int loopback in CSR15 */1053 x = a->read_csr(ioaddr, CSR15) & 0xfffc;1054 lp->a->write_csr(ioaddr, CSR15, x | 0x0044);1055 1056 teststatus = cpu_to_le16(0x8000);1057 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */1058 1059 /* Check status of descriptors */1060 for (x = 0; x < numbuffs; x++) {1061 ticks = 0;1062 rmb();1063 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {1064 spin_unlock_irqrestore(&lp->lock, flags);1065 msleep(1);1066 spin_lock_irqsave(&lp->lock, flags);1067 rmb();1068 ticks++;1069 }1070 if (ticks == 200) {1071 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);1072 break;1073 }1074 }1075 1076 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */1077 wmb();1078 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {1079 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");1080 1081 for (x = 0; x < numbuffs; x++) {1082 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);1083 skb = lp->rx_skbuff[x];1084 for (i = 0; i < size; i++)1085 pr_cont(" %02x", *(skb->data + i));1086 pr_cont("\n");1087 }1088 }1089 1090 x = 0;1091 rc = 0;1092 while (x < numbuffs && !rc) {1093 skb = lp->rx_skbuff[x];1094 packet = lp->tx_skbuff[x]->data;1095 for (i = 0; i < size; i++) {1096 if (*(skb->data + i) != packet[i]) {1097 netif_printk(lp, hw, KERN_DEBUG, dev,1098 "Error in compare! %2x - %02x %02x\n",1099 i, *(skb->data + i), packet[i]);1100 rc = 1;1101 break;1102 }1103 }1104 x++;1105 }1106 1107clean_up:1108 *data1 = rc;1109 pcnet32_purge_tx_ring(dev);1110 1111 x = a->read_csr(ioaddr, CSR15);1112 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */1113 1114 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */1115 a->write_bcr(ioaddr, 32, (x & ~0x0002));1116 1117 if (netif_running(dev)) {1118 pcnet32_netif_start(dev);1119 pcnet32_restart(dev, CSR0_NORMAL);1120 } else {1121 pcnet32_purge_rx_ring(dev);1122 lp->a->write_bcr(ioaddr, 20, 4); /* return to 16bit mode */1123 }1124 spin_unlock_irqrestore(&lp->lock, flags);1125 1126 return rc;1127} /* end pcnet32_loopback_test */1128 1129static int pcnet32_set_phys_id(struct net_device *dev,1130 enum ethtool_phys_id_state state)1131{1132 struct pcnet32_private *lp = netdev_priv(dev);1133 const struct pcnet32_access *a = lp->a;1134 ulong ioaddr = dev->base_addr;1135 unsigned long flags;1136 int i;1137 1138 switch (state) {1139 case ETHTOOL_ID_ACTIVE:1140 /* Save the current value of the bcrs */1141 spin_lock_irqsave(&lp->lock, flags);1142 for (i = 4; i < 8; i++)1143 lp->save_regs[i - 4] = a->read_bcr(ioaddr, i);1144 spin_unlock_irqrestore(&lp->lock, flags);1145 return 2; /* cycle on/off twice per second */1146 1147 case ETHTOOL_ID_ON:1148 case ETHTOOL_ID_OFF:1149 /* Blink the led */1150 spin_lock_irqsave(&lp->lock, flags);1151 for (i = 4; i < 8; i++)1152 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);1153 spin_unlock_irqrestore(&lp->lock, flags);1154 break;1155 1156 case ETHTOOL_ID_INACTIVE:1157 /* Restore the original value of the bcrs */1158 spin_lock_irqsave(&lp->lock, flags);1159 for (i = 4; i < 8; i++)1160 a->write_bcr(ioaddr, i, lp->save_regs[i - 4]);1161 spin_unlock_irqrestore(&lp->lock, flags);1162 }1163 return 0;1164}1165 1166/*1167 * process one receive descriptor entry1168 */1169 1170static void pcnet32_rx_entry(struct net_device *dev,1171 struct pcnet32_private *lp,1172 struct pcnet32_rx_head *rxp,1173 int entry)1174{1175 int status = (short)le16_to_cpu(rxp->status) >> 8;1176 int rx_in_place = 0;1177 struct sk_buff *skb;1178 short pkt_len;1179 1180 if (status != 0x03) { /* There was an error. */1181 /*1182 * There is a tricky error noted by John Murphy,1183 * <murf@perftech.com> to Russ Nelson: Even with full-sized1184 * buffers it's possible for a jabber packet to use two1185 * buffers, with only the last correctly noting the error.1186 */1187 if (status & 0x01) /* Only count a general error at the */1188 dev->stats.rx_errors++; /* end of a packet. */1189 if (status & 0x20)1190 dev->stats.rx_frame_errors++;1191 if (status & 0x10)1192 dev->stats.rx_over_errors++;1193 if (status & 0x08)1194 dev->stats.rx_crc_errors++;1195 if (status & 0x04)1196 dev->stats.rx_fifo_errors++;1197 return;1198 }1199 1200 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;1201 1202 /* Discard oversize frames. */1203 if (unlikely(pkt_len > PKT_BUF_SIZE)) {1204 netif_err(lp, drv, dev, "Impossible packet size %d!\n",1205 pkt_len);1206 dev->stats.rx_errors++;1207 return;1208 }1209 if (pkt_len < 60) {1210 netif_err(lp, rx_err, dev, "Runt packet!\n");1211 dev->stats.rx_errors++;1212 return;1213 }1214 1215 if (pkt_len > rx_copybreak) {1216 struct sk_buff *newskb;1217 dma_addr_t new_dma_addr;1218 1219 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB);1220 /*1221 * map the new buffer, if mapping fails, drop the packet and1222 * reuse the old buffer1223 */1224 if (newskb) {1225 skb_reserve(newskb, NET_IP_ALIGN);1226 new_dma_addr = dma_map_single(&lp->pci_dev->dev,1227 newskb->data,1228 PKT_BUF_SIZE,1229 DMA_FROM_DEVICE);1230 if (dma_mapping_error(&lp->pci_dev->dev, new_dma_addr)) {1231 netif_err(lp, rx_err, dev,1232 "DMA mapping error.\n");1233 dev_kfree_skb(newskb);1234 skb = NULL;1235 } else {1236 skb = lp->rx_skbuff[entry];1237 dma_unmap_single(&lp->pci_dev->dev,1238 lp->rx_dma_addr[entry],1239 PKT_BUF_SIZE,1240 DMA_FROM_DEVICE);1241 skb_put(skb, pkt_len);1242 lp->rx_skbuff[entry] = newskb;1243 lp->rx_dma_addr[entry] = new_dma_addr;1244 rxp->base = cpu_to_le32(new_dma_addr);1245 rx_in_place = 1;1246 }1247 } else1248 skb = NULL;1249 } else1250 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN);1251 1252 if (!skb) {1253 dev->stats.rx_dropped++;1254 return;1255 }1256 if (!rx_in_place) {1257 skb_reserve(skb, NET_IP_ALIGN);1258 skb_put(skb, pkt_len); /* Make room */1259 dma_sync_single_for_cpu(&lp->pci_dev->dev,1260 lp->rx_dma_addr[entry], pkt_len,1261 DMA_FROM_DEVICE);1262 skb_copy_to_linear_data(skb,1263 (unsigned char *)(lp->rx_skbuff[entry]->data),1264 pkt_len);1265 dma_sync_single_for_device(&lp->pci_dev->dev,1266 lp->rx_dma_addr[entry], pkt_len,1267 DMA_FROM_DEVICE);1268 }1269 dev->stats.rx_bytes += skb->len;1270 skb->protocol = eth_type_trans(skb, dev);1271 netif_receive_skb(skb);1272 dev->stats.rx_packets++;1273}1274 1275static int pcnet32_rx(struct net_device *dev, int budget)1276{1277 struct pcnet32_private *lp = netdev_priv(dev);1278 int entry = lp->cur_rx & lp->rx_mod_mask;1279 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];1280 int npackets = 0;1281 1282 /* If we own the next entry, it's a new packet. Send it up. */1283 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {1284 pcnet32_rx_entry(dev, lp, rxp, entry);1285 npackets += 1;1286 /*1287 * The docs say that the buffer length isn't touched, but Andrew1288 * Boyd of QNX reports that some revs of the 79C965 clear it.1289 */1290 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);1291 wmb(); /* Make sure owner changes after others are visible */1292 rxp->status = cpu_to_le16(0x8000);1293 entry = (++lp->cur_rx) & lp->rx_mod_mask;1294 rxp = &lp->rx_ring[entry];1295 }1296 1297 return npackets;1298}1299 1300static int pcnet32_tx(struct net_device *dev)1301{1302 struct pcnet32_private *lp = netdev_priv(dev);1303 unsigned int dirty_tx = lp->dirty_tx;1304 int delta;1305 int must_restart = 0;1306 1307 while (dirty_tx != lp->cur_tx) {1308 int entry = dirty_tx & lp->tx_mod_mask;1309 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);1310 1311 if (status < 0)1312 break; /* It still hasn't been Txed */1313 1314 lp->tx_ring[entry].base = 0;1315 1316 if (status & 0x4000) {1317 /* There was a major error, log it. */1318 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);1319 dev->stats.tx_errors++;1320 netif_err(lp, tx_err, dev,1321 "Tx error status=%04x err_status=%08x\n",1322 status, err_status);1323 if (err_status & 0x04000000)1324 dev->stats.tx_aborted_errors++;1325 if (err_status & 0x08000000)1326 dev->stats.tx_carrier_errors++;1327 if (err_status & 0x10000000)1328 dev->stats.tx_window_errors++;1329#ifndef DO_DXSUFLO1330 if (err_status & 0x40000000) {1331 dev->stats.tx_fifo_errors++;1332 /* Ackk! On FIFO errors the Tx unit is turned off! */1333 /* Remove this verbosity later! */1334 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");1335 must_restart = 1;1336 }1337#else1338 if (err_status & 0x40000000) {1339 dev->stats.tx_fifo_errors++;1340 if (!lp->dxsuflo) { /* If controller doesn't recover ... */1341 /* Ackk! On FIFO errors the Tx unit is turned off! */1342 /* Remove this verbosity later! */1343 netif_err(lp, tx_err, dev, "Tx FIFO error!\n");1344 must_restart = 1;1345 }1346 }1347#endif1348 } else {1349 if (status & 0x1800)1350 dev->stats.collisions++;1351 dev->stats.tx_packets++;1352 }1353 1354 /* We must free the original skb */1355 if (lp->tx_skbuff[entry]) {1356 dma_unmap_single(&lp->pci_dev->dev,1357 lp->tx_dma_addr[entry],1358 lp->tx_skbuff[entry]->len,1359 DMA_TO_DEVICE);1360 dev_kfree_skb_any(lp->tx_skbuff[entry]);1361 lp->tx_skbuff[entry] = NULL;1362 lp->tx_dma_addr[entry] = 0;1363 }1364 dirty_tx++;1365 }1366 1367 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);1368 if (delta > lp->tx_ring_size) {1369 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",1370 dirty_tx, lp->cur_tx, lp->tx_full);1371 dirty_tx += lp->tx_ring_size;1372 delta -= lp->tx_ring_size;1373 }1374 1375 if (lp->tx_full &&1376 netif_queue_stopped(dev) &&1377 delta < lp->tx_ring_size - 2) {1378 /* The ring is no longer full, clear tbusy. */1379 lp->tx_full = 0;1380 netif_wake_queue(dev);1381 }1382 lp->dirty_tx = dirty_tx;1383 1384 return must_restart;1385}1386 1387static int pcnet32_poll(struct napi_struct *napi, int budget)1388{1389 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);1390 struct net_device *dev = lp->dev;1391 unsigned long ioaddr = dev->base_addr;1392 unsigned long flags;1393 int work_done;1394 u16 val;1395 1396 work_done = pcnet32_rx(dev, budget);1397 1398 spin_lock_irqsave(&lp->lock, flags);1399 if (pcnet32_tx(dev)) {1400 /* reset the chip to clear the error condition, then restart */1401 lp->a->reset(ioaddr);1402 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */1403 pcnet32_restart(dev, CSR0_START);1404 netif_wake_queue(dev);1405 }1406 1407 if (work_done < budget && napi_complete_done(napi, work_done)) {1408 /* clear interrupt masks */1409 val = lp->a->read_csr(ioaddr, CSR3);1410 val &= 0x00ff;1411 lp->a->write_csr(ioaddr, CSR3, val);1412 1413 /* Set interrupt enable. */1414 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);1415 }1416 1417 spin_unlock_irqrestore(&lp->lock, flags);1418 return work_done;1419}1420 1421#define PCNET32_REGS_PER_PHY 321422#define PCNET32_MAX_PHYS 321423static int pcnet32_get_regs_len(struct net_device *dev)1424{1425 struct pcnet32_private *lp = netdev_priv(dev);1426 int j = lp->phycount * PCNET32_REGS_PER_PHY;1427 1428 return (PCNET32_NUM_REGS + j) * sizeof(u16);1429}1430 1431static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,1432 void *ptr)1433{1434 int i, csr0;1435 u16 *buff = ptr;1436 struct pcnet32_private *lp = netdev_priv(dev);1437 const struct pcnet32_access *a = lp->a;1438 ulong ioaddr = dev->base_addr;1439 unsigned long flags;1440 1441 spin_lock_irqsave(&lp->lock, flags);1442 1443 csr0 = a->read_csr(ioaddr, CSR0);1444 if (!(csr0 & CSR0_STOP)) /* If not stopped */1445 pcnet32_suspend(dev, &flags, 1);1446 1447 /* read address PROM */1448 for (i = 0; i < 16; i += 2)1449 *buff++ = inw(ioaddr + i);1450 1451 /* read control and status registers */1452 for (i = 0; i < 90; i++)1453 *buff++ = a->read_csr(ioaddr, i);1454 1455 *buff++ = a->read_csr(ioaddr, 112);1456 *buff++ = a->read_csr(ioaddr, 114);1457 1458 /* read bus configuration registers */1459 for (i = 0; i < 30; i++)1460 *buff++ = a->read_bcr(ioaddr, i);1461 1462 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */1463 1464 for (i = 31; i < 36; i++)1465 *buff++ = a->read_bcr(ioaddr, i);1466 1467 /* read mii phy registers */1468 if (lp->mii) {1469 int j;1470 for (j = 0; j < PCNET32_MAX_PHYS; j++) {1471 if (lp->phymask & (1 << j)) {1472 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {1473 lp->a->write_bcr(ioaddr, 33,1474 (j << 5) | i);1475 *buff++ = lp->a->read_bcr(ioaddr, 34);1476 }1477 }1478 }1479 }1480 1481 if (!(csr0 & CSR0_STOP)) /* If not stopped */1482 pcnet32_clr_suspend(lp, ioaddr);1483 1484 spin_unlock_irqrestore(&lp->lock, flags);1485}1486 1487static const struct ethtool_ops pcnet32_ethtool_ops = {1488 .get_drvinfo = pcnet32_get_drvinfo,1489 .get_msglevel = pcnet32_get_msglevel,1490 .set_msglevel = pcnet32_set_msglevel,1491 .nway_reset = pcnet32_nway_reset,1492 .get_link = pcnet32_get_link,1493 .get_ringparam = pcnet32_get_ringparam,1494 .set_ringparam = pcnet32_set_ringparam,1495 .get_strings = pcnet32_get_strings,1496 .self_test = pcnet32_ethtool_test,1497 .set_phys_id = pcnet32_set_phys_id,1498 .get_regs_len = pcnet32_get_regs_len,1499 .get_regs = pcnet32_get_regs,1500 .get_sset_count = pcnet32_get_sset_count,1501 .get_link_ksettings = pcnet32_get_link_ksettings,1502 .set_link_ksettings = pcnet32_set_link_ksettings,1503};1504 1505/* only probes for non-PCI devices, the rest are handled by1506 * pci_register_driver via pcnet32_probe_pci */1507 1508static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)1509{1510 unsigned int *port, ioaddr;1511 1512 /* search for PCnet32 VLB cards at known addresses */1513 for (port = pcnet32_portlist; (ioaddr = *port); port++) {1514 if (request_region1515 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {1516 /* check if there is really a pcnet chip on that ioaddr */1517 if ((inb(ioaddr + 14) == 0x57) &&1518 (inb(ioaddr + 15) == 0x57)) {1519 pcnet32_probe1(ioaddr, 0, NULL);1520 } else {1521 release_region(ioaddr, PCNET32_TOTAL_SIZE);1522 }1523 }1524 }1525}1526 1527static int1528pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)1529{1530 unsigned long ioaddr;1531 int err;1532 1533 err = pci_enable_device(pdev);1534 if (err < 0) {1535 if (pcnet32_debug & NETIF_MSG_PROBE)1536 pr_err("failed to enable device -- err=%d\n", err);1537 return err;1538 }1539 pci_set_master(pdev);1540 1541 if (!pci_resource_len(pdev, 0)) {1542 if (pcnet32_debug & NETIF_MSG_PROBE)1543 pr_err("card has no PCI IO resources, aborting\n");1544 err = -ENODEV;1545 goto err_disable_dev;1546 }1547 1548 err = dma_set_mask(&pdev->dev, PCNET32_DMA_MASK);1549 if (err) {1550 if (pcnet32_debug & NETIF_MSG_PROBE)1551 pr_err("architecture does not support 32bit PCI busmaster DMA\n");1552 goto err_disable_dev;1553 }1554 1555 ioaddr = pci_resource_start(pdev, 0);1556 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) {1557 if (pcnet32_debug & NETIF_MSG_PROBE)1558 pr_err("io address range already allocated\n");1559 err = -EBUSY;1560 goto err_disable_dev;1561 }1562 1563 err = pcnet32_probe1(ioaddr, 1, pdev);1564 1565err_disable_dev:1566 if (err < 0)1567 pci_disable_device(pdev);1568 1569 return err;1570}1571 1572static const struct net_device_ops pcnet32_netdev_ops = {1573 .ndo_open = pcnet32_open,1574 .ndo_stop = pcnet32_close,1575 .ndo_start_xmit = pcnet32_start_xmit,1576 .ndo_tx_timeout = pcnet32_tx_timeout,1577 .ndo_get_stats = pcnet32_get_stats,1578 .ndo_set_rx_mode = pcnet32_set_multicast_list,1579 .ndo_eth_ioctl = pcnet32_ioctl,1580 .ndo_set_mac_address = eth_mac_addr,1581 .ndo_validate_addr = eth_validate_addr,1582#ifdef CONFIG_NET_POLL_CONTROLLER1583 .ndo_poll_controller = pcnet32_poll_controller,1584#endif1585};1586 1587/* pcnet32_probe11588 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.1589 * pdev will be NULL when called from pcnet32_probe_vlbus.1590 */1591static int1592pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)1593{1594 struct pcnet32_private *lp;1595 int i, media;1596 int fdx, mii, fset, dxsuflo, sram;1597 int chip_version;1598 char *chipname;1599 struct net_device *dev;1600 const struct pcnet32_access *a = NULL;1601 u8 promaddr[ETH_ALEN];1602 u8 addr[ETH_ALEN];1603 int ret = -ENODEV;1604 1605 /* reset the chip */1606 pcnet32_wio_reset(ioaddr);1607 1608 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */1609 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {1610 a = &pcnet32_wio;1611 } else {1612 pcnet32_dwio_reset(ioaddr);1613 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&1614 pcnet32_dwio_check(ioaddr)) {1615 a = &pcnet32_dwio;1616 } else {1617 if (pcnet32_debug & NETIF_MSG_PROBE)1618 pr_err("No access methods\n");1619 goto err_release_region;1620 }1621 }1622 1623 chip_version =1624 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);1625 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))1626 pr_info(" PCnet chip version is %#x\n", chip_version);1627 if ((chip_version & 0xfff) != 0x003) {1628 if (pcnet32_debug & NETIF_MSG_PROBE)1629 pr_info("Unsupported chip version\n");1630 goto err_release_region;1631 }1632 1633 /* initialize variables */1634 fdx = mii = fset = dxsuflo = sram = 0;1635 chip_version = (chip_version >> 12) & 0xffff;1636 1637 switch (chip_version) {1638 case 0x2420:1639 chipname = "PCnet/PCI 79C970"; /* PCI */1640 break;1641 case 0x2430:1642 if (shared)1643 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */1644 else1645 chipname = "PCnet/32 79C965"; /* 486/VL bus */1646 break;1647 case 0x2621:1648 chipname = "PCnet/PCI II 79C970A"; /* PCI */1649 fdx = 1;1650 break;1651 case 0x2623:1652 chipname = "PCnet/FAST 79C971"; /* PCI */1653 fdx = 1;1654 mii = 1;1655 fset = 1;1656 break;1657 case 0x2624:1658 chipname = "PCnet/FAST+ 79C972"; /* PCI */1659 fdx = 1;1660 mii = 1;1661 fset = 1;1662 break;1663 case 0x2625:1664 chipname = "PCnet/FAST III 79C973"; /* PCI */1665 fdx = 1;1666 mii = 1;1667 sram = 1;1668 break;1669 case 0x2626:1670 chipname = "PCnet/Home 79C978"; /* PCI */1671 fdx = 1;1672 /*1673 * This is based on specs published at www.amd.com. This section1674 * assumes that a card with a 79C978 wants to go into standard1675 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,1676 * and the module option homepna=1 can select this instead.1677 */1678 media = a->read_bcr(ioaddr, 49);1679 media &= ~3; /* default to 10Mb ethernet */1680 if (cards_found < MAX_UNITS && homepna[cards_found])1681 media |= 1; /* switch to home wiring mode */1682 if (pcnet32_debug & NETIF_MSG_PROBE)1683 printk(KERN_DEBUG PFX "media set to %sMbit mode\n",1684 (media & 1) ? "1" : "10");1685 a->write_bcr(ioaddr, 49, media);1686 break;1687 case 0x2627:1688 chipname = "PCnet/FAST III 79C975"; /* PCI */1689 fdx = 1;1690 mii = 1;1691 sram = 1;1692 break;1693 case 0x2628:1694 chipname = "PCnet/PRO 79C976";1695 fdx = 1;1696 mii = 1;1697 break;1698 default:1699 if (pcnet32_debug & NETIF_MSG_PROBE)1700 pr_info("PCnet version %#x, no PCnet32 chip\n",1701 chip_version);1702 goto err_release_region;1703 }1704 1705 /*1706 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit1707 * starting until the packet is loaded. Strike one for reliability, lose1708 * one for latency - although on PCI this isn't a big loss. Older chips1709 * have FIFO's smaller than a packet, so you can't do this.1710 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.1711 */1712 1713 if (fset) {1714 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));1715 a->write_csr(ioaddr, 80,1716 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);1717 dxsuflo = 1;1718 }1719 1720 /*1721 * The Am79C973/Am79C975 controllers come with 12K of SRAM1722 * which we can use for the Tx/Rx buffers but most importantly,1723 * the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid1724 * Tx fifo underflows.1725 */1726 if (sram) {1727 /*1728 * The SRAM is being configured in two steps. First we1729 * set the SRAM size in the BCR25:SRAM_SIZE bits. According1730 * to the datasheet, each bit corresponds to a 512-byte1731 * page so we can have at most 24 pages. The SRAM_SIZE1732 * holds the value of the upper 8 bits of the 16-bit SRAM size.1733 * The low 8-bits start at 0x00 and end at 0xff. So the1734 * address range is from 0x0000 up to 0x17ff. Therefore,1735 * the SRAM_SIZE is set to 0x17. The next step is to set1736 * the BCR26:SRAM_BND midway through so the Tx and Rx1737 * buffers can share the SRAM equally.1738 */1739 a->write_bcr(ioaddr, 25, 0x17);1740 a->write_bcr(ioaddr, 26, 0xc);1741 /* And finally enable the NOUFLO bit */1742 a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11));1743 }1744 1745 dev = alloc_etherdev(sizeof(*lp));1746 if (!dev) {1747 ret = -ENOMEM;1748 goto err_release_region;1749 }1750 1751 if (pdev)1752 SET_NETDEV_DEV(dev, &pdev->dev);1753 1754 if (pcnet32_debug & NETIF_MSG_PROBE)1755 pr_info("%s at %#3lx,", chipname, ioaddr);1756 1757 /* In most chips, after a chip reset, the ethernet address is read from the1758 * station address PROM at the base address and programmed into the1759 * "Physical Address Registers" CSR12-14.1760 * As a precautionary measure, we read the PROM values and complain if1761 * they disagree with the CSRs. If they miscompare, and the PROM addr1762 * is valid, then the PROM addr is used.1763 */1764 for (i = 0; i < 3; i++) {1765 unsigned int val;1766 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;1767 /* There may be endianness issues here. */1768 addr[2 * i] = val & 0x0ff;1769 addr[2 * i + 1] = (val >> 8) & 0x0ff;1770 }1771 eth_hw_addr_set(dev, addr);1772 1773 /* read PROM address and compare with CSR address */1774 for (i = 0; i < ETH_ALEN; i++)1775 promaddr[i] = inb(ioaddr + i);1776 1777 if (!ether_addr_equal(promaddr, dev->dev_addr) ||1778 !is_valid_ether_addr(dev->dev_addr)) {1779 if (is_valid_ether_addr(promaddr)) {1780 if (pcnet32_debug & NETIF_MSG_PROBE) {1781 pr_cont(" warning: CSR address invalid,\n");1782 pr_info(" using instead PROM address of");1783 }1784 eth_hw_addr_set(dev, promaddr);1785 }1786 }1787 1788 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */1789 if (!is_valid_ether_addr(dev->dev_addr)) {1790 static const u8 zero_addr[ETH_ALEN] = {};1791 1792 eth_hw_addr_set(dev, zero_addr);1793 }1794 1795 if (pcnet32_debug & NETIF_MSG_PROBE) {1796 pr_cont(" %pM", dev->dev_addr);1797 1798 /* Version 0x2623 and 0x2624 */1799 if (((chip_version + 1) & 0xfffe) == 0x2624) {1800 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */1801 pr_info(" tx_start_pt(0x%04x):", i);1802 switch (i >> 10) {1803 case 0:1804 pr_cont(" 20 bytes,");1805 break;1806 case 1:1807 pr_cont(" 64 bytes,");1808 break;1809 case 2:1810 pr_cont(" 128 bytes,");1811 break;1812 case 3:1813 pr_cont("~220 bytes,");1814 break;1815 }1816 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */1817 pr_cont(" BCR18(%x):", i & 0xffff);1818 if (i & (1 << 5))1819 pr_cont("BurstWrEn ");1820 if (i & (1 << 6))1821 pr_cont("BurstRdEn ");1822 if (i & (1 << 7))1823 pr_cont("DWordIO ");1824 if (i & (1 << 11))1825 pr_cont("NoUFlow ");1826 i = a->read_bcr(ioaddr, 25);1827 pr_info(" SRAMSIZE=0x%04x,", i << 8);1828 i = a->read_bcr(ioaddr, 26);1829 pr_cont(" SRAM_BND=0x%04x,", i << 8);1830 i = a->read_bcr(ioaddr, 27);1831 if (i & (1 << 14))1832 pr_cont("LowLatRx");1833 }1834 }1835 1836 dev->base_addr = ioaddr;1837 lp = netdev_priv(dev);1838 /* dma_alloc_coherent returns page-aligned memory, so we do not have to check the alignment */1839 lp->init_block = dma_alloc_coherent(&pdev->dev,1840 sizeof(*lp->init_block),1841 &lp->init_dma_addr, GFP_KERNEL);1842 if (!lp->init_block) {1843 if (pcnet32_debug & NETIF_MSG_PROBE)1844 pr_err("Coherent memory allocation failed\n");1845 ret = -ENOMEM;1846 goto err_free_netdev;1847 }1848 lp->pci_dev = pdev;1849 1850 lp->dev = dev;1851 1852 spin_lock_init(&lp->lock);1853 1854 lp->name = chipname;1855 lp->shared_irq = shared;1856 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */1857 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */1858 lp->tx_mod_mask = lp->tx_ring_size - 1;1859 lp->rx_mod_mask = lp->rx_ring_size - 1;1860 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);1861 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);1862 lp->mii_if.full_duplex = fdx;1863 lp->mii_if.phy_id_mask = 0x1f;1864 lp->mii_if.reg_num_mask = 0x1f;1865 lp->dxsuflo = dxsuflo;1866 lp->mii = mii;1867 lp->chip_version = chip_version;1868 lp->msg_enable = pcnet32_debug;1869 if ((cards_found >= MAX_UNITS) ||1870 (options[cards_found] >= sizeof(options_mapping)))1871 lp->options = PCNET32_PORT_ASEL;1872 else1873 lp->options = options_mapping[options[cards_found]];1874 /* force default port to TP on 79C970A so link detection can work */1875 if (lp->chip_version == PCNET32_79C970A)1876 lp->options = PCNET32_PORT_10BT;1877 lp->mii_if.dev = dev;1878 lp->mii_if.mdio_read = mdio_read;1879 lp->mii_if.mdio_write = mdio_write;1880 1881 /* napi.weight is used in both the napi and non-napi cases */1882 lp->napi.weight = lp->rx_ring_size / 2;1883 1884 netif_napi_add_weight(dev, &lp->napi, pcnet32_poll,1885 lp->rx_ring_size / 2);1886 1887 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&1888 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))1889 lp->options |= PCNET32_PORT_FD;1890 1891 lp->a = a;1892 1893 /* prior to register_netdev, dev->name is not yet correct */1894 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {1895 ret = -ENOMEM;1896 goto err_free_ring;1897 }1898 /* detect special T1/E1 WAN card by checking for MAC address */1899 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&1900 dev->dev_addr[2] == 0x75)1901 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;1902 1903 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */1904 lp->init_block->tlen_rlen =1905 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);1906 for (i = 0; i < 6; i++)1907 lp->init_block->phys_addr[i] = dev->dev_addr[i];1908 lp->init_block->filter[0] = 0x00000000;1909 lp->init_block->filter[1] = 0x00000000;1910 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);1911 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);1912 1913 /* switch pcnet32 to 32bit mode */1914 a->write_bcr(ioaddr, 20, 2);1915 1916 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));1917 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));1918 1919 if (pdev) { /* use the IRQ provided by PCI */1920 dev->irq = pdev->irq;1921 if (pcnet32_debug & NETIF_MSG_PROBE)1922 pr_cont(" assigned IRQ %d\n", dev->irq);1923 } else {1924 unsigned long irq_mask = probe_irq_on();1925 1926 /*1927 * To auto-IRQ we enable the initialization-done and DMA error1928 * interrupts. For ISA boards we get a DMA error, but VLB and PCI1929 * boards will work.1930 */1931 /* Trigger an initialization just for the interrupt. */1932 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);1933 mdelay(1);1934 1935 dev->irq = probe_irq_off(irq_mask);1936 if (!dev->irq) {1937 if (pcnet32_debug & NETIF_MSG_PROBE)1938 pr_cont(", failed to detect IRQ line\n");1939 ret = -ENODEV;1940 goto err_free_ring;1941 }1942 if (pcnet32_debug & NETIF_MSG_PROBE)1943 pr_cont(", probed IRQ %d\n", dev->irq);1944 }1945 1946 /* Set the mii phy_id so that we can query the link state */1947 if (lp->mii) {1948 /* lp->phycount and lp->phymask are set to 0 by memset above */1949 1950 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f;1951 /* scan for PHYs */1952 for (i = 0; i < PCNET32_MAX_PHYS; i++) {1953 unsigned short id1, id2;1954 1955 id1 = mdio_read(dev, i, MII_PHYSID1);1956 if (id1 == 0xffff)1957 continue;1958 id2 = mdio_read(dev, i, MII_PHYSID2);1959 if (id2 == 0xffff)1960 continue;1961 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)1962 continue; /* 79C971 & 79C972 have phantom phy at id 31 */1963 lp->phycount++;1964 lp->phymask |= (1 << i);1965 lp->mii_if.phy_id = i;1966 if (pcnet32_debug & NETIF_MSG_PROBE)1967 pr_info("Found PHY %04x:%04x at address %d\n",1968 id1, id2, i);1969 }1970 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);1971 if (lp->phycount > 1)1972 lp->options |= PCNET32_PORT_MII;1973 }1974 1975 timer_setup(&lp->watchdog_timer, pcnet32_watchdog, 0);1976 1977 /* The PCNET32-specific entries in the device structure. */1978 dev->netdev_ops = &pcnet32_netdev_ops;1979 dev->ethtool_ops = &pcnet32_ethtool_ops;1980 dev->watchdog_timeo = (5 * HZ);1981 1982 /* Fill in the generic fields of the device structure. */1983 if (register_netdev(dev))1984 goto err_free_ring;1985 1986 if (pdev) {1987 pci_set_drvdata(pdev, dev);1988 } else {1989 lp->next = pcnet32_dev;1990 pcnet32_dev = dev;1991 }1992 1993 if (pcnet32_debug & NETIF_MSG_PROBE)1994 pr_info("%s: registered as %s\n", dev->name, lp->name);1995 cards_found++;1996 1997 /* enable LED writes */1998 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);1999 2000 return 0;2001 2002err_free_ring:2003 pcnet32_free_ring(dev);2004 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block),2005 lp->init_block, lp->init_dma_addr);2006err_free_netdev:2007 free_netdev(dev);2008err_release_region:2009 release_region(ioaddr, PCNET32_TOTAL_SIZE);2010 return ret;2011}2012 2013/* if any allocation fails, caller must also call pcnet32_free_ring */2014static int pcnet32_alloc_ring(struct net_device *dev, const char *name)2015{2016 struct pcnet32_private *lp = netdev_priv(dev);2017 2018 lp->tx_ring = dma_alloc_coherent(&lp->pci_dev->dev,2019 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,2020 &lp->tx_ring_dma_addr, GFP_KERNEL);2021 if (!lp->tx_ring) {2022 netif_err(lp, drv, dev, "Coherent memory allocation failed\n");2023 return -ENOMEM;2024 }2025 2026 lp->rx_ring = dma_alloc_coherent(&lp->pci_dev->dev,2027 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,2028 &lp->rx_ring_dma_addr, GFP_KERNEL);2029 if (!lp->rx_ring) {2030 netif_err(lp, drv, dev, "Coherent memory allocation failed\n");2031 return -ENOMEM;2032 }2033 2034 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),2035 GFP_KERNEL);2036 if (!lp->tx_dma_addr)2037 return -ENOMEM;2038 2039 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),2040 GFP_KERNEL);2041 if (!lp->rx_dma_addr)2042 return -ENOMEM;2043 2044 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),2045 GFP_KERNEL);2046 if (!lp->tx_skbuff)2047 return -ENOMEM;2048 2049 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),2050 GFP_KERNEL);2051 if (!lp->rx_skbuff)2052 return -ENOMEM;2053 2054 return 0;2055}2056 2057static void pcnet32_free_ring(struct net_device *dev)2058{2059 struct pcnet32_private *lp = netdev_priv(dev);2060 2061 kfree(lp->tx_skbuff);2062 lp->tx_skbuff = NULL;2063 2064 kfree(lp->rx_skbuff);2065 lp->rx_skbuff = NULL;2066 2067 kfree(lp->tx_dma_addr);2068 lp->tx_dma_addr = NULL;2069 2070 kfree(lp->rx_dma_addr);2071 lp->rx_dma_addr = NULL;2072 2073 if (lp->tx_ring) {2074 dma_free_coherent(&lp->pci_dev->dev,2075 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,2076 lp->tx_ring, lp->tx_ring_dma_addr);2077 lp->tx_ring = NULL;2078 }2079 2080 if (lp->rx_ring) {2081 dma_free_coherent(&lp->pci_dev->dev,2082 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,2083 lp->rx_ring, lp->rx_ring_dma_addr);2084 lp->rx_ring = NULL;2085 }2086}2087 2088static int pcnet32_open(struct net_device *dev)2089{2090 struct pcnet32_private *lp = netdev_priv(dev);2091 struct pci_dev *pdev = lp->pci_dev;2092 unsigned long ioaddr = dev->base_addr;2093 u16 val;2094 int i;2095 int rc;2096 unsigned long flags;2097 2098 if (request_irq(dev->irq, pcnet32_interrupt,2099 lp->shared_irq ? IRQF_SHARED : 0, dev->name,2100 (void *)dev)) {2101 return -EAGAIN;2102 }2103 2104 spin_lock_irqsave(&lp->lock, flags);2105 /* Check for a valid station address */2106 if (!is_valid_ether_addr(dev->dev_addr)) {2107 rc = -EINVAL;2108 goto err_free_irq;2109 }2110 2111 /* Reset the PCNET32 */2112 lp->a->reset(ioaddr);2113 2114 /* switch pcnet32 to 32bit mode */2115 lp->a->write_bcr(ioaddr, 20, 2);2116 2117 netif_printk(lp, ifup, KERN_DEBUG, dev,2118 "%s() irq %d tx/rx rings %#x/%#x init %#x\n",2119 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),2120 (u32) (lp->rx_ring_dma_addr),2121 (u32) (lp->init_dma_addr));2122 2123 lp->autoneg = !!(lp->options & PCNET32_PORT_ASEL);2124 lp->port_tp = !!(lp->options & PCNET32_PORT_10BT);2125 lp->fdx = !!(lp->options & PCNET32_PORT_FD);2126 2127 /* set/reset autoselect bit */2128 val = lp->a->read_bcr(ioaddr, 2) & ~2;2129 if (lp->options & PCNET32_PORT_ASEL)2130 val |= 2;2131 lp->a->write_bcr(ioaddr, 2, val);2132 2133 /* handle full duplex setting */2134 if (lp->mii_if.full_duplex) {2135 val = lp->a->read_bcr(ioaddr, 9) & ~3;2136 if (lp->options & PCNET32_PORT_FD) {2137 val |= 1;2138 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))2139 val |= 2;2140 } else if (lp->options & PCNET32_PORT_ASEL) {2141 /* workaround of xSeries250, turn on for 79C975 only */2142 if (lp->chip_version == 0x2627)2143 val |= 3;2144 }2145 lp->a->write_bcr(ioaddr, 9, val);2146 }2147 2148 /* set/reset GPSI bit in test register */2149 val = lp->a->read_csr(ioaddr, 124) & ~0x10;2150 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)2151 val |= 0x10;2152 lp->a->write_csr(ioaddr, 124, val);2153 2154 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */2155 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&2156 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||2157 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {2158 if (lp->options & PCNET32_PORT_ASEL) {2159 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;2160 netif_printk(lp, link, KERN_DEBUG, dev,2161 "Setting 100Mb-Full Duplex\n");2162 }2163 }2164 if (lp->phycount < 2) {2165 /*2166 * 24 Jun 2004 according AMD, in order to change the PHY,2167 * DANAS (or DISPM for 79C976) must be set; then select the speed,2168 * duplex, and/or enable auto negotiation, and clear DANAS2169 */2170 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {2171 lp->a->write_bcr(ioaddr, 32,2172 lp->a->read_bcr(ioaddr, 32) | 0x0080);2173 /* disable Auto Negotiation, set 10Mpbs, HD */2174 val = lp->a->read_bcr(ioaddr, 32) & ~0xb8;2175 if (lp->options & PCNET32_PORT_FD)2176 val |= 0x10;2177 if (lp->options & PCNET32_PORT_100)2178 val |= 0x08;2179 lp->a->write_bcr(ioaddr, 32, val);2180 } else {2181 if (lp->options & PCNET32_PORT_ASEL) {2182 lp->a->write_bcr(ioaddr, 32,2183 lp->a->read_bcr(ioaddr,2184 32) | 0x0080);2185 /* enable auto negotiate, setup, disable fd */2186 val = lp->a->read_bcr(ioaddr, 32) & ~0x98;2187 val |= 0x20;2188 lp->a->write_bcr(ioaddr, 32, val);2189 }2190 }2191 } else {2192 int first_phy = -1;2193 u16 bmcr;2194 u32 bcr9;2195 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };2196 2197 /*2198 * There is really no good other way to handle multiple PHYs2199 * other than turning off all automatics2200 */2201 val = lp->a->read_bcr(ioaddr, 2);2202 lp->a->write_bcr(ioaddr, 2, val & ~2);2203 val = lp->a->read_bcr(ioaddr, 32);2204 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */2205 2206 if (!(lp->options & PCNET32_PORT_ASEL)) {2207 /* setup ecmd */2208 ecmd.port = PORT_MII;2209 ecmd.transceiver = XCVR_INTERNAL;2210 ecmd.autoneg = AUTONEG_DISABLE;2211 ethtool_cmd_speed_set(&ecmd,2212 (lp->options & PCNET32_PORT_100) ?2213 SPEED_100 : SPEED_10);2214 bcr9 = lp->a->read_bcr(ioaddr, 9);2215 2216 if (lp->options & PCNET32_PORT_FD) {2217 ecmd.duplex = DUPLEX_FULL;2218 bcr9 |= (1 << 0);2219 } else {2220 ecmd.duplex = DUPLEX_HALF;2221 bcr9 |= ~(1 << 0);2222 }2223 lp->a->write_bcr(ioaddr, 9, bcr9);2224 }2225 2226 for (i = 0; i < PCNET32_MAX_PHYS; i++) {2227 if (lp->phymask & (1 << i)) {2228 /* isolate all but the first PHY */2229 bmcr = mdio_read(dev, i, MII_BMCR);2230 if (first_phy == -1) {2231 first_phy = i;2232 mdio_write(dev, i, MII_BMCR,2233 bmcr & ~BMCR_ISOLATE);2234 } else {2235 mdio_write(dev, i, MII_BMCR,2236 bmcr | BMCR_ISOLATE);2237 }2238 /* use mii_ethtool_sset to setup PHY */2239 lp->mii_if.phy_id = i;2240 ecmd.phy_address = i;2241 if (lp->options & PCNET32_PORT_ASEL) {2242 mii_ethtool_gset(&lp->mii_if, &ecmd);2243 ecmd.autoneg = AUTONEG_ENABLE;2244 }2245 mii_ethtool_sset(&lp->mii_if, &ecmd);2246 }2247 }2248 lp->mii_if.phy_id = first_phy;2249 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);2250 }2251 2252#ifdef DO_DXSUFLO2253 if (lp->dxsuflo) { /* Disable transmit stop on underflow */2254 val = lp->a->read_csr(ioaddr, CSR3);2255 val |= 0x40;2256 lp->a->write_csr(ioaddr, CSR3, val);2257 }2258#endif2259 2260 lp->init_block->mode =2261 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);2262 pcnet32_load_multicast(dev);2263 2264 if (pcnet32_init_ring(dev)) {2265 rc = -ENOMEM;2266 goto err_free_ring;2267 }2268 2269 napi_enable(&lp->napi);2270 2271 /* Re-initialize the PCNET32, and start it when done. */2272 lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));2273 lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));2274 2275 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */2276 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);2277 2278 netif_start_queue(dev);2279 2280 if (lp->chip_version >= PCNET32_79C970A) {2281 /* Print the link status and start the watchdog */2282 pcnet32_check_media(dev, 1);2283 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);2284 }2285 2286 i = 0;2287 while (i++ < 100)2288 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)2289 break;2290 /*2291 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton2292 * reports that doing so triggers a bug in the '974.2293 */2294 lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);2295 2296 netif_printk(lp, ifup, KERN_DEBUG, dev,2297 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",2298 i,2299 (u32) (lp->init_dma_addr),2300 lp->a->read_csr(ioaddr, CSR0));2301 2302 spin_unlock_irqrestore(&lp->lock, flags);2303 2304 return 0; /* Always succeed */2305 2306err_free_ring:2307 /* free any allocated skbuffs */2308 pcnet32_purge_rx_ring(dev);2309 2310 /*2311 * Switch back to 16bit mode to avoid problems with dumb2312 * DOS packet driver after a warm reboot2313 */2314 lp->a->write_bcr(ioaddr, 20, 4);2315 2316err_free_irq:2317 spin_unlock_irqrestore(&lp->lock, flags);2318 free_irq(dev->irq, dev);2319 return rc;2320}2321 2322/*2323 * The LANCE has been halted for one reason or another (busmaster memory2324 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,2325 * etc.). Modern LANCE variants always reload their ring-buffer2326 * configuration when restarted, so we must reinitialize our ring2327 * context before restarting. As part of this reinitialization,2328 * find all packets still on the Tx ring and pretend that they had been2329 * sent (in effect, drop the packets on the floor) - the higher-level2330 * protocols will time out and retransmit. It'd be better to shuffle2331 * these skbs to a temp list and then actually re-Tx them after2332 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com2333 */2334 2335static void pcnet32_purge_tx_ring(struct net_device *dev)2336{2337 struct pcnet32_private *lp = netdev_priv(dev);2338 int i;2339 2340 for (i = 0; i < lp->tx_ring_size; i++) {2341 lp->tx_ring[i].status = 0; /* CPU owns buffer */2342 wmb(); /* Make sure adapter sees owner change */2343 if (lp->tx_skbuff[i]) {2344 if (!dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[i]))2345 dma_unmap_single(&lp->pci_dev->dev,2346 lp->tx_dma_addr[i],2347 lp->tx_skbuff[i]->len,2348 DMA_TO_DEVICE);2349 dev_kfree_skb_any(lp->tx_skbuff[i]);2350 }2351 lp->tx_skbuff[i] = NULL;2352 lp->tx_dma_addr[i] = 0;2353 }2354}2355 2356/* Initialize the PCNET32 Rx and Tx rings. */2357static int pcnet32_init_ring(struct net_device *dev)2358{2359 struct pcnet32_private *lp = netdev_priv(dev);2360 int i;2361 2362 lp->tx_full = 0;2363 lp->cur_rx = lp->cur_tx = 0;2364 lp->dirty_rx = lp->dirty_tx = 0;2365 2366 for (i = 0; i < lp->rx_ring_size; i++) {2367 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];2368 if (!rx_skbuff) {2369 lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB);2370 rx_skbuff = lp->rx_skbuff[i];2371 if (!rx_skbuff) {2372 /* there is not much we can do at this point */2373 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",2374 __func__);2375 return -1;2376 }2377 skb_reserve(rx_skbuff, NET_IP_ALIGN);2378 }2379 2380 rmb();2381 if (lp->rx_dma_addr[i] == 0) {2382 lp->rx_dma_addr[i] =2383 dma_map_single(&lp->pci_dev->dev, rx_skbuff->data,2384 PKT_BUF_SIZE, DMA_FROM_DEVICE);2385 if (dma_mapping_error(&lp->pci_dev->dev, lp->rx_dma_addr[i])) {2386 /* there is not much we can do at this point */2387 netif_err(lp, drv, dev,2388 "%s pci dma mapping error\n",2389 __func__);2390 return -1;2391 }2392 }2393 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);2394 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);2395 wmb(); /* Make sure owner changes after all others are visible */2396 lp->rx_ring[i].status = cpu_to_le16(0x8000);2397 }2398 /* The Tx buffer address is filled in as needed, but we do need to clear2399 * the upper ownership bit. */2400 for (i = 0; i < lp->tx_ring_size; i++) {2401 lp->tx_ring[i].status = 0; /* CPU owns buffer */2402 wmb(); /* Make sure adapter sees owner change */2403 lp->tx_ring[i].base = 0;2404 lp->tx_dma_addr[i] = 0;2405 }2406 2407 lp->init_block->tlen_rlen =2408 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);2409 for (i = 0; i < 6; i++)2410 lp->init_block->phys_addr[i] = dev->dev_addr[i];2411 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);2412 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);2413 wmb(); /* Make sure all changes are visible */2414 return 0;2415}2416 2417/* the pcnet32 has been issued a stop or reset. Wait for the stop bit2418 * then flush the pending transmit operations, re-initialize the ring,2419 * and tell the chip to initialize.2420 */2421static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)2422{2423 struct pcnet32_private *lp = netdev_priv(dev);2424 unsigned long ioaddr = dev->base_addr;2425 int i;2426 2427 /* wait for stop */2428 for (i = 0; i < 100; i++)2429 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)2430 break;2431 2432 if (i >= 100)2433 netif_err(lp, drv, dev, "%s timed out waiting for stop\n",2434 __func__);2435 2436 pcnet32_purge_tx_ring(dev);2437 if (pcnet32_init_ring(dev))2438 return;2439 2440 /* ReInit Ring */2441 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);2442 i = 0;2443 while (i++ < 1000)2444 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)2445 break;2446 2447 lp->a->write_csr(ioaddr, CSR0, csr0_bits);2448}2449 2450static void pcnet32_tx_timeout(struct net_device *dev, unsigned int txqueue)2451{2452 struct pcnet32_private *lp = netdev_priv(dev);2453 unsigned long ioaddr = dev->base_addr, flags;2454 2455 spin_lock_irqsave(&lp->lock, flags);2456 /* Transmitter timeout, serious problems. */2457 if (pcnet32_debug & NETIF_MSG_DRV)2458 pr_err("%s: transmit timed out, status %4.4x, resetting\n",2459 dev->name, lp->a->read_csr(ioaddr, CSR0));2460 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);2461 dev->stats.tx_errors++;2462 if (netif_msg_tx_err(lp)) {2463 int i;2464 printk(KERN_DEBUG2465 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",2466 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",2467 lp->cur_rx);2468 for (i = 0; i < lp->rx_ring_size; i++)2469 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",2470 le32_to_cpu(lp->rx_ring[i].base),2471 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &2472 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),2473 le16_to_cpu(lp->rx_ring[i].status));2474 for (i = 0; i < lp->tx_ring_size; i++)2475 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",2476 le32_to_cpu(lp->tx_ring[i].base),2477 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,2478 le32_to_cpu(lp->tx_ring[i].misc),2479 le16_to_cpu(lp->tx_ring[i].status));2480 printk("\n");2481 }2482 pcnet32_restart(dev, CSR0_NORMAL);2483 2484 netif_trans_update(dev); /* prevent tx timeout */2485 netif_wake_queue(dev);2486 2487 spin_unlock_irqrestore(&lp->lock, flags);2488}2489 2490static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,2491 struct net_device *dev)2492{2493 struct pcnet32_private *lp = netdev_priv(dev);2494 unsigned long ioaddr = dev->base_addr;2495 u16 status;2496 int entry;2497 unsigned long flags;2498 2499 spin_lock_irqsave(&lp->lock, flags);2500 2501 netif_printk(lp, tx_queued, KERN_DEBUG, dev,2502 "%s() called, csr0 %4.4x\n",2503 __func__, lp->a->read_csr(ioaddr, CSR0));2504 2505 /* Default status -- will not enable Successful-TxDone2506 * interrupt when that option is available to us.2507 */2508 status = 0x8300;2509 2510 /* Fill in a Tx ring entry */2511 2512 /* Mask to ring buffer boundary. */2513 entry = lp->cur_tx & lp->tx_mod_mask;2514 2515 /* Caution: the write order is important here, set the status2516 * with the "ownership" bits last. */2517 2518 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);2519 2520 lp->tx_ring[entry].misc = 0x00000000;2521 2522 lp->tx_dma_addr[entry] =2523 dma_map_single(&lp->pci_dev->dev, skb->data, skb->len,2524 DMA_TO_DEVICE);2525 if (dma_mapping_error(&lp->pci_dev->dev, lp->tx_dma_addr[entry])) {2526 dev_kfree_skb_any(skb);2527 dev->stats.tx_dropped++;2528 goto drop_packet;2529 }2530 lp->tx_skbuff[entry] = skb;2531 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);2532 wmb(); /* Make sure owner changes after all others are visible */2533 lp->tx_ring[entry].status = cpu_to_le16(status);2534 2535 lp->cur_tx++;2536 dev->stats.tx_bytes += skb->len;2537 2538 /* Trigger an immediate send poll. */2539 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);2540 2541 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {2542 lp->tx_full = 1;2543 netif_stop_queue(dev);2544 }2545drop_packet:2546 spin_unlock_irqrestore(&lp->lock, flags);2547 return NETDEV_TX_OK;2548}2549 2550/* The PCNET32 interrupt handler. */2551static irqreturn_t2552pcnet32_interrupt(int irq, void *dev_id)2553{2554 struct net_device *dev = dev_id;2555 struct pcnet32_private *lp;2556 unsigned long ioaddr;2557 u16 csr0;2558 int boguscnt = max_interrupt_work;2559 2560 ioaddr = dev->base_addr;2561 lp = netdev_priv(dev);2562 2563 spin_lock(&lp->lock);2564 2565 csr0 = lp->a->read_csr(ioaddr, CSR0);2566 while ((csr0 & 0x8f00) && --boguscnt >= 0) {2567 if (csr0 == 0xffff)2568 break; /* PCMCIA remove happened */2569 /* Acknowledge all of the current interrupt sources ASAP. */2570 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);2571 2572 netif_printk(lp, intr, KERN_DEBUG, dev,2573 "interrupt csr0=%#2.2x new csr=%#2.2x\n",2574 csr0, lp->a->read_csr(ioaddr, CSR0));2575 2576 /* Log misc errors. */2577 if (csr0 & 0x4000)2578 dev->stats.tx_errors++; /* Tx babble. */2579 if (csr0 & 0x1000) {2580 /*2581 * This happens when our receive ring is full. This2582 * shouldn't be a problem as we will see normal rx2583 * interrupts for the frames in the receive ring. But2584 * there are some PCI chipsets (I can reproduce this2585 * on SP3G with Intel saturn chipset) which have2586 * sometimes problems and will fill up the receive2587 * ring with error descriptors. In this situation we2588 * don't get a rx interrupt, but a missed frame2589 * interrupt sooner or later.2590 */2591 dev->stats.rx_errors++; /* Missed a Rx frame. */2592 }2593 if (csr0 & 0x0800) {2594 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",2595 csr0);2596 /* unlike for the lance, there is no restart needed */2597 }2598 if (napi_schedule_prep(&lp->napi)) {2599 u16 val;2600 /* set interrupt masks */2601 val = lp->a->read_csr(ioaddr, CSR3);2602 val |= 0x5f00;2603 lp->a->write_csr(ioaddr, CSR3, val);2604 2605 __napi_schedule(&lp->napi);2606 break;2607 }2608 csr0 = lp->a->read_csr(ioaddr, CSR0);2609 }2610 2611 netif_printk(lp, intr, KERN_DEBUG, dev,2612 "exiting interrupt, csr0=%#4.4x\n",2613 lp->a->read_csr(ioaddr, CSR0));2614 2615 spin_unlock(&lp->lock);2616 2617 return IRQ_HANDLED;2618}2619 2620static int pcnet32_close(struct net_device *dev)2621{2622 unsigned long ioaddr = dev->base_addr;2623 struct pcnet32_private *lp = netdev_priv(dev);2624 unsigned long flags;2625 2626 del_timer_sync(&lp->watchdog_timer);2627 2628 netif_stop_queue(dev);2629 napi_disable(&lp->napi);2630 2631 spin_lock_irqsave(&lp->lock, flags);2632 2633 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);2634 2635 netif_printk(lp, ifdown, KERN_DEBUG, dev,2636 "Shutting down ethercard, status was %2.2x\n",2637 lp->a->read_csr(ioaddr, CSR0));2638 2639 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */2640 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);2641 2642 /*2643 * Switch back to 16bit mode to avoid problems with dumb2644 * DOS packet driver after a warm reboot2645 */2646 lp->a->write_bcr(ioaddr, 20, 4);2647 2648 spin_unlock_irqrestore(&lp->lock, flags);2649 2650 free_irq(dev->irq, dev);2651 2652 spin_lock_irqsave(&lp->lock, flags);2653 2654 pcnet32_purge_rx_ring(dev);2655 pcnet32_purge_tx_ring(dev);2656 2657 spin_unlock_irqrestore(&lp->lock, flags);2658 2659 return 0;2660}2661 2662static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)2663{2664 struct pcnet32_private *lp = netdev_priv(dev);2665 unsigned long ioaddr = dev->base_addr;2666 unsigned long flags;2667 2668 spin_lock_irqsave(&lp->lock, flags);2669 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);2670 spin_unlock_irqrestore(&lp->lock, flags);2671 2672 return &dev->stats;2673}2674 2675/* taken from the sunlance driver, which it took from the depca driver */2676static void pcnet32_load_multicast(struct net_device *dev)2677{2678 struct pcnet32_private *lp = netdev_priv(dev);2679 volatile struct pcnet32_init_block *ib = lp->init_block;2680 volatile __le16 *mcast_table = (__le16 *)ib->filter;2681 struct netdev_hw_addr *ha;2682 unsigned long ioaddr = dev->base_addr;2683 int i;2684 u32 crc;2685 2686 /* set all multicast bits */2687 if (dev->flags & IFF_ALLMULTI) {2688 ib->filter[0] = cpu_to_le32(~0U);2689 ib->filter[1] = cpu_to_le32(~0U);2690 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);2691 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);2692 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);2693 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);2694 return;2695 }2696 /* clear the multicast filter */2697 ib->filter[0] = 0;2698 ib->filter[1] = 0;2699 2700 /* Add addresses */2701 netdev_for_each_mc_addr(ha, dev) {2702 crc = ether_crc_le(6, ha->addr);2703 crc = crc >> 26;2704 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));2705 }2706 for (i = 0; i < 4; i++)2707 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,2708 le16_to_cpu(mcast_table[i]));2709}2710 2711/*2712 * Set or clear the multicast filter for this adaptor.2713 */2714static void pcnet32_set_multicast_list(struct net_device *dev)2715{2716 unsigned long ioaddr = dev->base_addr, flags;2717 struct pcnet32_private *lp = netdev_priv(dev);2718 int csr15, suspended;2719 2720 spin_lock_irqsave(&lp->lock, flags);2721 suspended = pcnet32_suspend(dev, &flags, 0);2722 csr15 = lp->a->read_csr(ioaddr, CSR15);2723 if (dev->flags & IFF_PROMISC) {2724 /* Log any net taps. */2725 netif_info(lp, hw, dev, "Promiscuous mode enabled\n");2726 lp->init_block->mode =2727 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<2728 7);2729 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);2730 } else {2731 lp->init_block->mode =2732 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);2733 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);2734 pcnet32_load_multicast(dev);2735 }2736 2737 if (suspended) {2738 pcnet32_clr_suspend(lp, ioaddr);2739 } else {2740 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);2741 pcnet32_restart(dev, CSR0_NORMAL);2742 netif_wake_queue(dev);2743 }2744 2745 spin_unlock_irqrestore(&lp->lock, flags);2746}2747 2748/* This routine assumes that the lp->lock is held */2749static int mdio_read(struct net_device *dev, int phy_id, int reg_num)2750{2751 struct pcnet32_private *lp = netdev_priv(dev);2752 unsigned long ioaddr = dev->base_addr;2753 u16 val_out;2754 2755 if (!lp->mii)2756 return 0;2757 2758 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));2759 val_out = lp->a->read_bcr(ioaddr, 34);2760 2761 return val_out;2762}2763 2764/* This routine assumes that the lp->lock is held */2765static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)2766{2767 struct pcnet32_private *lp = netdev_priv(dev);2768 unsigned long ioaddr = dev->base_addr;2769 2770 if (!lp->mii)2771 return;2772 2773 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));2774 lp->a->write_bcr(ioaddr, 34, val);2775}2776 2777static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)2778{2779 struct pcnet32_private *lp = netdev_priv(dev);2780 int rc;2781 unsigned long flags;2782 2783 /* SIOC[GS]MIIxxx ioctls */2784 if (lp->mii) {2785 spin_lock_irqsave(&lp->lock, flags);2786 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);2787 spin_unlock_irqrestore(&lp->lock, flags);2788 } else {2789 rc = -EOPNOTSUPP;2790 }2791 2792 return rc;2793}2794 2795static int pcnet32_check_otherphy(struct net_device *dev)2796{2797 struct pcnet32_private *lp = netdev_priv(dev);2798 struct mii_if_info mii = lp->mii_if;2799 u16 bmcr;2800 int i;2801 2802 for (i = 0; i < PCNET32_MAX_PHYS; i++) {2803 if (i == lp->mii_if.phy_id)2804 continue; /* skip active phy */2805 if (lp->phymask & (1 << i)) {2806 mii.phy_id = i;2807 if (mii_link_ok(&mii)) {2808 /* found PHY with active link */2809 netif_info(lp, link, dev, "Using PHY number %d\n",2810 i);2811 2812 /* isolate inactive phy */2813 bmcr =2814 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);2815 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,2816 bmcr | BMCR_ISOLATE);2817 2818 /* de-isolate new phy */2819 bmcr = mdio_read(dev, i, MII_BMCR);2820 mdio_write(dev, i, MII_BMCR,2821 bmcr & ~BMCR_ISOLATE);2822 2823 /* set new phy address */2824 lp->mii_if.phy_id = i;2825 return 1;2826 }2827 }2828 }2829 return 0;2830}2831 2832/*2833 * Show the status of the media. Similar to mii_check_media however it2834 * correctly shows the link speed for all (tested) pcnet32 variants.2835 * Devices with no mii just report link state without speed.2836 *2837 * Caller is assumed to hold and release the lp->lock.2838 */2839 2840static void pcnet32_check_media(struct net_device *dev, int verbose)2841{2842 struct pcnet32_private *lp = netdev_priv(dev);2843 int curr_link;2844 int prev_link = netif_carrier_ok(dev) ? 1 : 0;2845 u32 bcr9;2846 2847 if (lp->mii) {2848 curr_link = mii_link_ok(&lp->mii_if);2849 } else if (lp->chip_version == PCNET32_79C970A) {2850 ulong ioaddr = dev->base_addr; /* card base I/O address */2851 /* only read link if port is set to TP */2852 if (!lp->autoneg && lp->port_tp)2853 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);2854 else /* link always up for AUI port or port auto select */2855 curr_link = 1;2856 } else {2857 ulong ioaddr = dev->base_addr; /* card base I/O address */2858 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);2859 }2860 if (!curr_link) {2861 if (prev_link || verbose) {2862 netif_carrier_off(dev);2863 netif_info(lp, link, dev, "link down\n");2864 }2865 if (lp->phycount > 1) {2866 pcnet32_check_otherphy(dev);2867 }2868 } else if (verbose || !prev_link) {2869 netif_carrier_on(dev);2870 if (lp->mii) {2871 if (netif_msg_link(lp)) {2872 struct ethtool_cmd ecmd = {2873 .cmd = ETHTOOL_GSET };2874 mii_ethtool_gset(&lp->mii_if, &ecmd);2875 netdev_info(dev, "link up, %uMbps, %s-duplex\n",2876 ethtool_cmd_speed(&ecmd),2877 (ecmd.duplex == DUPLEX_FULL)2878 ? "full" : "half");2879 }2880 bcr9 = lp->a->read_bcr(dev->base_addr, 9);2881 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {2882 if (lp->mii_if.full_duplex)2883 bcr9 |= (1 << 0);2884 else2885 bcr9 &= ~(1 << 0);2886 lp->a->write_bcr(dev->base_addr, 9, bcr9);2887 }2888 } else {2889 netif_info(lp, link, dev, "link up\n");2890 }2891 }2892}2893 2894/*2895 * Check for loss of link and link establishment.2896 * Could possibly be changed to use mii_check_media instead.2897 */2898 2899static void pcnet32_watchdog(struct timer_list *t)2900{2901 struct pcnet32_private *lp = from_timer(lp, t, watchdog_timer);2902 struct net_device *dev = lp->dev;2903 unsigned long flags;2904 2905 /* Print the link status if it has changed */2906 spin_lock_irqsave(&lp->lock, flags);2907 pcnet32_check_media(dev, 0);2908 spin_unlock_irqrestore(&lp->lock, flags);2909 2910 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));2911}2912 2913static int __maybe_unused pcnet32_pm_suspend(struct device *device_d)2914{2915 struct net_device *dev = dev_get_drvdata(device_d);2916 2917 if (netif_running(dev)) {2918 netif_device_detach(dev);2919 pcnet32_close(dev);2920 }2921 2922 return 0;2923}2924 2925static int __maybe_unused pcnet32_pm_resume(struct device *device_d)2926{2927 struct net_device *dev = dev_get_drvdata(device_d);2928 2929 if (netif_running(dev)) {2930 pcnet32_open(dev);2931 netif_device_attach(dev);2932 }2933 2934 return 0;2935}2936 2937static void pcnet32_remove_one(struct pci_dev *pdev)2938{2939 struct net_device *dev = pci_get_drvdata(pdev);2940 2941 if (dev) {2942 struct pcnet32_private *lp = netdev_priv(dev);2943 2944 unregister_netdev(dev);2945 pcnet32_free_ring(dev);2946 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);2947 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block),2948 lp->init_block, lp->init_dma_addr);2949 free_netdev(dev);2950 pci_disable_device(pdev);2951 }2952}2953 2954static SIMPLE_DEV_PM_OPS(pcnet32_pm_ops, pcnet32_pm_suspend, pcnet32_pm_resume);2955 2956static struct pci_driver pcnet32_driver = {2957 .name = DRV_NAME,2958 .probe = pcnet32_probe_pci,2959 .remove = pcnet32_remove_one,2960 .id_table = pcnet32_pci_tbl,2961 .driver = {2962 .pm = &pcnet32_pm_ops,2963 },2964};2965 2966/* An additional parameter that may be passed in... */2967static int debug = -1;2968static int tx_start_pt = -1;2969static int pcnet32_have_pci;2970 2971module_param(debug, int, 0);2972MODULE_PARM_DESC(debug, DRV_NAME " debug level");2973module_param(max_interrupt_work, int, 0);2974MODULE_PARM_DESC(max_interrupt_work,2975 DRV_NAME " maximum events handled per interrupt");2976module_param(rx_copybreak, int, 0);2977MODULE_PARM_DESC(rx_copybreak,2978 DRV_NAME " copy breakpoint for copy-only-tiny-frames");2979module_param(tx_start_pt, int, 0);2980MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");2981module_param(pcnet32vlb, int, 0);2982MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");2983module_param_array(options, int, NULL, 0);2984MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");2985module_param_array(full_duplex, int, NULL, 0);2986MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");2987/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */2988module_param_array(homepna, int, NULL, 0);2989MODULE_PARM_DESC(homepna,2990 DRV_NAME2991 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");2992 2993MODULE_AUTHOR("Thomas Bogendoerfer");2994MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");2995MODULE_LICENSE("GPL");2996 2997#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)2998 2999static int __init pcnet32_init_module(void)3000{3001 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);3002 3003 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))3004 tx_start = tx_start_pt;3005 3006 /* find the PCI devices */3007 if (!pci_register_driver(&pcnet32_driver))3008 pcnet32_have_pci = 1;3009 3010 /* should we find any remaining VLbus devices ? */3011 if (pcnet32vlb)3012 pcnet32_probe_vlbus(pcnet32_portlist);3013 3014 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))3015 pr_info("%d cards_found\n", cards_found);3016 3017 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;3018}3019 3020static void __exit pcnet32_cleanup_module(void)3021{3022 struct net_device *next_dev;3023 3024 while (pcnet32_dev) {3025 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);3026 next_dev = lp->next;3027 unregister_netdev(pcnet32_dev);3028 pcnet32_free_ring(pcnet32_dev);3029 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);3030 dma_free_coherent(&lp->pci_dev->dev, sizeof(*lp->init_block),3031 lp->init_block, lp->init_dma_addr);3032 free_netdev(pcnet32_dev);3033 pcnet32_dev = next_dev;3034 }3035 3036 if (pcnet32_have_pci)3037 pci_unregister_driver(&pcnet32_driver);3038}3039 3040module_init(pcnet32_init_module);3041module_exit(pcnet32_cleanup_module);3042